TWI863679B - Substrate structure, electronic packakge having the same and the method of manufacture the electronic package - Google Patents
Substrate structure, electronic packakge having the same and the method of manufacture the electronic package Download PDFInfo
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Description
本發明係有關一種半導體裝置,尤指一種基板結構、具有該基板結構之電子封裝件與製法。 The present invention relates to a semiconductor device, in particular to a substrate structure, an electronic package having the substrate structure, and a manufacturing method.
隨著各種智慧型行動通訊裝置的大量普及並深入一般大眾的生活,使得消費者不僅是對於這些行動通訊裝置性能的要求越來越高,同時對於便攜性及製造成本等的要求也日益嚴苛。然而,要提高性能,就必須提高其核心之半導體組件,如中央處理器之運算能力及記憶晶片之容量以及所有這些組件的處理速度。而要提昇半導體組件的運算能力及記憶容量,就必須增加元件數量。另一方面,要提昇便攜性,就必須將這些組件製造得更為輕薄小巧。 As various smart mobile communication devices become more popular and penetrate into the lives of the general public, consumers not only have higher and higher requirements for the performance of these mobile communication devices, but also increasingly stringent requirements for portability and manufacturing costs. However, to improve performance, it is necessary to improve the core semiconductor components, such as the computing power of the central processing unit and the capacity of the memory chip, as well as the processing speed of all these components. To improve the computing power and memory capacity of semiconductor components, the number of components must be increased. On the other hand, to improve portability, these components must be made thinner and smaller.
在上述要求之下,現今之半導體組件中所使的基板厚度不斷地被薄化。然而,基板在經大幅薄化後,不僅是在製程中容易因為各種因素發生翹曲,而且這些翹曲現象也容易造成其電性連接件例如焊接墊等,因為翹曲所造成的不平整而與外界發生不必要的意外接觸並因此而受到如 刮傷等損傷,或者是受到製程藥劑汙染等傷害。此外,基板的翹曲也會在製程中造成一些其他最終會導致產品不良的問題,造成製造良率的下降,等於是提高了個別產品所需分攤的製造成本。 Under the above requirements, the thickness of the substrate used in today's semiconductor components is constantly being thinned. However, after being greatly thinned, the substrate is not only prone to warping due to various factors during the process, but these warping phenomena are also prone to causing its electrical connectors, such as solder pads, to have unnecessary accidental contact with the outside world due to the unevenness caused by the warping, and thus suffer damage such as scratches, or be contaminated by process chemicals. In addition, the warping of the substrate will also cause some other problems in the process that will eventually lead to defective products, resulting in a decrease in manufacturing yield, which is equivalent to increasing the manufacturing cost required to be shared by individual products.
因此,如何克服上述習知技術之種種問題,實已成為目前業界亟待克服之難題。 Therefore, how to overcome the above-mentioned problems of known technology has become a difficult problem that the industry needs to overcome urgently.
鑑於上述習知技術之種種缺失,本發明提供一種基板結構,係包括:基板本體,具有相對之第一表面與第二表面,該第二表面上設有至少一電性連接件;以及凹槽,設於該第二表面鄰近邊緣處並圍繞該至少一電性連接件。 In view of the various deficiencies of the above-mentioned prior art, the present invention provides a substrate structure, comprising: a substrate body having a first surface and a second surface opposite to each other, the second surface being provided with at least one electrical connector; and a groove, which is provided near the edge of the second surface and surrounds the at least one electrical connector.
本發明並提供一種電子封裝件,係包括:基板結構,包括基板本體及凹槽;以及至少一電子元件;其中,該基板本體具有相對之第一表面及第二表面,該第二表面上設有至少一電性連接件,該凹槽位於該第二表面鄰近邊緣處並圍繞該至少一電性連接件,該至少一電子元件則係設於該基板本體之該第一表面上。 The present invention also provides an electronic package, comprising: a substrate structure, including a substrate body and a groove; and at least one electronic component; wherein the substrate body has a first surface and a second surface opposite to each other, at least one electrical connector is provided on the second surface, the groove is located near the edge of the second surface and surrounds the at least one electrical connector, and the at least one electronic component is provided on the first surface of the substrate body.
前述之基板結構及電子封裝件中,該第二表面上復結合有一承載件以遮蓋該第二表面。 In the aforementioned substrate structure and electronic package, a carrier is composited on the second surface to cover the second surface.
前述之基板結構及電子封裝件中,該承載件上設有結合部,該結合部係與該凹槽對應結合以將該承載件結合於該第二表面上。 In the aforementioned substrate structure and electronic package, a bonding portion is provided on the carrier, and the bonding portion is bonded to the groove correspondingly to bond the carrier to the second surface.
本發明還提供一種電子封裝件的製法,係包括:提供一基板結構,該基板結構包括基板本體及凹槽,該基板本體具有相對之第表面及 第二表面,該第二表面上設有至少一電性連接件,該凹槽位於該第二表面鄰近邊緣處並圍繞該至少一電性連接件;將一設有結合部之承載件透過該結合部與該凹槽對應結合,以將該承載件結合於該第二表面上並遮蓋該第二表面;以及將至少一電子元件設於該基板本體之該第一表面上。 The present invention also provides a method for manufacturing an electronic package, which includes: providing a substrate structure, the substrate structure including a substrate body and a groove, the substrate body having a first surface and a second surface opposite to each other, the second surface being provided with at least one electrical connector, the groove being located near the edge of the second surface and surrounding the at least one electrical connector; a carrier having a coupling portion is coupled to the groove through the coupling portion to couple the carrier to the second surface and cover the second surface; and at least one electronic component is disposed on the first surface of the substrate body.
前述之電子封裝件的製法,復包括將該承載件自該第二表面上移除。 The aforementioned method for manufacturing the electronic package further includes removing the carrier from the second surface.
前述之電子封裝件及其製法中,復包括設置導電元件於該第二表面之該至少一電性連接件上。 The aforementioned electronic package and its manufacturing method further include disposing a conductive element on the at least one electrical connector on the second surface.
前述之電子封裝件及其製法中,復包括將一散熱件結合於該至少一電子元件。 The aforementioned electronic package and its manufacturing method further include combining a heat sink with the at least one electronic component.
由上可知,本發明之基板結構及具有該基板結構之電子封裝件可藉由以基板結構中之凹槽結合承載件,然後由承載件保護基板結構中之電性連接件以避免其在製程中受到損傷或遭到污染,並可補強該基板結構之強度,使其在製程中不致發生翹曲等變形以及因變形所造成之損壞或不良,進而提昇良率、降低製造成本。 As can be seen from the above, the substrate structure of the present invention and the electronic package having the substrate structure can be combined with the carrier by the groove in the substrate structure, and then the carrier can protect the electrical connector in the substrate structure to prevent it from being damaged or contaminated during the manufacturing process, and can also strengthen the strength of the substrate structure so that it will not be deformed such as warping during the manufacturing process, and damage or defects caused by deformation will be avoided, thereby improving the yield rate and reducing the manufacturing cost.
1:電子封裝件 1: Electronic packaging components
10:基板結構 10: Substrate structure
11:基板本體 11: Substrate body
11a:第一表面 11a: First surface
11b:第二表面 11b: Second surface
111:底膠 111: Base glue
112:散熱件 112: Heat sink
113:導熱介面材 113: Thermal conductive interface material
114:封裝膠材 114: Packaging plastic
12:凹槽 12: Groove
13:電性連接件 13: Electrical connectors
131:導電凸塊 131: Conductive bump
132:導電元件 132: Conductive element
14:承載件 14: Carrier
141:結合部 141:Joint part
141a:凸塊 141a: Bump
141b:軟墊 141b: Soft cushion
141c:凹部 141c: concave part
141d:軟柱 141d: Soft column
20:電子元件 20: Electronic components
圖1至4為本發明之基板結構及具有該基板結構之電子封裝件的製法之剖視示意圖。 Figures 1 to 4 are schematic cross-sectional views of the substrate structure of the present invention and a method for manufacturing an electronic package having the substrate structure.
圖1-1為本發明實施例之基板結構的一底面仰視圖。 Figure 1-1 is a bottom view of the substrate structure of an embodiment of the present invention.
圖1-2為本發明實施例之基板結構的一變化態樣之剖視示意圖。 Figure 1-2 is a cross-sectional schematic diagram of a variation of the substrate structure of an embodiment of the present invention.
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The following is a specific and concrete example to illustrate the implementation of the present invention. People familiar with this technology can easily understand other advantages and effects of the present invention from the content disclosed in this manual.
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」、「下」、「一」、「第一」及「第二」等用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。 It should be noted that the structures, proportions, sizes, etc. depicted in the drawings attached to this specification are only used to match the contents disclosed in the specification for understanding and reading by people familiar with this technology, and are not used to limit the restrictive conditions for the implementation of the present invention. Therefore, they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "one", "first" and "second" used in this specification are only for the convenience of description, and are not used to limit the scope of implementation of the present invention. Changes or adjustments to their relative relationships, without substantial changes to the technical content, should also be regarded as the scope of implementation of the present invention.
圖1至4為本發明之基板結構及具有該基板結構之電子封裝件的製法之剖視示意圖。 Figures 1 to 4 are schematic cross-sectional views of the substrate structure of the present invention and a method for manufacturing an electronic package having the substrate structure.
如圖1所示,提供一基板結構10,該基板結構10包括基板本體11及至少一凹槽12,該基板本體11具有一第一表面11a及與該第一表面11a相對之一第二表面11b,且該凹槽12設於該第二表面11b,以將一承載件14藉由設於其上的結合部141與該凹槽12對應結合於該第二表面11b上,俾遮蓋該第二表面11b。
As shown in FIG. 1 , a
基板本體11可以是具有核心層(core)之線路結構或無核心層(coreless)之線路結構的封裝基板(substrate)。以現今主流的半導體組件
結構而言,基板本體11通常包含至少一介電層(圖未示)及結合於該介電層內之線路層(圖未示)。例如是以線路重佈層(redistribution layer,簡稱RDL)之形式所形成的線路層。而用以形成介電層之材質例如可以是聚對二唑苯(Polybenzoxazole,簡稱PBO)、聚醯亞胺(Polyimide,簡稱PI)、預浸材(prepreg)等之介電材。應可理解地,基板本體11也可為其它能夠用以承載電子元件之板材,例如晶圓、矽中介板(silicon interposer)、玻璃等之板材,但並不以上述為限。
The
基板本體11具有一第一表面11a及與該第一表面11a相對之一第二表面11b。第二表面11b上設有複數電性連接件13。各電性連接件13例如可以是一個金屬連接墊(pad),但並不以此為限。而如圖1所示,本實施例中之基板本體11的第二表面11b上係設有多個金屬連接墊以作為該些電性連接件13。同時,本實施例中之基板本體11的第一表面11a上同樣也設有多個作為電性連接件13的金屬連接墊。另外,雖然圖1所示範例中第二表面11b與第一表面11a上之電性連接件13數量相同,但實際上係可依照線路的設計而有所不同,並不以圖1所示的態樣為限。
The
請一併參閱圖1-1,其係為基板本體11底面之仰視圖。該凹槽12係設於第二表面11b上,鄰近第二表面11b的邊緣處,並且圍繞該些電性連接件13。較佳地,該凹槽12係呈環狀,以將基板本體11之第二表面11b上的該些電性連接件13環繞包圍在其中。
Please refer to Figure 1-1, which is a top view of the bottom surface of the
在本實施例中,基板結構10中之基板本體11的第二表面11b上可進一步結合有一承載件14,以將基板本體11的第二表面11b給遮蓋
住。除此之外,承載件14也被用來在整個封裝製程中承載並支撐基板本體11。一般而言,承載件14通常是以金屬材料製成,但並不以此為限。
In this embodiment, a
在圖1所示之實施態樣中,結合部141包括形成於承載件14表面上之凸塊141a及套設在各凸塊141a上的軟墊141b。於一實施例中,該凸塊141a係與該基板本體11一體成形,並藉由將結合部141與凹槽12對應結合,而將承載件14連接至該第二表面11b上。
In the embodiment shown in FIG. 1 , the
請參見圖1-2,在一變化的實施態樣中,承載件14之結合部141也可由形成於該基板本體11之凹部141c與插置於該凹部141c中的軟柱141d構成。藉由將結合部141以迫緊的方式塞緊固定在對應的凹槽12中,而將承載件14固定於基板本體11的第二表面11b上。
Please refer to Figures 1-2. In a modified embodiment, the
除上述材料外,結合部141可以是用金屬、塑膠、橡膠、聚合物等材料製成,並利用例如卡扣、鎖扣、迫緊等方式與對應的凹槽12結合。而且該結合部141與凹槽12的結合方式通常是可輕易地被緊固或鬆開的,如此可讓結合部141與承載件14都能被重複使用。在本實施例中,該結合部141是以軟性材料構成(例如為耐熱塑膠軟墊),並以迫緊的方式將其一端密封地塞緊、固定在凹槽12內。在本實施例中,該結合部141係配合凹槽12形狀而呈環狀圍繞在承載件14上鄰近周緣處,可有效避免異物汙染電性連接件13,並防止基板本體11損傷。
In addition to the above materials, the
由於本實施例中之基板本體11的第二表面11b是被承載件14給遮蓋住的,而且位於第二表面11b的該些電性連接件13周圍又被以軟性材料構成而密封地塞緊、固定在各凹槽12內的結合部141給包圍,使得位於基板本體11第二表面11b的該些電性連接件13完全與外界環境隔
絕。因此可在後續的製程中受到承載件14的保護,而不致受到如刮傷或是製程藥劑侵蝕等的傷害。
Since the
如圖2所示,本實施例所提供之電子封裝件的製法在將承載件14結合於基板本體11的第二表面11b上之後,可將一電子元件20設置在基板本體11的第一表面11a上,並藉由複數個例如銲球之導電凸塊131(solder ball)而連接位在第一表面11a上對應之電性連接件13。
As shown in FIG. 2 , the method for manufacturing the electronic package provided in this embodiment can place an
本實施例中,電子元件20可以是一個半導體晶粒(die)或是晶片(chip)等的主動元件,也可以是電阻、電容或電感之類的被動元件,或者也可以是一個以上之上述主動及/或被動元件的組合。本實施例對此並無任何特別的限制,端視產品之設計需要而定。
In this embodiment, the
如圖3所示,將底膠111填充於電子元件20底部及基板本體11的第一表面11a之間,並可將一散熱件112經由例如導熱介面材113(Thermal Interface Material,簡稱TIM)之導熱材料結合於電子元件20的頂部,且藉由封裝膠材114將散熱件112結合固定在基板本體11的第一表面11a之周緣。
As shown in FIG. 3 , the
在此一製程階段中,由於所用到的膠材大多需要在熱熔狀態下被填充或塗佈,因此基板結構10的各個部位也會直接或間接地接受到不同程度的熱。但因為基板本體11係經由結合部141被固定結合在承載件14上,而非未受任何限制地簡單放置在承載件14表面,因此即使各個部位可能分別受到程度不一的熱,但卻可以因為有承載件14所提供的補強,故能不受影響或僅受到輕微影響地不致發生如翹曲等的變形。
In this stage of the manufacturing process, since most of the glue used needs to be filled or applied in a hot melt state, various parts of the
接著請參見圖4,將承載件14自第二表面11b上移除。之後可以在基板本體11的第二表面11b上進行植球製程,以在第二表面11b上的各個電性連接件13上設置導電元件132,如此就可得到本實施例之製法所要製得的電子封裝件1。
Then, please refer to FIG. 4 , and remove the
而此電子封裝件1即如前述地包括有基板結構10;以及至少一電子元件20。而基板結構10則包括具有第一表面11a及第二表面11b的基板本體11及位於第二表面11b鄰近邊緣處的凹槽12;且第二表面11b上設有被該凹槽12圍繞的至少一電性連接件13,電子元件20則係設於第一表面11a上。
As mentioned above, the
綜上所述,本發明之基板結構10及具有該基板結構10之電子封裝件1可藉由以基板結構10中之凹槽12結合承載件14,然後由承載件14保護基板結構10中之電性連接件13以避免其在製程中受到損傷或遭到污染,並可藉由該承載件14具有剛性,補強該基板結構10之強度,使其在製程中不致發生翹曲等變形以及因變形所造成之損壞或不良,進而提昇良率,同時該承載件14可重複使用,降低製造成本。
In summary, the
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如隨附之申請專利範圍所列。 The above embodiments are used to illustrate the principles and effects of the present invention, but are not used to limit the present invention. Anyone familiar with this technology can modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the attached patent application scope.
1:電子封裝件 1: Electronic packaging components
10:基板結構 10: Substrate structure
11:基板本體 11: Substrate body
11a:第一表面 11a: First surface
11b:第二表面 11b: Second surface
111:底膠 111: Base glue
112:散熱件 112: Heat sink
113:導熱介面材 113: Thermal conductive interface material
114:封裝膠材 114: Packaging plastic
12:凹槽 12: Groove
13:電性連接件 13: Electrical connectors
131:導電凸塊 131: Conductive bump
132:導電元件 132: Conductive element
20:電子元件 20: Electronic components
Claims (10)
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| TW112142684A TWI863679B (en) | 2023-11-06 | 2023-11-06 | Substrate structure, electronic packakge having the same and the method of manufacture the electronic package |
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| TW112142684A TWI863679B (en) | 2023-11-06 | 2023-11-06 | Substrate structure, electronic packakge having the same and the method of manufacture the electronic package |
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| TWI863679B true TWI863679B (en) | 2024-11-21 |
| TW202520449A TW202520449A (en) | 2025-05-16 |
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| TW200425360A (en) * | 2002-11-14 | 2004-11-16 | Samsung Electronics Co Ltd | Side-bonding method of flip-chip semiconductor device, MEMS device package and package method using the same |
| TW200524066A (en) * | 2003-12-03 | 2005-07-16 | Schott Ag | Process for packaging components, and packaged components |
| TW200539336A (en) * | 2004-02-23 | 2005-12-01 | Towa Intercon Technology Inc | Saw singulation |
| US20210391283A1 (en) * | 2020-06-11 | 2021-12-16 | Advanced Semiconductor Engineering, Inc. | Package substrate, electronic device package and method for manufacturing the same |
| US20220352083A1 (en) * | 2021-04-29 | 2022-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip package structure and method for forming the same |
| TW202247305A (en) * | 2021-05-26 | 2022-12-01 | 威盛電子股份有限公司 | Electronic package and manufacturing method thereof |
| TW202306057A (en) * | 2021-07-23 | 2023-02-01 | 新加坡商光寶科技新加坡私人有限公司 | Thermal sensor package |
| US20230057702A1 (en) * | 2021-08-19 | 2023-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and manufacturing method thereof |
| TW202326951A (en) * | 2021-12-30 | 2023-07-01 | 同欣電子工業股份有限公司 | Sensor package structure |
| US20230317671A1 (en) * | 2022-03-30 | 2023-10-05 | Taiwan Semiconductor Manufacturing Company Limited | Substrate trench for controlling underfill fillet area and methods of forming the same |
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2023
- 2023-11-06 TW TW112142684A patent/TWI863679B/en active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200425360A (en) * | 2002-11-14 | 2004-11-16 | Samsung Electronics Co Ltd | Side-bonding method of flip-chip semiconductor device, MEMS device package and package method using the same |
| TW200524066A (en) * | 2003-12-03 | 2005-07-16 | Schott Ag | Process for packaging components, and packaged components |
| TW200539336A (en) * | 2004-02-23 | 2005-12-01 | Towa Intercon Technology Inc | Saw singulation |
| US20210391283A1 (en) * | 2020-06-11 | 2021-12-16 | Advanced Semiconductor Engineering, Inc. | Package substrate, electronic device package and method for manufacturing the same |
| US20220352083A1 (en) * | 2021-04-29 | 2022-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip package structure and method for forming the same |
| TW202247305A (en) * | 2021-05-26 | 2022-12-01 | 威盛電子股份有限公司 | Electronic package and manufacturing method thereof |
| TW202306057A (en) * | 2021-07-23 | 2023-02-01 | 新加坡商光寶科技新加坡私人有限公司 | Thermal sensor package |
| US20230057702A1 (en) * | 2021-08-19 | 2023-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and manufacturing method thereof |
| TW202326951A (en) * | 2021-12-30 | 2023-07-01 | 同欣電子工業股份有限公司 | Sensor package structure |
| US20230317671A1 (en) * | 2022-03-30 | 2023-10-05 | Taiwan Semiconductor Manufacturing Company Limited | Substrate trench for controlling underfill fillet area and methods of forming the same |
Also Published As
| Publication number | Publication date |
|---|---|
| TW202520449A (en) | 2025-05-16 |
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