TWI863373B - Receiver performing adaptive calibration - Google Patents

Abstract

A receiver includes a channel compensator, a decoder and an adaptive controller. The channel compensator performs channel compensation on an input data signal to generate a feed data signal. The decoder demultiplexes a data signal to be decoded from the feed data signal into a plurality of demultiplexed data signals, and decodes the demultiplexed data signals into a plurality of decoded signals respectively. The adaptive controller generates an output data signal according to the decoded output, and performs adaptive calibration on the channel compensator with reference to an error portion of a first sample of the decoded signals and a data portion of a second sample of the decoded signals generated before the first sample of the decoded signals is generated, so as to adjust the gain of the channel compensator.

Description

Receiver performing adaptive calibration

The present invention relates to a receiver, and more particularly to a receiver for performing adaptive calibration.

The Serializer/Deserializer (SerDes) function is widely used in communication standards (e.g., Ethernet, PCIe (Peripheral Component Interconnect express), Universal Serial Bus (USB), etc.) and eXtra-Short Reach (XSR) applications (e.g., package-to-package computing chips, optical communication chips, etc.). It is critical that a receiver that converts serial input data to parallel output data can handle channel loss and process, voltage and temperature (PVT) variations in order to operate more stably and achieve higher yields.

Therefore, an object of the present invention is to provide a receiver capable of handling channel loss and at least one of process, voltage and temperature variations.

According to one aspect of the present invention, the receiver includes a channel compensator, a decoder and an adaptive controller. The channel compensator receives an input data signal and performs channel compensation on the input data signal to generate a feed data signal. The gain of the channel compensator is adjustable. The decoder is connected to the channel compensator to receive the feed data signal, demultiplexes a data signal to be decoded from the feed data signal into a number P of demultiplexed data signals, and decodes the demultiplexed data signals into a number P of decoded signals, wherein . Each of the decoded signals includes a plurality of samples, and the samples of the decoded signals are generated sequentially. Each sample of the decoded signals includes a data portion, and each sample of at least one of the decoded signals also includes an error portion. The adaptive controller is connected to the decoder to receive a decoded output from the decoded signals, and is also connected to the channel compensator. The adaptive controller generates an output data signal based on the decoded output, and performs adaptive calibration on the channel compensator with reference to the error portion of a first sample of the decoded signals and the data portion of a second sample of the decoded signals generated before the first sample of the decoded signals is generated, so as to adjust the gain of the channel compensator.

According to another aspect of the present invention, the receiver includes a voltage regulator, a decoder and an adaptive controller. The voltage regulator generates a reference voltage with an adjustable size. The decoder is connected to the voltage regulator to receive the reference voltage, demultiplexes a data signal to be decoded into a number P of demultiplexed data signals, and decodes the demultiplexed data signals into a number P of decoded signals according to the reference voltage, where P≥2. Each of the decoded signals includes a plurality of samples, and the samples of the decoded signals are generated sequentially. Each sample of the decoded signals includes a data portion, and each sample of at least one of the decoded signals also includes an error portion. The adaptive controller is connected to the decoder to receive the decoded output from the decoded signals and is connected to the voltage regulator. The adaptive controller generates an output data signal according to the decoded output and performs adaptive calibration on the voltage regulator with reference to the error part and the data part of a sample of the decoded signals to adjust the magnitude of the reference voltage.

According to another aspect of the present invention, the receiver includes a phase interpolator, a decoder device and an adaptive controller. The phase interpolator receives a clock input and performs phase interpolation on the clock input to obtain an interpolated clock signal of number N, wherein The decoder device includes a decoder having a phase shift relative to the clock input of each interpolated clock signal and a phase shift relative to the clock input of each interpolated clock signal. Each decoder is connected to the phase interpolator to receive a corresponding one of the interpolated clock signals and delay the corresponding interpolated clock signal to generate a correction clock signal whose delay relative to the corresponding interpolated clock signal is adjustable. The decoders cooperate with each other to receive a feed data signal and demultiplex the feed data signal into a first demultiplexed data signal of N number provided by the decoders respectively according to the correction clock signals generated by the decoders. Each decoder buffers the first demultiplexed data signal provided by itself to generate a data signal to be decoded, demultiplexes the data signal to be decoded into a number P of second demultiplexed data signals, and decodes the second demultiplexed data signals into a number P of decoded signals, respectively, wherein , each decoded signal includes a plurality of samples, the samples of the decoded signals are generated sequentially, each sample of the decoded signals includes a data portion and each sample of at least one of the decoded signals also includes an error portion. The adaptive controller is connected to the decoder device to receive a decoded output of the decoded signals generated by the decoders, and is also connected to the phase interpolator. The adaptive controller is connected to the decoder device to receive a decoded output of the decoded signals generated by the decoders, and is also connected to the phase interpolator. The adaptive controller generates an output data signal based on the decoded output, and performs adaptive calibration on the phase interpolator and the decoders to adjust the phase shift of the interpolated clock signals and the delay of the correction clock signals.

Before the present invention is described in detail, it should be noted that, where appropriate, reference numerals or the terminal parts of reference numerals are repeated among the drawings to indicate corresponding or similar elements, which elements may optionally have similar features.

1 and 2 , a receiver according to an embodiment of the present invention is suitable for converting serial input data into parallel output data, and includes a channel compensator 11, a voltage regulator 12, a multi-phase filter 13, a current mode logic (CML) to complementary metal oxide semiconductor (CMOS) converter 14, a phase interpolator 15, a decoder device 16 and an adaptive controller 17.

The channel compensator 11 receives an input data signal Din in a pulse amplitude modulation (PAM)-2 ^M format and performs channel compensation on the input data signal Din to generate a feed data signal in a PAM-2 ^M format, wherein M 2 and the gain of the channel compensator 11 is adjustable. For illustration, in this embodiment, the input data signal Din and the feed data signal are both in PAM-4 format (ie, M=2) and have a data rate of 112 Gbps (ie, 56 Gbaud).

In this embodiment, the channel compensator 11 includes an equalizer device 111 and a variable gain amplifier (VGA) 112. The equalizer device 111 includes a continuous time linear equalizer (CTLE) 116 and a low frequency equalizer (LFEQ) 117. Multiple high frequency components of the input data signal Din are compensated by the continuous time linear equalizer 116, and the intermediate frequency and low frequency components of the input data signal (Din) are compensated by the low frequency equalizer 117. The signal caused by the above compensation is adjusted in pulse amplitude by the variable gain amplifier 112 to generate the feed data signal. The gain of the channel compensator 11 can be changed by adjusting the parameters of the continuous time linear equalizer 116 and the low frequency equalizer 117.

The voltage regulator 12 generates a reference voltage with an adjustable magnitude.

The polyphase filter 13 receives a CML-level differential input clock signal pair CKin and divides the differential input clock signal pair CKin into two CML-level differential first clock signal pairs with a phase difference of 90°. For illustration, in this embodiment, the frequency of the differential input clock signal pair CKin is 14 GHz.

The CML to CMOS converter 14 is connected to the polyphase filter 13 to receive the differential first clock signal pairs and convert the differential first clock signal pairs into two differential second clock signal pairs of CMOS levels respectively.

The phase interpolator 15 cooperates with some components of the adaptive controller 17 to form a clock data recovery (CDR) circuit. The phase interpolator 15 is connected to the CML to CMOS converter 14 to receive the differential second clock signal pairs that together form a clock input, and performs phase interpolation on the clock input to generate N number of interpolated clock signals, wherein The phase shift of each interpolated clock signal relative to the clock input is adjustable. For illustration, in this embodiment, four interpolated clock signals are generated (ie, N=4).

The decoder device 16 includes a number N of decoders 160 (i.e., there are four decoders 160 in this embodiment). In this embodiment, each decoder 160 includes a clock corrector 161, a ring counter 162, a 1/Q frequency divider 163, a first demultiplexer 164, a buffer 165, a second demultiplexer 166, a number P of analog to digital converters (ADCs) 167, a phase calibration circuit 168, and a 1-to-Q demultiplexer 169, wherein And For illustration, in the present embodiment, a 1/2 frequency divider is used as the 1/Q frequency divider 163, four analog-to-digital converters 167 and a 1:2 demultiplexer is used as the 1:Q demultiplexer 169 (ie, P=4 and Q=2).

For each decoder 160, the clock corrector 161 is connected to the phase interpolator 15 to receive a corresponding interpolated clock signal, and delays the corresponding interpolated clock signal to generate a corrected clock signal. The delay of the corrected clock signal relative to the corresponding interpolated clock signal is adjustable. The first demultiplexer 164 is connected to the clock corrector 161 to receive the corrected clock signal, and is also connected to the channel compensator 11.

The first demultiplexers 164 of the decoders 160 cooperate with each other to receive the feed data signal from the channel compensator 11, and demultiplex the feed data signal into a number N of first demultiplexed data signals (i.e., there are four first demultiplexed data signals in this embodiment) outputted by the first demultiplexers 164 according to the correction clock signals generated by the clock correctors 161 of the decoders 160. In this embodiment, the data rate of each first demultiplexed data signal is 14 Gbaud.

It should be noted that for each calibration clock signal, the time lag between the calibration clock signal and any other calibration clock signal can be changed by adjusting the delay of the calibration clock signal.

In this embodiment, for each decoder 160, the first demultiplexer 164 includes a sampling switch 1641. The sampling switch 1641 has a first end connected to the channel compensator 11 to receive the feed data signal, a second end providing a corresponding first demultiplexed data signal, and a control end connected to the clock corrector 161 to receive the correction clock signal. The sampling switch 1641 switches between conduction and non-conduction according to the correction clock signal. When the sampling switch 1641 is turned on, the feed data signal is transmitted through the sampling switch 1641 as the corresponding first demultiplexed data signal.

For each decoder 160, the ring counter 162 is connected to the clock corrector 161 to receive the correction clock signal, and generates a P-bit wide (for example, 4-bit wide in this embodiment) count output based on the correction clock signal. A predetermined logical value (for example, logical value "1") cycles between the bits of the count output at a speed defined by the correction clock signal. The 1/Q divider 163 (for example, 1/2 divider 163 in this embodiment) is connected to the ring counter 162 to receive the count output, and generates a third clock signal with a frequency of 1/Q (for example, 1/2 in this embodiment) of the count output based on the count output.

For each decoder 160, the buffer 165 is connected to the second end of the sampling switch 1641 to receive the first demultiplexed data signal, and buffers the first demultiplexed data signal to generate a data signal to be decoded in a PAM- ^2M format (for example, a PAM-4 format in this embodiment). The second demultiplexer 166 is connected to the buffer 165 to receive the data signal to be decoded, and is also connected to the ring counter 162 to receive the count output, and demultiplexes the data signal to be decoded into a number P of second demultiplexed data signals (for example, four second demultiplexed data signals in this embodiment) according to the count output. Each ADC 167 is connected to the second demultiplexer 166 to receive the corresponding second demultiplexed data signal, and is also connected to the voltage regulator 12 to receive the reference voltage. One of the ADCs 167 is an (M+1)-bit ADC (for example, a 3-bit ADC in this embodiment), and performs analog-to-digital conversion on the corresponding second demultiplexed data signal according to the reference voltage to generate a first decoded signal in a non-return-to-zero (NRZ) format. The first decoded signal includes an M-bit wide (for example, 2-bit wide in this embodiment) data portion and a 1-bit wide error portion. Each of the other ADCs 167 is an M-bit ADC (for example, a 2-bit ADC in this embodiment), and performs analog-to-digital conversion on the corresponding second demultiplexed data signal according to the reference voltage to generate a second decoded signal in NRZ format. The second decoded signal includes a data portion with an M-bit width (for example, a 2-bit width in this embodiment). In this embodiment, the data rate of each second demultiplexed data signal is 3.5 Gbaud.

In this embodiment, for each decoder 160, the second demultiplexer 166 includes a number P of sampling switches 1661 (for example, four sampling switches 1661 in this embodiment). Each sampling switch 1661 has a first end connected to the buffer 165 to receive the data signal to be decoded, a second end providing a corresponding second demultiplexed data signal, and a control end connected to the ring counter 162 to receive the corresponding bit of the count output. Each sampling switch 1661 is turned on when the corresponding bit of the count output is at the predetermined logical value (for example, the logical value "1" in this embodiment), otherwise it is not turned on. For each sampling switch 1661, when the sampling switch 1661 is turned on, the feed data signal is transmitted through the sampling switch 1661 to serve as the corresponding second demultiplexed data signal. In addition, each ADC 167 is a successive approximation ADC.

For each decoder 160, the phase calibration circuit 168 is connected to the ADCs 167 to receive the first decoded signal and the second decoded signals, and is also connected to the ring counter 162 to receive the count output, and calibrates the first decoded signal and the second decoded signals according to the count output to generate a calibration signal including a data portion and an error portion. The data portion of the calibration signal is bit width (e.g., 8 bits in this embodiment), and is derived from the data parts of the first decoded signal and the second decoded signals. The error part of the calibration signal is 1 bit wide and is derived from the error part of the first decoded signal. The 1:2 demultiplexer 169 (e.g., 1:2 demultiplexer 169 in this embodiment) is connected to the phase calibration circuit 168 to receive the calibration signal, and is also connected to the 1/Q divider 163 (1/2 divider 163 in this embodiment) to receive the third clock signal, and demultiplexes the calibration signal into a demultiplexed signal including a data part and an error part according to the third clock signal. The data part of the demultiplexed signal is The demultiplexed signals are Q-bit wide (e.g., 16-bit wide in this embodiment) and are derived from the data portion of the first decoded signal and the second decoded signals. The error portion of the demultiplexed signal is Q-bit wide (e.g., 2-bit wide in this embodiment) and is derived from the error portion of the first decoded signal. The demultiplexed signals generated by the 1-to-Q demultiplexers 169 (e.g., 1:2 demultiplexers 169 in this embodiment) of the decoders 160 together constitute a decoded output. In this embodiment, for each decoder 160, the data rate of the data portion of the calibration signal is Gbps, and the data rate of the error portion of the calibration signal is Gbps; the data rate of the data portion of the demultiplexed signal is Gbps, and the data rate of the error portion of the demultiplexed signal is Gbps.

The adaptive controller 17 is connected to the 1-to-Q demultiplexers 169 (1:2 demultiplexers 169 in the present embodiment) of the decoders 160 to receive the decoded output, and is also connected to the quantizer device 111, the voltage regulator 12, the phase interpolator 15 and the clock corrector 161 of the decoders 160, and generates an output data signal Dout based on a data portion of the decoded output, wherein the data portion of the decoded output is derived from the data portions of the first decoded signals and the second decoded signals generated by the ADCs 167 of the decoders 160. The adaptive controller 17 also performs adaptive calibration on the equalizer device 111, the voltage regulator 12, the phase interpolator 13 and the clock corrector 161 of the decoders 160 to adjust the gain of the channel compensator 11, the reference voltage, the phase shift of the interpolated clock signals and the delay of the corrected clock signals according to an error portion of the decoded output derived from the error portions of the first decoded signals and the data portion of the decoded output, so as to obtain the best quality of the eye diagram of the feed data signal, the correct swing of the feed data signal and the best sample position of the feed data signal. In this embodiment, the data rate of the output data signal Dout is Gbps.

In the present embodiment, each of the first decoded signal and the second decoded signals comprises a plurality of samples arranged in sequence. The ADCs 167 of the decoders 160 operate one by one in a loop at a speed defined by a time interval corresponding to a frequency, which is N times (for example, four times in the present embodiment) the frequency of each interpolated clock signal, so as to generate the samples of the first decoded signals and the second decoded signals. Table 1 shows an exemplary order in which the samples of the first decoded signals and the second decoded signals are generated in each operation cycle, wherein D[] represents a data portion of a sample of the first decoded signals and the second decoded signals, which is one of a logical value "00" (corresponding to -3), a logical value "01" (corresponding to -1), a logical value "10" (corresponding to +1) and a logical value "11" (corresponding to +3); and E[] represents an error portion of a sample of the first decoded signals, which is one of a logical value "0" and a logical value "1". Table 1 3-bit ADC 2-bit ADC (I) 2-bit ADC (II) 2-bit ADC (III) Decoder(I) - - - Decoder(II) - - - Decoder (III) - - - Decoder(IV) - - - r: non-negative integer

In this embodiment, as shown in Table 2, the adaptive controller 17 adaptively calibrates the equalizer device 111 to adjust the gain of the channel compensator 11 with reference to the error portion (expressed as E[a]) of a sample of the first decoded signals and the data portion (expressed as D[aK]) of a sample of the first decoded signals and the second decoded signals generated before the sample of the first decoded signals is generated. In one example, the samples of the first decoded signals and the second decoded signals are generated within a time interval of a quantity K before the sample of the first decoded signals is generated, wherein Table 2 D[aK] E[a] Gain 1x 1 Increase 0x 0 Increase 1x 0 Reduce 0x 1 Reduce x: any value

The adaptive controller 17 increases the gain of the channel compensator 11 when any of the following conditions is met: (a) the data portion D[a-K] of the sample of the first decoded signals and the second decoded signals is represented by a positive value (i.e., at a logical value "10" corresponding to +1, or at a logical value "11" corresponding to +3), and the error part E[a] is at a logical value "1"; and (b) the data part D[a-K] of the sample of the first decoded signals and the second decoded signals is represented by a negative value (i.e., at a logical value "00" corresponding to -3, or at a logical value "01" corresponding to -1), and the error part E[a] of the sample of the first decoded signals is at a logical value "0".

The adaptive controller 17 reduces the gain of the channel compensator 11 when any of the following conditions is met: (a) the data portion D[a-K] of the sample of the first decoded signals and the second decoded signals is represented by a positive value, and the error portion E[a] of the sample of the first decoded signals is at a logical value of "0"; and (b) the data portion D[a-K] of the sample of the first decoded signals and the second decoded signals is represented by a negative value, and the error portion E[a] of the sample of the first decoded signals is at a logical value of "1".

Otherwise, the adaptive controller 17 keeps the gain of the channel compensator 11 unchanged.

In this embodiment, as shown in Table 3, the adaptive controller 17 performs adaptive calibration on the voltage regulator 12 to adjust the reference voltage with reference to the error portion E[a] and the data portion D[a] of the sample of the first decoded signals. Table 3 D[a] E[a] The size of the reference voltage 1x 1 Increase 0x 0 Increase 1x 0 Reduce 0x 1 Reduce x: not important

The adaptive controller 17 increases the magnitude of the reference voltage when any of the following conditions is met: (a) the data portion D[a] of the sample of the first decoded signals is represented by a positive value, and the error portion E[a] of the sample of the first decoded signals is at a logical value of "1"; and (b) the data portion D[a] of the sample of the first decoded signals is represented by a negative value, and the error portion E[a] of the sample of the first decoded signals is at a logical value of "0".

The adaptive controller 17 reduces the magnitude of the reference voltage when any of the following conditions is met: (a) the data portion D[a] of the sample of the first decoded signals is represented by a positive value, and the error portion E[a] of the sample of the first decoded signals is at a logical value of "0"; and (b) the data portion D[a] of the sample of the first decoded signals is represented by a negative value, and the error portion E[a] of the sample of the first decoded signals is at a logical value of "1".

Otherwise, the adaptive controller 17 keeps the magnitude of the reference voltage unchanged.

In this embodiment, as shown in Table 4, the adaptive controller 17 performs adaptive calibration on the phase interpolator 15 to adjust the phase shift of the interpolated clock signals with reference to the error portion E[a] and the data portion D[a] of the sample of the first decoded signals and the error portion (represented by E[a+1]) and the data portion (represented by D[a+1]) of another sample of the first decoded signals generated in the time interval after the sample of the first decoded signals is generated. Table 4 D[a] D[a+1] E[a] E[a+1] Phase Shift 11 00 1 1 delay 11 00 0 0 in advance 10 01 1 1 delay 10 01 0 0 in advance 01 10 1 1 in advance 01 10 0 0 delay 00 11 1 1 in advance 00 11 0 0 delay

When any of the following conditions is met, the adaptive controller 17 adjusts the phase shift of the interpolated clock signals to delay the phase of the interpolated clock signals: (a) the data portion D[a] of the sample of the first decoded signals is represented by a value of +L, the data portion D[a+1] of the other sample of the first decoded signals is represented by a value of -L, the error portion E[a] of the sample of the first decoded signals is at a logical value "1", and the other sample of the first decoded signals is The error part E[a+1] of the sample is at a logical value "1"; and (b) the data part D[a] of the sample of the first decoded signals is represented by a value of -L, the data part D[a+1] of the other sample of the first decoded signals is represented by a value of +L, the error part E[a] of the sample of the first decoded signals is at a logical value "0", and the error part E[a+1] of the other sample of the first decoded signals is at a logical value "0", where L is a positive odd number less than 2 ^M (for example, L=1 or L=3 in this embodiment).

When any of the following conditions is met, the adaptive controller 17 adjusts the phase shift of the interpolated clock signals to advance the phase of the interpolated clock signals: (a) the data portion D[a] of the sample of the first decoded signals is represented by a value of +L, the data portion D[a+1] of the other sample of the first decoded signals is represented by a value of -L, the error portion E[a] of the sample of the first decoded signals is at a logical value of "0", and the error portion E[a] of the sample of the first decoded signals is at a logical value of "0". The error portion E[a+1] of one sample is at a logical value "0"; and (b) the data portion D[a] of the sample of the first decoded signals is represented by a value of -L, the data portion D[a+1] of the other sample of the first decoded signals is represented by a value of +L, the error portion E[a] of the sample of the first decoded signals is at a logical value "1", and the error portion E[a+1] of the other sample of the first decoded signals is at a logical value "1".

Otherwise, the adaptive controller 17 keeps the phase shift of the interpolated clock signals unchanged.

In this embodiment, as shown in Table 5, the adaptive controller 17 performs adaptive calibration on the isochronous clock corrector 161 of the decoders 160 to adjust the error portion E[a] and the data portion D[a] of the sample of the first decoded signals, the error portion E[a+1] and the data portion D[a] of the other sample of the first decoded signals generated in the time interval after the sample of the first decoded signals is generated, and the adaptive controller 17 performs adaptive calibration on the isochronous clock corrector 161 of the decoders 160 to adjust the error portion E[a] and the data portion D[a] of the sample of the first decoded signals, and the error portion E[a+1] and the data portion D[a+1] of the other sample of the first decoded signals generated in the time interval after the sample of the first decoded signals is generated. a+1], the data portion D[a-1] of the sample of the first decoded signals and the second decoded signals generated in the time interval before the sample of the first decoded signals is generated, and the data portion D[a+2] of the sample of the first decoded signals and the second decoded signals generated in the time interval after the another sample of the first decoded signals is generated to adjust the delay of the calibration clock signals. Table 5 D[a-1] D[a] D[a+1] D[a+2] E[a] E[a+1] Time lag 11 11 00 00 1 0 Reduce 11 11 00 00 0 1 Increase 10 10 01 01 1 0 Reduce 10 10 01 01 0 1 Increase 01 01 10 10 1 0 Increase 01 01 10 10 0 1 Reduce 00 00 11 11 1 0 Increase 00 00 11 11 0 1 Reduce 00 11 11 00 1 1 Increase 00 11 11 00 0 0 Reduce 01 10 10 01 1 1 Increase 01 10 10 01 0 0 Reduce 10 01 01 10 1 1 Reduce 10 01 01 10 0 0 Increase 11 00 00 11 1 1 Reduce 11 00 00 11 0 0 Increase

When any of the following conditions is met, the adaptive controller 17 adjusts the delay of the correction clock signals to reduce the time lag between two correction clock signals generated by the decoder 160 that respectively generates the sample of the first decoded signals and the other sample: (a) the data portion D[a-1] of the sample of the first decoded signals and the second decoded signals is represented by a value of +L, the data portion D[a] of the sample of the first decoded signals is represented by a value of +L, the data portion D[a+1] of the other sample of the first decoded signals is represented by a value of -L, and the data portion D[a+2] of the other sample of the first decoded signals and the second decoded signals is represented by a value of -L. L is used to represent the error portion E[a] of the sample of the first decoded signals being at a logical value "1", and the error portion E[a+1] of the other sample of the first decoded signals being at a logical value "0"; and (b) the data portion D[a-1] of the sample of the first decoded signals and the second decoded signals being represented by a value of -L, the data portion (D[a]) of the sample of the first decoded signals being represented by a value of -L, the data portion D[a+1] of the other sample of the first decoded signals being represented by a value of +L, the data portion D[a+2] of the other sample of the first decoded signals and the second decoded signals being represented by a value of +L, and the error portion E[a] of the sample of the first decoded signals being at a logical value "1", and the error portion E[a+1] of the other sample of the first decoded signals being at a logical value "0"; [a] is at a logical value "0", and the error part E[a+1] of the other sample of the first decoded signals is at a logical value "1"; (c) the data part D[a-1] of the sample of the first decoded signals and the second decoded signals is represented by a value of -L, the data part D[a] of the sample of the first decoded signals is represented by a value of +L, the data part D[a+1] of the other sample of the first decoded signals is represented by a value of +L, the data part D[a+2] of the other sample of the first decoded signals and the second decoded signals is represented by a value of -L, the error part E[a] of the sample of the first decoded signals is at a logical value "0", and the other sample of the first decoded signals is The error portion E[a+1] of the sample is at a logical value "0"; and (d) the data portion D[a-1] of the sample of the first decoded signals and the second decoded signals is represented by a value of +L, the data portion D[a] of the sample of the first decoded signals is represented by a value of -L, the data portion D[a+1] of the other sample of the first decoded signals is represented by a value of -L, the data portion D[a+2] of the other sample of the first decoded signals and the second decoded signals is represented by a value of +L, the error portion E[a] of the sample of the first decoded signals is at a logical value "1", and the error portion E[a+1] of the other sample of the first decoded signals is at a logical value "1", where L is less than 2. ^M is a positive odd number (for example, L=1 or L=3 in this embodiment).

When any of the following conditions is met, the adaptive controller 17 adjusts the delay of the correction clock signals to increase the time lag: (a) the data portion D[a-1] of the sample of the first decoded signals and the second decoded signals is represented by a value of +L, the data portion D[a] of the sample of the first decoded signals is represented by a value of +L, the data portion D[a+1] of the other sample of the first decoded signals is represented by a value of -L, the data portion D[a+2] of the other sample of the first decoded signals and the second decoded signals is represented by a value of -L, the error portion E[a] of the sample of the first decoded signals is at a logical value of "0", and the first decoded signals are The error portion E[a+1] of the other sample of the first decoded signal is at a logical value "1"; (b) the data portion D[a-1] of the sample of the first decoded signal and the second decoded signal is represented by a value of -L, the data portion D[a] of the sample of the first decoded signal is represented by a value of -L, the data portion D[a+1] of the other sample of the first decoded signal is represented by a value of +L, the data portion D[a+2] of the other sample of the first decoded signal and the second decoded signal is represented by a value of +L, the error portion E[a] of the sample of the first decoded signal is at a logical value "1", and the data portion D[a-1] of the other sample of the first decoded signal is represented by a value of -L. The error part E[a+1] of the sample is at a logical value "0"; (c) the data part D[a-1] of the sample of the first decoded signals and the second decoded signals is represented by a value of -L, the data part D[a] of the sample of the first decoded signals is represented by a value of +L, the data part D[a+1] of the other sample of the first decoded signals is represented by a value of +L, the data part D[a+2] of the other sample of the first decoded signals and the second decoded signals is represented by a value of -L, the error part E[a] of the sample of the first decoded signals is at a logical value "1", the error part E[a+1] of the other sample of the first decoded signals is is at a logical value of "1"; and (d) the data portion D[a-1] of the sample of the first decoded signals and the second decoded signals is represented by a value of +L, the data portion D[a] of the sample of the first decoded signals is represented by a value of -L, the data portion D[a+1] of the other sample of the first decoded signals is represented by a value of -L, the data portion D[a+2] of the other sample of the first decoded signals and the second decoded signals is represented by a value of +L, the error portion E[a] of the sample of the first decoded signals is at a logical value of "0", and the error portion E[a+1] of the other sample of the first decoded signals is at a logical value of "0".

Otherwise, the adaptive controller 17 keeps the delays of the calibration clock signals unchanged.

In summary, the receiver of this embodiment has the following advantages.

First, the continuous time linear equalizer 116 is only used to compensate the high frequency components of the input data signal Din, so the receiver is suitable for operating in an environment where the input data signal Din is transmitted through a low loss channel. In addition, the ADCs 167 of the decoders 160 are all continuous approximation ADCs, and are operated in a time-interleaved manner due to the first demultiplexers 164 and the second demultiplexers 166 of the decoders 160. The above factors are conducive to reducing the power consumption of the decoder device 16.

Second, for each decoder 160, only one ADC 167 is an (M+1)-bit ADC (a 3-bit ADC in this embodiment), which extracts error terms of 2 ^M data values (for example, M=2, i.e., 4 data values in this embodiment) respectively corresponding to the data portion of the first decoded signals, for use in the adaptive calibration performed by the equalizer device 111 and the phase interpolator 15. This can help the clock data recovery circuit achieve an acceptable jitter tolerance, enhance the performance of the receiver, and reduce the power consumption of the receiver.

3. The voltage regulator 12 generates a reference voltage for use by all ADCs 167 of the decoders 160, which is beneficial to reducing the size and power consumption of the voltage regulator 12.

Fourth, by connecting the buffer 165 between the first demultiplexer 164 and the second demultiplexer 166 in each decoder 160, the channel compensator 11 has a light load capacitor at its output end, thereby having a wide bandwidth.

5. By performing adaptive calibration on the equalizer device 111, the voltage regulator 12, the phase interpolator 15, and the isochronous clock corrector 161 of the decoders 160 by the adaptive controller 17, the receiver can handle channel loss and process, voltage and temperature (PVT) variations, thereby operating more stably and achieving higher yield.

6. In the adaptive calibration performed on the quantizer devices 111, only the sign (positive or negative) of the data portion D[a-K] of the sample of the first decoded signals and the second decoded signals is considered, which can increase the effective pattern density.

7. In the adaptive calibration performed on the clock corrector 161 of the decoders 160, the data portion D[a-1] of the sample of the first decoded signals and the second decoded signals and the data portion D[a+2] of the other sample of the first decoded signals and the second decoded signals are taken into account, so that the influence of inter-symbol interference (ISI) can be eliminated to improve the accuracy of the adaptive calibration.

8. More transition modes are taken into account in the adaptive calibration performed on the phase interpolator 15, so that the loop bandwidth of the clock data recovery circuit can be increased and the clock jitter of the clock data recovery circuit can be reduced.

However, the above is only an example of the implementation of the present invention, and it should not be used to limit the scope of the implementation of the present invention. All simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the content of the patent specification are still within the scope of the patent of the present invention.

11: Channel Compensator

111: Equalizer device

112: Variable gain amplifier

116: Continuous Time Linear Equalizer

117: Low frequency equalizer

12: Voltage regulator

13: Polyphase Filter

14: CML to CMOS Converter

15: Phase Interpolator

16: Decoder device

160:Decoder

161:Clock Corrector

162: Ring counter

163:1/Q Crossover

164: First Demultiplexer

1641: Sampling switch

165: Buffer

166: Second Demultiplexer

1661: Sampling switch

167:Analog-to-digital converter

168: Phase calibration circuit

169:1 to Q demultiplexer

17: Adaptive Controller

Din: Input data signal

CKin: differential input clock signal pair

Dout: output data signal

Other features and functions of the present invention will be clearly presented in the following embodiments with reference to the drawings. It should be noted that various features may not be drawn to scale. FIG. 1 is a circuit block diagram illustrating a receiver according to an embodiment of the present invention; and FIG. 2 is a block diagram illustrating a channel compensator of the embodiment.

11: Channel compensator

12: Voltage regulator

13: Polyphase filter

14: CML to CMOS: Converter

15: Phase interpolator

16: Decoder device

160:Decoder

161: Clock Corrector

162: Ring counter

163:1/Q crossover

164: The first demultiplexer

1641: Sampling switch

165: Buffer

166: Second demultiplexer

1661: Sampling switch

167:Analog-to-digital converter

168: Phase calibration circuit

169:1 to Q demultiplexer

17: Adaptive controller

Din: Input data signal

CKin: differential input clock signal pair

Dout: output data signal

Claims (14)

A receiver includes: a channel compensator, receiving an input data signal, and performing channel compensation on the input data signal to generate a feed data signal, wherein the gain of the channel compensator is adjustable, and the input data signal is in a pulse amplitude modulation-2 ^M format, wherein M

2; a decoder connected to the channel compensator to receive the feed data signal, demultiplexing a data signal to be decoded from the feed data signal into a number P of demultiplexed data signals, and respectively decoding the demultiplexed data signals into a number P of decoded signals, wherein P

2, the decoded signals include a first decoded signal and (P-1) second decoded signals, each of the decoded signals includes a plurality of samples, the samples of the decoded signals are generated sequentially, each sample of the decoded signals includes a data portion, and each sample of at least one of the decoded signals further includes an error portion; the decoder includes a demultiplexer, receiving the data signal to be decoded, and demultiplexing the data signal to be decoded. The demultiplexer is configured to generate the demultiplexed data signals, and a number P of analog-to-digital converters, each of which is connected to the demultiplexer to receive a corresponding one of the demultiplexed data signals, one of the analog-to-digital converters is an (M+1)-bit analog-to-digital converter, and performs analog-to-digital conversion on the corresponding demultiplexed data signal to generate the first decoded signal, the first decoded signal including an M-bit wide data portion and a 1-bit wide error portion, Each of the other analog-to-digital converters is an M-bit analog-to-digital converter, and performs analog-to-digital conversion on the corresponding demultiplexed data signal to generate a corresponding second decoded signal including a data portion with a width of M bits; and an adaptive controller is connected to the decoder to receive a decoded output from the decoded signals, and is also connected to the channel compensator; the adaptive controller generates an output data signal based on the decoded output, and performs adaptive calibration on the channel compensator with reference to an error portion of a first sample of the decoded signals and a data portion of a second sample of the decoded signals generated before the first sample of the decoded signals is generated, so as to adjust the gain of the channel compensator. A receiver as described in claim 1, wherein: the samples of the decoded signals are generated sequentially at a rate defined by a time interval; and the second sample of the decoded signals is generated within a time interval of a number K before the first sample of the decoded signals is generated, wherein 1

K

3. A receiver as claimed in claim 1, wherein the adaptive controller increases the gain of the channel compensator when any of the following conditions is met: the data portion of the second sample of the decoded signals is represented by a positive value, and the error portion of the first sample of the decoded signals is at a logical value of "1"; and the data portion of the second sample of the decoded signals is represented by a negative value, and the error portion of the first sample of the decoded signals is at a logical value of "0". A receiver as claimed in claim 1, wherein the adaptive controller reduces the gain of the channel compensator when any of the following conditions is met: the data portion of the second sample of the decoded signals is represented by a positive value, and the error portion of the first sample of the decoded signals is at a logical value of "0"; and the data portion of the second sample of the decoded signals is represented by a negative value, and the error portion of the first sample of the decoded signals is at a logical value of "1". A receiver comprises: a voltage regulator, generating a reference voltage with an adjustable magnitude; a decoder, connected to the voltage regulator to receive the reference voltage, demultiplexing a data signal to be decoded into a number P of demultiplexed data signals, and decoding the demultiplexed data signals into a number P of decoded signals according to the reference voltage, wherein P

2. The signal to be decoded is in the pulse amplitude modulation-2 ^M format, where M

2, the decoded signals include a first decoded signal and a number (P-1) of second decoded signals, each of the decoded signals includes a plurality of samples, the samples of the decoded signals are generated sequentially, each sample of the decoded signals includes a data portion, and each sample of at least one of the decoded signals also includes an error portion; the decoder includes a demultiplexer that receives the data signal to be decoded and demultiplexes the data signal to be decoded into the demultiplexed data signals, and a number P of analog-to-digital converters, each of which is connected to the demultiplexer to receive a corresponding one of the demultiplexed data signals and is also connected to the voltage regulator to receive the reference voltage, one of the analog-to-digital converters is a (M+1)-bit analog-to-digital converter, and based on the The reference voltage performs analog-to-digital conversion on the corresponding demultiplexed data signal to generate the first decoded signal including an M-bit wide data portion and a 1-bit wide error portion, and each of the other analog-to-digital converters is an M-bit analog-to-digital converter, and performs analog-to-digital conversion on the corresponding demultiplexed data signal based on the reference voltage to generate a data portion including an M-bit wide data portion. A second decoded signal corresponding to a portion of the decoded signal; and an adaptive controller connected to the decoder to receive a decoded output derived from the decoded signals and connected to the voltage regulator; the adaptive controller generates an output data signal according to the decoded output, and performs adaptive calibration on the voltage regulator with reference to the error portion and the data portion of a sample of the decoded signals to adjust the size of the reference voltage. A receiver as described in claim 5, wherein the adaptive controller increases the magnitude of the reference voltage when any of the following conditions is met: the data portion of the sample of the decoded signals is represented by a positive value, and the error portion of the sample of the decoded signals is at a logical value of "1"; and the data portion of the sample of the decoded signals is represented by a negative value, and the error portion of the sample of the decoded signals is at a logical value of "0". A receiver as claimed in claim 5, wherein the adaptive controller reduces the magnitude of the reference voltage when any of the following conditions is met: the data portion of the sample of the decoded signals is represented by a positive value, and the error portion of the sample of the decoded signals is at a logical value of "0"; and the data portion of the sample of the decoded signals is represented by a negative value, and the error portion of the sample of the decoded signals is at a logical value of "1". A receiver includes: a phase interpolator receiving a clock input and performing phase interpolation on the clock input to generate N interpolated clock signals, wherein N

2 and a phase shift of each interpolated clock relative to the clock input is adjustable; a decoder device, including a number N of decoders; each decoder is connected to the phase interpolator to receive a corresponding one of the interpolated clock signals and delay the corresponding interpolated clock signal to generate a correction clock signal whose delay relative to the corresponding interpolated clock signal is adjustable; the decoders cooperate with each other to receive a feed data signal and demultiplex the feed data signal into a number N of first demultiplexed data signals respectively provided by the decoders according to the correction clock signals generated by the decoders, the feed data signal being a pulse amplitude modulation- ^2M format, wherein M

2; Each decoder buffers the first demultiplexed data signal provided by itself to generate a data signal to be decoded, demultiplexes the data signal to be decoded into a number P of second demultiplexed data signals, and decodes the second demultiplexed data signals into a number P of decoded signals, wherein P

2, the decoded signals include a first decoded signal and a number (P-1) of second decoded signals, each decoded signal includes a plurality of samples, the samples of the decoded signals are generated sequentially, each sample of the decoded signals includes a data portion, and each sample of at least one of the decoded signals also includes an error portion; each decoder includes a clock corrector, a first demultiplexer, a buffer, a second demultiplexer, and a number P of analog-to-digital converters; for each decoder, the clock corrector is connected to The phase interpolator receives the corresponding interpolated clock signal and delays the corresponding interpolated clock signal to generate the corrected clock signal, and the first demultiplexer is connected to the clock corrector to receive the corrected clock signal; the first demultiplexers of the decoders cooperate with each other to receive the feed data signal, and demultiplex the feed data signal into the first demultiplexed data signals outputted by the first demultiplexers respectively according to the corrected clock signals generated by the clock correctors of the decoders; for each decoder, The buffer is connected to the first demultiplexer to receive the first demultiplexed data signal output by the first demultiplexer and buffer the first demultiplexed data signal to generate the data signal to be decoded. The second demultiplexer is connected to the buffer to receive the data signal to be decoded and demultiplex the data signal to be decoded into the second demultiplexed data signals. Each analog-to-digital converter is connected to the second demultiplexer to receive a corresponding one of the second demultiplexed data signals. One of the analog-to-digital converters is an (M+1)-bit analog-to-digital converter and performs analog-to-digital conversion on the corresponding second demultiplexed data signal to generate a data portion including an M-bit width and a 1 The first decoded signal of the error portion of the bit width, and each of the other analog-to-digital converters is an M-bit analog-to-digital converter and performs analog-to-digital conversion on the corresponding second demultiplexed data signal to generate a corresponding second decoded signal including a data portion of the M-bit width; and an adaptive controller connected to the decoder device to receive the decoded output of the decoded signals generated by the decoders, and also connected to the phase interpolator; the adaptive controller generates an output data signal based on the decoded output, and performs adaptive calibration on the phase interpolator and the decoders to adjust the phase shift of the interpolated clock signals and the delay of the correction clock signals. A receiver as described in claim 8, wherein: the samples of the decoded signals are generated sequentially at a rate defined by a time interval; and the adaptive controller performs adaptive calibration on the phase interpolator to adjust the phase shift of the interpolated clock signals with reference to the error portion and data portion of a first sample of the decoded signals and the error portion and data portion of a second sample of the decoded signals generated in the time interval after the first sample of the decoded signals is generated. A receiver as described in claim 9, wherein the adaptive controller adjusts the phase shift of the interpolated clock signals to delay the phase of the interpolated clock signals when any of the following conditions is met: the data portion of the first sample of the decoded signals is represented by a value of +L, the data portion of the second sample of the decoded signals is represented by a value of -L, the error portion of the first sample of the decoded signals is at a logical value of "1", and the error portion of the second sample of the decoded signals is at a logical value of "1", where L is less than 2 ^M is a positive odd number; and the data portion of the first sample of the decoded signal is represented by a value of -L, the data portion of the second sample of the decoded signal is represented by a value of +L, the error portion of the first sample of the decoded signal is at a logical value "0", and the error portion of the second sample of the decoded signal is at a logical value "0". A receiver as described in claim 9, wherein the adaptive controller adjusts the phase shift of the interpolated clock signals to advance the phase of the interpolated clock signals when any of the following conditions is met: the data portion of the first sample of the decoded signals is represented by a value of +L, the data portion of the second sample of the decoded signals is represented by a value of -L, the error portion of the first sample of the decoded signals is at a logical value of "0", and the error portion of the second sample of the decoded signals is at a logical value of "0", where L is less than 2 ^M is a positive odd number; and the data portion of the first sample of the decoded signal is represented by a value of -L, the data portion of the second sample of the decoded signal is represented by a value of +L, the error portion of the first sample of the decoded signal is at a logical value "1", and the error portion of the second sample of the decoded signal is at a logical value "1". A receiver as claimed in claim 8, wherein: the samples of the decoded signals are sequentially generated at a speed defined by a time interval; and the adaptive controller performs adaptive calibration on the decoders to adjust the delay of the correction clock signals with reference to the error portion and data portion of a first sample of the decoded signals, the error portion and data portion of a second sample of the decoded signals generated in the time interval after the first sample of the decoded signals is generated, the data portion of a third sample of the decoded signals generated in the time interval before the first sample of the decoded signals is generated, and the data portion of a fourth sample of the decoded signals generated in the time interval after the second sample of the decoded signals is generated. A receiver as described in claim 12, wherein the adaptive controller adjusts the delay of the correction clock signals to reduce the time lag between two correction clock signals generated by two decoders that respectively generate the first sample and the second sample of the decoded signals when any of the following conditions is met: the data portion of the third sample of the decoded signals is represented by a value of +L, and the decoded signals The data portion of the first sample of the signal is represented by a value of +L, the data portion of the second sample of the decoded signal is represented by a value of -L, the data portion of the fourth sample of the decoded signal is represented by a value of -L, the error portion of the first sample of the decoded signal is at a logical value "1", and the error portion of the second sample of the decoded signal is at a logical value "0", where L is less than 2 ^M is a positive odd number; the data portion of the third sample of the decoded signal is represented by a value of -L, the data portion of the first sample of the decoded signal is represented by a value of -L, the data portion of the second sample of the decoded signal is represented by a value of +L, the data portion of the fourth sample of the decoded signal is represented by a value of +L, the error portion of the first sample of the decoded signal is at a logical value "0", and the error portion of the second sample of the decoded signal is at a logical value "1"; the data portion of the third sample of the decoded signal is represented by a value of -L, the data portion of the first sample of the decoded signal is represented by a value of +L, the data portion of the second sample of the decoded signal is at a value of +L. to indicate that the data portion of the fourth sample of the decoded signal is represented by a value of +L, the error portion of the first sample of the decoded signal is at a logical value of "0", and the error portion of the second sample of the decoded signal is at a logical value of "0"; and the data portion of the third sample of the decoded signal is represented by a value of +L, the data portion of the first sample of the decoded signal is represented by a value of -L, the data portion of the second sample of the decoded signal is represented by a value of -L, the data portion of the fourth sample of the decoded signal is represented by a value of +L, the error portion of the first sample of the decoded signal is at a logical value of "1", and the error portion of the second sample of the decoded signal is at a logical value of "1". A receiver as described in claim 12, wherein the adaptive controller adjusts the delay of the correction clock signals to increase the time lag between two correction clock signals generated by two decoders that respectively generate the first sample and the second sample of the decoded signals when any of the following conditions is met: the data portion of the third sample of the decoded signals is represented by a value of +L, and the decoded signals are The data portion of the first sample of the signal is represented by a value of +L, the data portion of the second sample of the decoded signal is represented by a value of -L, the data portion of the fourth sample of the decoded signal is represented by a value of -L, the error portion of the first sample of the decoded signal is at a logical value "0", and the error portion of the second sample of the decoded signal is at a logical value "1", where L is less than 2 ^M is a positive odd number; the data portion of the third sample of the decoded signal is represented by a value of -L, the data portion of the first sample of the decoded signal is represented by a value of -L, the data portion of the second sample of the decoded signal is represented by a value of +L, the data portion of the fourth sample of the decoded signal is represented by a value of +L, the error portion of the first sample of the decoded signal is at a logical value "1", and the error portion of the second sample of the decoded signal is at a logical value "0"; the data portion of the third sample of the decoded signal is represented by a value of -L, the data portion of the first sample of the decoded signal is represented by a value of +L, the data portion of the second sample of the decoded signal is represented by a value of +L Indicates that the data portion of the fourth sample of the decoded signal is represented by a value of -L, the error portion of the first sample of the decoded signal is at a logical value "1", and the error portion of the second sample of the decoded signal is at a logical value "1"; and the data portion of the third sample of the decoded signal is represented by a value of +L, the data portion of the first sample of the decoded signal is represented by a value of -L, the data portion of the second sample of the decoded signal is represented by a value of -L, the data portion of the fourth sample of the decoded signal is represented by a value of +L, the error portion of the first sample of the decoded signal is at a logical value "0", and the error portion of the second sample of the decoded signal is at a logical value "0".

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