TWI863365B - Switching circuit for parallel chip testing and chip testing system including the same - Google Patents

Abstract

The present invention mainly discloses a switch circuit, which is used in conjunction with a test fixture (such as a probe card) of a chip test system, so that the chip test system can perform a parallel test (multi-site test) of the output voltage of the electronic chip with multiple output channels through the switch circuit and the test fixture. The switch circuit of the present invention includes: a first switch unit including two switches, a second switch unit including two switches, a first switch module including two medium voltage switches and two inverters, and a second switch module including two medium voltage switches and two inverters.

Description

Switching circuit for parallel chip testing and chip testing system including the same

The present invention relates to the technical field of chip testing, and in particular to a switching circuit that is used in conjunction with a test fixture (such as a probe card) of a chip testing system, so that the chip testing system can perform a parallel test (Multi-site test) of the output voltage of a multi-channel display driver chip through the switching circuit.

FIG1 is a block diagram of a known flat display device. As shown in FIG1 , the known flat display device 1a mainly includes: a display panel 11a, a display controller (Tcon) 120a, a gate driver unit 121a, and a source driver unit 122a. At one application end, the source driver unit 122a exists in the form of a source driver chip. And, at another application end, the display controller 120a, the gate driver unit 121a, and the source driver unit 122a are integrated into a single display driver chip (DDIC).

FIG2 is a circuit block diagram of the source driver unit shown in FIG1. As shown in FIG2, the conventional source driver unit 122a includes: a shift register 1221a, a data register 1222a, a data latch 1223a, a level shifter 1224a, a plurality of digital-to-analog converters (DACs) 1225a, and a plurality of buffer amplifiers 1226a. It should be known that the manufacturing process of integrated circuit chips (or electronic chips) includes: circuit design, CAD drawing, mask production, wafer manufacturing, CP testing, wafer cutting, chip packaging, and chip testing, wherein CP is the abbreviation of chip probe, which specifically refers to the use of a probe card to contact the chip on the wafer to perform a functional test on the chip. However, with the improvement of the resolution of the flat display device 1a, the total number of output channels CH1~CHn of the source drive unit 122a also increases, resulting in an increase in the test time and cost of the CP test. Therefore, when performing CP testing on source driver chips or display driver chips, multiple output channels will be connected to multiple switch units, so that the chip test system can perform parallel output voltage testing (Multi-site test) on multi-channel source driver chips or display driver chips through the multiple switch units, thereby saving test time and reducing costs.

FIG3 is a circuit topology diagram of the four buffer amplifiers shown in FIG2. As shown in FIG3, if the display panel 11a is an LCD panel, a polarity switching circuit 1227a is further provided between the odd output channel and the even output channel. Moreover, when performing CP testing, the parallel test (Multi-site) can be designed as four-point parallel (4 sites), eight-point parallel (8 sites), or sixteen-point parallel (16 sites). A switch unit 2a including two switches shown in FIG3 is coupled between the output channels CH1 and CH2, so that the source drive unit 122a can realize four-point parallel testing when performing CP testing.

It should be known that the buffer amplifier 1226a is composed of a plurality of medium voltage (e.g. 6V) MOSFET components to achieve high voltage (e.g. 12V) output. However, the conventional technology does not use medium and high voltage MOSFET components as the two switches included in the switch unit 2a, which leads to cross-voltage problems when performing output voltage testing, thereby affecting the accuracy of the CP test.

From the above description, it can be seen that the field urgently needs a new switching circuit for parallel chip testing.

The main purpose of the present invention is to provide a switch circuit, which is used in conjunction with a test fixture (such as a probe card) of a chip test system, so that the chip test system can perform parallel output voltage testing (Multi-site test) on the electronic chip with multiple output channels through the switch circuit and the test fixture. The switch circuit of the present invention includes: a first switch unit including two switches, a second switch unit including two switches, a first switch module including two medium voltage switches and two inverters, and a second switch module including two medium voltage switches and two inverters.

When performing CP testing, the chip testing system can perform positive and negative output tests on the same output channel through the switch circuit of the present invention, and will not cause damage to MOSFET components when measuring outputs of different polarities.

To achieve the above-mentioned purpose, the present invention proposes an embodiment of the switch circuit, which is used to electrically connect an electronic chip with multiple output channels, and includes: a first switch unit, coupled between the P+1th output channel and the P+3th output channel, wherein P is 0 or 4Q, and Q is a positive integer; a second switch unit, coupled between the P+2th output channel and the P+4th output channel; A switch module, coupled between the P+1th output channel and the P+2th output channel, coupled to the second switch unit, and coupled to the first switch unit on the P+1th output channel; and a second switch module, coupled between the P+3th output channel and the P+4th output channel, coupled to the second switch unit, and coupled to the first switch unit on the P+3th output channel.

In one embodiment, the first switch module and the second switch module are biased by a first operating voltage, a second operating voltage, and a third operating voltage, and are controlled by a first polarity switching signal, a second polarity switching signal, a first operating voltage, a second operating voltage, a third operating voltage, a first substrate bias voltage, a second substrate bias voltage, a third substrate bias voltage, and a fourth substrate bias voltage.

In one embodiment, the first switch is controlled by a first enable signal and a second enable signal, and the second switch is controlled by a third enable signal and a fourth enable signal.

In one embodiment, among the plurality of output channels of the electronic chip, a polarity switching circuit is provided between the odd-numbered output channels and the even-numbered output channels, so that the first switch unit is coupled to the polarity switching circuit on the P+1th output channel, the first switch module is coupled to the polarity switching circuit, and the second switch unit is coupled to the polarity switching circuit.

In one embodiment, among the plurality of output channels of the electronic chip, a polarity switching circuit is provided between the odd-numbered output channels and the even-numbered output channels, so that the first switch unit is coupled to the polarity switching circuit on the P+3th output channel, the second switch module is coupled to the polarity switching circuit, and the second switch unit is coupled to the polarity switching circuit.

In one embodiment, the first switch unit includes: a first switch having a first control terminal, a second control terminal, a first electrical terminal, and a second electrical terminal, wherein the first control terminal is coupled to a first enable signal, the second control terminal is coupled to a second enable signal, and the first electrical terminal is coupled to the P+1th output channel; and a second switch, also having a first control terminal, a second control terminal, a first electrical terminal, and a second electrical terminal, wherein the first control terminal is coupled to the first enable signal, the second control terminal is coupled to the second enable signal, the first electrical terminal is coupled to the P+3th output channel, and the second electrical terminal is coupled to the second electrical terminal of the first switch.

In one embodiment, the second switch unit includes: a third switch having a first control terminal, a second control terminal, a first electrical terminal, and a second electrical terminal, wherein the first control terminal is coupled to a third enable signal, the second control terminal is coupled to a fourth enable signal, and the first electrical terminal is coupled to the first switch module; and a fourth switch, also having a first control terminal, a second control terminal, a first electrical terminal, and a second electrical terminal, wherein the first control terminal is coupled to the third enable signal, the second control terminal is coupled to the fourth enable signal, the first electrical terminal is coupled to the second switch module, and the second electrical terminal is coupled to the second electrical terminal of the third switch.

In one embodiment, the first switch module includes: a fifth switch having a first control terminal, a second control terminal, a first electrical terminal, a second electrical terminal, a first base terminal, and a second base terminal, wherein the first control terminal is coupled to a first polarity switching signal, the second control terminal is coupled to a first working voltage, and the first electrical terminal is coupled to the first electrical terminal of the first switch on the P+1th output channel; and a sixth switch having a first control terminal, a second control terminal, a first electrical terminal, a second electrical terminal, a first base terminal, and a second base terminal, wherein the first control terminal is coupled to a second polarity switching signal , the second control end is coupled to a first working voltage, the first electrical end is coupled to the polarity switching circuit, and the second electrical end is coupled to the P+2th output channel; a first inverter is biased by a second working voltage and the first working voltage, its input end is coupled to a first substrate bias voltage, and its output end is simultaneously coupled to the second substrate end of the fifth switch and the second substrate end of the seventh switch; and a second inverter is biased by the first working voltage and a third working voltage, its input end is coupled to a second substrate bias voltage, and its output end is simultaneously coupled to the first substrate end of the fifth switch and the first substrate end of the seventh switch.

In one embodiment, the second switch module includes: a seventh switch, having a first control terminal, a second control terminal, a first electrical terminal, a second electrical terminal, a first base terminal, and a second base terminal, wherein the first control terminal is coupled to the first working voltage, the second control terminal is coupled to the first polarity switching signal, the first electrical terminal is coupled to the first electrical terminal of the third switch, the second electrical terminal is coupled to the P+1th output channel, the first base terminal is coupled to the first base terminal of the fifth switch, and the second base terminal is coupled to the second base terminal of the fifth switch; an eighth switch, having a first control terminal, a second control terminal, a first electrical terminal, a second electrical terminal, a first base terminal, and a second base terminal, wherein the first control terminal is coupled to the first working voltage, the second control terminal is coupled to the first polarity switching signal, the first electrical terminal is coupled to the first electrical terminal of the third switch, the second electrical terminal is coupled to the P+1th output channel, the first base terminal is coupled to the first base terminal of the fifth switch, and the second base terminal is coupled to the second base terminal of the fifth switch. voltage, the second control end is coupled to the second polarity switching signal, the first electrical end is coupled to the polarity switching circuit, the second electrical end is coupled to the P+2th output channel, the first substrate end is coupled to the first substrate end of the sixth switch, and the second substrate end is coupled to the second substrate end of the sixth switch; a third inverter is biased by the second working voltage and the first working voltage, its input end is coupled to a third substrate bias voltage, and its output end is simultaneously coupled to the second substrate end of the sixth switch and the second substrate end of the eighth switch; and a fourth inverter is biased by the first working voltage and the third working voltage, its input end is coupled to a fourth substrate bias voltage, and its output end is simultaneously coupled to the first substrate end of the sixth switch and the first substrate end of the eighth switch.

On the other hand, the present invention also provides a chip testing system, which includes a test fixture for multi-point connection of an electronic chip and a control unit; the feature is that the test fixture and the switch circuit of the present invention as described above are used in conjunction with each other, so that the control unit can perform parallel output voltage testing (Multi-site test) on the electronic chip with multiple output channels through the test fixture and the switch circuit.

1a: Flat panel display

11a: Display panel

120a: Display controller

121a: Gate drive unit

122a: Source drive unit

1221a: Shift register

1222a: Data register

1223a: Data lock register

1224a:Level shifter

1225a: Digital to Analog Converter

1226a: Buffer amplifier

1227a: Polarity switching circuit

2a: Switch unit

1: Chip testing system

10: Control unit

11: Test fixture

1226: Buffer amplifier

1227: Polarity switching circuit

2: Electronic chips

3: Switching circuit

31: First switch unit

32: Second switch unit

33: First switch module

34: Second switch module

S1: First switch

S2: Second switch

S3: The third switch

S4: The fourth switch

S5: The fifth switch

S6: The sixth switch

S7: The seventh switch

S8: The eighth switch

IV1: First inverter

IV2: Second inverter

IV3: The third inverter

IV4: The fourth inverter

S1a: First switch group

S2a: Second switch group

S3a: The third switch group

S4a: The fourth switch group

FIG. 1 is a block diagram of a known flat display device; FIG. 2 is a circuit block diagram of the source drive unit shown in FIG. 1; FIG. 3 is a circuit topology diagram of the four buffer amplifiers shown in FIG. 2; FIG. 4 is a block diagram of a chip test system including a switching circuit of the present invention; FIG. 5 is a schematic diagram of a switching circuit of the present invention; FIG. 6A and FIG. 6B are circuit topology diagrams of the switching circuit of the present invention; and FIG. 7 is a timing diagram of multiple control signals used to control the operation of the switching circuit of the present invention.

In order to enable the review committee to further understand the structure, features, purpose, and advantages of the present invention, the detailed description of the drawings and preferred specific embodiments is attached as follows.

FIG4 is a block diagram of a chip test system including a switch circuit of the present invention. As shown in FIG4, the chip test system 1 mainly includes: a control unit 10 and a test fixture (such as a probe card) 11 for multi-point connection of an electronic chip 2. The present invention mainly discloses a switch circuit 3, which is used in conjunction with the test fixture 11 (such as a probe card), so that the chip test system 1 can perform parallel output voltage testing (Multi-site test) on the electronic chip 2 with multiple output channels through the switch circuit 2 and the test fixture 11.

FIG5 is a schematic diagram of a switch circuit of the present invention, and FIG6A and FIG6B are circuit topology diagrams of the switch circuit of the present invention. It is worth noting that, according to the design of the present invention, the switch circuit 3 is used to electrically connect between the four output channels of the electronic chip 2. For example, if the electronic chip 2 has four output channels, one switch circuit 3 can be used to electrically connect between the four output channels. For another example, if the electronic chip 2 has eight output channels, one switch circuit 3 can be used to electrically connect between the four output channels in the first order, and another switch circuit 3 can be used to electrically connect between the four output channels in the last order. To explain in more detail, as shown in FIG. 5 , FIG. 6A and FIG. 6B , the switch circuit includes: a first switch unit 31 including a first switch S1 and a second switch S2, a second switch unit 31 including a third switch S3 and a fourth switch S4, a first switch module 33 including two medium voltage switches and two inverters, and a second switch module 34 including two medium voltage switches and two inverters.

According to the design of the present invention, the first switch unit 31 is coupled between the P+1th output channel and the P+3th output channel, and is controlled by a first enable signal EN_P and a second enable signal ENB_P; wherein P is 0 or 4Q, and Q is a positive integer. In contrast, the second switch unit 32 is coupled between the P+2th output channel and the P+4th output channel, and the second switch 32 is controlled by a third enable signal EN_N and a fourth enable signal ENB_N.

On the other hand, the first switch module 33 is coupled between the P+1th output channel and the P+2th output channel, coupled to the second switch unit 32, and coupled to the first switch unit 31 on the P+1th output channel. In addition, the second switch module 34 is coupled between the P+3th output channel and the P+4th output channel, coupled to the second switch unit 32, and coupled to the first switch unit 31 on the P+3th output channel. As shown in FIG. 5, FIG. 6A and FIG. 6B, the first switch module 33 and the second switch module 34 are biased by a first working voltage V5, a second working voltage V10 and a third working voltage V0, and are controlled by a first polarity switching signal HPOLB, a second polarity switching signal HPOL, a first substrate bias voltage HBULK_P, a second substrate bias voltage HBULK_N, a third substrate bias voltage HBULKB_P, and a fourth substrate bias voltage HBULKB_N.

It is additionally explained that if the electronic chip 2 is a display driver chip (DDIC) or a source driver chip for driving an LCD panel to display images, a polarity switching circuit 1227 is provided between the odd-numbered output channels and the even-numbered output channels among the N output channels of the electronic chip 2 (N=4Q). In this case, as shown in FIG. 5 , FIG. 6A and FIG. 6B , the first switch unit 31 is coupled to the polarity switching circuit 1227 on the P+1th output channel, and the first switch module 33 is coupled to the polarity switching circuit 1227 through the polarity switching circuit 1227. Furthermore, the first switch unit 31 is coupled to the polarity switching circuit 1227 on the P+3th output channel, and the second switch module 34 is coupled to the second switch unit 32 via the polarity switching circuit 1227.

Specifically, the first switch unit 31 includes: a first switch S1 and a second switch S2. As shown in FIG5, FIG6A and FIG6B, in an exemplary embodiment, the first switch S1 is a CMOS switch composed of an N-type MOSFET element and a P-type MOSFET element, and has a first control terminal, a second control terminal, a first electrical terminal, and a second electrical terminal, wherein the first control terminal is coupled to the first enable signal EN_P, the second control terminal is coupled to the second enable signal ENB_P, and the first electrical terminal is coupled to the P+1th output channel. Furthermore, the second switch S2 is also a CMOS switch composed of an N-type MOSFET element and a P-type MOSFET element, and has a first control terminal, a second control terminal, a first electrical terminal, and a second electrical terminal, wherein the first control terminal is coupled to the first enable signal EN_P, the second control terminal is coupled to the second enable signal ENB_P, the first electrical terminal is coupled to the P+3th output channel, and the second electrical terminal and the second electrical terminal of the first switch S1 are coupled to a contact (CHS8S_P).

As shown in FIG5, FIG6A and FIG6B, the second switch unit 32 includes: a third switch S3 and a fourth switch S4. In an exemplary embodiment, the third switch S3 is a CMOS switch composed of an N-type MOSFET element and a P-type MOSFET element, and has a first control terminal, a second control terminal, a first electrical terminal, and a second electrical terminal, wherein the first control terminal is coupled to a third enable signal EN_N, the second control terminal is coupled to a fourth enable signal ENB_N, and the first electrical terminal is coupled to the first switch module 33. Furthermore, the fourth switch S4 is also a CMOS switch composed of an N-type MOSFET element and a P-type MOSFET element, and has a first control terminal, a second control terminal, a first electrical terminal, and a second electrical terminal, wherein the first control terminal is coupled to the third enable signal EN_N, the second control terminal is coupled to the fourth enable signal ENB_N, the first electrical terminal is coupled to the second switch module 34, and the second electrical terminal and the second electrical terminal of the third switch S3 are coupled to a contact (CHS8S_N).

In more detail, the first switch module 33 includes: a fifth switch S5, a sixth switch S6, a first inverter IV1, and a second inverter IV2. As shown in FIG5, FIG6A and FIG6B, in particular, the fifth switch S5 is a CMOS switch composed of a medium voltage N-type MOSFET element and a medium voltage P-type MOSFET element, and has a first control terminal, a second control terminal, a first electrical terminal, a second electrical terminal, a first base terminal, and a second base terminal, wherein the first control terminal is coupled to the first polarity switching signal HPOLB, the second control terminal is coupled to the first working voltage V5, and the first electrical terminal is coupled to the first electrical terminal of the first switch S1 on the P+1th output channel. Furthermore, the sixth switch S6 is also a CMOS switch composed of a medium voltage N-type MOSFET element and a medium voltage P-type MOSFET element, and has a first control end, a second control end, a first electrical end, a second electrical end, a first base end, and a second base end, wherein the first control end is coupled to a second polarity switching signal HPOL, the second control end is coupled to a first working voltage V5, the first electrical end is coupled to the polarity switching circuit 1227, and the second electrical end is coupled to the P+2th output channel.

According to the above description, the first inverter IV1 is composed of an N-type MOSFET element and a P-type MOSFET element, and is biased by the second working voltage V10 and the first working voltage V5. As shown in Figures 6A and 6B, the input end of the first inverter IV1 is coupled to the first base bias voltage HBULK_P, and its output end is simultaneously coupled to the second base end of the fifth switch S5 and the second base end of the seventh switch S7. In addition, the second inverter IV2 is also composed of an N-type MOSFET element and a P-type MOSFET element, and is biased by the first working voltage V5 and the third working voltage V0, its input end is coupled to the second base bias voltage HBULK_N, and its output end is simultaneously coupled to the first base end of the fifth switch S5 and the first base end of the seventh switch S7.

In addition, the second switch module 33 includes: a seventh switch S7, an eighth switch S8, a third inverter IV3, and a fourth inverter IV4. As shown in FIG5, FIG6A and FIG6B, in particular, the seventh switch S7 is a CMOS switch composed of a medium voltage N-type MOSFET element and a medium voltage P-type MOSFET element, and has a first control terminal, a second control terminal, a first electrical terminal, a second electrical terminal, a first base terminal, and a second base terminal, wherein the first control terminal is coupled to the first working voltage V5, the second control terminal is coupled to the first polarity switching signal HPOLB, the first electrical terminal is coupled to the first electrical terminal of the third switch S3, the second electrical terminal is coupled to the P+1th output channel, the first base terminal is coupled to the first base terminal of the fifth switch S5, and the second base terminal is coupled to the second base terminal of the fifth switch S5. Moreover, the eighth switch S8 is also a CMOS switch composed of a medium voltage N-type MOSFET element and a medium voltage P-type MOSFET element, and has a first control end, a second control end, a first electrical end, a second electrical end, a first base end, and a second base end, wherein the first control end is coupled to the first working voltage V5, the second control end is coupled to the second polarity switching signal HPOL, the first electrical end is coupled to the polarity switching circuit 1227, the second electrical end is coupled to the P+2th output channel, the first base end is coupled to the first base end of the sixth switch S6, and the second base end is coupled to the second base end of the sixth switch S6.

According to the above description, the third inverter IV3 is composed of an N-type MOSFET element and a P-type MOSFET element, and is biased by the second working voltage V10 and the first working voltage V5. As shown in Figures 6A and 6B, the input end of the third inverter IV3 is coupled to a third base bias voltage HBULKB_P, and its output end is simultaneously coupled to the second base end of the sixth switch S6 and the second base end of the eighth switch S8. In addition, the fourth inverter IV4 is also composed of an N-type MOSFET element and a P-type MOSFET element, and is biased by the first working voltage V5 and the third working voltage V0, its input end is coupled to a fourth base bias voltage HBULKB_N, and its output end is simultaneously coupled to the first base end of the sixth switch S6 and the first base end of the eighth switch S8.

FIG7 is a timing diagram of a plurality of control signals for controlling the operation of the switch circuit of the present invention. As shown in FIG6A, FIG6B and FIG7, according to the design of the present invention, the voltage levels of the first polarity switching signal HPOLB in the time intervals T0, T1, T2, T3, and T4 are 10V, 5V, 0V, 5V, and 10V, respectively, and the voltage levels of the second polarity switching signal HPOL in the time intervals T0, T1, T2, T3, and T4 are 0V, 5V, 10V, 5V, and 0V, respectively. In other words, the first polarity switching signal HPOLB is the inverted signal of the second polarity switching signal HPOL. Moreover, as shown in Figures 6A, 6B and 7, the voltage levels of the first substrate bias voltage HBULK_P in the time intervals T0, T1, T2, T3, and T4 are 5V, 5V, 10V, 5V, and 5V, respectively, and the voltage levels of the second substrate bias voltage HBULK_N in the time intervals T0, T1, T2, T3, and T4 are 0V, 5V, 5V, 5V, and 0V, respectively. In addition, the voltage levels of the third base bias voltage HBULKB_P in the time intervals T0, T1, T2, T3, and T4 are 10V, 5V, 5V, 5V, and 10V, respectively, and the voltage levels of the fourth base bias voltage HBULKB_N in the time intervals T0, T1, T2, T3, and T4 are 5V, 5V, 0V, 5V, and 5V, respectively.

It is additionally explained that, as shown in FIG. 5, FIG. 6A and FIG. B, the output ends of the four buffer amplifiers 1226 of the electronic chip 2 are connected to two polarity switching circuits 1227, and each of the polarity switching circuits 1227 includes: a first switch group S1a, a second switch group S2a, a third switch group S3a and a fourth switch group S4a. The first polarity switching circuit 1227 is controlled by a first control signal SWA1_P, a second control signal SWB1_P, a third control signal SWB1_N, and a fourth control signal SWA1_N, and the second polarity switching circuit 1227 is controlled by a fifth control signal SWA2_P, a sixth control signal SWB2_P, a seventh control signal SWB2_N, and an eighth control signal SWA2_N.

When testing the output voltage of the P+1th output channel (e.g., CH1) of the electronic chip 2, the first switch unit 31, the second switch unit 32, the first switch module 33, and the second switch module 34 are turned on. At the same time, only the first switch group S1a (controlled SWA1_P) and the fourth switch group S4a (controlled SWA1_N) of the first polarity switching circuit 1227 are turned on, thereby preventing the buffer amplifier 1226 on the output channel CH1 from generating a large current due to a short circuit.

Furthermore, when testing the output voltage of the P+2 output channel (e.g., CH2) of the electronic chip 2, the first switch unit 31, the second switch unit 32, the first switch module 33, and the second switch module 34 are turned on. At the same time, only the second switch group S2a (controlled SWB1_P) and the third switch group S3a (controlled SWB1_N) of the first polarity switching circuit 1227 are turned on, thereby preventing the buffer amplifier 1226 on the output channel CH2 from generating a large current due to a short circuit.

Furthermore, when testing the output voltage of the P+3 output channel (e.g., CH3) of the electronic chip 2, the first switch unit 31, the second switch unit 32, the first switch module 33, and the second switch module 34 are turned on. At the same time, only the first switch group S1a (controlled SWA2_P) and the fourth switch group S4a (controlled SWA2_N) of the second polarity switching circuit 1227 are turned on, thereby preventing the buffer amplifier 1226 on the output channel CH3 from generating a large current due to a short circuit.

Furthermore, when testing the output voltage of the P+4th output channel (e.g., CH4) of the electronic chip 2, the first switch unit 31, the second switch unit 32, the first switch module 33, and the second switch module 34 are turned on. At the same time, only the second switch group S2a (controlled SWB2_P) and the third switch group S3a (controlled SWB2_N) of the second polarity switching circuit 1227 are turned on, thereby preventing the buffer amplifier 1226 on the output channel CH4 from generating a large current due to a short circuit.

Thus, the above has completely and clearly described a new type of switch circuit used in parallel chip testing of the present invention; and, from the above, it can be known that the present invention has the following advantages:

(1) The present invention discloses a switch circuit, which is used in conjunction with a test fixture (such as a probe card) of a chip test system, so that the chip test system can perform a parallel test (multi-site test) of the output voltage of the electronic chip with multiple output channels through the switch circuit and the test fixture. The switch circuit of the present invention includes: a first switch unit including two switches, a second switch unit including two switches, a first switch module including two medium voltage switches and two inverters, and a second switch module including two medium voltage switches and two inverters.

(2) When performing CP testing, the chip testing system can perform positive and negative output tests on the same output channel through the switch circuit of the present invention, and will not cause damage to MOSFET components when measuring outputs of different polarities.

(3) The present invention also provides a chip testing system, which includes a test fixture for multi-point connection of an electronic chip and a control unit; the feature is that the test fixture and the switch circuit of the present invention as described above are used in conjunction with each other, so that the control unit can perform parallel output voltage testing (Multi-site test) on the electronic chip with multiple output channels through the test fixture and the switch circuit.

It must be emphasized that the above-mentioned case is a preferred embodiment. Any partial changes or modifications that are derived from the technical ideas of this case and are easily inferred by people familiar with the art do not deviate from the scope of the patent rights of this case.

In summary, this case shows that it is very different from the known technology in terms of purpose, means and effect, and it is the first invention that is practical and indeed meets the patent requirements for invention. We sincerely ask the review committee to examine it carefully and grant a patent as soon as possible to benefit the society. This is our utmost prayer.

1226: Buffer amplifier

1227: Polarity switching circuit

3: Switching circuit

31: First switch unit

32: Second switch unit

33: First switch module

34: Second switch module

S1: First switch

S2: Second switch

S3: The third switch

S4: The fourth switch

S1a: First switch group

S2a: Second switch group

S3a: The third switch group

S4a: The fourth switch group

Claims (10)

A switch circuit is used to electrically connect an electronic chip with multiple output channels, and includes: a first switch unit, coupled between the P+1th output channel and the P+3th output channel, wherein P is 0 or 4Q, and Q is a positive integer; a second switch unit, coupled between the P+2th output channel and the P+4th output channel; a first switch module, coupled between the P+1th output channel and the P+2th output channel, coupled to the second switch unit, and coupled to the first switch unit on the P+1th output channel; and a second switch module, coupled between the P+3th output channel and the P+4th output channel, coupled to the second switch unit, and coupled to the first switch unit on the P+3th output channel. A switch circuit as described in claim 1, wherein the first switch module and the second switch module are biased by a first operating voltage, a second operating voltage, and a third operating voltage, and are controlled by a first polarity switching signal, a second polarity switching signal, a first substrate bias voltage, a second substrate bias voltage, a third substrate bias voltage, and a fourth substrate bias voltage. A switch circuit as described in claim 1, wherein the first switch unit is controlled by a first enable signal and a second enable signal, and the second switch unit is controlled by a third enable signal and a fourth enable signal. The switch circuit as described in claim 1, wherein, among the plurality of output channels of the electronic chip, a polarity switching circuit is provided between the odd-numbered output channels and the even-numbered output channels, so that the first switch unit is coupled to the polarity switching circuit on the P+1th output channel, the first switch module is coupled to the polarity switching circuit, and the second switch unit is coupled to the polarity switching circuit. The switch circuit as described in claim 4, wherein, among the plurality of output channels of the electronic chip, a polarity switching circuit is provided between the odd-numbered output channels and the even-numbered output channels, so that the first switch unit is coupled to the polarity switching circuit on the P+3th output channel, the second switch module is coupled to the polarity switching circuit, and the second switch unit is coupled to the polarity switching circuit. A switch circuit as described in claim 5, wherein the first switch unit comprises: a first switch having a first control terminal, a second control terminal, a first electrical terminal, and a second electrical terminal, wherein the first control terminal is coupled to a first enable signal, the second control terminal is coupled to a second enable signal, and the first electrical terminal is coupled to the P+1th output channel; and a second switch, also having a first control terminal, a second control terminal, a first electrical terminal, and a second electrical terminal, wherein the first control terminal is coupled to the first enable signal, the second control terminal is coupled to the second enable signal, the first electrical terminal is coupled to the P+3th output channel, and the second electrical terminal is coupled to the second electrical terminal of the first switch. A switch circuit as described in claim 6, wherein the second switch unit comprises: a third switch having a first control terminal, a second control terminal, a first electrical terminal, and a second electrical terminal, wherein the first control terminal is coupled to a third enable signal, the second control terminal is coupled to a fourth enable signal, and the first electrical terminal is coupled to the first switch module; and a fourth switch, also having a first control terminal, a second control terminal, a first electrical terminal, and a second electrical terminal, wherein the first control terminal is coupled to the third enable signal, the second control terminal is coupled to the fourth enable signal, the first electrical terminal is coupled to the second switch module, and the second electrical terminal is coupled to the second electrical terminal of the third switch. A switch circuit as described in claim 7, wherein the first switch module includes: a fifth switch having a first control end, a second control end, a first electrical end, a second electrical end, a first substrate end, and a second substrate end, wherein the first control end is coupled to a first polarity switching signal, the second control end is coupled to a first operating voltage, and the first electrical end is coupled to the first electrical end of the first switch on the P+1th output channel; a sixth switch having a first control end, a second control end, a first electrical end, a second electrical end, a first substrate end, and a second substrate end, wherein the first control end is coupled to a first polarity switching signal, the second control end is coupled to a first operating voltage, and the first electrical end is coupled to the first electrical end of the first switch on the P+1th output channel. A control terminal coupled to a second polarity switching signal, the second control terminal coupled to a first operating voltage, the first electrical terminal coupled to the polarity switching circuit, and the second electrical terminal coupled to the P+2th output channel; A first inverter biased by a second operating voltage and the first operating voltage, its input terminal coupled to a first substrate bias voltage, and its output terminal simultaneously coupled to the second substrate terminal of the fifth switch; and a second inverter biased by the first operating voltage and a third operating voltage, its input terminal coupled to a second substrate bias voltage, and its output terminal simultaneously coupled to the first substrate terminal of the fifth switch. A switch circuit as described in claim 8, wherein the second switch module includes: a seventh switch having a first control end, a second control end, a first electrical end, a second electrical end, a first substrate end, and a second substrate end, wherein the first control end is coupled to the first operating voltage, the second control end is coupled to the first polarity switching signal, the first electrical end is coupled to the first electrical end of the third switch, the second electrical end is coupled to the P+1th output channel, the first substrate end is coupled to the first substrate end of the fifth switch, and the second substrate end is coupled to the second substrate end of the fifth switch; an eighth switch having a first control end, a second control end, a first electrical end, a second electrical end, a first substrate end, and a second substrate end, wherein the first control end is coupled to the first operating voltage, the second control end is coupled to the first polarity switching signal, the first electrical end is coupled to the first electrical end of the third switch, the second electrical end is coupled to the P+1th output channel, the first substrate end is coupled to the first substrate end of the fifth switch, and the second substrate end is coupled to the second substrate end of the fifth switch. a working voltage, the second control end is coupled to the second polarity switching signal, the first electrical end is coupled to the polarity switching circuit, the second electrical end is coupled to the P+2th output channel, the first substrate end is coupled to the first substrate end of the sixth switch, and the second substrate end is coupled to the second substrate end of the sixth switch; a third inverter is biased by the second working voltage and the first working voltage, its input end is coupled to a third substrate bias voltage, and its output end is simultaneously coupled to the second substrate end of the sixth switch and the second substrate end of the eighth switch; and a fourth inverter is biased by the first working voltage and the third working voltage, its input end is coupled to a fourth substrate bias voltage, and its output end is simultaneously coupled to the first substrate end of the sixth switch and the first substrate end of the eighth switch. A chip testing system includes a test fixture for connecting an electronic chip at multiple points and a control unit; the test fixture and the switch circuit described in any one of claim 1 to claim 9 are used in conjunction with each other, so that the control unit can perform parallel output voltage testing on the electronic chip with multiple output channels through the test fixture and the switch circuit.

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