TWI863362B - Resistive random-access memory devices with metal-nitride compound electrodes - Google Patents

Abstract

The present invention relates to a resistive random access memory (RRAM) device. In some embodiments, the RRAM device includes: a first electrode including a metal nitride, a second electrode including a first conductive material, and a switching oxide layer located between the first electrode and the second electrode. The switching oxide layer includes at least one transitional metal oxide. In some embodiments, the metal nitride in the first electrode includes titanium nitride and/or tantalum nitride. The first electrode does not include a non-reactive metal, such as platinum (Pt), palladium (Pd), etc.

Description

Resistive random access memory device having metal nitride compound electrodes

The present invention relates to a resistive random access memory (RRAM), and more specifically to a RRAM device having a metal nitride compound electrode.

RRAM devices are two-terminal passive devices with adjustable and non-volatile resistance. The resistance of the RRAM device can be electrically switched between a high resistance state (HRS) and a low resistance state (LRS) by applying a suitable programming signal to the RRAM device. RRAM devices can be used to form a crossbar array, which can be used to implement in-memory computing applications, non-volatile solid-state storage, image processing applications, neural networks, etc.

The following is a brief summary of the invention, which is intended to provide a basic understanding of some aspects of the invention. The content of the invention is not a broad overview of the invention. The content of the invention is not intended to identify the key or important elements of the invention, nor is it intended to illustrate any scope of a specific implementation of the invention or any scope of the scope of the patent application. The sole purpose of the content of the invention is to simplify some concepts of the invention as a language for a more detailed description presented later.

According to one or more aspects of the present invention, a resistive random access memory (RRAM) device may include: a first electrode including a metal nitride; a second electrode including a first conductive material; and a switching oxide layer between the first electrode and the second electrode. The switching oxide layer includes at least one transitional metal oxide. The first electrode does not include a non-reactive metal, such as platinum (Pt), palladium (Pd), etc.

According to one or more aspects of the present invention, a method for manufacturing a RRAM device is provided. The method includes manufacturing one or more layers on a first electrode including a metal nitride; and manufacturing a second electrode on a top layer of the one or more layers. The second electrode includes a conductive material. The one or more layers include a switching oxide layer located between the first electrode and the second electrode. The switching oxide layer includes at least one transitional metal oxide.

In some embodiments, the metal nitride in the first electrode includes titanium nitride.

In some embodiments, the metal nitride in the first electrode includes tantalum nitride.

2.0且y

2.5。 In some embodiments, the at least one transition metal oxide comprises at least one of HfO _x or TaO y , wherein x

2.0 and y

2.5.

In some embodiments, the conductive material in the second electrode includes tantalum.

In some embodiments, the RRAM device further includes an interface layer A located between the switching oxide layer and the second electrode.

In some embodiments, the interface layer A includes aluminum oxide.

In some embodiments, the RRAM device further includes an interface layer B located between the switching oxide layer and the first electrode.

In some embodiments, the interface layer A or the interface layer B comprises aluminum oxide.

In some embodiments, both the interface layer A and the interface layer B include aluminum oxide.

100: Cross-switch circuit

111a, 111b, 111i, 111n: lines

113a, 113b, 113j, 113m: alignment lines

120a, 120b, 120ij, 120z: Cross-point devices

200: Cross-point device

201:RRAM devices

203: Transistor

211: bit line

213: Line selection

215: Word line

G: Grid pole

S: Source

D: Drain

300a, 300b, 330c: RRAM devices

310: Lining

320: First electrode

330: Switching oxide layer

340: Second electrode

335a: Conductive channel

335b: Interrupt the conduction channel

400: Manufacturing method example

410, 420, 430: Steps

600A:Characteristic curve

600B:Characteristic curve

700:RRAM devices

720: First electrode

730: Switching oxide layer

740: Second electrode

750:Interface layer A (ILA)

800: Manufacturing method example

810, 820, 830, 840: Steps

900:RRAM devices

920: First electrode

930: Switching oxide layer

940: Second electrode

950:Interface layer A (ILA)

960:Interface layer B (ILB)

1000: Manufacturing method example

1010, 1020, 1030, 1040, 1050: Steps

1100: Manufacturing method example

1110, 1120: Steps

The present invention will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present invention. However, the drawings should not be used to limit the present invention to specific embodiments, but are only used for explanation and understanding.

FIG1 is a schematic diagram showing an example of a cross-switch circuit according to some embodiments of the present invention.

FIG2 is a schematic diagram showing an example of a cross-point device according to some embodiments of the present invention.

FIG. 3A shows a cross-sectional view of a first example RRAM device using a metal nitride instead of platinum (Pt) in a non-reactive electrode.

FIG3B and FIG3C respectively show cross-sectional views of the RRAM device in FIG3A in a low resistance state and a high resistance state.

FIG4 is a flow chart showing a method for manufacturing an RRAM device according to some embodiments of the present invention.

FIG. 5A shows the I-V (current-voltage) characteristics of the RRAM device according to some embodiments of the present invention.

FIG. 5B shows an I-V curve of simulated behavior of an RRAM device according to some embodiments of the present invention.

Figures 6A and 6B show the read current stability of an example RRAM device over time at room temperature and 135°C, respectively.

FIG7 shows a cross-sectional view of a second example RRAM device using a metal nitride instead of platinum (Pt) in a non-reactive electrode.

FIG8 shows a flow chart of a method for manufacturing an RRAM device according to some embodiments of the present invention.

FIG9 shows a cross-sectional view of a third example RRAM device using a metal nitride instead of platinum (Pt) in a non-reactive electrode.

Figures 10 and 11 show flow charts of methods for manufacturing RRAM devices according to some embodiments of the present invention.

Various aspects of the present invention provide RRAM devices and methods for making RRAM devices. RRAM devices are two-terminal passive devices with adjustable resistance. The RRAM device may include a first electrode, a second electrode, and a switching oxide layer located between the first electrode and the second electrode. In some embodiments, the first electrode and the second electrode may be the bottom electrode and the top electrode of the RRAM device, respectively. In some embodiments, the first electrode and the second electrode may be the top electrode and the bottom electrode of the RRAM device, respectively. The first electrode may include a non-reactive metal, such as platinum (Pt), palladium (Pd), etc. The second electrode may include a reactive metal, such as tantalum (Ta). An electrode including a non-reactive metal may also be referred to as a "non-reactive electrode". Electrodes comprising reactive metals may also be referred to as "reactive electrodes". The switching oxide layer may include a transition metal oxide, such as tantalum oxide ( _HfOx ) or tantalum oxide ( _TaOx ). The RRAM device may be in an initial state or a primitive state and have an initial high resistance before it receives an appropriate electrical stimulus (e.g., a voltage or current signal applied to the RRAM device). The RRAM device may be converted from the primitive state to a low resistance state by a formation process, or may be switched from a high resistance state to a low resistance state by a setup process. The formation process refers to programming the device from the primitive state. The setup process refers to programming the device from a high resistance state (HRS). After the reactive metal electrode is deposited on the switching oxide, the reactive metal can absorb oxygen ions from the switching oxide layer, creating oxygen vacancies in the switching oxide layer, and the oxygen ions can migrate in the switching oxide through a vacancy mechanism. During the formation process, an appropriate programming signal (e.g., a voltage or current signal) applied to the RRAM device can cause the oxygen ions to drift from the switching oxide to the reactive electrode. Therefore, a conductive channel or conductive filament can pass through the switching oxide layer (e.g., from the reactive electrode to the non-reactive electrode). Then, the RRAM device can be reset to a high-resistance state by applying a reset signal (e.g., a voltage signal, a current signal) to the RRAM device. Applying the reset signal to the RRAM device can cause the oxygen ions to migrate back to the switching oxide layer, thereby interrupting the conductive filament. By applying an appropriate programming signal (e.g., a voltage signal, a current signal) to the RRAM device, the RRAM device can be electrically switched between a high resistance state and a low resistance state. In a crossbar array circuit, the programming signal can be provided to a specified RRAM device through a selector (e.g., a transistor).

RRAM devices containing platinum (Pt) in a non-reactive electrode can provide RRAM high performance, such as reliability, durability, multi-level, retention, etc. In an RRAM device including a bottom electrode containing platinum, a switching oxide layer including tantalum oxide, and Ta (also referred to as a "Pt/ _TaOx /Ta system"), Ta filaments in _TaOx exhibit excellent linearity, analog, retention, and durability. In a Pt/ _HfOx /Ta system, Ta can migrate to _HfOx to form Ta-rich filaments in _HfOx and exhibit excellent linearity, analog, retention, and durability in IMC applications. However, the material and processing costs of platinum are high, and major manufacturers may not be ready to incorporate platinum in their production processes. Therefore, it is desirable to be able to replace Pt in the non-reactive electrode of RRAM devices with a suitable alternative material that is chemically stable so that it does not react with oxygen during the RRAM switching process and can enable RRAM devices to be multi-level or modular in IMC applications.

In the present invention, some embodiments use metal nitrides, such as TiN or TaN, as an alternative material to the non-reactive electrode Pt in the RRAM device. The first electrode does not include non-reactive metals, such as platinum (Pt) and palladium (Pd). TiN and TaN are both conductive materials. Both TiN and TaN are compatible with the manufacturing process of CMOS (complementary metal oxide semiconductor), can be mass-produced, and the production cost is much lower than Pt. Both TiN and TaN are chemically stable, and they do not react with oxygen during the RRAM switching process. For IMC applications, RRAM devices containing TiN or TaN in the non-reactive electrode have multi-level or analog characteristics.

In some embodiments, the RRAM device may include a device stack of TiN/ _HfOx /Ta for the first electrode, the switching oxide layer, and the second electrode, respectively. In another embodiment, the RRAM device may include a device stack of TiN/ _HfOx / _AlOx /Ta for the first electrode, the switching oxide layer, the interface layer, and the second electrode. For the interface layer including aluminum oxide, the RRAM device may be a high resistance and annealing resistant RRAM device. In a further embodiment, the RRAM device may include a device stack of TiN/ _AlOx / _HfOx / _AlOx /Ta for the first electrode, the first interface layer, the switching oxide layer, the second interface layer, and the second electrode, respectively.

Compared with RRAM devices using Pt-based non-reactive electrodes, RRAM devices using TiN or TaN-based non-reactive electrodes have lower material and manufacturing costs, can be used in CMOS processes, and can be mass-produced. The RRAM devices invented in this article exhibit appropriate performance and capabilities in multi-level switching and analog behavior.

FIG. 1 is a schematic diagram showing an example 100 of a crossover switch circuit according to some embodiments of the present invention. As shown in the figure, the crossover switch circuit 100 may include a plurality of interconnected conductive lines for a crossover array of n rows by m columns, such as one or more row lines 111a, 111b, ..., 111i, ..., 111n, and column lines 113a, 113b, ..., 113j, ..., 113m. The crossover switch circuit 100 may further include crossover devices 120a, 120b, ..., 120z, etc. Each crossover device may connect a row line and a column line. For example, the crossover device 120ij may connect a row line 111i and a column line 113j. In some embodiments, the crossbar switch circuit 100 may further include a digital-to-analog converter (DAC, not shown), an analog-to-digital converter (ADC, not shown), a switch (not shown), and one or more suitable circuit components for implementing a crossbar switch device. The number of column lines 113a-m and the number of row lines 111a-n may be the same or different.

The row lines 111 may include a first row line 111a, a second row line 111b, ..., 111i, ..., and an nth row line 111n. Each row line 111a, ..., 111n may be and/or include any suitable conductive material. In some embodiments, each row line 111a-n may be a metal line.

The column lines 113 may include a first column line 113a, a second column line 113b, ... and an mth column line 113m. Each column line 113a-m may be and/or include any suitable conductive material. In some embodiments, each column line 113a-m may be a metal line.

Each cross-point device 120 may be and/or include any suitable device having adjustable resistance, such as a memory resistor, a phase change memory (PCM) device, a floating gate, a spintronic device, a resistive random access memory (RRAM), a static random access memory (SRAM), etc. In some embodiments, one or more of the cross-point devices 120 may include an RRAM device as described in conjunction with FIGS. 3A-12 .

The cross-switch circuit 100 can perform parallel weighted voltage multiplication and current summation. For example, an input voltage signal can be applied to one or more rows (e.g., one or more selected rows) of the cross-switch circuit 100. The input signal can flow through the cross-point devices of the rows of the cross-switch circuit 100. The conductance of the cross-point device can be adjusted to a specific value (also referred to as a "weighted value"). According to Ohm's law, the input voltage is multiplied by the cross-point conductance and generates a current flowing through the cross-point device. Through Kirchhoff's law, the sum of the currents through the devices on each column generates a current as an output signal, which can be read from the column (e.g., the output of an ADC). According to Ohm's law and Kirchhoff's current law, the input-output relationship of the crossbar array can be expressed as I=VG, where I is the output signal matrix, expressed as current; V is the input signal matrix, expressed as voltage; and G is the conductivity matrix of the crosspoint device. Therefore, according to Ohm's law, the input signal is weighted by its conductivity at each crosspoint device. The weighted current is output through each column line and accumulated according to Kirchhoff's current law. This can be achieved by implementing parallel multiplication and summation in the crossbar array to achieve in-memory computing (IMC).

FIG2 shows a schematic diagram of an example 200 of a cross-point device according to an embodiment of the present invention. As shown, the cross-point device 200 can connect a bit line (BL) 211, a select line (SEL) 213, and a word line (WL) 215. The bit line 211 and the word line 215 shown can be a column line and a row line as described in FIG1, respectively.

The cross-point device 200 may include a RRAM device 201 and a transistor 203. A transistor is a three-terminal device that may be labeled as a gate (G), a source (S), and a drain (D). The transistor 203 may be connected in series to the RRAM device 201. As shown in FIG. 2 , a first electrode of the RRAM device 201 may be connected to a drain of the transistor 203. A second electrode of the RRAM device 201 may be connected to a bit line 211. A source of the transistor 203 may be connected to a word line 215. A gate of the transistor 203 may be connected to a select line 213. The RRAM device 201 may include one or more RRAM devices combined as described in FIGS. 3A-11 below. The cross-point device 200 may also be referred to as a one-transistor-one-resistor (1T1R) configuration. The transistor 203 can be used as a selector as well as a current controller, which can set the current compliance of the RRAM device 201 during programming. The gate voltage of the transistor 203 can set the current compliance of the cross-point device 200 during programming, and thus control the conductance and analog behavior of the cross-point device 200. For example, when the cross-point device 200 is set from a high-resistance state to a low-resistance state, a set signal (e.g., a voltage signal, a current signal) can be provided through the bit line (BL) 211. Another voltage, also referred to as a select voltage or gate voltage, can be applied to the transistor gate through the select line (SEL) 213 to open the gate and set the current compliance, and the word line (WL) 215 can be set to ground. When the cross-point device 200 is reset from a low resistance state to a high resistance state, a gate voltage can be applied to the gate of the transistor through the select line 213 to open the transistor gate. At the same time, a reset signal can be sent to the RRAM device 201 through the word line 215, and the bit line 211 can be set to ground.

3A, 3B, and 3C show cross-sectional views of example RRAM devices according to some embodiments of the present invention. RRAM devices 300b and 300c may correspond to the low resistance state and the high resistance state of RRAM device 300a, respectively.

As shown in FIG3A , the RRAM device 300a may include a substrate 310, a first electrode 320 fabricated on the substrate 310, a switching oxide layer 330, and a second electrode 340. The switching oxide layer 330 is fabricated between the first electrode 320 and the second electrode 340. The substrate 310 may include one or more layers of any suitable material that may be used for a substrate of an RRAM device, such as silicon (Si), silicon dioxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), etc. In some embodiments, the substrate 310 may include a diode, a transistor, an interconnect, an integrated circuit, etc. In some embodiments, the substrate may include a driver circuit including one or more circuits (e.g., a circuit array) that can be individually controlled. In some embodiments, the driver circuit may include one or more complementary metal oxide semiconductor (CMOS) drivers.

The first electrode 320 may include a metal nitride. The metal nitride is conductive and non-reactive to the switching oxide. The metal nitride may have suitable chemical stability, i.e., it does not react with oxygen during RRAM switching. For example, the first electrode 320 may include titanium nitride (TiN), tantalum nitride (TaN), etc. The first electrode 320 does not include a non-reactive metal, such as platinum (Pt), palladium (Pd), etc. In some embodiments, the first electrode 320 does not include Pt or Pd. RRAM devices that include metal nitrides in their non-reactive metals have multi-level or analog behaviors required for IMC applications.

In some embodiments, a Ta layer and/or a Ti layer (not shown) may be formed between the first electrode and the substrate 310 to enhance adhesion between the substrate 310 and components of the RRAM device 300a.

2.0，對於TaO_x(其中Ta₂O₅是完全氧化物)，x

2.5。 The switching oxide layer 330 may include one or more transition metal oxides of binary oxides, ternary oxides, and higher oxides, such as _TaOx , _HfOx , _TiOx , _NbOx , _ZrOx , etc. In some embodiments, the chemical stability of the non-reactive material in the first electrode 320 may be higher than the chemical stability of the transition metal oxide in the switching oxide layer 330. In some embodiments, the transition metal oxide includes at least one of _HfOx or _TaOx , where x can be used to indicate that the oxide is oxygen-deficient compared to its complete (or terminal) oxide, and the value of x can vary according to the ratio of oxygen and metal atoms in the stoichiometry of its complete oxide, for example, for _HfOx (where _HfO2 is a complete oxide), x is 0.1477 W/m2.

2.0, for TaO _x (where Ta ₂ O ₅ is a complete oxide), x

2.5.

The thermochemical stability between the first electrode (comprising TiN) and the switching oxide layer (comprising HfO _x ) can be evaluated by, for example, the following chemical reaction (1): HfO ₂ +TiN=TiO ₂ +HfN (1)

△H°=△H° _TiO2 +△H° _HfN -△H° _HfO 2-△H° _TiN =32.4kcal>0

△S°=S° _TiO2 +S° _HfN -S° _HfO2 -S° _TiN =0.04cal/deg~0

△G°=△H°-T△S°=32400-0.04T>0

△H°, △S°, and △G° are the enthalpy change, entropy change, and free energy change of reaction (1) at 298K (or 25℃), respectively.

△H° >> 0 and △G° >> 0 indicate that the chemical reaction is thermodynamically unfavorable (1), or that _HfO2 and TiN do not spontaneously react to form _TiO2 and HfN when they come into contact.

For thermochemical stability assessment, here is a reference table based on the 5th edition of Metallurgical Thermochemistry by O.Kubaschewski and C.B.Alcock.

The second electrode 340 may include any suitable metal material that is electronically conductive and reactive to the switching oxide. For example, the metal material in the second electrode 340 may include Ta, Hf, Ti, TiN, TaN, etc. The second electrode 340 may react with the switching oxide and have a suitable oxygen solubility so that oxygen can be absorbed from the switching oxide layer 330 and oxygen vacancies can be generated in the switching oxide layer 330. In other words, the reactive metal material in the second electrode 340 may have a suitable oxygen solubility and/or oxygen mobility. In some embodiments, the second electrode 340 may not only generate oxygen vacancies in the switching oxide layer 330 (e.g., by scavenging oxygen), but may also serve as an oxygen reservoir or oxygen source for the switching oxide layer 330 during cell programming.

The RRAM device 330a may have an initial resistance (also referred to herein as "original resistance") after fabrication. The initial resistance of the RRAM device 300a may be changed, and the RRAM device 300a may be switched to a lower resistance state through a formation process. For example, an appropriate voltage or current may be applied to the RRAM device 300a. The voltage applied to the RRAM device 300a may cause the metal material in the second electrode to absorb oxygen from the switching oxide layer 330 and generate oxygen vacancies in the switching oxide layer. As a result, a conductive channel (e.g., a conductive filament) rich in oxygen vacancies may be formed in the switching oxide layer 330. For example, as shown in FIG. 3B , a conductive channel 335a may be formed in the switching oxide layer. As shown, the conductive path 335a can cross the switching oxide layer 330 from the second electrode 340 to the first electrode 320. The RRAM device 300b can be reset to a high resistance state. For example, a reset signal (e.g., a voltage signal or a current signal) can be applied to the RRAM device 300b during the reset process. In some embodiments, the set signal and the reset signal can have opposite polarities, such as a positive signal and a negative signal, respectively. The application of the reset signal can cause oxygen to drift back to the switching oxide layer 330 and recombine with one or more oxygen vacancies. For example, during the reset process, an interrupted conductive path 335b as shown in FIG. 3C can be formed in the switching oxide layer 330. As shown, the conductive channel can be interrupted by an oxide gap between the interrupted conductive channel 335b and the first electrode 320. The lateral dimension of the interrupted conductive channel 335b can be smaller than the lateral dimension of the conductive channel 335a. In some embodiments, the interrupted conductive channel 335b discontinuously connects the first electrode 320 and the second electrode 340. The RRAM device 300a-c can be electrically switched between a high resistance state and a low resistance state by applying an appropriate programming signal (e.g., a voltage signal, a current signal, etc.) to the RRAM device.

In one embodiment, the second electrode 340 may include one or more alloys. Each alloy may include two or more metal elements. Each of the alloys may include a binary alloy (e.g., an alloy containing two metal elements), a ternary alloy (e.g., an alloy containing three metal elements), a quaternary alloy (e.g., an alloy containing four metal elements), a quinary alloy (e.g., an alloy containing five metal elements), and/or a high-order alloy (e.g., an alloy containing six or more metal elements). In some embodiments, the second electrode 340 may include one or more alloys containing a first metal element and one or more second metal elements. Each second metal element has a reactivity to the transitional metal oxide in the switching oxide layer that is less than or greater than the first metal element. In some embodiments, the first metal element may be Ta. The second metal element may include one or more of tungsten (W), niobium (Hf), molybdenum (Mo), niobium (Nb), zirconium (Zr), etc. In some embodiments, the ratio of the first metal element to the second metal element of the alloy in the second electrode 340 may be 50 atomic percent. In some embodiments, the appropriate ratio of the first metal element to the second metal element in the alloy may be optimized from the entire composition range. During the formation process, the second metal element may generate fewer oxygen vacancies in the switching oxide layer than the first metal element. Therefore, the lateral size of the conductive filament formed in the RRAM device including the second electrode containing the alloy may be smaller than the lateral size of the conductive filament formed in the RRAM device including the second electrode made of only the first metal.

In some embodiments, the second electrode 340 may include multiple layers of different metal materials. For example, the second electrode 340 may include a titanium (Ti) layer and a tantalum (Ta) layer. The Ti layer may be much thinner than the Ta layer. For example, the thickness of the Ti layer may be between about 0.2nm and 5nm. The thickness of the Ta layer may be about 50nm. In some embodiments, the thickness of the Ti layer may be between 0.3nm and 2nm. Both Ti and Ta can capture and release oxygen during device operation. Adding a thin Ti layer to a RRAM device can change the original resistance of the RRAM device, resulting in a less obtrusive formation process, lower formation voltage, lower reset current, and lower voltage and/or current requirements in subsequent operations.

In some embodiments, the RRAM device 300a may include a device stack of TiN/HfO _x /Ta for the first electrode 320, the switching oxide layer 330, and the second electrode 340, respectively.

FIG. 4 shows a flow chart of an example method 400 for manufacturing an RRAM device including the Pt-free RRAM devices 330a-300c in FIGS. 3A-3C according to an embodiment of the present invention.

In 410, a first electrode may be fabricated on a substrate. Fabricating the first electrode may include depositing one or more layers of a metal nitride, such as TiN or TaN. For example, fabricating the first electrode may include depositing one or more layers of TiN using an atomic layer deposition (ALD) technique, a physical vapor deposition (PVD) technique, a Ti reactive sputtering technique, and/or any other suitable deposition technique. The first electrode may be and/or include the first electrode 320 described above in conjunction with FIG. 3A. In some embodiments, a thin layer of bonding material, such as Ti, Ta, etc., may be fabricated between the substrate and the first electrode.

In 420, a switching oxide layer including one or more transition metal oxides may be formed on the first electrode. The transition metal oxide may include, for example, _HfOx . For example, fabricating the switching oxide layer may include depositing HfOx using an atomic layer deposition (ALD) technique, a physical vapor deposition (PVD) technique, a reactive sputtering technique of Hf, and/or _any other suitable deposition technique. The switching oxide layer may be and/or include the switching oxide layer 330 described above in conjunction with FIG. 3A.

In 430, a second electrode may be fabricated on the switching oxide layer. Fabricating the second electrode may include fabricating one or more layers of one or more metal materials, wherein the metal materials are electronically conductive and reactive to the switching oxide. For example, fabricating the second electrode may include depositing one or more layers of Ta using a physical vapor deposition (PVD) technique and/or any other suitable deposition technique. The second electrode may be and/or include the second electrode 340 described above in conjunction with FIG. 3A .

5A shows IV (current-voltage) characteristics of a RRAM device 300a using a TiN/HfO _x /Ta device stack according to some embodiments of the present invention. The RRAM device 300a provides repeatable and desirable set-reset operations for Switch 1, Switch 2, and Switch 3 in FIG5A, demonstrating multi-switching robustness.

5B is an IV curve showing the analog behavior of the RRAM device 300a using the TiN/ _HfOx /Ta device stack according to some embodiments of the present invention. The RRAM device 300a exhibits the desired analog behavior, i.e., the device resistance can be adjusted to multiple levels (or analog behavior) by controlling the current compliance, and the current is linearly proportional to the voltage (or linear behavior) in each resistance state.

6A and 6B show characteristic graphs 600A and 600B of device read current characteristics over time of an example RRAM device in some embodiments according to the present invention. The example RRAM device may include a device stack of TiN/HfO _x /Ta. Characteristic graphs 600A and 600B represent device read current characteristics of an example RRAM device at room temperature and at 135° C., respectively. Characteristic graphs 600A and 600B may represent the results of a device retention test of the ability of the RRAM device to maintain a resistance level over time. Characteristic graphs 600A and 600B may also represent the results of a read stability test because the RRAM device is under constant read (with a read voltage of 0.2V) due to its ability to maintain a resistance level over time. As shown in Figure 6A, the RRAM device exhibits the desired device read stability over time at room temperature. As shown in Figure 6B, the RRAM device exhibits the desired read stability over time at 135°C. Therefore, the RRAM device exhibits the desired resistance stability or retention at the device operating temperature.

FIG. 7 shows a cross-sectional view of an example RRAM device 700 according to another embodiment of the present invention, wherein the example RRAM device 700 uses a metal nitride instead of platinum (Pt) in its non-reactive electrode. The RRAM device 700 may be referred to as a Pt-free RRAM device.

The RRAM device 700 may include a first electrode 720, a switching oxide layer 730, an interface layer A (ILA) 750, and a second electrode 740. The first electrode 720, the switching oxide layer 730, and the second electrode 740 may be respectively the same as the first electrode 320, the switching oxide layer 330, and the second electrode 340 described in conjunction with FIG. 3A. In some embodiments, the RRAM device 700 may further include a substrate (not shown) described in conjunction with FIG. 3A.

_The ILA ₇₅₀ (which may also be referred to as a "first interface layer") may include a first material that is more chemically stable than a transitional metal oxide. The first material may include, for example, _Al2O3 , MgO, _Y2O3 , _La2O3 , _etc. The ILA 750 may include a non-continuous film of the first material and/or a continuous film of the first material. In some embodiments, the thickness of the ILA 750 may be between approximately 0.2nm and 0.5nm. In some embodiments, the ILA 750 may include _{an Al2O3} film having a thickness equal to or less than 0.5nm. In some embodiments, the ILA 750 may be and/or include _{an Al2O3} film having a thickness less than 1nm.

In some embodiments, the RRAM device 700 may include a device stack of TiN/ _HfOx / _AlOx /Ta for the first electrode 720, the switching oxide layer 730, the ILA 750, and the second electrode 740. In the case where the ILA 750 includes aluminum oxide, the RRAM device 700 may be a high resistance and annealing resistant RRAM device.

FIG8 shows a flow chart of an example method 800 for manufacturing an RRAM device including the RRAM device 700 in FIG7 according to some embodiments of the present invention.

In 810, a first electrode may be fabricated on a substrate. Fabricating the first electrode may include depositing one or more layers of a metal nitride, such as TiN or TaN. For example, fabricating the first electrode may include depositing one or more layers of TiN using an atomic layer deposition (ALD) technique, a physical vapor deposition (PVD) technique, a Ti reactive sputtering technique, and/or any other suitable deposition technique. The first electrode may be and/or include the first electrode 720 described above in conjunction with FIG. 7 .

At 820, a switching oxide layer including one or more transition metal oxides may be fabricated on the first electrode. The transition metal oxide may include, for example, _HfOx . For example, fabricating the switching oxide layer may include depositing HfOx using an atomic layer deposition (ALD) technique, a physical vapor deposition (PVD) technique, a reactive sputtering technique of Hf, and/or any other suitable deposition _technique . The switching oxide layer may be and/or include the switching oxide layer 730 described above in conjunction with FIG. 7.

At 830, an interface layer may be fabricated on the switching oxide layer. The first interface layer may include a metal that is more chemically stable than the transition metal oxide in the switching oxide layer, such as _AlOx , such as _Al2O3 . For example, fabricating the first interface layer may include depositing _AlOx using an atomic layer deposition (ALD) technique, a physical vapor deposition ( _PVD ) technique, an Al reactive sputtering technique, and/or any other suitable deposition technique. The interface layer A may be and/or include the ILA 750 described above in conjunction with FIG. 7.

In 840, a second electrode may be fabricated on the interface layer. Fabricating the second electrode may include fabricating one or more layers of one or more metal materials that are electronically conductive and reactive to the switching oxide. For example, fabricating the second electrode may include depositing one or more layers of Ta using physical vapor deposition (PVD) techniques and/or any other suitable deposition techniques. The second electrode may be and/or include the second electrode 740 described above in conjunction with FIG. 7 .

FIG. 9 shows a cross-sectional view of an example RRAM device 900 according to a further embodiment of the present invention, which uses a metal nitride instead of platinum (Pt) in its non-reactive electrode. The RRAM device 900 may be referred to as a Pt-free RRAM. The RRAM device 900 may include a first electrode 920, an interface layer B (ILB) 960, a switching oxide layer 930, an interface layer A (ILA) 950, and a second electrode 940. The first electrode 920, the switching oxide layer 930, and the second electrode 940 may be the same as the first electrode 320, the switching oxide layer 330, and the second electrode 340 described in conjunction with FIG. 3A, respectively. ILA 950 may be the same as ILA 750 in FIG. 7. In some embodiments, the RRAM device 900 may further include a substrate (not shown) as described in conjunction with FIG. 3A.

The ILB 960 may include a second material that is more chemically stable than the transition metal oxide. The second material may include, for example, Al ₂ O ₃ , MgO, Y ₂ O ₃ , La ₂ O ₃ , etc. The ILB 960 may include a discontinuous film of the second material and/or a continuous film of the second material. In some embodiments, the thickness of the ILB 960 may be between about 0.2 nm and about 0.5 nm. In some embodiments, the ILB 960 may include an Al ₂ O ₃ film having a thickness equal to or less than 0.5 nm. In some embodiments, the ILB 960 may include an Al ₂ O ₃ film having a thickness less than 1 nm.

The RRAM device 900 may use a device stack of TiN/ _AlOx / _HfOx / _AlOx /Ta for the first electrode 920, the ILB 960, the switching oxide layer 930, the ILA 950, and the second electrode 940. The RRAM device 900 may be a high resistance and annealing resistant RRAM device through the first interface layer and the second interface layer.

FIG. 10 is a flow chart of an example method 1000 for manufacturing an RRAM device including the RRAM device 900 in FIG. 9 according to some embodiments of the present invention.

In 1010, a first electrode may be fabricated on a substrate. Fabricating the first electrode may include depositing one or more layers of a metal nitride, such as TiN or TaN. For example, fabricating the first electrode may include depositing one or more layers of TiN using an atomic layer deposition (ALD) technique, a physical vapor deposition (PVD) technique, a Ti reactive sputtering technique, and/or any other suitable deposition technique. The first electrode may be and/or include the first electrode 920 described above in conjunction with FIG. 9 .

In 1020, an interface layer B (ILB) may be fabricated on the first electrode. The ILB may include a metal that is more chemically stable than a transition metal oxide (e.g., _AlOx , such as _{Al2O3 )} in a switching oxide layer described later. For example, fabricating the interface layer B may include depositing _AlOx using an atomic layer deposition (ALD) technique, a physical vapor deposition (PVD) technique, an Al reactive sputtering technique, and/or any other suitable deposition technique. The interface layer B may be and/or include the ILB 960 described above in conjunction with FIG. 9 .

In 1030, the switching oxide layer including one or more transition metal oxides may be fabricated on the interface layer B. The transition metal oxide may include, for example, _HfOx . For example, fabricating the switching oxide layer may include depositing HfOx using an atomic layer deposition (ALD) technique, a physical vapor deposition (PVD) technique, a reactive sputtering technique of Hf, and/or any other suitable deposition _technique . The switching oxide layer may be and/or include the switching oxide layer 930 described above in conjunction with FIG. 9.

In 1040, an interface layer A (ILA) may be fabricated on the switching oxide layer. The ILA may include a metal that is more chemically stable than the transition metal oxide in the switching oxide layer, such as _AlOx , such as _Al2O3 . For _example , fabricating the interface layer A may include depositing _AlOx using an atomic layer deposition (ALD) technique, a physical vapor deposition (PVD) technique, an Al reactive sputtering technique, and/or any other suitable deposition technique. The interface layer A may be and/or include the ILA 950 described above in conjunction with FIG. 9.

In 1050, a second electrode may be fabricated on the interface layer A. Fabricating the second electrode may include fabricating one or more layers of one or more metal materials that are electronically conductive and reactive to the switching oxide. For example, fabricating the second electrode may include depositing one or more Ta layers using physical vapor deposition (PVD) techniques and/or any other suitable deposition techniques. The second electrode may be and/or include the second electrode 940 described above in conjunction with FIG. 9 .

FIG. 11 is a flow chart of an example method 1100 for manufacturing an RRAM device including the RRAM device 300a in FIG. 3A , the RRAM device 700 in FIG. 7 , and/or the RRAM device 900 in FIG. 9 according to some embodiments of the present invention.

2.0且y

2.5)。 In 1110, one or more layers may be fabricated on a first electrode. The first electrode may include a metal nitride, such as titanium nitride, tantalum nitride, etc. The one or more layers may include a switching oxide layer between the first electrode and the second electrode of the RRAM device. The switching oxide layer may include at least one transition metal oxide (e.g., HfO _x and/or TaO _y , where x is greater than or equal to 1.0).

2.0 and y

2.5).

In some embodiments, the one or more layers on the first electrode may further include one or more interface layers, such as an interface layer A between the switching oxide layer and the second electrode and/or an interface layer B between the switching oxide layer and the first electrode. Each of the interface layer A and the interface layer B may include Al ₂ O ₃ , MgO, Y ₂ O ₃ , La ₂ O ₃ , etc. In some embodiments, at least one of the interface layer A and the interface layer B includes Al ₂ O ₃ .

In 1120, a second electrode may be fabricated on the top layer of the one or more layers. The second electrode may include a conductive material. In some embodiments, the conductive material includes Ta, such as one or more alloys of Ta, a Ta layer, etc. In some embodiments, the second electrode includes a Ta layer and a Ti layer.

In some embodiments, the top layer of the one or more layers may be an interface layer A between a switching oxide layer and a second electrode. In some embodiments, the top layer of the one or more layers may be the switching oxide layer.

For simplicity of illustration, the method of the present invention is depicted and described as a series of actions. However, the actions according to the present invention can occur in various orders and/or simultaneously, and with other actions not proposed and described in the present invention. In addition, not all of the actions described may be required to implement the method according to the disclosed subject matter. In addition, those skilled in the art will understand and recognize that the method can alternatively be represented as a series of interrelated states via state diagrams or events.

As used herein, the terms "approximately," "about," and "substantially" may refer to within a normal tolerance range in the art, such as within 2 standard deviations of the mean, within ±20% of a target size in some embodiments, within ±10% of a target size in some embodiments, within ±5% of a target size in some embodiments, within ±2% of a target size in some embodiments, within ±1% of a target size in some embodiments, and within ±0.1% of a target size in some embodiments. The terms "approximately" and "about" may include the target size. Unless otherwise specified or apparent from the context, all numerical values described herein are modified by the term "about."

As used herein, a range includes all values within the range. For example, a range of 1 to 10 may include any number, combination of numbers, sub-ranges of numbers from 1, 2, 3, 4, 5, 6, 7, 8, 9, and 10, and fractions thereof.

The present invention is described in many details in the above description. However, it is obvious that the present invention can be implemented without these specific details. In some examples, in order to highlight the content of the present invention, well-known structures and devices are shown in the form of block diagrams rather than specific details.

The terms "first", "second", "third", "fourth", etc. used in this article are used to distinguish different components and may not necessarily have the ordinal meaning of the numerical numbers used.

The words "example" or "exemplary" as used herein refer to serving as an example, instance or illustration. Any aspect or design described herein as "example" or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs. On the contrary, the purpose of using the words "example" or "exemplary" is to present the concept in a concrete way. In the present invention, the term "or" means inclusive "or" rather than exclusive "or". That is, unless otherwise specified or clear from the context, "X includes A or B" means any natural inclusive permutation combination. That is, if X includes A; X includes B; or X includes both A and B, then in any of the above cases, "X includes A or B" is satisfied. In addition, "a" and "an" used in the present invention and the attached patent scope should generally be understood as "one or more", unless otherwise specified or clear from the context that it is directed to the singular form. The "one embodiment" or "an embodiment" mentioned in this specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment. Therefore, the phrases "one embodiment" or "an embodiment" appearing in different places in this specification do not necessarily refer to the same embodiment.

As used herein, when an element or layer is referred to as being "on" another element or layer, the element or layer may be directly on the other element or layer, or intervening elements or layers may be present. Conversely, when an element or layer is referred to as being "directly on" another element or layer, there are no intervening elements or layers present.

Although it is obvious to a person skilled in the art that additional changes and modifications to the content of the invention are made after understanding the above description, it should be understood that any specific embodiment shown and described in an illustrative manner should not be considered as limiting. Therefore, the details of the various embodiments are not intended to limit the scope of the patent application, which itself only describes the technical features of the invention.

1000: Manufacturing method example

1010, 1020, 1030, 1040, 1050: Steps

Claims (20)

A resistive random access memory (RRAM) device, characterized in that it includes: a first electrode including a metal nitride; a second electrode including a conductive material; a switching oxide layer between the first electrode and the second electrode; wherein the switching oxide layer includes at least one transitional metal oxide, and the conductive material is reactive to the transitional metal oxide; an interface layer A between the switching oxide layer and the second electrode; wherein the interface layer A includes aluminum oxide; and an interface layer B between the switching oxide layer and the first electrode; wherein the first electrode does not react with oxygen during RRAM operation. An RRAM device as described in claim 1, wherein the metal nitride in the first electrode includes at least one of titanium nitride or tantalum nitride. An RRAM device as described in claim 2, wherein the first electrode does not include a non-reactive metal. An RRAM device as described in claim 3, wherein the first electrode does not include platinum (Pt) or palladium (Pd). The RRAM device of claim 1, wherein the at least one transition metallization comprises at least one of HfO _x or TaO _y , wherein x

2.0 and y

2.5. An RRAM device as described in claim 1, wherein the conductive material in the second electrode includes tantalum. The RRAM device as described in claim 1, wherein the interface layer A or the interface layer B comprises aluminum oxide. An RRAM device as described in claim 1, wherein both interface layer A and interface layer B include aluminum oxide. The RRAM device as described in claim 1 further comprises: a substrate, and a layer of adhesive material prepared between the substrate and the first electrode. An RRAM device as described in claim 1, wherein the bonding material includes at least one Ti or Ta. A method for manufacturing a resistive random access memory (RRAM) device, characterized in that it includes: manufacturing one or more layers on a first electrode, the first electrode including a metal nitride; and manufacturing a second electrode on a top layer of the one or more layers, the second electrode including a conductive material that is reactive to a transitional metal oxide; wherein the one or more layers include a conductive layer located between the first electrode and the second electrode. A switching oxide layer between two electrodes; wherein the switching oxide layer includes at least one transitional metal oxide; an interface layer A is fabricated between the switching oxide layer and the second electrode; wherein the interface layer A includes aluminum oxide; and an interface layer B is fabricated between the switching oxide layer and the first electrode; wherein the first electrode does not react with oxygen during RRAM operation. A method as described in claim 11, wherein the metal nitride in the first electrode includes titanium nitride. A method as described in claim 11, wherein the metal nitride in the first electrode includes tantalum nitride. The method of claim 11, wherein the at least one transition metal oxide comprises at least one of HfO _x or TaO _y , wherein x

2.0 and y

2.5. A method as described in claim 11, wherein the conductive material in the second electrode includes tantalum. A method as described in claim 11, wherein the top layer of the one or more layers includes: an interface layer A located between the switching oxide layer and the second electrode. A method as described in claim 16, wherein the interface layer A comprises aluminum oxide. The method of claim 16, wherein the one or more layers further include: an interface layer B located between the switching oxide layer and the first electrode. The method as claimed in claim 18, wherein the interface layer A or the interface layer B comprises aluminum oxide. A method as described in claim 18, wherein both the interface layer A and the interface layer B include aluminum oxide.

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