TWI863026B - Transistor structure and related manufacture method - Google Patents

Abstract

A transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a first isolation region. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The first isolation region is next to the first conductive region. A length of the first conductive region is controlled by a single photolithography process which is originally configured to define the length of the gate structure.

Description

Transistor structure and related manufacturing method

The present invention relates to a transistor structure and a related manufacturing method thereof, and in particular to a transistor structure and a related manufacturing method thereof that can accurately control the length of the source/drain and the contact opening to effectively reduce the size.

Since the design criteria for reducing all dimensions of metal-oxide-semiconductor field-effect transistors (MOSFETs) were published in a paper by R. Dennard et al. in 1974, reducing the size of transistors has become a major technical requirement, which has changed the minimum feature size of the linear dimensions of silicon wafers from a few microns to a few nanometers. The minimum feature size or length is usually called Lamda (λ), which depends on the miniaturization capability of photolithographic masking technology and device reduction technology (for simplicity and comparison, the measurement by minimizing the printed line width resolution is also called λ). However, another difficult-to-control factor that limits the miniaturization of components is the misalignment tolerance (Delta-Lamda (△λ)) caused by the deficiencies and inaccuracies of photolithography equipment. In addition, due to the misalignment tolerance, it is difficult to make the distance between the gate edge of the transistor and the source (or drain) edge less than the sum of λ and △λ. Later, if it is necessary to use the photolithography mask technology again to make a square contact hole on the drain (or source) as a connection between the future metal interconnection to the drain (or the source), the minimum size of each side of the contact hole is difficult to be less than λ. In addition, to ensure that the contact hole within the drain contains misalignment tolerance, the length of each side of the drain (with a rectangular periphery) is also difficult to be less than the sum of λ and △λ. However, reducing the size of transistors is necessary to integrate more transistors within a planar area of a silicon wafer, and reducing the area occupied by the drain and source of the transistor separately is a necessary and effective way to achieve the above goal, which also helps to reduce leakage current and power consumption.

An embodiment of the present invention discloses a method for manufacturing a transistor, wherein the transistor includes a gate structure and a first conductive region. The manufacturing method includes forming an active region on a substrate; forming the gate structure and a dummy shield gate structure above the active region; forming a first isolation region to replace the dummy shield gate structure; forming a self-alignment pillar above the active region; and removing the self-alignment pillar and forming the first conductive region between the gate structure and the first isolation region.

In another embodiment of the present invention, before removing the self-alignment column, the manufacturing method further includes forming a second isolation region above the first isolation region, wherein the self-alignment column is located between the gate structure and the second isolation region.

In another embodiment of the present invention, after removing the self-alignment column, the manufacturing method further includes forming a spacer between the gate structure and the first isolation region to define a contact hole, wherein the contact hole is located above the first conductive region.

In another embodiment of the present invention, the length of the contact hole is less than a minimum feature length.

In another embodiment of the present invention, the substrate is a silicon substrate, and the self-aligned pillar is an intrinsic silicon pillar formed by selective epitaxy growth.

Another embodiment of the present invention discloses a method for manufacturing a transistor, wherein the transistor includes a gate structure and a first conductive region. The manufacturing method includes forming an active region on a substrate; forming the gate structure on the active region; and forming a self-alignment column, wherein the self-alignment column is used to allocate a contact hole above the first conductive region.

In another embodiment of the present invention, the manufacturing method further includes forming an isolation region on the active region before forming the self-alignment column.

In another embodiment of the present invention, the manufacturing method further includes removing the self-alignment column, wherein the self-alignment column is formed between the gate structure and the isolation region; and forming a spacer between the gate structure and the isolation region to define a contact hole, wherein the contact hole is located above the first conductive region.

In another embodiment of the present invention, the length of the contact hole is less than a minimum characteristic length.

Another embodiment of the present invention discloses a method for manufacturing a transistor, wherein the transistor includes a gate structure and a first conductive region. The manufacturing method includes forming an active region on a substrate; forming the gate structure above the active region; forming the first conductive region next to the gate structure; and defining a contact hole above the first conductive region, wherein defining the contact hole is independent of a photolithography process.

In another embodiment of the present invention, the first conductive region is formed between the gate structure and an isolation region, wherein the isolation region extends upwardly above the active region.

In another embodiment of the present invention, the contact hole is defined by forming a spacer layer, wherein the spacer layer covers a side wall of the gate structure and a side wall of the isolation region.

In another embodiment of the present invention, the length of the contact hole is less than a minimum characteristic length.

Another embodiment of the present invention discloses a method for manufacturing a transistor, wherein the transistor includes a gate structure and a first conductive region. The manufacturing method includes implementing a first photolithography process, wherein the first photolithography process is used to define the width of the gate structure and the length of an active region; implementing a second photolithography process, wherein the second photolithography process is used to define the length of the gate structure in the active region, wherein the second photolithography process is also used to define the length of the first conductive region.

In another embodiment of the present invention, the length of the first conductive region defined by the second photolithography process is equal to or substantially equal to a minimum feature length.

In another embodiment of the present invention, the length of the gate structure defined by the second photolithography process is equal to or substantially equal to a minimum feature length.

In another embodiment of the present invention, the length of the active region defined by the first photolithography process is approximately equal to 4 times a minimum feature length.

Another embodiment of the present invention discloses a method for manufacturing a transistor, wherein the transistor includes a gate structure and a first conductive region. The manufacturing method includes forming an active region on a substrate; forming the gate structure on the active region; forming the first conductive region next to the gate structure; and forming a contact hole above the first conductive region, wherein the shape of the contact hole does not need to be defined by a photolithography process.

In another embodiment of the present invention, the first conductive region is formed between the gate structure and an isolation region.

In another embodiment of the present invention, the contact hole is defined by forming a spacer layer, wherein the spacer layer covers a side wall of the gate structure and a side wall of the isolation region.

In another embodiment of the present invention, the length of the contact hole is less than a minimum characteristic length.

Another embodiment of the present invention discloses a transistor structure. The transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region and a contact hole. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The contact hole is located above the first conductive region. The periphery of the contact hole is surrounded by the periphery of the first conductive region.

In another embodiment of the present invention, the outer periphery of the first conductive region is a rectangle.

In another embodiment of the present invention, the length of the contact hole is less than a minimum characteristic length.

Another embodiment of the present invention discloses a transistor structure. The transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a contact hole. The semiconductor substrate has a semiconductor surface. The channel region is located below the gate structure. The contact hole is located above the first conductive region. The length of the contact hole is less than a minimum characteristic length.

In another embodiment of the present invention, a horizontal distance between a side wall of the gate structure and a side wall of the contact hole is less than the minimum characteristic length, wherein the side wall of the contact hole is far from the side wall of the gate structure.

In another embodiment of the present invention, a horizontal distance between a sidewall of the gate structure and a sidewall of the first conductive region is approximately equal to the minimum characteristic length, wherein the sidewall of the first conductive region is farther from the sidewall of the gate structure.

Another embodiment of the present invention discloses a transistor structure. The transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first isolation region, a first spacer layer, a second spacer layer, a first conductive region, and a first contact hole. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The channel region is located below the semiconductor surface. The first isolation region extends upward and downward from the semiconductor surface. The first spacer layer covers a first side wall of the gate structure, and the second spacer layer covers a side wall of the first isolation region. The first conductive region is electrically coupled to the channel region and is located between the gate structure and the first isolation region. The first contact hole is formed between the first spacer layer and the second spacer layer.

In another embodiment of the present invention, the transistor structure further includes a covering layer and a first metal region. The covering layer covers the gate structure. The first metal region is filled in the first contact hole and contacts the first conductive region, and the first metal region extends upward from the first conductive region to a predetermined position, wherein the predetermined position is higher than the top of the covering layer.

In another embodiment of the present invention, the width of the first metal region is substantially equal to the length of the first contact hole plus a minimum feature length.

In another embodiment of the present invention, the transistor structure further includes a second isolation region and a second conductive region. The second isolation region extends upward and downward from the semiconductor surface. The second conductive region is electrically coupled to the channel region and is located between the gate structure and the second isolation region.

In another embodiment of the present invention, a horizontal distance between a second sidewall of the gate structure and a sidewall of the second isolation region is substantially equal to a minimum characteristic length, wherein the sidewall of the first isolation region is away from the sidewall of the gate structure.

In another embodiment of the present invention, the transistor structure further includes a second contact hole. The second contact hole is located above the second conductive region, wherein the length of the second contact hole is less than a minimum characteristic length.

In another embodiment of the present invention, the transistor structure further includes a third spacer layer and a fourth spacer layer. The third spacer layer covers a second sidewall of the gate structure. The fourth spacer layer covers a sidewall of the second isolation region, wherein the second contact hole is formed between the third spacer layer and the fourth spacer layer.

Another embodiment of the present invention discloses a transistor structure. The transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a first isolation region. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The first isolation region is located next to the first conductive region. The length of the first conductive region is controlled by a single photolithography process, and the single photolithography process is originally used to define the length of the gate structure.

In another embodiment of the present invention, the length of the first conductive region is equal to or substantially equal to a minimum characteristic length.

Another embodiment of the present invention discloses a transistor structure. The transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region and a first contact hole. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The periphery of the first contact hole is independent of a photolithography process.

In another embodiment of the present invention, the length of the first contact hole is less than a minimum characteristic length.

In another embodiment of the present invention, the length of the first conductive region is equal to or substantially equal to the minimum characteristic length.

In another embodiment of the present invention, the first contact hole is located above the first conductive region.

100: MOSFET

101: Gate structure

103, 1704, 2402: Source

105, 1102: Isolation area

107, 1706, 2404: Drainage

109, 111: contact holes

102: Base

302: Pad oxide layer

304: Pad nitride layer

306: Shallow trench isolation-first oxide layer

402: Dielectric insulator

404, 602: Gate layer

406, 604: Nitride layer

702: Spin-on dielectric layer

802: Gate anode mask layer

902: Groove

1002, 2102, STI-oxide-2: Shallow trench isolation-second oxide layer

1502, 2202: The third oxide spacer layer

1504, 2204: lightly doped drain

1506, 2206: Nitrided spacer layer

1602, 2302: Essential silicon

1702, 2304: Chemical vapor deposition-shallow trench isolation-third oxide layer

1802, 2406: Oxidation spacer layer

1804: First contact hole

1806: Second contact hole

1902, 2502: First metal layer

1904, 2504: minimum space

1906: First semiconductor region

1908: The first metal-bearing zone

1910: Second semiconductor region

1912: The second metal-bearing zone

1914: First oxide protective layer

1916: Second oxide protective layer

D(L), G(L), S(L), C-S(L), C-D(L): Length

D(W), G(W), S(W), C-S(W), C-D(W): Width

GEBESI, GEBEDI: distance

HSS: Horizontal Silicon Surface

DSG: pseudo shielding gate

TG, TG2, TG3: True gate

λ: minimum feature length

△λ: Photolithography misalignment tolerance

10-70, 202-228: Steps

Figure 1 is a top view of a miniaturized MOSFET disclosed in an embodiment of the present invention.

Figure 2A is a flow chart of a method for manufacturing a miniaturized metal oxide semi-conductor field effect transistor disclosed in another embodiment of the present invention.

Figures 2B, 2C, 2D, 2E, and 2F are flow charts for explaining Figure 2A.

Figure 3 is a top view illustrating the liner nitride layer and shallow trench isolation-first oxide layer.

Figure 4 is a cross-sectional view along the X-axis in Figure 3.

FIG5 is a schematic diagram illustrating the photolithographic misalignment tolerance (PMT) of the alignment of the gate structure edge of the MOSFET to the source and the boundary edge between the shallow trench isolation and the first oxide layer.

Figure 6 is a schematic diagram illustrating a new structure that can eliminate the negative effects caused by photolithography misalignment tolerance.

Figure 7 is a schematic diagram illustrating the deposition of a spin-on dielectric layer.

Figure 8 is a schematic diagram illustrating the deposition and etching of a well-designed gate aurora mask.

FIG. 9 is a schematic diagram illustrating the removal of the dummy shielding gate, the nitride layer, the dielectric insulator, and the substrate corresponding to the dummy shielding gate by anisotropic etching technology.

Figure 10 is a schematic diagram illustrating the removal of the gate aurora mask layer, etching of the spin-on dielectric layer, deposition of the second oxide layer, and etching back of the second oxide layer to form a shallow trench isolation-second oxide layer.

Figures 11, 12, 13, and 14 are schematic diagrams illustrating the relationship between the position of the true gate and the position of the pseudo shielding gate.

FIG. 15 is a schematic diagram illustrating deposition and etching of a third oxide layer to form a third oxide spacer, formation of a lightly doped drain in a substrate, deposition and etching back of a nitride layer to form a nitride spacer, and removal of a dielectric insulator.

Figure 16 is a schematic diagram illustrating the use of selective epitaxial growth technology to produce primary silicon.

Figure 17 is a schematic diagram illustrating the deposition and etching back of CVD-STI-tertiary oxide layer, removal of native silicon, and formation of source and drain of MOSFET.

Figure 18 is a schematic diagram illustrating the deposition and etching of an oxide spacer layer to form contact hole openings.

FIG. 19 is a schematic diagram illustrating the deposition and etching back of the first metal layer to form the first metal layer interconnect.

FIG. 20 is a schematic diagram of another embodiment of the present invention, which discloses the use of a combined semiconductor junction and a metal conductor structure to form a source and a drain, and to form a first metal layer interconnection.

FIG. 21 is a schematic diagram illustrating the removal of the gate aurora mask layer, the deposition of the second oxide layer to fill the trenches and other vacancies on the horizontal silicon surface to form the shallow trench isolation-second oxide layer, and then the planarization of the shallow trench isolation-second oxide layer by chemical mechanical polishing technology.

FIG. 22 is a schematic diagram illustrating deposition and etching of a third oxide layer to form a third oxide spacer layer, formation of a lightly doped region in a substrate, deposition and etching back of a nitride layer to form a nitride spacer layer, and removal of a dielectric insulator.

Figure 23 is a schematic diagram illustrating the production of primary silicon using the selective epitaxial growth technology.

Figure 24 is a schematic diagram illustrating the deposition and etching of an oxide spacer layer to form contact hole openings.

FIG. 25 is a schematic diagram illustrating deposition and etching of a first metal layer to form first metal layer interconnects.

The present invention discloses a new method for accurately controlling the linear dimension of the source (or drain) of a transistor, wherein the dimension can be as small as the minimum characteristic dimension Lamda (λ), that is, the transistor can be printed or manufactured on a wafer (e.g., a silicon wafer) without adding a misalignment tolerance Delta-Lamda (△λ). Furthermore, a contact hole with a linear dimension less than λ can be realized in the drain (or source) of the transistor. Therefore, the present invention produces a new structure of source and drain with a minimum characteristic dimension, wherein the minimum characteristic dimension is from the edge of the gate structure of the transistor to the edge of the source (or drain) next to the edge of the transistor isolation region, and there are contact holes with a linear dimension less than λ on the source and the drain. Therefore, the present invention can avoid the misalignment tolerance caused by the photolithography mask technology when forming the source and the drain.

Please refer to FIG. 1. FIG. 1 is a top view of a miniaturized MOSFET 100 disclosed in an embodiment of the present invention. As shown in FIG. 1, the MOSFET 100 includes: (1) a gate structure 101, wherein the gate structure 101 has a length G(L) and a width G(W), (2) on the left side of the gate structure 101 is a source 103, wherein the source 103 has a length S(L) and a width S(W), and the length S(L) is from the edge of the gate structure 101 to an isolation region 103. 05, (3) on the right side of the gate structure 101 is a drain 107, wherein the drain 107 has a length D(L) and a width D(W), and the length D(L) is a linear dimension from the edge of the gate structure 101 to the edge of the isolation region 105, (4) in the center of the source 103, is a self-alignment technique. The contact hole 109 is formed by the self-alignment technology, wherein the length and width of the contact hole 109 are C-S (L) and C-S (W), respectively. (5) Similarly, in the center of the drain 107, there is a contact hole 111 formed by the self-alignment technology, wherein the length and width of the contact hole 111 are C-D (L) and C-D (W), respectively.

To form the MOSFET 100, a first photolithography process can be used to define the width G(W) and the pseudo length of an active region, and a second photolithography process can be used to define the length G(L) in the active region, wherein the second photolithography process can be used to control the length S(L) between the gate structure 101 and the isolation region 105. In one embodiment of the present invention, the pseudo length of the active region defined by the first photolithography process is approximately 4 times the minimum feature length λ. In one embodiment of the present invention, the length G(L) can be equal to or substantially equal to the minimum feature length λ. Of course, in other embodiments, the length G(L) can be greater than the minimum feature length λ.

The first feature of the present invention is that both the length S(L) and the length D(L) can be accurately designed and defined according to a target size, wherein the target size can be manufactured on the surface of a wafer and will not be affected by unavoidable photolithographic misalignment tolerances (PMT).

A second feature of the present invention is that both the length S(L) and the length D(L) can be as small as a minimum feature length λ, which is a specific process limit defined at a process node (e.g., the minimum feature length λ is 7 nm at a 7 nm node, or 28 nm at a 28 nm node, or 180 nm at a 180 nm node).

The third feature of the present invention is that if the length G(L) is designed to be λ, the minimum dimension along the length direction of the MOSFET 100 (i.e., the distance from the left edge of the source 103 to the right edge of the drain 107) can be as small as 3λ (i.e., 1λ is the length S(L), 1λ is the length D(L), and 1λ is the length G(L)). Then the linear dimension of the MOSFET 100 along the length direction can be miniaturized. When the linear dimension of the MOSFET 100 along the length direction does not include the isolation region 105, the linear dimension of the MOSFET 100 along the length direction is reduced to only 3λ.

A fourth feature of the present invention is that the length S(L) and the length D(L) can create a narrower length C-S(L) of the contact hole 109 and a narrower length C-D(L) of the contact hole 111 without being limited by the lithography misalignment tolerance (because most of the key mask steps for manufacturing the contact holes 109 and the contact holes 111 are eliminated), and other lengths S(L) and length D(L) can be clearly defined by self-alignment technology. Furthermore, the deposited interconnect layer of the first metal layer (metal-1) can be effectively defined by the photolithographic masking technique to achieve a narrower width of the first metal layer (i.e., the sum of the contact hole opening and twice the photolithographic misalignment tolerance), wherein the deposited interconnect layer can fully fill the contact hole 109 and the contact hole 111 to produce native metal contacts connecting the first metal layer to the source 103 and the drain 107, respectively.

As described above, the minimum device length dimension of the MOSFET structure (including the isolation region and the interconnection of the first metal layer) can be miniaturized without being enlarged by the unavoidable lithography misalignment tolerance.

Please refer to Figures 2A, 2B, 2C, 2D, 2E, 2F, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, and 19. Figure 2A is a flow chart of a method for manufacturing a miniaturized MOSFET disclosed in another embodiment of the present invention. The method for manufacturing the MOSFET in Figure 2A can accurately control the length of the source and drain of the MOSFET. The detailed steps of the manufacturing method are as follows: Step 10: Start; Step 20: Form an active region and a trench structure on the substrate 102; Step 30: Form a dummy shield gate and a true gate of the MOSFET on the horizontal silicon surface (HSS) of the substrate 102; gate); Step 40: replace the dummy shielding gate with an isolation region to define the source/drain boundary of the MOSFET; Step 50: form the source and the drain of the MOSFET; Step 60: form a smaller contact hole within the boundary of the source and the drain, and form a first metal layer interconnect to contact the source or the drain through the contact hole; Step 70: end.

Please refer to FIG. 2B and FIGS. 3 and 4. Step 20 may include: Step 202: forming a liner oxide layer 302 on the substrate 102 and depositing a liner nitride layer 304; Step 204: defining the active region of the MOSFET and removing part of the silicon material outside the active region to manufacture the trench structure; Step 206: depositing a first oxide layer in the trench structure and etching back the first oxide layer to form a shallow trench isolation-first oxide layer 306 (shallow trench) below the horizontal silicon surface HSS. isolation-oxide-1, STI-oxide-1); Step 207: remove the pad oxide layer 302 and the pad nitride layer 304, and form a dielectric insulation layer 402 above the horizontal silicon surface HSS.

Please refer to FIG. 2C and FIG. 6. Step 30 may include: Step 208: depositing a gate layer 602 and a nitride layer 604 on the horizontal silicon surface HSS; Step 210: etching the gate layer 602 and the nitride layer 604 to form a true gate and a dummy shielding gate of the MOSFET, wherein the dummy shielding gate has a desired linear distance to the true gate.

Please refer to FIG. 2D and FIGS. 7, 8, 9, and 10. Step 40 may include: step 212: depositing a spin-on dielectric layer (SOD) 702, and then etching back the spin-on dielectric layer 702; step 214: forming a well-designed gate anode mask layer 802 by the photolithography mask technology; step 216: using anisotropic etching technology (anisotropic etching technology) Technique) removes the nitride layer 604 on the dummy shielding gate DSG, and removes the dummy shielding gate DSG, the dielectric insulation layer 402 corresponding to the dummy shielding gate DSG, and the substrate 102 corresponding to the dummy shielding gate DSG; Step 218: removes the gate mask layer 802, etches the spin-on dielectric layer 702, and deposits a second oxide layer, and then etches back the second oxide layer to form a shallow trench isolation-second oxide layer 1002.

Please refer to FIG. 2E and FIGS. 15, 16, and 17. Step 50 may include: Step 220: depositing and etching back a third oxide layer to form a third oxide spacer layer 1502, forming a lightly doped drain (LDD) 1504 in the substrate 102, depositing and etching back a nitride layer to form a nitride spacer layer 1506, and removing the dielectric insulating layer 402; Step 222: using a selective epitaxy growth (SEG) technique to generate an intrinsic silicon (intrinsic silicon) 1602; Step 224: Deposition and etching back a chemical vapor deposition-shallow trench isolation-third oxide layer 1702, remove the intrinsic silicon 1602, and form the source (n+ source) 1704 and drain (n+ drain) 1706 of the metal oxide semi-conductor field effect transistor.

Please refer to FIG. 2F and FIGS. 18 and 19. Step 60 may include: step 226: depositing and etching an oxide spacer layer 1802 to form contact-hole openings on the source (n+ source) 1704 and the drain (n+ drain) 1706; step 228: depositing and etching a first metal layer 1902 to form the first metal layer interconnection.

Part 1: Using a dummy-shield-gate (DSG) added to the gate mask and avoiding the lithography misalignment tolerance to achieve a designed distance GEBESI from the edge of the gate to the boundary edge between the source and the isolation region. Similarly, there is also a designed distance GEBEDI from the edge of the gate to the boundary edge between the drain and the isolation region.

Taking an n-type MOSFET as an example, the substrate 102 may be a p-type substrate, and the detailed description of the aforementioned manufacturing method is as follows. Starting from step 20, please refer to FIG. 2B and FIGS. 3 and 4. In step 202, a pad oxide layer 302 is formed on the horizontal silicon surface HSS of the substrate 102, and then a pad nitride layer 304 is deposited on the pad oxide layer 302.

In step 204, the active region of the MOSFET can be defined by the photolithography mask technology, resulting in the horizontal silicon surface HSS outside the active region being exposed. Because the horizontal silicon surface HSS outside the active region is exposed, part of the silicon material outside the active region can be removed by the anisotropic etching technology to manufacture the trench structure.

In step 206, the first oxide layer is deposited to fill the trench structure, and then the first oxide layer is etched back to form a shallow trench isolation-first oxide layer 306 below the horizontal silicon surface HSS, as shown in FIG. 4. FIG. 4 is a cross-sectional view along the X-axis direction shown in FIG. 3. In addition, because FIG. 3 is a top view, FIG. 3 only shows the liner nitride layer 304 and the shallow trench isolation-first oxide layer 306. Then, in step 207, the liner oxide layer 302 and the liner nitride layer 304 on the active region are removed, and a dielectric insulation layer 402 (with a high dielectric constant) is formed above the horizontal silicon surface HSS.

FIG5 is a schematic diagram of the prior art for realizing the geometric relationship between the gate and the transistor isolation region at a relatively small size. After forming a dielectric insulating layer 402 on the horizontal silicon surface HSS, a gate layer 404 (metal gate) is deposited on the dielectric insulating layer 402. Then a nitride layer 406 (nitride cap layer) with a well-designed thickness is deposited on the gate layer 404. Next, as shown in FIG. 5, the photolithography mask technology is used to define the gate structure 1, wherein the gate structure 1 includes a gate layer 404 and a nitride layer 406 so that the gate structure 1 has a suitable metal gate material, and the metal gate material can provide the work function required for the metal insulator to the substrate 102 to achieve the appropriate critical voltage of the metal oxide semi-conductor field effect transistor. In addition, because the shallow trench isolation-first oxide layer 306 is formed below the horizontal silicon surface HSS, a tri-gate transistor (Tri-gate FET) structure or a fin field-effect transistor (FinFET) structure can be formed (as shown in FIG. 5).

After using the first photolithography process to define the pseudo length of the active region and using the second photolithography process to define the length G (L) of the active region, the distance from the edge of the gate structure 1 to the boundary edge between the source of the MOSFET and the shallow trench isolation (called GEBESI) can be defined (as shown in Figure 5). Similarly, the distance from the edge of the gate structure to the boundary edge between the drain of the MOSFET and the shallow trench isolation (called GEBEDI) can also be defined.

However, as shown in FIG. 5 , when the edge of the gate structure 1 and the boundary edge between the source of the MOSFET (or the drain of the MOSFET) and the shallow trench isolation-first oxide layer 306 are aligned using the photolithography mask technology, there is an unavoidable non-ideal factor, called the photolithography misalignment tolerance. If the linear dimension of the photolithography misalignment tolerance measured along the X-axis direction is Δλ, then Δλ should be related to the minimum feature size specified by the photolithography resolution of the equipment available for a specific process node. For example, the minimum feature size λ of the 7nm process node should be equal to 7nm and the photolithography misalignment tolerance Δλ can be 3.5nm. Therefore, if the desired actual size of the source of the MOSFET (or the drain of the MOSFET) is set to λ (e.g., 7 nanometers), then in the prior art process method, the required length of the source of the MOSFET (or the drain of the MOSFET) must be greater than the sum of λ and Δλ (e.g., greater than 10.5 nanometers).

Therefore, the present invention utilizes a new structure to eliminate the negative effects caused by the photolithography misalignment tolerance. That is to say, any dimension of the distance GEBESI from the edge of the gate structure to the boundary edge between the source of the MOSFET and the shallow trench isolation (or the distance GEBEDI from the edge of the gate structure to the boundary edge between the drain of the MOSFET and the shallow trench isolation) can be realized without reserving additional dimensions for the photolithography misalignment tolerance along the length direction of the MOSFET (that is, the X-axis direction as shown in Figures 4 and 5).

In step 208, as shown in FIG. 6, after forming a dielectric insulating layer 402 on the horizontal silicon surface HSS, a gate layer 602 and a nitride layer 604 are deposited. Then in step 210, the gate layer 602 and the nitride layer 604 are etched to form the gate structure (wherein the gate layer 602 can be the gate structure of the MOSFET). The main difference between the new structure shown in FIG. 6 and the structure shown in FIG. 5 is that when the true gate TG of the MOSFET is defined by the photolithography mask technology, the dummy shielding gate DSG parallel to the true gate TG can also be defined as required so that a target linear distance (e.g., λ, 7 nm in a 7 nm process node) can exist between the dummy shielding gate DSG and the true gate TG without having to reserve any additional dimension (i.e., Δλ) for the photolithography misalignment tolerance. The dummy shielding gate DSG and the true gate TG designed on the same mask can be formed simultaneously on top of the dielectric insulation layer 402 covering the active region. In addition, as shown in Figure 6, true gates TG2 and TG3 correspond to other MOSFETs.

The next step is to explain how to replace the pseudo shielding gate DSG with an isolation region raised above the horizontal silicon surface HSS. In step 212, as shown in FIG. 7, a spin-on dielectric layer 702 is deposited, and then the spin-on dielectric layer 702 is etched back using a chemical mechanical polishing (CMP) technique so that the top of the spin-on dielectric layer 702 is the same height as the top of the nitride layer 604.

In step 214, as shown in FIG. 8, a gate anode mask layer 802 is deposited, and then the gate anode mask layer 802 is etched by the photolithography mask technology to cover the true gates TG, TG2, and TG3 but expose the dummy shielding gate DSG, wherein the exposed dummy shielding gate DSG has a safe photolithography misalignment tolerance △λ in the middle of the length from GEBESI and the length from GEBEDI, respectively.

For clarity, in FIG. 8 , the distance between the true gate TG under the gate anode mask layer 802 and the dummy shielding gate DSG on the left may be marked as GEBESI, and the distance between the true gate TG under the gate anode mask layer 802 and the dummy shielding gate DSG on the right may be marked as GEBEDI. Because after replacing the dummy shielding gate DSG with the isolation region shown in the following Figures 9-10, the distance between the true gate TG and the dummy shielding gate DSG in Figure 8 will become the distance from the edge of the true gate TG to the source of the MOSFET (or the drain of the MOSFET) and the boundary edge between the isolation region, which is GEBESI (or GEBEDI) mentioned previously in Figure 5.

In step 216, as shown in FIG. 9(a), the anisotropic etching technique may be used to etch the dummy shielding gate DSG and the nitride layer 604 corresponding to the dummy shielding gate DSG, and may also be used to etch the dielectric insulation layer 402 corresponding to the dummy shielding gate DSG to reach the horizontal silicon surface HSS. Then, the anisotropic etching technique is used to remove the silicon material of the substrate 102 below the horizontal silicon surface HSS to form a trench 902 below the horizontal silicon surface HSS, wherein the depth of the trench 902 may be equal to the depth of the bottom of the shallow trench isolation-first oxide layer 306. Therefore, as shown in FIG. 9(a), the lithography misalignment tolerance is avoided in creating the precisely controlled distance GEBESI and distance GEBEDI, respectively. Because the lengths of the distance GEBESI and the distance GEBEDI are well defined by the true gate TG and the dummy shielding gate DSG on the same mask, the length S(L) of the source and the length D(L) of the drain shown in FIG. 1 can be well defined. That is, the single lithography mask technology is not only used to define the true gate TG and the dummy shielding gate DSG, but also to control the lengths of the distance GEBESI and the distance GEBEDI. Therefore, the size of the length S(L) and the length D(L) can be accurately controlled, and even the optimal miniaturization size as small as the minimum feature size λ can be achieved. Since the length S(L) and the length D(L) can be equal to λ, the length S(L) and the length D(L) are substantially equal to the length of the true gate TG (that is, the gate structure). In addition, Figure 9(b) is a top view corresponding to Figure 9(a).

In step 218, as shown in FIG. 10(a), the gate aurora mask layer 802 and the spin-on dielectric layer 702 are removed, and then a second oxide layer is deposited to fill the trench 902 and other vacancies of the horizontal silicon surface HSS. Then, the second oxide layer can be etched back to the same surface height as the horizontal silicon surface HSS to form a shallow trench isolation-second oxide layer 1002. FIG. 10(b) is a top view corresponding to FIG. 10(a).

Therefore, the temporarily formed pseudo shielding gate DSG can be replaced by a shallow trench isolation-second oxide layer 1002 to define the source/drain boundary. Then, any existing technology capable of forming a lightly doped drain (LDD), a spacer layer surrounding the true gate TG, the source, and the drain can be used to complete the MOSFET, wherein the source and the drain can be formed according to the accurately controlled distances GEBESI and GEBEDI, respectively.

Part II: Using the dummy shielding gate DSG design principle, the target lengths of distance GEBESI and distance GEBEDI are achieved for a deformable active area (on an active area (AA) mask) through an adaptive dummy shielding gate design.

Because the shape of an isolation region of a transistor and the location of the isolation region between the transistor and an adjacent transistor may vary greatly (even in the above-mentioned embodiment), another structure will be described below, which is designed by extending the principles of the above-mentioned embodiment to design an adaptive pseudo-shielding gate.

FIG. 11 illustrates a layout geometry of an active region of a neighboring transistor, wherein the layout geometry of the active region of the neighboring transistor is different from FIG. 6. For example, as shown in FIG. 6, before the true gate TG, true gate TG2, true gate TG3 and dummy shielding gate DSG are deposited, the adjacent active regions of the neighboring transistor are connected. The connected active regions can then be divided into individual precise target distances by the length of the dummy shielding gate DSG. However, as shown in FIG. 11 , it is assumed that the active region on the source (or drain) of the transistor is completely isolated from any other active region by the isolation region 1102 before and after the true gate of the transistor is defined. Therefore, as described below, it is proposed here how to design the active region on the source and the adaptive pseudo shielding gate DSG (the same is true for the drain). For example, if the final length of the distance GEBESI is set to λ (or any other target length L(S)), the length of the active region mask (AA mask) corresponding to the distance GEBESI should be designed to be equal to the sum of λ and Δλ (or the sum of the length L(S) and Δλ). Then on the gate mask, the dummy shielding gate DSG can have a shape as shown in FIG. 11, that is, the length of the rectangular shape of the dummy shielding gate DSG is equal to λ, and the width is equal to the sum of the width of the active region and 2△λ (each side shares 0.5△λ). In addition, the design distance between the true gate TG and the dummy shielding gate DSG on the source side is still exactly the length of the distance GEBESI (e.g., λ).

The results derived from the mask stage to the wafer stage of the active region and gate of FIG. 11 are depicted in FIG. As shown in FIG. 12, when the true gate TG is defined by the photolithography mask technology, the dummy shielding gate DSG is designed to be parallel to the true gate TG, and there is a target distance (e.g., λ, where λ is 7 nm in the 7 nm process node) between the dummy shielding gate DSG and the true gate TG. As a result of the nominal process (i.e., no obvious misalignment is introduced in the photolithography process), the dummy shielding gate DSG covers the active region (corresponding to the source) at a distance of △λ, and both the true gate TG and the dummy shielding gate DSG are disposed above the dielectric insulating layer 402 covering the active region. In addition, there is a nitride cap layer (i.e., nitride layer 604) above the true gate TG and the dummy shielding gate DSG.

As shown in FIG. 13 , if the lithography misalignment tolerance causes a displacement (e.g., △λ) to the right of the active region for both the true gate TG and the dummy shielding gate DSG, the next process is to remove the dummy shielding gate DSG to realize the isolation region STI-oxide-2 (i.e., shallow trench isolation-second oxide layer 1002), wherein the position of the isolation region STI-oxide-2 is exactly the position of the originally existing dummy shielding gate DSG described in the process steps of the first part. In addition, the subsequent process can make the length of the isolation region STI-oxide-2 λ, and the isolation region STI-oxide-2 can become the physical geometry of the source, where the length of the distance GEBESI between the true gate TG and the source is equal to λ (because the distance between the true gate TG and the dummy shielding gate DSG is designed to be λ). On the other hand, as shown in FIG. 14, if the lithography misalignment tolerance causes a displacement (e.g., Δλ) to the left of the active region for both the true gate TG and the dummy shielding gate DSG, the subsequent process steps for removing the dummy shielding gate DSG and forming the isolation region STI-oxide-2 will make the length of the isolation region STI-oxide-2 λ, and the length of the distance GEBESI between the true gate TG and the source still equal to λ.

When the lithography misalignment tolerance causes an undesirable displacement along the width direction of the active region (i.e., the up and down direction), the design of the adaptive pseudo-shielding gate (the width of the pseudo-shielding gate is the sum of the width of the active region and 2△λ) will not affect the geometric size of the active region. This innovative design using an adaptive pseudo-shielding gate always produces an isolation region STI-oxide-2 with a length λ, and produces a length from GEBESI that meets the design target (e.g., λ). The present invention can certainly be applied to all different shapes of isolation regions, sources, and drains with respective target lengths.

Part 3: The precisely defined source (or drain) can be precisely controlled through the self-aligned spacer layer to reduce the steps of contact mask and hole opening process.

After disclosing how to optimally design and manufacture the distance GEBESI and the distance GEBEDI to precisely controlled small dimensions (as small as λ), another new invention is how to manufacture contact hole openings with lengths C-S(L) and C-D(L), respectively, where the lengths C-S(L) and C-D(L) are smaller than the distance GEBESI and the distance GEBEDI, respectively. The following will describe two designs and processes.

A. Design and Process (I)

Please continue to refer to FIG. 10(a) and use the true gate TG for the following description. In step 220, as shown in FIG. 15(a), the third oxide layer is deposited and etched back to form a third oxide spacer 1502, wherein the third oxide spacer 1502 covers the true gate TG. Then, a lightly doped region is formed in the substrate 102, and rapid thermal annealing (RTA) is performed on the lightly doped region to form a lightly doped drain 1504 next to the true gate TG. The nitride layer is then deposited and etched back to form a nitride spacer layer 1506, wherein the nitride spacer layer 1506 covers the third oxide spacer layer 1502. The dielectric insulating layer 402 not covered by the nitride spacer layer 1506 and the third oxide spacer layer 1502 is then removed. In addition, FIG. 15(b) is a top view corresponding to FIG. 15(a).

In step 222, as shown in FIG. 16(a), by using the exposed horizontal silicon surface HSS as a silicon seed, the intrinsic silicon 1602 is generated only above the exposed horizontal silicon surface HSS using the selective epitaxial growth technology, and the height of the intrinsic silicon 1602 is the same as the top of the nitride layer 604 (above the top of the true gate TG). In addition, FIG. 16(b) is a top view corresponding to FIG. 16(a).

In step 224, as shown in FIG. 17(a), a CVD-STI-tertiary oxide layer 1702 is deposited to fill all vacancies, and the CVD-STI-tertiary oxide layer 1702 is planarized by chemical-mechanical polishing (CMP) technology so that the height of the CVD-STI-tertiary oxide layer 1702 is flush with the top of the nitride layer 604, wherein the nitride layer 604 is above the top of the true gate TG. Next, the intrinsic silicon 1602 is removed to expose the horizontal silicon surface HSS corresponding to the source and the drain, wherein the horizontal silicon surface HSS corresponding to the source and the drain is surrounded by the chemical vapor deposition-shallow trench isolation-third oxide layer 1702 and the nitride spacer layer 1506.

The intrinsic silicon 1602 is used like a self-alignment pillar (SPR) to surround or seal the area where a contact hole will be configured later, but the self-alignment pillar is not limited to silicon material. According to the material of the seed used for the selective epitaxial growth technology, the self-alignment pillar can be a metal material or other semiconductor material (for example: silicon carbide (SiC), silicon germanium (SiGe), (gallium nitride GaN), etc.). In addition, the substrate 102 can be a silicon substrate, a silicon carbide substrate, a silicon germanium substrate, or a gallium nitride substrate, etc.

Any existing technology capable of forming the source (n+ source) 1704 and the drain (n+ drain) 1706 of the MOSFET can use the horizontal silicon surface HSS to realize the flat surface of the source 1704 and the drain 1706, wherein the source (n+ source) 1704 can be a first conductive region, and the drain (n+ drain) 1706 can be a second conductive region. In addition, as shown in FIG. 17(a), a channel region exists between the lightly doped drains 1504 and below the horizontal silicon surface HSS, and the channel region can electrically couple the source (n+ source) 1704 and the drain (n+ drain) 1706. In addition, as shown in FIG. 17(a), the source (n+ source) 1704 is placed on the gate structure (i.e., the true gate TG (gate layer 602)) and the shallow trench isolation-second oxide layer 1002 and the chemical vapor deposition-shallow trench isolation-third oxide layer 1002 on the left side of the gate structure. 702, wherein the shallow trench isolation-second oxide layer 1002 and the chemical vapor deposition-shallow trench isolation-third oxide layer 1702 on the left side of the gate structure can be called a first isolation region, and the first isolation region is adjacent to the first conductive region (that is, the source (n+ source) 1704). In addition, as shown in FIG. 17( a), the drain (n+ drain) 1706 is placed between the gate structure and the shallow trench isolation-second oxide layer 1002 and the chemical vapor deposition-shallow trench isolation-third oxide layer 1702 on the right side of the gate structure, wherein the shallow trench isolation-second oxide layer 1002 and the chemical vapor deposition-shallow trench isolation-third oxide layer 1702 on the right side of the gate structure can be referred to as a second isolation region, and the second isolation region is adjacent to the second conductive region (i.e., the drain (n+ drain) 1706). In addition, as shown in FIG. 17(a), it is very obvious that the first isolation region and the second isolation region extend upward and downward from the horizontal silicon surface HSS. In addition, FIG. 17(b) is a top view corresponding to FIG. 17(a).

In step 226, as shown in FIG. 18(a), because the chemical vapor deposition-shallow trench isolation-third oxide layer 1702 on the isolation region (i.e., the first isolation region and the second isolation region) and the nitride spacer 1506 surrounding the true gate TG are higher than the horizontal silicon surface HSS, like four sidewalls, a well-designed oxide spacer 1802 (referred to as oxide spacer for contact hole) is formed. A first contact hole 1804 may be formed outside the four sidewalls, wherein the first contact hole 1804 is located above the first conductive region (i.e., the source (n+source) 1704) and within the boundary of the source (n+source) 1704. Similarly, a second contact hole 1806 is located above the second conductive region (i.e., the drain (n+drain) 1706) and within the boundary of the drain (n+drain) 1706. Therefore, as shown in Figure 18(a), the first contact hole 1804 and the second contact hole 1806 are naturally formed in a self-aligned manner without the need to utilize any etching technology to manufacture the contact hole openings, and through the appropriate design of the oxide spacer layer used for the contact holes (having a thickness of tOSCH), the length of the contact hole opening can be less than the length of the distance GEBESI and the distance GEBEDI, respectively. The innovative part of the present invention is that the position of the contact hole opening is almost in the center of the boundary of the source 1704 (or the drain 1706), and the length of the contact hole opening can be designed to be less than λ (because the length of the contact hole opening = the length from GEBESI - 2 times the thickness tOSCH. So for example, if the thickness tOSCH = 0.2λ, the length from GEBESI = λ, then the length of the contact hole opening = 0.6λ). Therefore, because the length of the contact hole opening is mainly dominated by the thickness tOSCH of the oxide spacer layer 1802, the periphery of the first contact hole 1804 (and the second contact hole 1806) is independent of the photolithography mask technology, and as shown in FIG. 18(b), it can be clearly seen that the periphery of the first contact hole 1804 is within the periphery of the first conductive region, and the periphery of the second contact hole 1806 is within the periphery of the second conductive region.

In addition, as shown in FIG. 18( b ), because the length of the contact hole opening is less than λ, the length of the first contact hole 1804 (the length of the second contact hole 1806 ) is less than the length of the gate structure (because as shown in FIG. 6 , the length of the gate structure is equal to λ). In addition, as shown in FIG. 18( a), because the oxide spacer 1802 has a thickness of tOSCH and a length from GEBESI equal to the length of the gate structure, it is obvious that a horizontal distance between a first sidewall of the gate structure (located on the left side of the gate structure) and a sidewall of the first contact hole 1804 far from the gate structure is smaller than the length of the gate structure (i.e., λ). In addition, as shown in FIG. 18( a), a horizontal distance between a first sidewall of the gate structure and a sidewall of the first conductive region (i.e., the source 1704) far from the gate structure is approximately equal to the length of the gate structure. Similarly, as shown in FIG. 18(a), the horizontal distance between a second side wall of the gate structure (located on the right side of the gate structure) and a side wall of the second isolation region away from the gate structure is substantially equal to the length of the gate structure.

In addition, as shown in FIG. 18(a), an oxide spacer 1802 (i.e., a first spacer) located on the left side of the gate structure and close to the gate structure covers a first sidewall of the gate structure, and an oxide spacer 1802 (i.e., a second spacer) located on the left side of the gate structure and away from the gate structure covers a sidewall of the first isolation region, wherein a first contact hole 1804 is formed between the first spacer and the second spacer.

In addition, as shown in FIG. 18(a), the oxide spacer 1802 located on the right side of the gate structure and close to the gate structure (e.g., a third spacer) covers a second sidewall of the gate structure (located on the right side of the gate structure), and the oxide spacer 1802 located on the right side of the gate structure and farther from the gate structure (e.g., a fourth spacer) covers a sidewall of the second isolation region, wherein the second contact hole 1806 is formed between the third spacer and the fourth spacer.

In addition, as shown in FIG. 18(b), it is obvious that the periphery of the first contact hole 1804 is surrounded by the periphery of the first conductive region (or source 1704), the shape of the periphery of the first contact hole 1804 is similar to the shape of the periphery of the first conductive region, and the periphery of the first conductive region is similar to a rectangular shape. In addition, similar situations also apply to the second contact hole 1806 and the second conductive region (or drain 1706).

According to the present invention, the self-aligned contact holes (first contact holes 1804 and second contact holes 1806) show the minimum contact hole length (whose size can be less than λ), which is smaller than the length of any prior art design and the contact hole opening produced by the photolithography mask technology and complex etching process. In addition, the present invention omits most of the difficult-to-control factors and most of the expensive masks used to define and produce the first metal layer contacts (such as the first contact holes 1804 and the second contact holes 1806 for the source 1704 and the drain 1706, respectively) and the subsequent drilling of the contact hole openings. In addition, FIG. 18(b) is a top view corresponding to FIG. 18(a).

In step 228, as shown in FIG19, after the first metal layer 1902 is deposited to fill the contact holes (the first contact hole 1804 and the second contact hole 1806), the photolithography mask technology can be used to define the first metal layer 1902. As shown in FIG19, the first metal layer 1902 must have a width with a precisely controlled size, wherein the width of the first metal layer 1902 must be able to completely cover the contact hole opening and reserve any unavoidable photolithography misalignment tolerance. That is to say, the width of the first metal layer 1902 corresponding to the source 1704 is equal to the length C-S(L) of the contact hole opening (on the source 1704) plus 2△λ, and the width of the first metal layer 1902 corresponding to the drain 1706 is equal to the length C-D(L) of the contact hole opening (on the drain 1706) plus 2△λ. If the length of the contact hole opening can be controlled at 0.6λ (which should be controllable, because the size of the oxide spacer layer 1802 in the contact hole can be well controlled according to the calculation described above), the width of the first metal layer 1902 can be as small as the sum of the length of the contact hole opening and 2Δλ (if in one embodiment of the present invention, Δλ=0.5λ (that is, half the length of the gate structure) , the length of the contact hole opening = 0.6λ, then in order to completely cover the contact hole opening under the unavoidable lithography misalignment tolerance, the width of the first metal layer 1902 can be as narrow as 1.6λ. That is to say, in order to completely cover the contact hole opening under the unavoidable lithography misalignment tolerance, the width of the first metal layer 1902 can be equal to the length of the first contact hole 1804 plus the length of the gate structure). According to the present invention, the width of the first metal layer 1902 as narrow as 1.6λ can be one of the minimum widths of the first metal layer interconnection. In addition, a minimum space 1904 between two closest first metal layer interconnections cannot be less than λ. In addition, as shown in FIG. 19, the first metal layer 1902 (i.e., a first metal region) is filled in the first contact hole 1804 and contacts the first conductive region (i.e., the source 1704), wherein the first metal region extends upward from the first conductive region to a predetermined position, and the predetermined position is higher than the top of the nitride layer 604 (i.e., the nitride cap layer).

In addition, as shown in Figure 20, if there is no adjacent first metal layer interconnect for the source (and/or drain), for example, using a merged semiconductor junction and metal conductor (MSMC) structure (disclosed in U.S. Patent Application No. 16/991,044, filed on August 12, 2020, cited herein in its entirety), the width of the chemical vapor deposition-shallow trench isolation-third oxide layer 1702 defined by the pseudo-shielding gate can be made as small as the minimum feature size λ without being limited by the space between any adjacent first metal layer interconnects, where the source (and/or drain) is grounded and directly connected to the substrate 102 of the MOSFET. In addition, as shown in FIG. 20, the source includes a first semiconductor region (n+ heavily doped semiconductor region) 1906 and a first metal-containing region 1908, and the drain includes a second semiconductor region (n+ heavily doped semiconductor region) 1910 and a second metal-containing region 1912, wherein a first oxide guard layer (OGL) 1914 only covers one side wall of the first metal-containing region 1908, but does not cover the bottom of the first metal-containing region 1908, and a second oxide guard layer 1916 (in the groove shown in FIG. 20) covers one side wall and the bottom of the second metal-containing region 1912. Therefore, the first metal-containing region 1908 is coupled to the substrate 102 through the bottom of the first metal-containing region 1908.

The important advantage of the present invention is that almost every critical dimension, such as the length of the distance GEBESI and the distance GEBEDI, the length of the contact hole opening, and the width of the first metal layer interconnection can be precisely controlled without being affected by the uncertain photolithography misalignment tolerance. In this way, based on the consistency of the critical dimensions, the repeatability, quality and reliability of each critical dimension can be ensured.

B. Design and Process (II)

The above principle will continue to be adopted in the following embodiments, but the difference lies in how to form the spacer layer and the contact hole opening. Continuing with FIG. 9(a), as shown in FIG. 21(a), the gate aurora mask layer 802 is removed, and then the second oxide layer is deposited to fill the trench 902 and other vacancies above the horizontal silicon surface HSS to form a shallow trench isolation-second oxide layer 2102. Then, the shallow trench isolation-second oxide layer 2102 is planarized by the chemical mechanical polishing technology to make the top of the shallow trench isolation-second oxide layer 2102 flush with the top of the spin-on dielectric layer 702 and the top of the nitride layer 604, wherein the nitride layer 604 is above the true gate TG. In addition, FIG. 21(b) is a top view corresponding to FIG. 21(a).

Then, as shown in FIG. 22( a), the spin-on dielectric layer 702 is removed. Then, the third oxide layer is deposited, and the third oxide layer is etched back using the anisotropic etching technique to form a third oxide spacer 2202, wherein the third oxide spacer 2202 covers the true gate TG. Then, a lightly doped region is formed in the substrate 102, and a rapid thermal annealing is performed on the lightly doped region to form the lightly doped drain 2204 next to the true gate TG. Then, the nitride layer is deposited and etched back to form a nitride spacer 2206, wherein the nitride spacer 2206 covers the third oxide spacer 2202. Then, the dielectric insulating layer 402 under the existing spin-on dielectric layer 702 is removed. In addition, FIG. 22(b) is a top view corresponding to FIG. 22(a).

Next, as shown in FIG. 23( a), by using the exposed horizontal silicon surface HSS region as a silicon seed, a native silicon 2302 is generated only above the exposed horizontal silicon surface HSS using the selective epitaxial growth technology, wherein the height of the native silicon 2302 is flush with the top of the nitride layer 604, and the nitride layer 604 is above the top of the true gate TG. Different from the aforementioned paragraph A of the third part, the shape of the intrinsic silicon 2302 grown by the selective epitaxial growth can be better controlled because two sides of the intrinsic silicon 2302 are sandwiched between the shallow trench isolation-second oxide layer 2102 and the true gate TG, and the other two sides of the intrinsic silicon 2302 face the air above the cliff edge of the active region, wherein the active region is still covered by the dielectric insulation layer 402 and above the adjacent shallow trench isolation-first oxide layer 306 (STI-oxide-1). Then, a chemical vapor deposition-shallow trench isolation-third oxide layer 2304 is deposited (as shown in FIG. 23(b)) to fill all the gaps, and the top of the chemical vapor deposition-shallow trench isolation-third oxide layer 2304 is planarized by the chemical mechanical polishing technology to make the top of the nitride layer 604 (above the top of the true gate TG) flush. In addition, FIG. 23(b) is a top view corresponding to FIG. 23(a).

In addition, as shown in FIG. 24( a), the intrinsic silicon 2302 is removed to expose a horizontal silicon surface HSS corresponding to a source (n+ source) 2402 and a drain (n+ drain) 2404 region, wherein the source 2402 and the drain 2404 are surrounded by two walls of the chemical vapor deposition-shallow trench isolation-third oxide layer 2304, one wall of the nitride spacer 2206 on the shallow trench isolation-second oxide layer 2102, and one wall of the nitride spacer 2206 surrounding the true gate TG. Any existing technology capable of forming the source 2402 and drain 2404 of the MOSFET can use the horizontal silicon surface HSS to realize the flat surface of the source 2402 and drain 2404.

As shown in FIG. 24( a), because the two walls of the CVD-shallow trench isolation-third oxide layer 2304, the nitride spacer 2206 on the shallow trench isolation-second oxide layer 2102, and the nitride spacer 2206 surrounding the true gate TG are higher than the horizontal silicon surface HSS like four sidewalls, another well-designed four oxide spacers 2406 (called oxide spacer for contact hole (oxide-SCH)) can be newly created to cover the four sidewalls. Therefore, the contact hole opening is naturally formed in a self-aligned manner without utilizing any etching technology for making the contact hole opening, and by a suitable design of the oxide spacer layer (oxide-SCH) for the contact hole (having a thickness tOSCH), the length dimension of the contact hole opening can be less than the lengths from GEBESI and from GEBEDI, respectively. The innovative part of the present invention is that the position of the contact hole opening is at the center of the boundaries of the source and the drain, respectively, and the length of the contact hole opening can be designed to be less than λ (because the length of the contact hole = the length from GEBESI - 2 times the thickness tOSCH. So for example, if the thickness tOSCH = 0.2λ and the length from GEBESI = λ, then the length of the contact hole = 0.6λ). According to the present invention, the self-aligned contact hole shows a minimum contact hole length (whose size can be less than λ), which is smaller than any prior art design and the length of the contact hole opening produced by the photolithography mask technology and complex etching process. In addition, the present invention omits most of the difficult-to-control factors and most of the expensive masks used to define and produce the first metal layer contact and the subsequent task of drilling the contact hole opening. In addition, Figure 24(b) is a top view corresponding to Figure 24(a).

FIG. 25 is a schematic diagram illustrating the use of the photolithography mask technology to define the first metal layer 2502 after depositing the first metal layer 2502 to fill the contact hole opening. As shown in FIG. 25, the first metal layer 2502 must have a width with a precisely controlled size, wherein the width of the first metal layer 2502 must be able to completely cover the contact hole opening and reserve any unavoidable photolithography misalignment tolerance. That is to say, the width of the first metal layer 2502 corresponding to the source is equal to the length C-S(L) of the contact hole opening (on the source) plus 2△λ, and the width of the first metal layer 2502 corresponding to the drain is equal to the length C-D(L) of the contact hole opening (on the drain) plus 2△λ. If the length of the contact hole opening can be controlled at 0.6λ (which should be controllable, because it can be known from the calculation described above that the size of the oxide spacer 2406 in the contact hole can be well controlled), the width of the first metal layer 2502 can be as small as the sum of the length of the contact hole opening and 2Δλ (if in one embodiment of the present invention, Δλ=0.5λ, the length of the contact hole opening=0.6λ, then in order to completely cover the contact hole opening under the unavoidable lithography misalignment tolerance, the width of the first metal layer 2502 can be as narrow as 1.6λ. According to the present invention, a width as narrow as 1.6 The width of the first metal layer 2502 of λ can be one of the minimum widths of the first metal layer interconnection. In addition, a minimum space 2504 between two closest first metal layer interconnections cannot be less than λ. In addition, an important advantage of the present invention is that almost every critical dimension, such as the length of the distance GEBESI and the distance GEBEDI, the length of the contact hole opening, and the width of the first metal layer interconnection can be accurately controlled without being affected by the uncertain photolithography misalignment tolerance. In this way, based on the consistency of the critical dimensions, the reproducibility, quality and reliability of each critical dimension can be ensured.

In summary, the MOSFET structure disclosed in the embodiment of the present invention can avoid the tolerance of photolithography misalignment, especially the geometric relationship between the gate and the source, the gate and the drain, the first metal layer and the contact hole opening between the source/drain, and the width of the first metal layer interconnection and the self-alignment method of filling the contact hole, etc., which brings several major improvements to the design of future integrated circuits:

(1) By eliminating the uncertainty caused by the photolithography misalignment tolerance, the length S(L) and length D(L) of the two edges of the gate are accurately defined.

(2) Both the length S(L) and the length D(L) can be designed to be the minimum feature length λ allowed by the lithography mask and process resolution, thereby significantly reducing the size of the source and the drain. In this way, the area of the MOSFET can be reduced and the standby and operating current and power consumption can be reduced, thereby increasing the operating speed of the MOSFET.

(3) Because the length S(L) and the length D(L) can be precisely controlled, the self-alignment technology of the present invention can precisely manufacture self-alignment contact holes (SACH) with controllable shapes and sizes and close to the center of the source and the drain, respectively, through the spacer created by the four side walls surrounding the source and the drain.

(4) The length of the self-aligned contact hole can be designed to be smaller than the minimum feature size λ, for example as small as 0.6λ or even narrower.

(5) Other width dimensions of the self-aligned contact hole can be well designed by the self-aligned spacer layer and the well-defined active area width; because the self-aligned contact hole is formed by the spacer layer technology, which depends on the well-developed technology of using chemical film deposition with controllable thickness and utilizing the anisotropic etching technology, rather than the existing technology of defining the contact hole by photolithography mask technology with difficult to control misalignment tolerance and contact hole shape. The contact hole opening of the present invention can be well designed and defined (although the contact hole may not have a consistent square contact shape, the contact hole has a well-defined rectangular shape and the filling result is actually determined by the narrower length dimension of the contact hole).

(6) Eliminate the most difficult and expensive contact steps and masks.

(7) Completely separate a square hole or multiple square holes from multiple contact holes to a single rectangular contact hole or a single contact trench to change the contact hole design; thus, the width (or length) of the source (or the drain) can be exactly the same as the width (or length) of the gate without being limited to using a dog-bone layout to adjust the size difference between the width of the gate and the width of the source (or the drain) that may have multiple square contact holes.

(8) Since the success of filling the first metal layer interconnect with a well-designed thickness depends on the minimum size of the contact hole (usually the length of the self-aligned contact (SACH) hole), the first metal layer interconnect can actually fill all existing contact holes, so that the two steps used in the prior art to form contact pillars (such as filling with tungsten plus a planarization process, that is, the tungsten pillar process and the first metal layer embedding process disclosed in the prior art) can be simplified into a first metal layer deposition process.

(9) Through the above-mentioned integrated self-aligned contact hole and the first metal layer formation process and the gate being covered under the nitride cap layer and protected by the spacer layer (wherein the nitride cap layer and the spacer layer can both create a flat surface on the area outside the self-aligned contact hole), the first metal layer interconnect can be designed to have a variety of layouts to create an optimally distributed first metal layer interconnect network.

(10) Combining the above advantages, the MOSFET structure disclosed in the present invention can be manufactured to have a very small size, wherein the MOSFET structure has a minimum length size of 4λ (that is, including a length S(L) equal to λ, a length D(L) equal to λ, a gate length equal to λ, 1/2λ for the left isolation, and 1/2λ for the right isolation) and a minimum width size of 2λ, that is, a world's smallest single transistor with a contact hole and a first metal layer interconnect connected to the source and the drain respectively can be realized within an area of 8λ2.

Of course, according to design requirements, the length G(L), length S(L) or length D(L) can be greater than the minimum characteristic length λ.

Because the present invention eliminates the uncertainty of lithography misalignment tolerance and adopts new self-alignment design and process technology, all the advantages of the present invention are not limited to application in single metal oxide semiconductor field effect transistors, but can also be applied to complementary metal oxide semiconductor (CMOS) circuits. For example, functional units with many area optimizations (such as static random access memory (SRAM), NAND gate, NOR gate, and any logic gate) can be reduced in chip area, current, power consumption and speed through the design and manufacturing principles of the present invention, and have accuracy, repeatability, consistency and better margin.

The above is only the preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: MOSFET

101: Gate structure

103: Source

105: Isolation area

107: Drain

109, 111: contact holes

D(L), G(L), S(L), C-S(L), C-D(L): Length

D(W), G(W), S(W), C-S(W), C-D(W): Width

Claims (16)

A transistor structure comprises: a semiconductor substrate having a semiconductor surface; a gate structure having a length; a channel region; a first isolation region; a first semiconductor region electrically coupled to a first end of the channel region; a second semiconductor region electrically coupled to a second end of the channel region; and a metal region at least contacting a top surface of the first semiconductor region and an outermost sidewall of the first semiconductor region; wherein the first semiconductor region is located between the first isolation region and the gate structure. The transistor structure as described in claim 1, wherein the metal region includes a first metal-containing region and a first metal layer, wherein the first metal layer contacts the top surface of the first semiconductor region, and the first metal-containing region contacts the side wall of the first semiconductor region. The transistor structure as described in claim 2 further includes a contact hole located between the first isolation region and the gate structure; a portion of the first metal layer fills the contact hole, and another portion of the first metal layer is located outside the contact hole. In the transistor structure as described in claim 3, the lateral length of the contact hole is not greater than a minimum characteristic length. A transistor structure as described in claim 2, wherein the first metal layer is located above the semiconductor surface, and the first metal-containing region is located below the semiconductor surface. The transistor structure as described in claim 5 further includes a contact hole located between the first isolation region and the gate structure; a portion of the first metal layer fills the contact hole, and another portion of the first metal layer is located outside the contact hole. A transistor structure as described in claim 1, wherein the metal region further contacts a bottom surface of the first semiconductor region. The transistor structure as described in claim 1 further comprises a first protective layer located below the metal region and the first semiconductor region; the first protective layer isolates a bottom surface of the metal region from contacting the semiconductor substrate, and isolates a bottom surface of the first semiconductor region from contacting the semiconductor substrate. A transistor structure as described in claim 8, wherein the first protective layer is an L-type oxide protective layer. A transistor structure comprises: a semiconductor substrate having a semiconductor surface and a groove, wherein the groove is below the semiconductor surface; a gate structure having a length; a channel region; a first isolation region; a first semiconductor region electrically coupled to a first end of the channel region; a second semiconductor region electrically coupled to a second end of the channel region; a first metal region in contact with the first semiconductor region; and a first protective layer located below the first metal region and the bottom of the first semiconductor region, the first protective layer isolates a bottom surface of the first semiconductor region from the semiconductor substrate, and the first protective layer contacts the first semiconductor region and the bottom of the first metal region, wherein the first protective layer is an L-type oxide protective layer. A transistor structure as described in claim 10, wherein the first protective layer further isolates a bottom surface of the first metal region from contacting the semiconductor substrate. The transistor structure as described in claim 11 further comprises a second metal region contacting the second semiconductor region, wherein a bottom surface of the second metal region contacts the semiconductor substrate. The transistor structure as described in claim 11 further includes a second protective layer located below the second semiconductor region to isolate a bottom surface of the second semiconductor region from contacting the semiconductor substrate. The transistor structure as described in claim 10 further includes a contact hole located between the first isolation region and the gate structure; a portion of the first metal layer fills the contact hole and contacts the first semiconductor region, and another portion of the first metal layer is located outside the contact hole. In the transistor structure as described in claim 14, the lateral length of the contact hole is not greater than a minimum characteristic length. A transistor structure comprises: a semiconductor substrate having a semiconductor surface and an active region; a gate structure having a length; a channel region; a shallow trench isolation higher than the semiconductor surface and surrounding the active region; a first semiconductor region electrically coupled to a first end of the channel region; a second semiconductor region electrically coupled to a second end of the channel region; and a metal region contacting at least one sidewall of the first semiconductor region; wherein the first semiconductor region and the metal region are located in the same groove.

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