TWI862378B - 3d memory device and method of manufacturing the same - Google Patents

Abstract

A 3D memory device and a method of manufacturing the same are provided. The 3D memory device includes a substrate, a bottom conductive layer, a plurality of stacked structures, a selective gate, a channel structure, gate oxide layers, a memory layer, and a plurality of silicon carbide layers. The bottom conductive layer is disposed on the substrate. The plurality of stacked structures is disposed on the bottom conductive layer and are alternately stacked by oxide layers and gate layers. The select gate is disposed on the stacked structures. The plurality of silicon carbide layers is disposed in the bottom conductive layer to separate the bottom conductive layer into a plurality of blocks. The channel structure includes a connecting portion and a plurality of channel pillars, wherein the connecting portion is disposed inside one of the blocks between the silicon carbide layers, and the channel pillars penetrate the select gate and the stack structures and extend to the connecting portion. The memory layer is disposed between the channel pillars and the stacked structures. The gate oxide layers are disposed between the connecting portion and the bottom conductive layer and between the channel pillars and the select gate.

Description

3D memory device and manufacturing method thereof

The present invention relates to a semiconductor element, and more particularly to a 3D memory device and a manufacturing method thereof.

3D non-volatile memory is a highly developed memory device that has a lower bit cost, breaks through the limitations of miniaturization, and has the potential to achieve high density by stacking more layers. U-shaped pipe-shaped 3D memory has been developed to further improve the reliability of the device.

However, due to the longer current path, this U-shaped tubular 3D memory has a larger resistance, resulting in a lower cell current. Therefore, during the read operation of the memory array, the aforementioned low current will cause sensing errors and the read access speed is relatively slow.

The present invention provides a 3D memory device and a manufacturing method thereof, which can improve the electron mobility of the device and thus increase the string current.

A manufacturing method of a 3D memory device of the present invention comprises the following steps. A bottom conductive layer is formed on a substrate, and the bottom conductive layer has a connecting channel and a plurality of first openings, the connecting channel is formed inside the bottom conductive layer, and the plurality of first openings penetrate from the top surface of the bottom conductive layer to the connecting channel. A first gate dielectric layer is formed on the top surface of the bottom conductive layer, the side walls of the plurality of first openings, and the inner surface of the connecting channel. A first sacrificial layer is filled in the plurality of first openings and the connecting channel. The first sacrificial layer and the first gate dielectric layer outside the plurality of first openings are removed to expose the top surface of the bottom conductive layer. A stacking structure is formed on the top surface of the bottom conductor layer, wherein the stacking structure is formed by alternately stacking multiple oxide layers and multiple material layers. A plurality of through holes are formed in the stacking structure, wherein the plurality of through holes are aligned with the plurality of first openings and expose the top surface of the first sacrificial layer. A memory layer and a semiconductor liner are formed on the side walls of the plurality of through holes, and the top surface of the first sacrificial layer is exposed, wherein the memory layer is between the stacking structure and the semiconductor liner. The first sacrificial layer is removed. A first channel material layer is formed in the connecting channel, the plurality of first openings and the plurality of through holes. A patterned interlayer dielectric layer and a selective gate layer are formed on the stacked structure, wherein the patterned interlayer dielectric layer and the selective gate layer have a plurality of second openings, exposing the first channel material layer. A second gate dielectric layer is formed on the sidewalls of the plurality of second openings. A second channel material layer is formed in the plurality of second openings. At the same time, a first slot is formed in the interlayer dielectric layer, the selective gate layer and the stacked structure between the plurality of through holes, and a plurality of second slots are formed in the interlayer dielectric layer, the selective gate layer and the stacked structure connecting the two sides of the channel, and the top surface of the bottom conductor layer is exposed. A dielectric spacer is formed on the sidewalls of the first slot and the plurality of second slots. A second sacrificial layer is formed in the first slot between the plurality of through holes. The bottom conductive layer exposed in the plurality of second slots is removed to form a plurality of third openings. A silicon carbide layer is formed in the plurality of third openings. The second sacrificial layer is removed.

In one embodiment of the present invention, the above-mentioned multiple material layers are conductor layers.

In one embodiment of the present invention, the method for forming the above-mentioned connecting channel and the first opening includes forming a first conductive sublayer on a substrate, forming the above-mentioned connecting channel in the first conductive sublayer, forming a third sacrificial layer in the connecting channel, covering the first conductive sublayer and the third sacrificial layer with a second conductive sublayer, and then forming the above-mentioned first opening in the second conductive sublayer and exposing a portion of the top surface of the third sacrificial layer, and then removing the third sacrificial layer to expose a plurality of side walls of the first opening and the inner surface of the connecting channel.

In one embodiment of the present invention, the method of forming the first channel material layer includes filling the connecting channel, the first opening and the through hole with the first channel material, and then planarizing the first channel material.

In one embodiment of the present invention, the method for forming the first channel material layer includes conformally depositing the first channel material layer on the inner surface of the connecting channel, the side wall of the first opening and the inner surface of the through hole, and then filling the connecting channel, the first opening and the through hole with insulating material.

In one embodiment of the present invention, the method for forming the second channel material layer includes forming the second channel material layer on the second gate dielectric layer of the second opening, and then filling the second opening with an insulating material.

In one embodiment of the present invention, the method for forming the plurality of through holes includes forming a hard mask layer on the stacked structure; patterning the hard mask layer to form a plurality of fourth openings, wherein the fourth openings are aligned with the first openings, and then using the patterned hard mask layer as an etching mask to remove the stacked structure in the fourth openings until the top surface of the first sacrificial layer is exposed.

In an embodiment of the present invention, the multi-layer material layer is a silicon nitride layer. After removing the second sacrificial layer, an insulating layer may be formed in the first slot and the plurality of second slots, and then a metal gate replacement process may be performed to replace the multi-layer material layer in the stacked structure with a multi-layer metal gate.

In one embodiment of the present invention, the method of forming the insulating layer in the first slot and the plurality of second slots includes depositing the insulating layer in the first slot and the second slot, and then flattening the insulating layer until the second channel material layer is exposed.

Another method for manufacturing a 3D memory device of the present invention includes the following steps. A bottom conductive layer is formed on a substrate, and the bottom conductive layer has a connecting channel and a plurality of first openings therein, the connecting channel is formed inside the bottom conductive layer, and the plurality of first openings penetrate from the top surface of the bottom conductive layer to the connecting channel. A first gate dielectric layer is formed on the top surface of the bottom conductive layer, the side walls of the plurality of first openings, and the inner surface of the connecting channel. A first channel material layer is filled in the plurality of first openings and the connecting channel. The first channel material layer and the first gate dielectric layer outside the plurality of first openings are removed to expose the top surface of the bottom conductive layer. A stacking structure is formed on the top surface of the bottom conductor layer, wherein the stacking structure is formed by alternately stacking multiple oxide layers and multiple material layers. A plurality of through holes are formed in the stacking structure, wherein the plurality of through holes are aligned with the plurality of first openings and expose the top surface of the first channel material layer. A memory layer and a semiconductor liner are formed on the side walls of the plurality of through holes and expose the top surface of the first channel material layer, wherein the memory layer is between the stacking structure and the semiconductor liner. A second channel material layer is formed in the plurality of through holes. A patterned interlayer dielectric layer and a selection gate layer are formed on the stacking structure, wherein the plurality of second openings are provided and the second channel material layer is exposed. A second gate dielectric layer is formed on the sidewalls of the plurality of second openings. A third channel material layer is formed in the plurality of second openings. A first slot is formed in the interlayer dielectric layer, the selective gate layer and the stacked structure between the plurality of through holes, and a plurality of second slots are formed in the interlayer dielectric layer, the selective gate layer and the stacked structure connecting the two sides of the channel, and the top surface of the bottom conductor layer is exposed. A dielectric spacer is formed on the sidewalls of the first slot and the plurality of second slots. A first sacrificial layer is formed in the first slot between the plurality of through holes. The bottom conductor layer exposed in the plurality of second slots is removed to form a plurality of third openings. A silicon carbide layer is formed in the plurality of third openings. Remove the first sacrificial layer.

In another embodiment of the present invention, the above-mentioned multiple material layers are conductor layers.

In another embodiment of the present invention, the method for forming the above-mentioned connecting channel and the first opening includes forming a first conductive sublayer on a substrate, forming the above-mentioned connecting channel in the first conductive sublayer, forming a second sacrificial layer in the connecting channel, covering the first conductive sublayer and the second sacrificial layer with the second conductive sublayer, and then forming the above-mentioned first opening in the second conductive sublayer and exposing a portion of the top surface of the second sacrificial layer, and then removing the second sacrificial layer to expose a plurality of side walls of the first opening and the inner surface of the connecting channel.

In another embodiment of the present invention, the method of forming the second channel material layer includes filling the through hole with the second channel material and then planarizing the second channel material.

In another embodiment of the present invention, the method of forming the third channel material layer includes forming the third channel material layer on the second gate dielectric layer of the plurality of second openings, and then filling the second openings with an insulating material.

In another embodiment of the present invention, the method of forming the second channel material layer includes conformally depositing the second channel material layer on the inner surface of the through hole, and then filling the plurality of through holes with an insulating material.

In another embodiment of the present invention, the method for forming the through hole includes forming a hard mask layer on the stacked structure; patterning the hard mask layer to form a plurality of fourth openings, wherein the fourth openings are aligned with the first openings, and then using the patterned hard mask layer as an etching mask to remove the stacked structure in the fourth openings until the top surface of the first channel material layer is exposed.

In another embodiment of the present invention, the multi-layer material layer is a silicon nitride layer. After removing the first sacrificial layer, an insulating layer may be formed in the first slot and the plurality of second slots, and then a metal gate replacement process may be performed to replace the multi-layer material layer in the stacked structure with a multi-layer metal gate.

In another embodiment of the present invention, the method of forming an insulating layer in the first slot and the plurality of second slots includes depositing the insulating layer entirely in the first slot and the second slot, and then planarizing the insulating layer until the third channel material layer is exposed.

In the above embodiments of the present invention, the method of forming the silicon carbide layer includes an epitaxial process.

Another 3D memory device of the present invention includes a substrate, a bottom conductor layer, a plurality of stacked structures, a selection gate, a channel structure, a gate dielectric layer, a memory layer, and a plurality of silicon carbide layers. The bottom conductor layer is disposed on the substrate. A plurality of stacked structures are disposed on the bottom conductor layer and are formed by alternately stacking a plurality of oxide layers and a plurality of gate layers. The selection gate is disposed on the stacked structures. A plurality of silicon carbide layers are disposed in the bottom conductor layer to separate the bottom conductor layer into a plurality of blocks. The channel structure includes a connecting portion and a plurality of channel pillars, wherein the connecting portion is arranged inside one of the plurality of blocks between the plurality of silicon carbide layers, and the channel pillars penetrate the selection gate and the stacking structure and extend to the connecting portion. The memory layer is arranged between the channel pillars and the stacking structure. The gate dielectric layer is arranged between the connecting portion and the bottom conductor layer and between the channel pillars and the selection gate.

In another embodiment of the present invention, the connecting portion is conformally disposed on the surface of the first gate dielectric layer, and the channel pillar is conformally disposed on the sidewalls of the selection gate and the plurality of stacked structures.

In yet another embodiment of the present invention, the 3D memory device may further include an insulating material disposed in the inner spaces of the plurality of channel pillars and the inner space of the communication portion.

In another embodiment of the present invention, the 3D memory device may further include a semiconductor inter-silicon wall disposed between the memory layer and the channel pillar.

In another embodiment of the present invention, the multi-layer gate layer includes a semiconductor gate or a metal gate.

In the above embodiments of the present invention, the bottom conductive layer includes a polysilicon layer.

In the above embodiments of the present invention, the above memory layer includes an ONO layer.

Based on the above, the present invention forms a silicon carbide layer in the bottom conductor layer, which can enhance the tensile strain of the bottom conductor layer, thereby increasing the electron mobility and thus increasing the series current. Moreover, the method of the present invention separately manufactures the gate dielectric layer of the connecting part and the gate dielectric layer of the channel column, so the gate dielectric layer of the traditional channel column (i.e., the memory layer, such as the ONO layer) will not be formed around the connecting part, and the gate dielectric layer of the connecting part can adjust its thickness by itself or only grow a layer of oxide. Therefore, compared with the general process of forming the gate dielectric layer and the semiconductor layer first, the thickness of the gate dielectric layer of the connecting part of the present invention can be thick enough to avoid the problem of leakage current, and because the gate dielectric layer of the connecting part does not contain silicon nitride, the Vt shift phenomenon can be avoided.

In order to make the above features and advantages of the present invention more clearly understood, embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

The following description provides a number of embodiments for implementing different features of the present invention. In addition, these embodiments are exemplary only and are not intended to limit the scope and application of the present invention. Moreover, for the sake of clarity, the relative sizes (e.g., length, width, spacing, etc.) and relative positions of regions or structural components may be reduced or enlarged. In addition, similar or identical element symbols used in different figures represent similar or identical components or features.

Furthermore, although the terms "first", "second", etc. are used herein to describe different elements, regions, and/or layers, these elements, regions, and/or layers should not be limited to these terms. Rather, these terms are only used to distinguish one element, region, and/or layer from another element, region, and/or layer. Therefore, the first element, region, and/or layer discussed below in one embodiment may be referred to as the second element, region, and/or layer in other embodiments without violating the teachings of the exemplary embodiments.

1A to 1X are schematic cross-sectional views of a manufacturing process of a 3D memory device according to a first embodiment of the present invention.

Please refer to FIG. 1A . In order to form a structure as a pipe gate on a substrate 100, a first conductor sublayer SL1 may be formed on the substrate 100, a connecting channel CT may be formed in the first conductor sublayer SL1, and a sacrificial layer 106 may be formed in the connecting channel CT. The material of the sacrificial layer 106 may be, for example, silicon nitride or other suitable materials. Then, a second conductor sublayer SL2 may be covered on the first conductor sublayer SL1 and the sacrificial layer 106. The first conductor sublayer SL1 and the second conductor sublayer SL2 may be, for example, polysilicon layers. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. In this embodiment, the insulating layer 102 may be first formed between the substrate 100 and the first conductive sub-layer SL1, but the present invention is not limited thereto. In another embodiment, the insulating layer 102 may not be grown, so that the first conductive sub-layer SL1 is directly formed on the substrate 100.

Then, referring to FIG. 1B , a plurality of first openings O1 are formed in the second conductive sublayer SL2 to expose a portion of the top surface of the sacrificial layer 106 . The location of the first opening O1 is where the channel will be formed later. The first conductive sublayer SL1 and the second conductive sublayer SL2 constitute the bottom conductive layer 104 .

Afterwards, referring to FIG. 1C , the sacrificial layer 106 in FIG. 1B is removed to expose the sidewalls of the first opening O1 and the inner surface of the connecting channel CT. The bottom conductive layer 104 formed has the connecting channel CT and the first opening O1. The connecting channel CT is formed inside the bottom conductive layer 104. A plurality of first openings O1 pass through the top surface of the bottom conductive layer 104 to the connecting channel CT.

Then, referring to FIG. 1D , a first gate dielectric layer GO1 is formed on the top surface of the bottom conductive layer 104, the sidewalls of the first opening O1, and the inner surface of the connecting channel CT.

Next, referring to FIG. 1E , another sacrificial layer 108 is filled in the first opening O1 and the connecting channel CT, wherein the material of the sacrificial layer 108 is, for example, silicon nitride or other suitable materials.

Afterwards, referring to FIG. 1F , the sacrificial layer 108 and the first gate dielectric layer GO1 outside the first opening O1 are removed to expose the top surface of the bottom conductive layer 104.

Then, referring to FIG. 1G , a stacked structure S1 is formed on the top surface of the bottom conductor layer 104. The stacked structure S1 is formed by alternately stacking multiple oxide layers OX and multiple material layers 110. The material of the material layer 110 is, for example, polysilicon or silicon nitride or other suitable materials. For the subsequent etching process, a hard mask layer 112 may be formed on the stacked structure S1.

Next, referring to FIG. 1H , the hard mask layer 112 is patterned to form a plurality of second openings O2 aligned with the first openings O1, and the patterned hard mask layer 112 is then used as an etching mask to remove the stacked structure S1 in the second openings O2 until the top surface of the sacrificial layer 108 is exposed, thereby forming a plurality of through holes TH in the stacked structure S1, wherein the plurality of through holes TH are aligned with the plurality of first openings O1 and expose the top surface of the sacrificial layer 108. However, the present invention is not limited thereto, and the through holes TH may also be formed by other methods.

Then, referring to FIG. 1I , after removing the hard mask layer 112, a memory layer 114 and a semiconductor material layer 115 are conformally deposited on the sidewalls of the through hole TH, the surface of the stacked structure S1, and the top surface of the sacrificial layer 108, wherein the memory layer 114 includes an ONO layer. The semiconductor material layer 115 is used to protect the memory layer 114 from the influence of subsequent processes. In one embodiment, the semiconductor material layer 115 can be made of the same material as the channel layer formed subsequently.

Thereafter, referring to FIG. 1J , the memory layer 114 and the semiconductor material layer 115 on the surface of the stacking structure S1 and the top surface of the sacrificial layer 108 are removed by etching back or the like, so as to form the memory layer 114 and the semiconductor liner 116 on the side wall of the through hole TH and expose the top surface of the sacrificial layer 108, wherein the memory layer 114 is between the stacking structure S1 and the semiconductor liner 116.

Then, referring to FIG. 1K , the sacrificial layer 108 is removed, so that the through hole TH and the connecting channel CT form a space connected to each other.

Next, referring to FIG. 1L , a first channel material layer 118 is formed in the connecting channel CT, the first opening O1, and the plurality of through holes TH. The method for forming the first channel material layer 118 may be to first fill the connecting channel CT, the first opening O1, and the through holes TH with the first channel material, and then planarize the first channel material. The material of the first channel material layer 118 is, for example, a semiconductor material. In some embodiments, the semiconductor material is, for example, polysilicon.

Subsequently, referring to FIG. 1M , a patterned interlayer dielectric layer ILD and a select gate layer SG are formed, wherein a plurality of third openings O3 are provided to expose the first channel material layer 118 .

1N , a second gate dielectric layer GO2 is formed on the sidewall of the third opening O3, and a second channel material layer 120 is formed in the third opening O3. The first channel material layer 118 and the second channel material layer 120 may be made of the same material, but the present invention is not limited thereto.

10 , a first slit 122a and a plurality of second slits 122b are formed in the interlayer dielectric layer ILD, the select gate layer SG and the stack structure S1 to expose the top surface of the bottom conductive layer 104. The first slit 122a and the second slit 122b are both strip-shaped trenches extending in the page direction.

Then, referring to FIG. 1P , dielectric spacers 124 may be formed on the sidewalls of the first slot 122 a and the plurality of second slots 122 b.

Then, referring to FIG. 1Q , a sacrificial layer 126 is formed in both the first groove 122a and the second groove 122b, wherein the material of the sacrificial layer 126 is, for example, silicon nitride or other suitable materials. The sacrificial layer 126 is formed by, for example, depositing silicon nitride all over the surface and then removing the silicon nitride outside the first groove 122a and the second groove 122b by an etching back process.

1R, the patterned photoresist layer PR may be used to cover the portion outside the second groove 122b, and the patterned photoresist layer PR may be used as an etching mask to remove the sacrificial layer 126 in the second groove 122b until the bottom conductive layer 104 is exposed.

Next, referring to FIG. 1S , the bottom conductive layer 104 exposed in the second slot 122 b is removed to form a plurality of fourth openings O4. Since the second slot 122 b is a strip-shaped groove extending toward the page direction, the fourth openings O4 are also strip-shaped openings. The patterned photoresist layer PR may be removed later, or the patterned photoresist layer PR may be removed before forming the fourth openings O4.

Then, referring to FIG. 1T , a silicon carbide layer 128a is formed in a plurality of fourth openings O4, wherein the method for forming the silicon carbide layer 128a is, for example, an epitaxial process. Since the fourth opening O4 is a strip-shaped opening, the silicon carbide layer 128a therein is also a strip-shaped structure extending in the page direction. Since the second channel material layer 120 exposed during the epitaxial silicon carbide layer 128a may also grow into a silicon carbide layer 128b, it is necessary to remove it later. However, the present invention is not limited thereto; in another embodiment, before forming the silicon carbide layer 128a, the second channel material layer 120 may be covered with a mask layer (not shown), and the mask layer may be removed in a subsequent step.

1U, the sacrificial layer 126 is removed first. In order to form the insulating layer only in the first slot 122a and the plurality of second slots 122b, the insulating layer 130 may be fully deposited in the first slot 122a and the plurality of second slots 122b.

Then, referring to FIG. 1V , the planarized insulating layer 130 will first expose the silicon carbide layer 128 b.

Subsequently, referring to FIG. 1W , the silicon carbide layer 128 b is removed to expose the second channel material layer 120 .

Next, please refer to FIG. 1X , and continue to planarize the insulating layer 130 until the second channel material layer 120 is exposed or the insulating layer 130 is flush with the second channel material layer 120. At this time, if the material of the material layer 110 is a conductive layer (such as a polysilicon layer), a semiconductor gate (polysilicon) 3D memory device is formed.

If the material of the material layer 110 is silicon nitride or other materials that are not suitable as a gate, the metal gate replacement process can be performed with reference to the step of FIG. 1Y, which is another embodiment, to replace the multiple material layers 110 in the stacked structure S1 of FIG. 1X with multiple metal gate layers MG to form a stacked structure S2. In addition, if the material of the select gate layer SG is the same as the material of the sacrificial layer in the stacked structure S1, it will also be replaced with a metal select gate layer SG.

The metal gate replacement process can be listed but not limited to, first remove the insulating layer 130 and dielectric spacer in the first slot 122a and the plurality of second slots 122b of FIG. 1X, then perform wet etching to remove the material layer 110 in FIG. 1G and retain the oxide layer OX, and then first deposit a high-k dielectric layer (not shown) on the exposed portion and then form a metal material (such as tungsten) to form a metal gate MG. Subsequently remove the unwanted metal material, and then form an insulating layer 132 in the first slot 122a and the plurality of second slots 122b, and the structure of FIG. 1Y can be obtained. However, the present invention is not limited to this, and other suitable processes can also be used to perform metal gate replacement.

Therefore, the 3D memory device of the present invention includes a substrate 100, a bottom conductive layer 104, a plurality of stacked structures S1 (semiconductor gates) or stacked structures S2 (metal gates), a selection gate SG, a channel structure, a gate dielectric layer, a memory layer 114, and a plurality of silicon carbide layers 128a. The bottom conductive layer 104 is disposed on the substrate 100. The plurality of stacked structures S1 or stacked structures S2 are disposed on the bottom conductive layer 104 and are formed by alternately stacking a plurality of oxide layers OX and a plurality of semiconductor gates (material layers 110) or a plurality of oxide layers OX and a plurality of metal gates MG. The selection gate SG is disposed on the stacking structure S1 or the stacking structure S2. A plurality of silicon carbide layers 128a are disposed in the bottom conductor layer 104 to separate the bottom conductor layer 104 into a plurality of blocks. The channel structure includes a connecting portion 118' and a plurality of channel pillars (a second channel material layer 120 and a first channel material layer 118 passing through the stacking structure S2), wherein the connecting portion 118' is disposed inside the block between the plurality of silicon carbide layers 128a, and the channel pillars penetrate the selection gate SG and the stacking structure S1 or the stacking structure S2 and extend to the connecting portion 118'. The memory layer 114 is disposed between the channel pillar and the stacked structure S1 or the stacked structure S2. The first gate dielectric layer GO1 is disposed between the connecting portion 118' and the bottom conductive layer 104, and the second gate dielectric layer GO2 is disposed between the channel pillar and the selection gate SG. A semiconductor liner 116 may also be disposed between the memory layer 114 and the channel pillar to protect the memory layer 114 during the manufacturing process, wherein the semiconductor liner 116 and the second channel material layer 120 may be made of the same material.

Since the silicon carbide layer 128a can enhance the tensile strain of the bottom connecting portion 118' of the polysilicon, the electron mobility can be improved to increase the string current.

Moreover, according to the process of the first embodiment, the first gate dielectric layer GO1 around the connecting portion 118' can be first manufactured, and then the memory layer 114 can be formed. Therefore, compared with the general process of simultaneously depositing the memory layer (ONO) to form the memory gate dielectric layer and the first gate dielectric layer, the first gate dielectric layer GO1 of the present invention can be formed with sufficient thickness on the bottom conductive layer 104 to avoid the occurrence of leakage current and critical voltage shift (Vt shift).

FIG2 is a cross-sectional schematic diagram of a 3D memory device according to the second embodiment of the present invention, wherein the same element symbols as those in the first embodiment are used to represent the same or similar components, and some omitted technical descriptions, such as the position, material, and formation method of each layer or space, can refer to the relevant contents in the first embodiment and will not be repeated.

2 , the 3D memory device of the second embodiment is different from the first embodiment in terms of the channel structure. The channel structure of the first embodiment is cylinder type, while the channel structure of this embodiment is macaroni-shaped.

For example, the formation method of the first channel material layer is changed from completely filling the channel material in FIG. 1L to conformally depositing the first channel material layer 200 on the inner surface of the connecting channel CT, the sidewall of the first opening O1 and the inner surface of the through hole TH, and then filling the insulating material 204a in the connecting channel CT, the first opening O1 and the through hole TH. Moreover, the formation method of the second channel material layer is changed from completely filling the channel material in FIG. 1N to first forming the second channel material layer 202 on the second gate dielectric layer GO2 of the third opening O3, and then filling it with the insulating material 204b.

Therefore, the finally formed connecting portion (the first channel material layer 200 in the connecting channel CT) is conformally disposed on the surface of the first gate dielectric layer GO1, and the channel column (the second channel material layer 202 and the first channel material layer 200 passing through the stacked structure S1 or the stacked structure S2) is conformally disposed on the side walls of the selection gate SG and multiple stacked structures S1 or stacked structures S2.

3A to 3F are cross-sectional schematic diagrams of an intermediate process of manufacturing a 3D memory device according to the third embodiment of the present invention, wherein the same element symbols as those in the first embodiment are used to represent the same or similar components, and some omitted technical descriptions, such as the position, material, and formation method of each layer or space, can refer to the relevant contents in the first embodiment and will not be repeated.

The difference between the manufacturing method of the third embodiment and the manufacturing method of the first embodiment lies in the intermediate steps. Therefore, the third embodiment can use the steps of FIG. 1A to FIG. 1D and perform the following steps after forming the first gate dielectric layer GO1.

3A , a first channel material layer 300 is filled in the plurality of first openings O1 and the connecting channels CT, and the formation method, position, and material thereof can be the same as those of the first channel material layer 118 in the first embodiment.

Afterwards, referring to FIG. 3B , the first channel material layer 300 and the first gate dielectric layer GO1 outside the plurality of first openings O1 are removed to expose the top surface of the bottom conductor layer 104. In another embodiment, the first channel material layer 300 may also be similar to the structure of FIG. 2 , and is only formed on the sidewalls of the first openings O1 and the inner surface of the connecting channel CT, and the first openings O1 and the connecting channel CT are filled with an insulating material (not shown).

Then, referring to FIG. 3C , a stacking structure S1 is formed on the top surface of the bottom conductive layer 104, and its formation method, position and material can be the same as those in FIG. 1G of the first embodiment, wherein the stacking structure S1 is formed by alternately stacking multiple oxide layers OX and multiple material layers 110.

Subsequently, referring to FIG. 3D , a plurality of through holes TH are formed in the stacked structure S1 , wherein the plurality of through holes TH are aligned with the plurality of first openings O1 and expose the top surface of the first channel material layer 300 .

Next, referring to FIG. 3E , a memory layer 114 and a semiconductor liner 116 similar to those shown in FIG. 1J are formed on the sidewalls of the plurality of through holes TH, and the top surface of the first channel material layer 300 is exposed, wherein the memory layer 114 is between the stack structure S1 and the semiconductor liner 116 .

Then, referring to FIG. 3F , a second channel material layer 302 is formed in the plurality of through holes TH, and its formation method, position, and material, etc. can be similar to the first channel material layer in the first embodiment (such as the first channel material layer 118 in FIG. 1L ). In another embodiment, the second channel material layer 302 can also be similar to the structure of FIG. 2 , for example, the second channel material layer (such as the first channel material layer 200 in FIG. 2 ) is formed on the sidewall of the through hole TH, and then an insulating material (not shown) is filled in the plurality of through holes TH.

The steps after FIG. 3F may follow the steps of FIG. 1M to FIG. 1Y. Although different element symbols are used, it should be noted that the terms "first", "second", etc. are used to describe film layers formed at different times, but these film layers should not be limited to these terms. Therefore, the first channel material layer in the first embodiment is actually the same structure as the second channel material layer in the third embodiment. Similarly, the second channel material layer in the first embodiment (such as the second channel material layer 120 in FIG. 1N) is called the third channel material layer in the third embodiment; and so on.

Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

100: Substrate

102, 130, 132: Insulating layer

104: Bottom conductor layer

106, 108, 126: Sacrifice layer

110: Material layer

112: Hard cover layer

114:Memory layer

115:Semiconductor material layer

116:Semiconductor liner

118, 200, 300: first channel material layer

118’: Communication Department

120, 202, 302: second channel material layer

122a: first groove

122b: Second groove

124: Dielectric spacer

128a, 128b: Silicon carbide layer

204a, 204b: Insulation material

CT: Connecting Channel

GO1: First gate dielectric layer

GO2: Second gate dielectric layer

ILD: Interlayer Dielectric

MG:Metal Gate

O1: First opening

O2: Second opening

O3: The third opening

O4: The fourth opening

OX: Oxide layer

PR: Patterned Photoresist

S1, S2: stack structure

SG: Select gate layer

SL1: First conductor sublayer

SL2: Second conductor layer

TH:Through Hole

Figures 1A to 1X are schematic cross-sectional views of a manufacturing process of a 3D memory device according to the first embodiment of the present invention. Figure 1Y is a schematic cross-sectional view of another 3D memory device of the first embodiment. Figure 2 is a schematic cross-sectional view of a 3D memory device according to the second embodiment of the present invention. Figures 3A to 3F are schematic cross-sectional views of an intermediate process of manufacturing a 3D memory device according to the third embodiment of the present invention.

100: Substrate

102, 132: Insulation layer

104: Bottom conductor layer

114: Memory layer

116: Semiconductor substrate

118: First channel material layer

118’: Communication Department

120: Second channel material layer

122a: First groove seam

122b: Second groove

128a: Silicon carbide layer

GO1: First gate dielectric layer

GO2: Second gate dielectric layer

ILD: Interlayer Dielectric

MG: Metal Gate

OX: oxide layer

S2: Stacked structure

SG: Select gate layer

Claims (27)

A method for manufacturing a 3D memory device, comprising: Forming a bottom conductive layer on a substrate, wherein the bottom conductive layer has a connecting channel and a plurality of first openings, wherein the connecting channel is formed inside the bottom conductive layer, and the plurality of first openings penetrate from the top surface of the bottom conductive layer to the connecting channel; Forming a first gate dielectric layer on the top surface of the bottom conductive layer, the side walls of the plurality of first openings, and the inner surface of the connecting channel; Filling the plurality of first openings and the connecting channel with a first sacrificial layer; Removing the first sacrificial layer and the first gate dielectric layer outside the plurality of first openings to expose the top surface of the bottom conductive layer; A stacking structure is formed on the top surface of the bottom conductor layer, wherein the stacking structure is formed by alternately stacking multiple oxide layers and multiple material layers; A plurality of through holes are formed in the stacking structure, wherein the plurality of through holes are aligned with the plurality of first openings and expose the top surface of the first sacrificial layer; A memory layer and a semiconductor liner are formed on the side walls of the plurality of through holes and the top surface of the first sacrificial layer is exposed, wherein the memory layer is between the stacking structure and the semiconductor liner; The first sacrificial layer is removed; A first channel material layer is formed in the connecting channel, the plurality of first openings and the plurality of through holes; A patterned interlayer dielectric layer and a selective gate layer are formed on the stacked structure, wherein the patterned interlayer dielectric layer and the selective gate layer have a plurality of second openings, exposing the first channel material layer; A second gate dielectric layer is formed on the sidewalls of the plurality of second openings; A second channel material layer is formed in the plurality of second openings; A first slot is formed in the interlayer dielectric layer, the selective gate layer and the stacked structure between the plurality of through holes, and a plurality of second slots are formed in the interlayer dielectric layer, the selective gate layer and the stacked structure on both sides of the connecting channel, and the top surface of the bottom conductor layer is exposed; A dielectric spacer is formed on the sidewalls of the first slot and the plurality of second slots; Forming a second sacrificial layer in the first slots between the plurality of through holes; Removing the bottom conductor layer exposed in the plurality of second slots to form a plurality of third openings; Forming a silicon carbide layer in the plurality of third openings; and Removing the second sacrificial layer. The method for manufacturing a 3D memory device as described in claim 1, wherein the multiple material layers are conductive layers. A method for manufacturing a 3D memory device as described in claim 1, wherein the method for forming the connecting channel and the plurality of first openings comprises: forming a first conductor sublayer on the substrate; forming the connecting channel in the first conductor sublayer; forming a third sacrificial layer in the connecting channel; covering the first conductor sublayer and the third sacrificial layer with a second conductor sublayer; forming the plurality of first openings in the second conductor sublayer to expose a portion of the top surface of the third sacrificial layer; and removing the third sacrificial layer to expose the side walls of the plurality of first openings and the inner surface of the connecting channel. The manufacturing method of the 3D memory device as described in claim 1, wherein the method of forming the first channel material layer includes: Filling the connecting channel, the plurality of first openings and the plurality of through holes with the first channel material; and Flattening the first channel material. The manufacturing method of the 3D memory device as described in claim 1, wherein the method of forming the first channel material layer comprises: Conformally depositing the first channel material layer on the inner surface of the connecting channel, the sidewalls of the plurality of first openings, and the inner surface of the plurality of through holes; and Filling the connecting channel, the plurality of first openings, and the plurality of through holes with insulating material. The manufacturing method of the 3D memory device as described in claim 1, wherein the method of forming the second channel material layer comprises: forming the second channel material layer on the second gate dielectric layer of the plurality of second openings; and filling the plurality of second openings with insulating material. A method for manufacturing a 3D memory device as described in claim 1, wherein the method for forming the plurality of through holes comprises: forming a hard mask layer on the stacked structure; patterning the hard mask layer to form a plurality of fourth openings, wherein the plurality of fourth openings are aligned with the plurality of first openings; and using the patterned hard mask layer as an etching mask to remove the stacked structure in the plurality of fourth openings until the top surface of the first sacrificial layer is exposed. The manufacturing method of the 3D memory device as described in claim 1, wherein the multi-layer material layer is a silicon nitride layer, further comprises: forming an insulating layer in the first slot and the plurality of second slots after removing the second sacrificial layer; and performing a metal gate replacement process to replace the multi-layer material layer in the stacked structure with a multi-layer metal gate. The manufacturing method of the 3D memory device as described in claim 8, wherein the method of forming the insulating layer in the first groove and the plurality of second grooves comprises: Depositing the insulating layer in the first groove and the plurality of second grooves; and Planning the insulating layer until the second channel material layer is exposed. A method for manufacturing a 3D memory device, comprising: Forming a bottom conductive layer on a substrate, wherein the bottom conductive layer has a connecting channel and a plurality of first openings, wherein the connecting channel is formed inside the bottom conductive layer, and the plurality of first openings penetrate from the top surface of the bottom conductive layer to the connecting channel; Forming a first gate dielectric layer on the top surface of the bottom conductive layer, the side walls of the plurality of first openings, and the inner surface of the connecting channel; Filling the plurality of first openings and the connecting channel with a first channel material layer; Removing the first channel material layer and the first gate dielectric layer outside the plurality of first openings to expose the top surface of the bottom conductive layer; A stacking structure is formed on the top surface of the bottom conductor layer, wherein the stacking structure is formed by alternately stacking multiple oxide layers and multiple material layers; A plurality of through holes are formed in the stacking structure, wherein the plurality of through holes are aligned with the plurality of first openings and expose the top surface of the first channel material layer; A memory layer and a semiconductor liner are formed on the side walls of the plurality of through holes, and the top surface of the first channel material layer is exposed, wherein the memory layer is between the stacking structure and the semiconductor liner; A second channel material layer is formed in the plurality of through holes; A patterned interlayer dielectric layer and a selective gate layer are formed on the stacked structure, wherein the patterned interlayer dielectric layer and the selective gate layer have a plurality of second openings, exposing the second channel material layer; A second gate dielectric layer is formed on the sidewalls of the plurality of second openings; A third channel material layer is formed in the plurality of second openings; A first slot is formed in the interlayer dielectric layer, the selective gate layer and the stacked structure between the plurality of through holes, and a plurality of second slots are formed in the interlayer dielectric layer, the selective gate layer and the stacked structure on both sides of the connecting channel, and the top surface of the bottom conductor layer is exposed; A dielectric spacer is formed on the sidewalls of the first slot and the plurality of second slots; Forming a first sacrificial layer in the first slot between the plurality of through holes; Removing the bottom conductor layer exposed in the plurality of second slots to form a plurality of third openings; Forming a silicon carbide layer in the plurality of third openings; and Removing the first sacrificial layer. A method for manufacturing a 3D memory device as described in claim 10, wherein the multiple material layers are conductive layers. A method for manufacturing a 3D memory device as described in claim 10, wherein the method for forming the connecting channel and the plurality of first openings comprises: forming a first conductor sublayer on the substrate; forming the connecting channel in the first conductor sublayer; forming a second sacrificial layer in the connecting channel; covering the second conductor sublayer on the first conductor sublayer and the second sacrificial layer; forming the plurality of first openings in the second conductor sublayer to expose a portion of the top surface of the second sacrificial layer; and removing the second sacrificial layer to expose the side walls of the plurality of first openings and the inner surface of the connecting channel. The method for manufacturing a 3D memory device as described in claim 10, wherein the method for forming the second channel material layer comprises: filling the plurality of through holes with the second channel material; and flattening the second channel material. The method for manufacturing a 3D memory device as described in claim 10, wherein the method for forming the second channel material layer comprises: conformally depositing the second channel material layer on the inner surface of the plurality of through holes; and filling the plurality of through holes with an insulating material. The manufacturing method of the 3D memory device as described in claim 10, wherein the method of forming the third channel material layer comprises: forming the third channel material layer on the second gate dielectric layer of the plurality of second openings; and filling the plurality of second openings with insulating material. A method for manufacturing a 3D memory device as described in claim 10, wherein the method for forming the plurality of through holes comprises: forming a hard mask layer on the stacked structure; patterning the hard mask layer to form a plurality of fourth openings, wherein the plurality of fourth openings are aligned with the plurality of first openings; and using the patterned hard mask layer as an etching mask to remove the stacked structure in the plurality of fourth openings until the top surface of the first channel material layer is exposed. The manufacturing method of the 3D memory device as described in claim 10, wherein the multi-layer material layer is a silicon nitride layer, further comprises: forming an insulating layer in the first slot and the plurality of second slots after removing the first sacrificial layer; and performing a metal gate replacement process to replace the multi-layer material layer in the stacked structure with a multi-layer metal gate. The manufacturing method of the 3D memory device as described in claim 17, wherein the method of forming the insulating layer in the first groove and the plurality of second grooves comprises: Depositing the insulating layer in the first groove and the plurality of second grooves; and Planning the insulating layer until the third channel material layer is exposed. The method for manufacturing a 3D memory device as described in claim 1 or 10, wherein the method for forming the silicon carbide layer includes an epitaxial process. A method for manufacturing a 3D memory device as described in claim 1 or 10, wherein the memory layer includes an ONO layer. A 3D memory device comprises: a substrate; a bottom conductor layer disposed on the substrate; a plurality of stacked structures disposed on the bottom conductor layer, wherein the stacked structures are formed by alternating stacking of multiple oxide layers and multiple gate layers; a selection gate disposed on the multiple stacked structures; a plurality of silicon carbide layers disposed in the bottom conductor layer to separate the bottom conductor layer into multiple blocks; A channel structure, comprising a connecting portion and a plurality of channel pillars, wherein the connecting portion is disposed inside one of the plurality of blocks between the plurality of silicon carbide layers, and the plurality of channel pillars penetrate the selection gate and the plurality of stacked structures and extend to the connecting portion; a first gate dielectric layer, disposed between the connecting portion and the bottom conductor layer; a second gate dielectric layer, disposed between the channel pillar and the selection gate; and a memory layer, disposed between the channel pillar and the stacked structure. The 3D memory device as described in claim 21, wherein the connecting portion is conformally disposed on a surface of the first gate dielectric layer, and the plurality of channel pillars are conformally disposed on sidewalls of the selection gate and the plurality of stacked structures. The 3D memory device as described in claim 22 further includes an insulating material disposed in the inner space of the plurality of channel pillars and the inner space of the connecting portion. A 3D memory device as described in claim 21, wherein the memory layer includes an ONO layer. The 3D memory device of claim 21, wherein the bottom conductive layer comprises a polysilicon layer. The 3D memory device as described in claim 21 further includes a semiconductor inter-silicon wall disposed between the memory layer and the channel pillar. The 3D memory device of claim 21, wherein the multi-layer gate layer comprises a semiconductor gate or a metal gate.