TWI862355B - Controllable current source circuit and pulse generator - Google Patents

Abstract

A controllable current source circuit includes a control circuit, a current source, a detection circuit, and a reset circuit. The control circuit generates an enable signal according to ae control signal and a flag signal. The current source is coupled between a supply voltage and an output node and controlled by the enable signal. In a charging period, the control circuit generates the enable signal according to the flag signal with an enabled state to control the current source to provide a charging current to the output node. In the charging period, when the detection circuit detects that an output voltage at the output node is greater than or equal to a threshold voltage, the detection circuit switches the flag signal to a disabled state. In the charging period, the control circuit generates the enable signal according to the flag signal with the disabled state to control the current source to stop providing the charging current. The reset circuit resets the flag signal to the enabled state from the disabled state according to the control signal.

Description

Controllable current source circuit and pulse generator

The present invention relates to a pulse generator, and in particular to a controllable current source circuit for the pulse generator.

Generally speaking, in a pulse generator, a pre-charge circuit is provided to charge a capacitor to generate a corresponding voltage, thereby triggering the pulse generator to generate a pulse signal. The signal used to control the pre-charge circuit first passes through a plurality of delay buffers connected in series. The delay time provided by the delay buffer determines the pulse width of the pulse signal. However, the delay time is easily changed with process variation, resulting in the pulse width of the pulse signal being distributed in a wider range, making it difficult to control the pulse width of the pulse signal.

In view of this, the present invention proposes a controllable current source circuit. The controllable current source circuit includes a control circuit, a current source, a detection circuit, and a reset circuit. The control circuit receives a control signal and a flag signal, and generates an enable signal according to the control signal and the flag signal. The enabled control signal indicates that the controllable current source circuit enters a charging period. The current source is coupled between a supply voltage and an output node, and is controlled by the enable signal. During the charging period, the control circuit generates an enable signal according to the flag signal in an enable state to control the current source to provide a charging current to charge the output node. The detection circuit is coupled to the output node, has a critical voltage, and detects an output voltage of the output node. During the charging period, when the detection circuit detects that the output voltage is greater than or equal to the critical voltage, the detection circuit switches the flag signal to a disabled state. During the charging period, the control circuit generates an enable signal according to the flag signal in the disabled state to control the current source to stop providing the charging current. The reset circuit receives the control signal and resets the flag signal from the disabled state to the enabled state according to the control signal.

The present invention provides a pulse generator. The pulse generator includes a first inverter, a delay buffer circuit, a capacitor, a first controllable current source circuit, a second inverter, a third inverter, a pulse generating circuit, and a second controllable current source circuit. The first inverter receives a control signal and inverts the control signal to generate a reverse control signal. The enabled control signal indicates that the pulse generator enters a charging period. The delay buffer circuit receives the reverse control signal and delays the reverse control signal to generate a delayed control signal. The capacitor is coupled between a first node and a ground. The first controllable current source circuit is coupled to a supply voltage and the first node, and receives the reverse control signal and the delay control signal. During charging, the first controllable current source circuit provides a first charging current to the first node according to the reverse control signal and the delay control signal to charge the capacitor. The second inverter is coupled between the first node and a second node. The third inverter is coupled between the second node and a third node. The second inverter and the third inverter generate a trigger signal at the third node according to a trigger voltage of the first node. The pulse generating circuit is coupled to the third node to receive the trigger signal, receive the control signal, and generate a pulse signal. The pulse generating circuit determines the width of a pulse of the pulse signal according to the trigger signal and the control signal. The second controllable current source circuit is coupled to the first node and receives the control signal. During the charging period, the second controllable current source circuit provides a second charging current to the first node according to the control signal to charge the capacitor.

In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, a preferred embodiment is specifically described below in detail with reference to the accompanying drawings.

FIG. 1 shows a controllable current source circuit according to an embodiment of the present invention. As shown in FIG. 1, the controllable current source circuit 1 operates to provide a charging current I10 to an output node N11, and includes a reset circuit 10, a control circuit 11, a current source 12, and a detection circuit 13. The control circuit 11 receives a control signal S10 and a flag signal S11, and generates an enable signal S12 according to the control signal S10 and the flag signal S11. When the control signal S10 is enabled, it indicates that the controllable current source circuit 1 enters a charging period P20 (shown in FIG. 2). In one embodiment, the control circuit 11 includes an anti-AND gate 110, which receives the control signal S10 and the flag signal S11, and outputs an enable signal S12.

The current source 12 is coupled between the supply voltage VD and the output node N11, and is controlled by the enable signal S12. During the charging period P20, when the flag signal S11 is in the enable state, the control circuit 11 controls the current source 12 through the enable signal S12, so that it provides a charging current I10 to charge the output node N11. In one embodiment, the current source 12 includes a P-type transistor 120, which has a control electrode for receiving the enable signal S12, an input electrode coupled to the supply voltage VD, and an output electrode coupled to the output node N11. In this embodiment, the P-type transistor 120 is implemented as a P-type metal-oxide-semiconductor (PMOS) transistor. The control electrode, input electrode, and output electrode of the P-type transistor 120 correspond to the gate, source, and drain of the PMOS transistor, respectively.

The detection circuit 13 is coupled to the output node N11, and is coupled to the NAND gate 110 at the node N10. The flag signal S11 is generated at the node N10. The reset circuit 10 and the detection circuit 13 are coupled to the node N10. The detection circuit 13 has a critical voltage, and detects the output voltage V11 of the output node N11. During the charging period P20, when the detection circuit 13 detects that the output voltage V11 is greater than or equal to the critical voltage, the detection circuit 13 switches the flag signal S11 to a disabled state. In addition, during the charging period P20, when the flag signal S11 is in the disabled state, the control circuit 12 generates an enable signal S12 to control the current source 12 to stop providing the charging current I10. The reset circuit 10 receives the control signal S10 and resets the flag signal S11 from the disabled state to the enabled state according to the control signal S10.

In one embodiment, the detection circuit 13 includes an N-type transistor 130 having a control electrode coupled to the output node N11, an input electrode coupled to the node N10, and an output electrode coupled to the ground GND. In this embodiment, the N-type transistor 130 is implemented by an N-type metal-oxide-semiconductor (NMOS) transistor. The control electrode, input electrode, and output electrode of the N-type transistor 130 correspond to the gate, drain, and source of the NMOS transistor, respectively. The critical voltage VTH of the NMOS transistor 130 serves as the critical voltage of the detection circuit 13.

Referring to FIG. 1 , the reset circuit 10 includes a P-type transistor 100 having a control electrode for receiving a control signal S10, an input electrode coupled to a supply voltage VD, and an output electrode coupled to a node N10. In this embodiment, the P-type transistor 100 is implemented as a PMOS transistor. The control electrode, input electrode, and output electrode of the P-type transistor 100 correspond to the gate, source, and drain of the PMOS transistor, respectively.

FIG. 2 shows a timing diagram of the change of the control signal S10, the flag signal S11, the enable signal S12, and the output voltage V11. Referring to FIG. 1 and FIG. 2, before the time point T20, the control signal S10 is at a low voltage level (e.g., a low voltage level of the voltage VS of the ground GND) to turn on the PMOS transistor 100. At this time, the flag signal S11 is at a high voltage level of the supply voltage VD, that is, the flag signal S11 is in an enabled state. According to the low voltage level of the control signal S10 and the high voltage level of the flag signal S11, the enable signal S12 generated by the NAND gate 110 is at a high voltage level of the supply voltage VD to turn off the PMOS transistor 120. The current source 12 does not provide the charging current I10 to the output node N11.

At time point T20, the control signal S10 switches from a low voltage level to a high voltage level of the supply voltage VD (i.e., the control signal S10 is enabled), which indicates that the controllable current source circuit 1 enters the charging period P20. The high voltage level control signal S10 turns off the PMOS transistor 100. At this time, the flag signal S11 is still at a high voltage level of the supply voltage VD. According to the high voltage level control signal S10 and the high voltage level flag signal S11, the enable signal S12 generated by the NAND gate 110 switches to a low voltage level of the voltage VS to turn on the PMOS transistor 120. At this time, the current source 12 provides a charging current I10 to the output node N11, so that the output voltage V11 gradually increases toward the supply voltage VD.

At time point T21, the output voltage V11 increases to the critical voltage VTH0 of the NMOS transistor 130 (the critical voltage VTH serves as the critical voltage of the detection circuit 13), and the NMOS transistor 130 is turned on, so that the flag signal S11 switches from a high voltage level to a low voltage level of the voltage VS. In other words, at time point T21, the detection circuit 13 detects that the output voltage V11 is equal to the critical voltage VTH0, and the flag signal S11 switches to a disabled state. At this time, the control signal S10 is still at a high voltage level. According to the high voltage level control signal S10 and the low voltage level flag signal S11, the enable signal S12 generated by the NAND gate 110 switches to a high voltage level to turn off the PMOS transistor 120. At this time, the current source 12 stops providing the charging current I10 to the output node N11, and the output voltage V11 is maintained at the critical voltage VTH.

In this embodiment, at time point T22, the control signal S10 is switched from a high voltage level to a low voltage level (i.e., the control signal S10 is disabled), which indicates that the charging period P20 ends. The low voltage level control signal S10 turns on the PMOS transistor 100. At this time, the flag signal S11 is switched from a low voltage level to a high voltage level. The enable signal S12 generated by the NAND gate 110 is at a high voltage level to turn off the PMOS transistor 120. The output voltage V11 continues to be at the critical voltage VTH.

According to the above, according to the control signal S10 and the flag signal S11, the current source 12 can provide the charging current I10 to the output node N11. The controllable current source circuit 1 of the present case has a self-stop mechanism. Through the detection circuit 13 to detect the output voltage V11, when the output voltage V11 reaches the critical voltage VTH, the controllable current source circuit 1 stops the current source 12 from providing the charging current I10.

The controllable current source circuit 1 of the present case can be applied to various applications. For example, the controllable current source circuit 1 of the present case can be applied to a pulse generator. Referring to FIG. 3 , the pulse generator 3 includes the controllable current source circuit 1. The pulse generator 3 also includes an inverter 30, a delay buffer circuit 31, a controllable current source circuit 32, a discharge circuit 33, a capacitor 34, inverters 35 and 36, a pulse generating circuit 37, and a finite state machine (FSM) 38. The output node N11 of the controllable current source circuit 1 is directly connected to the node N33 of FIG. 3. Therefore, in this embodiment, the output voltage V11 on the output node N11 is equal to the trigger voltage V33 on the node N33. In the following description, in order to briefly explain the operation of the pulse generator 3, the trigger voltage V33 is used to describe the voltage changes at the node N33 and the output node N11.

Referring to FIG. 3 , the inverter 30 receives the control signal S10 and inverts the control signal S10 to generate an inverted control signal S30 at the node N30. In this embodiment, the enabled control signal S10 indicates that the pulse generator 3 enters a charging period P40 (shown in FIG. 4 ). The delay buffer circuit 31 couples the inverter 30 at the node N30 to receive the inverted control signal S30 and delays the inverted control signal S30 to generate a delayed control signal S31 at the node N31. In this embodiment, the delay buffer circuit 31 includes a plurality of delay buffers 310 connected in series between the node N30 and the node N31. The sum of the delay amounts of these delay buffers 310 corresponds to the time td (shown in FIG. 4 , referred to as delay time) that the delay buffer circuit 31 delays the reverse control signal S30.

The controllable current source circuit 32 is coupled between the supply voltage VD and the node N32, and receives the reverse control signal S30 and the delay control signal S31. The capacitor 34 is coupled between the node N33 and the ground GND. During the charging period P40, the controllable current source circuit 32 provides a charging current I30 to the node N33 according to the reverse control signal S30 and the delay control signal S31 to charge the capacitor 34. In this embodiment, the controllable current source circuit 32 includes P-type transistors 320 and 321. The control electrode of the P-type transistor 320 is coupled to the node N30 to receive the reverse control signal S30, its input electrode is coupled to the supply voltage VD, and its output electrode is coupled to the node N32. The control electrode of the P-type transistor is coupled to the node N31 to receive the delay control signal S31, the input electrode is coupled to the node N32, and the output electrode is coupled to the node N33. In this embodiment, each of the P-type transistors 320 and 321 is implemented by a PMOS transistor. The control electrode, input electrode, and output electrode of each of the P-type transistors 320 and 321 correspond to the gate, source, and drain of the PMOS transistor, respectively.

Referring to FIG. 3 , the output node N11 of the controllable current source circuit 1 is directly connected to the node N33. The detailed circuit structure of the controllable current source circuit 1 is shown in FIG. 1 , and the description is omitted here. During the charging period P40 , the controllable current source circuit 1 provides a charging current I10 to the node N33 according to the control signal S10 to charge the capacitor 34 .

According to the above, during the charging period P40, not only the controllable current source circuit 32 provides the charging current I30 to the node N33 to charge the capacitor 34, but the controllable current source circuit 1 also provides the charging current I10 to the node N33 to charge the capacitor 34. Therefore, in the embodiment of FIG. 3, the change of the trigger voltage V33 on the node N33 is different from the change of the output voltage V11 on the output node N11 shown in FIG. 2. Hereinafter, the change of the trigger voltage V33 will be described in detail.

The discharge circuit 33 is coupled between the node N33 and the ground GND, and receives the reverse control signal S30. The discharge circuit 33 includes an N-type transistor 330. The control electrode of the N-type transistor is coupled to the node N30 to receive the reverse control signal S30, its input electrode is coupled to the node N33, and its output electrode is coupled to the ground GND. In this embodiment. The N-type transistor 330 is implemented by an NMOS transistor. The control electrode, input electrode, and output electrode of the N-type transistor 330 correspond to the gate, drain, and source of the NMOS transistor, respectively. In this embodiment, the disabled control signal S10 indicates that the charging period P40 of the pulse generator 3 ends, and the pulse generator 3 enters the discharge period. Through the operation of the inverter 30, during the discharge period, the NMOS transistor 330 is turned on according to the reverse control signal S30. The turned-on NMOS transistor 330 provides a discharge path between the node N33 and the ground to discharge the capacitor 34.

Referring to FIG. 3 , an inverter 35 is coupled between a node N33 and a node N34, and an inverter 36 is coupled between a node N34 and a node N35. The inverters 35 and 36 operate together to generate a trigger signal S36. The inverters 35 and 36 each have a trigger point voltage Vp. According to the trigger voltage V33 on the node N33 and the trigger point voltage Vp, the inverters 35 and 36 switch the trigger signal S36.

The pulse generating circuit 37 is coupled to the node N35 to receive the trigger signal S36, receive the control signal S10, and generate a pulse signal S37. The pulse generating circuit 37 determines the width of a pulse of the pulse signal S37 according to the trigger signal S36 and the control signal S10. For example, in this embodiment, the pulse generating circuit 37 switches the pulse signal S37 from a high voltage level to a low voltage level according to the enable edge (rising edge) of the control signal S10 to have a disable edge (falling edge), and the pulse generating circuit 37 switches the pulse signal S37 from a low voltage level to a high voltage level according to the enable edge (rising edge) of the trigger signal S36 to have a consistent enable edge (rising edge). The disable edge, the enable edge, and the low voltage level of the pulse signal S37 form a pulse, such as the pulse 40 of FIG. 4, which can be called a reverse pulse. According to the above, the width W40 between the disable edge and the enable edge of the pulse 40 is determined by the enable edge of the trigger signal S36 and the enable edge of the control signal S10. The duration of the width W40 of the pulse 40 is the sum of the durations P41 to P43.

The finite state machine 38 receives the trigger signal S36 and disables the control signal S10 according to the consistent energy edge of the trigger signal S36.

FIG. 4 shows a timing diagram of main signals and voltages of the pulse generator 3 of FIG. 3 according to an embodiment of the present invention. The operation of the pulse generator 3 will be described in detail below through FIG. 3 and FIG. 4.

Before time point T40, control signal S10 is at a low voltage level (e.g., a low voltage level of voltage VS of ground GND) to turn on PMOS transistor 100. At this time, flag signal S11 is at a high voltage level of supply voltage VD, i.e., flag signal S11 is in an enabled state. Based on the control signal S10 at a low voltage level and the flag signal S11 at a high voltage level, the enable signal S12 generated by NAND gate 110 is at a high voltage level of supply voltage VD to turn off PMOS transistor 120. Controllable current source circuit 1 does not provide charging current I10 to node N33. In addition, through the operation of the inverter 30, the reverse control signal S30 is at a high voltage level of the supply voltage VD to turn off the PMOS transistor 320. Therefore, the controllable current source circuit 32 does not provide the charging current I30 to the node N33. The total current I(V33) provided to the node N33 is zero, and the trigger voltage V33 on the node N33 is at a low voltage level of the voltage VS of the ground GND.

At time point T40, the control signal S10 switches from a low voltage level to a high voltage level of the supply voltage VD (i.e., the control signal S10 is enabled), which indicates that the pulse generator 3 enters the charging period P40. The high voltage level control signal S10 turns off the PMOS transistor 100. At this time, the flag signal S11 is still at a high voltage level of the supply voltage VD. According to the high voltage level control signal S10 and the high voltage level flag signal S11, the enable signal S12 generated by the NAND gate 110 switches to a low voltage level of the voltage VS of the ground GND to turn on the PMOS transistor 120. At this time, the controllable current source circuit 1 provides a charging current I10 to the node N33. The trigger voltage V33 gradually increases toward the supply voltage VD. In addition, through the operation of the inverter 30, the reverse control signal S30 is switched from a high voltage level to a low voltage level of the voltage VS to turn on the PMOS transistor 320. It should be noted that due to the delay operation of the delay buffer circuit 31, the delay control signal S31 is still at a high voltage level of the supply voltage VD to turn off the PMOS transistor 321. Since the PMOS transistor 321 is turned off, the controllable current source circuit 32 does not provide the charging current I30 to the node N33.

In addition, at time point T40, the pulse generating circuit 37 switches the pulse signal S37 from the high voltage level of the supply voltage VD to the low voltage level of the voltage VS according to the enabling edge (rising edge) of the control signal S10, so as to have a disabling edge F40 (falling edge).

Referring to FIG. 4 , the charging period P40 includes the periods P41 to P44. The period during which the trigger voltage V33 rises from the level of the voltage VS to the level of the trigger point voltage Vp includes the periods P41 to P43. In the period P41 between the time points T40 and T41, the node N33 is charged only by the charging current I10.

As shown in FIG. 4 , due to the delay operation of the delay buffer circuit 31, at time point T41, the delay control signal S31 responds to the voltage level switching of the reverse control signal S30 and switches to the low voltage level of the voltage VS. The period between time points T40 and T41 is the delay time td provided by the delay buffer circuit 31. Based on the delay control signal S31 switching to the low voltage level, the PMOS transistor 321 is turned on. At this time, both the PMOS transistors 320 and 321 are turned on, so the controllable current source circuit 32 provides the charging current I30 to the node N33. Referring to FIG. 4, in the period P42 between time points T41 and T42, the node N33 is charged by the charging current I10 and the charging current I30, and the trigger voltage V33 continues to gradually increase toward the supply voltage VD. Since the amount of current (charging currents I10 and I30) charged to the node N33 in the period P42 is greater than the amount of current (charging current I10) charged to the node N33 in the period P41, the rising slope of the trigger voltage V33 in the period P42 is greater than the rising slope of the trigger voltage V33 in the period P41.

At time point T42, the trigger voltage V33 increases to the critical voltage VTH of the NMOS transistor 130, and the NMOS transistor 130 is turned on, so that the flag signal S11 switches from a high voltage level to a low voltage level of the voltage VS. In other words, at time point T42, the detection circuit 13 detects that the trigger voltage V33 is equal to the critical voltage VTH, and the flag signal S11 switches to a disabled state. At this time, the control signal S10 is still at a high voltage level. According to the high voltage level control signal S10 and the low voltage level flag signal S11, the enable signal S12 generated by the NAND gate 110 is switched to a high voltage level to turn off the PMOS transistor 120. At this time, the controllable current source circuit 1 stops providing the charging current I10 to the node N33. Referring to FIG. 4, during the period P43 between the time points T42 and T43, only the charging current I30 continues to charge the node N33, and the trigger voltage V33 continues to gradually increase from the critical voltage VTH toward the supply voltage VD. Since the amount of current (charging current I30) charging the node N33 in period P43 is less than the amount of current (charging currents I10 and I30) charging the node N33 in period P42, the rising slope of the trigger voltage V33 in period P43 is less than the rising slope of the trigger voltage V33 in period P42.

Before the time point T43, the inverters 35 and 36 are not triggered, and the trigger signal S36 is at the low voltage level of the voltage VS. At the time point T43, the trigger voltage V33 increases to the trigger point voltage Vp of the inverters 35 and 36. At this time, the inverters 35 and 36 transition the trigger signal S36 to switch it from the low voltage level to the high voltage level of the supply voltage VD. In addition, at the time point T43, the pulse generating circuit 37 switches the pulse signal S37 from the low voltage level to the high voltage level according to the enable edge (rising edge) of the trigger signal S36, so as to have the enable edge R40 (rising edge). The falling edge F40 at time point T40 and the rising edge R40 at time point T43 define the width W40 of the pulse 40.

In addition, at time point T43, the finite state machine 38 disables the control signal S10 after a predetermined time according to the enabling edge (rising edge) of the trigger signal S36. Referring to FIG. 4, the finite state machine 38 disables the control signal S10 at time point T44.

During the period between time point T43 and time point T44, node N33 is continuously charged only by charging current I30, and trigger voltage V33 continues to gradually increase toward supply voltage VD.

At time point T44, the control signal S10 is switched from a high voltage level to a low voltage level (i.e., the control signal S10 is disabled), which indicates that the charging period P40 ends. The low voltage level control signal S10 turns on the PMOS transistor 100. At this time, the flag signal S11 is switched from a low voltage level to a high voltage level. The enable signal S12 generated by the NAND gate 110 is at a high voltage level to turn off the PMOS transistor 120. At time point T44, through the operation of the inverter 30, the reverse control signal S30 is switched from a low voltage level to a high voltage level to turn off the PMOS transistor 320. Therefore, the controllable current source circuit 32 does not provide the charging current I30 to the node N33. According to the above, at time point T44, the controllable current source circuit 1 does not provide the charging current I10 to the node N33, and the controllable current source circuit 32 does not provide the charging current I30 to the node N33. The trigger voltage V33 is close to the maximum voltage level, that is, the voltage level of the supply voltage VD.

In addition, at time point T44, the reverse control signal S30 switches from a low voltage level to a high voltage level, and the pulse generator 3 enters a discharge period. At this time, the NMOS transistor 330 is turned on, providing a discharge path between the node N33 and the ground to discharge the capacitor 34. The trigger voltage V33 starts to decrease from the voltage level of the supply voltage VD.

At time point T45, the trigger voltage V33 drops to the trigger point voltage Vp. At this time, the inverters 35 and 36 switch the trigger signal S36 from a high voltage level to a low voltage level.

According to the above, the pulse generator 3 of the present invention provides the charging current I10 through the controllable current source circuit 1 to help control the width W40 of the pulse 40, so that the distribution range of the width W40 in time can be close to the desired range. In this way, it can be avoided that the width W40 of the pulse 40 cannot be accurately controlled due to the delay time td of the delay buffer circuit 31 being affected by the process variation.

In the above embodiment, the critical voltage provided by the detection circuit 13 of the controllable current source circuit 1 is the critical voltage VTH of the NMOS transistor 130. In other embodiments, the critical voltage provided by the detection circuit 13 may be N times the critical voltage VTH, where N is a positive integer greater than 1.

Referring to FIG. 5 , the circuit architecture of the pulse generator 5 is substantially the same as the circuit architecture of the pulse generator 3 of FIG. 3 . The difference between the pulse generator 5 and the pulse generator 3 lies in the architecture of the detection circuit 13 of the controllable current source circuit 1 .

As shown in FIG. 5 , the detection circuit 13 of FIG. 5 includes not only an NMOS transistor 130 but also at least one diode. In this embodiment, a diode 50 is used as an example for explanation. The diode 50 is coupled between the source of the NMOS transistor 130 and the ground GND. The diode 50 is implemented by an NMOS transistor 500. The gate and drain of the NMOS transistor 500 are connected to each other and to the source of the NMOS transistor 130. The source of the NMOS transistor 500 is coupled to the ground GND. It can be seen that the NMOS transistor 500 is a diode-connected transistor. In this embodiment, the critical voltage provided by the detection circuit 13 is the sum of the critical voltage VTH of the NMOS transistor 130 and the critical voltage VTH of the NMOS transistor 500, that is, twice the critical voltage VTH.

FIG. 6 shows a timing diagram of the main signals and voltages of the pulse generator 5 of FIG. 5 according to an embodiment of the present invention. The operation of the pulse generator 5 is substantially the same as that of the pulse generator 3, except that the rise of the trigger voltage V33 in the periods P42 and P43 is different. For the sake of simplicity, only the change of the trigger voltage V33 in the periods P42 and P43 is described below.

Referring to FIG. 6 , during the period P42 between time points T41 and T42, the node N33 is charged by the charging current I10 and the charging current I30, and the trigger voltage V33 continues to gradually increase toward the supply voltage VD. At time point T42, the trigger voltage V33 increases to twice the critical voltage VTH (2*VTH) of the NMOS transistor 130, and the NMOS transistor 130 is turned on. In other words, at time point T42, the detection circuit 13 detects that the trigger voltage V33 is equal to twice the critical voltage VTH (2*VTH), and the flag signal S11 switches to a disabled state. At this time, the control signal S10 is still at a high voltage level. According to the high voltage level control signal S10 and the low voltage level flag signal S11, the enable signal S12 generated by the NAND gate 110 switches to a high voltage level to turn off the PMOS transistor 120. At this time, the controllable current source circuit 1 stops providing the charging current I10 to the node N33. Referring to FIG. 6, in period P42, the trigger voltage V33 is increased to 2 times the critical voltage VTH (2*VTH). Therefore, the period P42 of FIG. 6 is longer than the period P42 of FIG. 4. Specifically, the period P42 of FIG. 6 is equal to 2 times the period P42 of FIG. 4.

Referring to FIG. 6, during the period P43 between time points T42 and T43, the node N33 is continuously charged only by the charging current I30, and the trigger voltage V33 gradually increases from twice the critical voltage VTH (2*VTH) toward the supply voltage VD. Since the starting point voltage of the trigger voltage V33 rising during the period P43 of FIG. 6 is twice the critical voltage VTH (2*VTH), the trigger voltage V33 rises to the trigger point voltage Vp faster, which shortens the length of the period P43. Referring to FIG. 4 and FIG. 6, the period P43 of FIG. 6 is shorter than the period P43 of FIG. 4. In general, the sum of the periods P41 to P43 in FIG. 6 is smaller than the sum of the periods P41 to P43 in FIG. 4 , that is, the width W40 of the pulse 40 in FIG. 6 is smaller than the width W40 of the pulse 40 in FIG. 4 .

According to the above, the width W40 of the pulse 40 can be changed by adjusting or changing the critical voltage of the detection circuit 13. Therefore, the pulse generator proposed in this case can adaptively change the width W40 of the pulse 40 according to system requirements.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined in the attached patent application.

1: Controllable current source circuit 3,5: Pulse generator 10: Reset circuit 11: Control circuit 12: Current source 13: Detection circuit 30: Inverter 31: Delay buffer circuit 32: Controllable current source circuit 33: Discharge circuit 34: Capacitor 35,36: Inverter 37: Pulse generator circuit 38: Finite state machine (FSM) 40: Pulse 50: Diode 500: N-type transistor (NMOS transistor) 100: P-type transistor (PMOS transistor) 110: FAND gate 120: P-type transistor (PMOS transistor) 130: N-type transistor (NMOS transistor) 310: Delay buffer 320,321: P-type transistor (PMOS transistor) 330: N-type transistor (NMOS transistor) F40: Disable edge (falling edge) GND: Ground I10,I30: Charging current I(V33): Total current of node N33 N10: Node N11: Output node N30~N35: Node P20, P40: Charging period P41~P43: Period R40: Enable edge (rising edge) S10: Control signal S11: Flag signal S12: Enable signal S30: Reverse control signal S31: Delay control signal S36: trigger signal S37: pulse signal T20~T22: time point T40~T45: time point V11: output voltage V33: trigger voltage Vp: trigger point voltage VD: supply voltage VS: ground voltage VTH: critical voltage W40: width

FIG. 1 shows a controllable current source circuit according to an embodiment of the present invention. FIG. 2 shows a timing diagram of the main signal and voltage change of the controllable current source circuit of FIG. 1 according to an embodiment of the present invention. FIG. 3 shows a pulse generator according to an embodiment of the present invention. FIG. 4 shows a timing diagram of the main signal and voltage of the pulse generator of FIG. 3 according to an embodiment of the present invention. FIG. 5 shows a pulse generator according to another embodiment of the present invention. FIG. 6 shows a timing diagram of the main signal and voltage of the pulse generator of FIG. 6 according to an embodiment of the present invention.

1: Controllable current source circuit

10: Reset circuit

11: Control circuit

12: Current source

13: Detection circuit

100: P-type transistor (PMOS transistor)

110: Anti-gate

120: P-type transistor (PMOS transistor)

130: N-type transistor (NMOS transistor)

GND: Ground

I10: Charging current

N10: Node

N11: Output node

S10: Control signal

S11: Flag signal

S12: Enable signal

V11: Output voltage

VD: Supply voltage

VS: Voltage of ground GND

Claims (19)

A controllable current source circuit comprises: A control circuit, receiving a control signal and a flag signal, and generating an enable signal according to the control signal and the flag signal, wherein the enabled control signal indicates that the controllable current source circuit enters a charging period; A current source, coupled between a supply voltage and an output node, and controlled by the enable signal, wherein during the charging period, the control circuit generates the enable signal according to the flag signal in an enabled state to control the current source to provide a charging current to charge the output node; A detection circuit, coupled to the output node, having a critical voltage, and detecting an output voltage of the output node, wherein during the charging period: When the detection circuit detects that the output voltage is greater than or equal to the critical voltage, the detection circuit switches the flag signal to a disabled state, and the control circuit generates the enable signal according to the flag signal in the disabled state to control the current source to stop providing the charging current; and a reset circuit receives the control signal and resets the flag signal from the disabled state to the enabled state according to the control signal. A controllable current source circuit as claimed in claim 1, wherein: the control signal being disabled indicates the end of the charging period, and when the control signal is disabled, the reset circuit resets the flag signal to the enabled state. A controllable current source circuit as claimed in claim 1, wherein the control circuit comprises: an NAND gate, receiving the control signal and the flag signal, and outputting the enable signal. A controllable current source circuit as claimed in claim 1, wherein the current source comprises: A P-type transistor having a control electrode for receiving the enable signal, an input electrode coupled to the supply voltage, and an output electrode coupled to the output node. A controllable current source circuit as claimed in claim 1, wherein the detection circuit is coupled to the reset circuit at a first node, the flag signal is generated at the first node, and the detection circuit comprises: an N-type transistor having a control electrode coupled to the output node, an input electrode coupled to the first node, and an output electrode coupled to a ground, wherein the N-type transistor determines the critical voltage. As in claim 5, the controllable current source circuit, wherein the detection circuit further comprises: At least one diode coupled between the output electrode of the N-type transistor and the ground, wherein the N-type transistor and the at least one diode determine the critical voltage. A controllable current source circuit as claimed in claim 1, wherein the detection circuit is coupled to the reset circuit at a first node, the flag signal is generated at the first node, and the reset circuit comprises: A P-type transistor having a control electrode for receiving the control signal, an input electrode coupled to the supply voltage, and an output electrode coupled to the first node. A pulse generator includes: a first inverter, receiving a control signal, and inverting the control signal to generate a reverse control signal, wherein the enabled control signal indicates that the pulse generator enters a charging period; a delay buffer circuit, receiving the reverse control signal, and delaying the reverse control signal to generate a delay control signal; a capacitor, coupled between a first node and a ground; a first controllable current source circuit, coupled to a supply voltage and the first node, and receiving the reverse control signal and the delay control signal, wherein, during the charging period, the first controllable current source circuit provides a first charging current to the first node according to the reverse control signal and the delay control signal to charge the capacitor; A second inverter coupled between the first node and a second node; A third inverter coupled between the second node and a third node, wherein the second inverter and the third inverter generate a trigger signal at the third node according to a trigger voltage of the first node; A pulse generating circuit coupled to the third node to receive the trigger signal, receive the control signal, and generate a pulse signal, wherein the pulse generating circuit determines the width of a pulse of the pulse signal according to the trigger signal and the control signal; and A second controllable current source circuit is coupled to the first node and receives the control signal, wherein during the charging period, the second controllable current source circuit provides a second charging current to the first node according to the control signal to charge the capacitor. The pulse generator of claim 8 further includes: a discharge circuit coupled to the first node and receiving the reverse control signal, wherein the enabled reverse control signal instructs the controllable current source circuit to enter a discharge period, wherein during the discharge period, the discharge circuit discharges the capacitor. A pulse generator as claimed in claim 8, wherein the first controllable current source circuit comprises: a first P-type transistor having a control electrode for receiving the reverse control signal, an input electrode coupled to a supply voltage, and an output electrode coupled to a fourth node; and a second P-type transistor having a control electrode for receiving the delay control signal, an input electrode coupled to a fourth node, and an output electrode coupled to the first node. The pulse generator of claim 8, wherein the second controllable current source circuit comprises: A control circuit, receiving the control signal and a flag signal, and generating an enable signal according to the control signal and the flag signal; A current source, coupled between the supply voltage and the first node, and controlled by the enable signal, wherein, during the charging period, the control circuit generates the enable signal according to the flag signal in an enable state to control the current source to provide the second charging current to the first node; A detection circuit, coupled to the first node, having a critical voltage, and detecting the trigger voltage of the first node, wherein, during the charging period: When the detection circuit detects that the trigger voltage is greater than or equal to the critical voltage, the detection circuit switches the flag signal to a disabled state, and the control circuit generates the enable signal according to the flag signal in the disabled state to control the current source to stop providing the second charging current; and a reset circuit receives the control signal and resets the flag signal from the disabled state to the enabled state according to the control signal. A pulse generator as claimed in claim 11, wherein: the control signal being disabled indicates the end of the charging period, and when the control signal is disabled, the reset circuit resets the flag signal to the enabled state. The pulse generator of claim 11, wherein the control circuit of the second controllable current source circuit includes: An NAND gate, receiving the control signal and the flag signal, and outputting the enable signal. A pulse generator as claimed in claim 11, wherein the current source of the second controllable current source circuit comprises: A P-type transistor having a control electrode for receiving the enable signal, an input electrode coupled to the supply voltage, and an output electrode coupled to the first node. A pulse generator as claimed in claim 11, wherein the detection circuit of the second controllable current source circuit is coupled to the reset circuit at a fourth node, the flag signal is generated at the fourth node, and the detection circuit comprises: an N-type transistor having a control electrode coupled to the first node, an input electrode coupled to the fourth node, and an output electrode coupled to the ground, wherein the N-type transistor determines the critical voltage. The pulse generator of claim 15, wherein the detection circuit of the second controllable current source circuit further comprises: At least one diode coupled between the output electrode of the N-type transistor and the ground, wherein the N-type transistor and the at least one diode determine the critical voltage. A pulse generator as claimed in claim 11, wherein the detection circuit of the second controllable current source circuit is coupled to the reset circuit at a fourth node, the flag signal is generated at the fourth node, and the reset circuit comprises: A P-type transistor having a control electrode for receiving the control signal, an input electrode coupled to the supply voltage, and an output electrode coupled to the fourth node. A pulse generator as claimed in claim 8, wherein: the charging period includes a first period, a second period, and a third period in sequence, the second controllable current source circuit provides the second charging current to the first node during the first period and the second period, and the first controllable current source circuit provides the first charging current to the first node during the second period and the third period. The pulse generator of claim 8 further comprises: a finite state machine that receives the trigger signal, wherein, according to the consistent energy edge of the trigger signal, the finite state machine disables the control signal.

Images