TWI862185B - Memory clock control method and control device - Google Patents

Abstract

The memory clock control method includes: sending an initial signal to the auxiliary input and output chip by the basic input and output chip which is triggered by a start signal; setting a voltage of a pin according to a pre-stored voltage control data by the auxiliary input and output chip which is triggered by the start signal, wherein the pin is connected to a memory and the voltage is used to control a clock mode of the memory; adjusting the voltage control data of the auxiliary input and output chip according to a change clock command and executing a reboot procedure to re-send the start signal to the auxiliary input and output chip by the basic input and output chip, wherein a first clock mode corresponding to the voltage control data before adjustment is a non-overclocking mode, and a second clock mode corresponding to the adjusted voltage control data is an overclocking mode.

Description

Memory clock control method and control device

The present invention relates to a memory clock control method and a control device.

In general computer equipment, random-access memory (RAM) is the memory that directly exchanges data with the central processing unit. Its clock rate indicates the frequency of data entering and exiting the memory. The higher the clock rate, the more transfers can be performed per second. In order to ensure the stability of their products, manufacturers of non-overclocked memory usually pre-set the clock rate of the memory to only be within a factory default clock rate range when it leaves the factory. The factory default clock rate range is smaller than the clock rate range that the memory itself is capable of operating. Therefore, if users want to make the non-overclocked memory of computer equipment work at a higher processing speed, they often need to manually adjust the factory settings of the memory before performing the so-called overclocking operation. The process is complicated and prone to problems.

In view of the above, the present invention provides a memory clock control method and a control device.

According to an embodiment of the present invention, a memory clock control method comprises the steps of: a basic input-output chip is triggered by a power-on signal to send a start signal to an auxiliary input-output chip; the auxiliary input-output chip is triggered by the start signal to set a voltage of a pin according to a pre-stored voltage control data, wherein the pin is connected to a memory and the voltage is used to control a clock mode of the memory; when the basic input-output chip is controlled to generate a start signal, the auxiliary input-output chip is triggered by the start signal to set a voltage of a pin according to a pre-stored voltage control data; When a change clock instruction associated with the memory is generated, the basic input-output chip adjusts the voltage control data of the auxiliary input-output chip according to the change clock instruction, and executes a restart procedure to re-send the start signal to the auxiliary input-output chip, wherein a first clock mode corresponding to the voltage control data before adjustment is a non-overclocking mode, and a second clock mode corresponding to the voltage control data after adjustment is an overclocking mode.

A memory clock control device according to an embodiment of the present invention comprises a processor, a memory, an auxiliary input-output chip and a basic input-output chip. The memory is connected to the processor. The auxiliary input-output chip is connected to the memory and is used to be triggered by a start signal to set a voltage of a pin of the auxiliary input-output chip according to a pre-stored voltage control data, wherein the pin is connected to the memory and the voltage is used to control a clock mode of the memory. The basic input-output chip is connected to the processor and the auxiliary input-output chip, and is used to be triggered by a power-on signal to send a start signal to the auxiliary input-output chip; when a change clock instruction related to the memory is generated under control, the voltage control data of the auxiliary input-output chip is adjusted according to the change clock instruction, and a restart procedure is executed to re-send the start signal to the auxiliary input-output chip, wherein a first clock mode corresponding to the voltage control data before adjustment is a non-overclocking mode, and a second clock mode corresponding to the voltage control data after adjustment is an overclocking mode.

Through the above structure, the memory clock control method and control device disclosed in this case can store the corresponding voltage control data in the auxiliary input and output chip according to the memory overclocking mode last stored and set by the user through the basic input and output chip, and then decide whether to change the voltage of a specific pin of the auxiliary input and output chip based on whether the voltage control data in the auxiliary input and output chip changes, and the specific pin is connected to the memory, thereby adjusting the memory to operate in a clock frequency range that is not preset by the factory. The computer device using the memory clock control method and control device of the present case can automatically detect whether the memory is to enter the overclocking mode and make corresponding adjustments during the process from starting the power supply to the basic input and output chip boot program.

The above description of the disclosed content and the following description of the implementation methods are used to demonstrate and explain the spirit and principle of the present invention, and provide a further explanation of the scope of the patent application of the present invention.

The following detailed description of the features and advantages of the present invention is provided in the implementation mode, and the content is sufficient to enable any person skilled in the relevant art to understand the technical content of the present invention and implement it accordingly. Moreover, according to the content disclosed in this specification, the scope of the patent application and the drawings, any person skilled in the relevant art can easily understand the relevant purposes and advantages of the present invention. The following embodiments are to further explain the viewpoints of the present invention in detail, but are not to limit the scope of the present invention by any viewpoint.

Please refer to FIG. 1, which is a block diagram of a memory clock control device according to an embodiment of the present invention. As shown in FIG. 1, the memory clock control device 100 includes a processor 1, a memory 2, an auxiliary input-output chip 3, and a basic input-output chip 4. The memory 2 is connected to the processor 1. The auxiliary input-output chip 3 is connected to the memory 2, and is used to be triggered by a start signal to set a voltage of a pin of the auxiliary input-output chip 3 according to a pre-stored voltage control data, wherein the pin is connected to the memory 2 and the voltage is used to control a clock mode of the memory 2. The basic input-output chip 4 is connected to the processor 1 and the auxiliary input-output chip 3, and is used to be triggered by a power-on signal to send a start signal to the auxiliary input-output chip 3; when a change clock instruction related to the memory 2 is generated by the control, the voltage control data of the auxiliary input-output chip 3 is adjusted according to the change clock instruction, and a restart procedure is executed to re-send the start signal to the auxiliary input-output chip 3, wherein a first clock mode corresponding to the voltage control data before adjustment is a non-overclocking mode, and a second clock mode corresponding to the voltage control data after adjustment is an overclocking mode.

In this example, the memory clock control device 100 can be set on a motherboard of a computer device, but the present invention is not limited to this. The processor 1 can be a central processing unit (CPU), a graphics processing unit (GPU), or a computing chip that integrates a central processing unit and a graphics processing unit at the same time, and the present invention is not limited to this. The memory 2 can be a synchronous dynamic random-access memory (SDRAM), and in particular can be a fifth-generation double data rate synchronous dynamic random access memory (DDR5 SDRAM). The memory 2 is connected to the processor 1 to provide various data required by the processor 1. For different memories, their overclocking mode and non-overclocking mode may correspond to different clock frequencies. Specifically, when the clock frequency of a memory is operated within a factory default clock range, it is considered to be in a non-overclocking mode. When the clock frequency of a memory is operated beyond the factory default clock range, it is considered to be in an overclocking mode. The factory default clock range of the above memory depends on each memory manufacturer and memory specification. However, generally speaking, the newer the memory is, the higher the factory default clock range is. In particular, memory 2 may be a non-overclocking memory that is factory defaulted and does not open the overclocking mode. Taking the fifth generation double data rate synchronous DRAM as an example, the base clock frequency of memory 2 in non-overclocking mode can reach 4400 million Hertz (MHz), or it can perform 4400 million data transfers per second (MT/s); while the clock frequency of memory 2 in overclocking mode can be higher than 4400 million Hertz (MHz), or it can perform higher than 4400 million data transfers per second (MT/s). It should be noted that for different memories, the boundary between the base clock frequency in non-overclocking mode and the clock frequency in overclocking mode can be different.

The auxiliary input/output chip 3 and the basic input/output chip 4 are both related to the operation of other hardware and software in the computer device. The basic input/output chip 4 stores the firmware of the basic input/output system (BIOS), which can be realized through a read-only memory (ROM) chip, and can control the basic operation of the computer device, such as the boot process and the power on self-test (POST). The auxiliary input/output chip 3 can be a chip integrating multiple communication link paths, responsible for connecting to other devices, such as keyboards, mice, fans, etc., and can be used to manage the power parameters of multiple devices. In this example, the auxiliary input/output chip 3 can be connected to a specific pin of the memory 2 through a general-purpose input/output (GPIO) pin (to provide a VR_Enabled signal), and the voltage of the general-purpose input/output pin is used to control the clock mode of the memory 2 to be an overclocked clock mode or a non-overclocked clock mode. In this example, the auxiliary input/output chip 3 can be a super I/O chip, and the voltage of the general-purpose input/output pin can be adjusted through a preset value stored in a specific address (such as offset) in the chip. For example, a high level of the general-purpose input/output pin corresponds to the overclocking mode of memory 2, and a low level of the general-purpose input/output pin corresponds to the non-overclocking mode of memory 2. Alternatively, a low level of the general-purpose input/output pin corresponds to the overclocking mode of memory 2, and a high level of the general-purpose input/output pin corresponds to the non-overclocking mode of memory 2. As mentioned above, memory 2 is particularly a non-overclocking memory that does not open the overclocking mode by factory default. The memory clock control device 100 of this embodiment can control the memory 2 to enter the non-overclocking mode through the auxiliary input and output chip 3 by connecting the pins of the auxiliary input and output chip 3 with the memory 2, thereby improving the operating performance of the memory 2.

The voltage of the pin of the auxiliary input output chip 3 is determined according to a voltage control data pre-stored in the auxiliary input output chip 3, and the voltage control data of the auxiliary input output chip 3 can be adjusted by the basic input output chip 4, which will be described in detail later. As shown in FIG. 1 , the memory clock control device 100 may further include a platform path controller 5 (Platform Controller Hub, PCH) as a connection interface between the processor 1, the auxiliary input output chip 3 and the basic input output chip 4. For example, when the computer device is turned on, the basic input output chip 4 can transmit a start signal to the processor 1 and the auxiliary input output chip 3 through the platform path controller 5. Specifically, data can be transmitted between the basic input/output chip 4 of the memory clock control device 100 and the platform path controller 5 via the Serial Peripheral Interface Bus (SPI), data can be transmitted between the auxiliary input/output chip 3 and the platform path controller 5 via the Low Pin Count (LPC), and data can be transmitted between the processor 1 and the platform path controller 5 via the Direct Media Interface (DMI).

Please refer to FIG. 2, which is a flow chart of a memory clock control method according to an embodiment of the present invention. As shown in FIG. 2, the memory clock control method of this embodiment is executed by the memory clock control device 100 shown in FIG. 1, step S1: the basic input and output chip is triggered by a power-on signal to send a start signal to the auxiliary input and output chip; step S3: the auxiliary input and output chip is triggered by the start signal to set a pin of the auxiliary input and output chip according to a pre-stored voltage control data. When the basic input/output chip is controlled to generate a change clock instruction related to the memory, step S5 is executed: the basic input/output chip adjusts the voltage control data of the auxiliary input/output chip according to the change clock instruction; and step S7: the basic input/output chip executes a restart procedure to re-send a start signal to the auxiliary input/output chip (return to step S1). It should be noted that the first clock mode corresponding to the voltage control data before the adjustment is a non-overclocking mode, and the second clock mode corresponding to the voltage control data after the adjustment is an overclocking mode.

In step S1, after the computer device is powered on and before the basic input and output chip executes the boot process and the self-test before booting, the basic input and output chip can be triggered by the boot signal to send a start signal to the auxiliary input and output chip. In step S3, when the auxiliary input and output chip is triggered by the start signal of the basic input and output chip, the voltage of a pin of the auxiliary input and output chip can be set according to the pre-stored voltage control data, for example, to a high potential or a low potential, wherein the pin is connected to the memory, and the voltage of the pin is used to control a clock mode of the memory. That is, when the computer device is shut down, the auxiliary input-output chip may store voltage control data corresponding to the last set clock mode, and the clock mode of the memory may be controlled based on this data when the computer device is turned on next time. In step S5, when the basic input-output chip is controlled to generate a change clock instruction related to the memory, the voltage control data of the input-output chip may be adjusted according to the change clock instruction, and a restart procedure including system parameter reset is executed in step S7, and then step S1 is re-executed. That is, after the memory clock control method of this example returns to step S1 after step S7, the voltage control data in the auxiliary input-output chip has been changed. Therefore, the voltage of the pin of the auxiliary I/O chip connected to the memory has been changed in step S3, thereby controlling the memory to enter the overclocking mode.

Please refer to FIG. 3 in conjunction with FIG. 2. FIG. 3 is a flow chart of a memory clock control method according to another embodiment of the present invention. As shown in FIG. 2 and FIG. 3, the memory clock control method of this embodiment can be executed after step S3 in which the auxiliary input and output chip is triggered by the start signal to set a voltage of a pin of the auxiliary input and output chip according to a pre-stored voltage control data, step S41: receiving a designated clock associated with the memory with the basic input and output chip; step S42: comparing the designated clock with the basic input and output chip; step S43: comparing the designated clock with the basic input and output chip; step S44: comparing the designated clock with the basic input and output chip; step S45: comparing the designated clock with the basic input and output chip; step S46: comparing the designated clock with the basic input and output chip; step S47: comparing the designated clock with the basic input and output chip; step S48: comparing the designated clock with the basic input and output chip; step S49: comparing the designated clock with the basic input and output chip; step S50: comparing the designated clock with the basic input and output chip; step S51: comparing the designated clock with the basic input and output chip; step S51: comparing the designated clock with the basic input and output chip; step S52: comparing the designated clock with the basic input and output chip; step S53: comparing the designated clock with the basic input and output chip; step S54: comparing the designated clock with the basic input and output chip; step S55: The designated clock is the same as a preset clock in the memory, wherein the preset clock corresponds to the pre-stored voltage control data; if the designated clock is the same as the preset clock, then executing step S9: obtaining and executing an operating program with a processor; if the designated clock is different from the preset clock, then executing step S43: generating a clock change instruction according to the designated clock, and executing the above step S5.

In step S41, during the booting process of the computer device, the BIOS chip can be awakened and connected to a user interface (such as a setting interface of the BIOS), and the user interface can output a specified clock related to the memory to the BIOS chip. In step S42, the BIOS chip can compare whether the specified clock is equal to the default clock of the memory to determine whether to change the voltage control data of the auxiliary BIOS chip. When the specified clock is different from the default clock, in step S43, the BIOS chip can generate a change clock instruction according to the specified clock, that is, the change clock instruction includes a first data corresponding to the specified clock. In one embodiment, the designated clock of step S42 may refer to information corresponding to an instruction in the user interface to check the overclocking mode or an instruction not to check the overclocking mode. In other words, the determination in step S42 that the designated clock is different from the default clock may refer to the determination that there is an instruction in the user interface to check the overclocking mode. Further, in step S5, the basic input-output chip may adjust the voltage control data of the auxiliary input-output chip according to the first data corresponding to the designated clock in the clock change instruction. On the other hand, when the designated clock is the same as the default clock (for example, when it is determined that there is no instruction to check the overclocking mode in the user interface), the BIOS can control the processor to obtain and execute an operating program, that is, to execute a normal boot procedure, wherein the operating program refers to a program that runs the operating system (OS). It should be noted that the process of "the BIOS compares the designated clock and the default clock to be different from each other" in this case is also equivalent to the process of "the BIOS does not generate the change clock instruction associated with the memory under control". That is to say, in other implementations, step S9 can also be executed as: when the BIOS does not generate the change clock instruction associated with the memory under control, the processor is controlled to obtain and execute the operating program.

Through the above structure, the memory clock control method and control device disclosed in this case can store the corresponding voltage control data in the auxiliary input and output chip according to the memory overclocking mode last stored and set by the user through the basic input and output chip, and then decide whether to change the voltage of a specific pin of the auxiliary input and output chip based on whether the voltage control data in the auxiliary input and output chip changes, and the specific pin is connected to the memory, thereby adjusting the memory to operate in a clock frequency range that is not preset by the factory. The computer device using the memory clock control method and control device of the present case can automatically detect whether the memory is to enter the overclocking mode and make corresponding adjustments during the process from starting the power supply to the basic input and output chip boot program.

Although the present invention is disclosed as above with the aforementioned embodiments, it is not intended to limit the present invention. Any changes and modifications made without departing from the spirit and scope of the present invention are within the scope of patent protection of the present invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

100: Memory clock control device

1: Processor

2: Memory

3: Auxiliary input and output chip

4: Basic input and output chip

5: Platform path controller

S1~S9,S41~S43: Steps

FIG1 is a block diagram of a memory clock control device according to an embodiment of the present invention. FIG2 is a flow chart of a memory clock control method according to an embodiment of the present invention. FIG3 is a flow chart of a memory clock control method according to another embodiment of the present invention.

S1~S7: Steps

Claims (6)

A memory clock control method comprises: a basic input-output chip is triggered by a power-on signal to send a start signal to an auxiliary input-output chip; the auxiliary input-output chip is triggered by the start signal to set a voltage of a pin of the auxiliary input-output chip according to a pre-stored voltage control data, wherein the pin is connected to a memory and the voltage is used to control a clock mode of the memory; and when the basic input-output chip is controlled to generate a change clock instruction related to the memory, the basic input-output chip adjusts the voltage control data of the auxiliary input-output chip according to the change clock instruction, and executes a restart procedure to re-send the voltage control data to the auxiliary input-output chip. The start signal, wherein a first clock mode corresponding to the voltage control data before adjustment is a non-overclocking mode, and a second clock mode corresponding to the voltage control data after adjustment is an overclocking mode, and the memory clock control method further includes: receiving a designated clock associated with the memory with the basic input and output chip; comparing the designated clock with a preset clock of the memory, wherein the preset clock corresponds to the pre-stored voltage control data; when the designated clock is different from the preset clock, generating the clock change instruction according to the designated clock; and when the basic input and output chip is not controlled to generate the clock change instruction associated with the memory, controlling a processor to obtain and execute an operating program. The memory clock control method as described in claim 1, wherein the auxiliary input-output chip is used to set the voltage of the pin of the auxiliary input-output chip according to the pre-stored voltage control data, including: the auxiliary input-output chip is used to set the voltage of a universal input-output pin of the auxiliary input-output chip according to the pre-stored voltage control data. A memory clock control method as described in claim 1, wherein the memory is a fifth-generation double data rate synchronous dynamic random access memory, and the clock frequency of the overclocking mode is greater than 4400MHz. A memory clock control device comprises: a processor; a memory connected to the processor; an auxiliary input-output chip connected to the memory, which is used to be triggered by a start signal to set a voltage of a pin of the auxiliary input-output chip according to a pre-stored voltage control data, wherein the pin is connected to the memory and the voltage is used to control the memory. a clock mode; a basic input-output chip connected to the processor and the auxiliary input-output chip, and used to: be triggered by a power-on signal to send the start signal to the auxiliary input-output chip; and when a change clock instruction related to the memory is generated by the control, the voltage control data of the auxiliary input-output chip is adjusted according to the change clock instruction, and a restart procedure is executed to re-send the start signal to the auxiliary input-output chip, wherein, a first clock mode corresponding to the voltage control data before adjustment is a non-overclocking mode, and a second clock mode corresponding to the voltage control data after adjustment is an overclocking mode, wherein the basic input-output chip is further used to: receive a command related to the memory timing pulse; comparing the designated timing pulse with a preset timing pulse of the memory, wherein the preset timing pulse corresponds to the pre-stored voltage control data; when the designated timing pulse is different from the preset timing pulse, generating the change timing pulse instruction according to the designated timing pulse; and when the change timing pulse instruction associated with the memory is not received, controlling the processor to obtain and execute an operating program. A memory clock control device as described in claim 4, wherein the pin of the auxiliary input/output chip is a general-purpose input/output pin. A memory clock control device as described in claim 4, wherein the memory is a fifth-generation double data rate synchronous dynamic random access memory, and the clock frequency of the overclocking mode is greater than 4400 MHz.

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