TWI861925B - Phase-locked loop device and phase frequency detector - Google Patents

Abstract

A phase-locked loop device and a phase-frequency detector, the main technology of which is that a first pulse latch circuit receives an inverted reset signal and a reference frequency signal and generates a first storage signal accordingly, a second pulse latch circuit receives an inverted reset signal and a feedback frequency signal and generates a second storage signal accordingly, a first inverter inverts the first storage signal to generate an up signal, a second inverter inverts the second storage signal to generate a down signal, and a first retainer and a second retainer are used to respectively maintain the potentials of the up signal and the down signal. The reset circuit generates an inverted reset signal according to the up-count signal and the down-count signal. When the up-count signal and the down-count signal are both at the first logic level, the inverted reset signal is at the second logic level, so as to achieve the effects of high performance, minimum blind area, increased loop bandwidth, and low power consumption.

Description

Phase-locked loop device and phase frequency detector

The present invention relates to a phase-locked loop technology, and in particular to a high-performance minimum blind-zone pulse latching phase-locked loop device and a phase-frequency detector.

As 5G artificial intelligence Internet of Things develops towards more diversified innovative applications, the components required for 5G communication equipment must meet application requirements such as low power consumption, low latency, small size, low cost, high efficiency, and high performance, especially the phase-locked loop device, which is the core clock component of 5G communication equipment. The existing phase-locked loop device is mainly used in 5G communication equipment to generate one or more different high-frequency, accurate and stable clock signals. The circuit components mainly include phase/frequency detector (PFD), charge pump (CP), loop filter (LF), and voltage-controlled oscillator (VCO). Among them, as the phase frequency detector at the front end of the phase-locked loop device, its design not only affects the locking time of the phase-locked loop, but also affects the reference surge and phase noise of the phase-locked loop. It is also the circuit that has the greatest impact on the accuracy and stability of the phase-locked loop. In terms of design implementation, in addition to the reduction of process technology (relatively increased manufacturing cost), factors such as circuit architecture, component transmission delay, component and routing layout (Layout), and parasitic effects generated by the layout will all limit its working performance and maximum operating frequency. In addition, the traditional phase frequency detector has a pulse generator that also functions as a pulse latch circuit. The pulse generator and the pulse latch circuit are not designed independently. As a result, when the pulse generator is not needed at high frequency, the pulse generator cannot be removed, resulting in increased power consumption.

Therefore, an object of the present invention is to provide a phase-locked loop device and a phase-frequency detector that can reduce power consumption when operating at high frequencies to overcome the shortcomings of the prior art.

Therefore, the phase-locked loop device includes a frequency regulator, a frequency divider and a phase frequency detector.

The frequency adjuster receives an up-counting signal and a down-counting signal, and generates a clock frequency signal accordingly, wherein an operating frequency of the clock frequency signal is positively related to the pulse width of the up-counting signal, and the operating frequency is inversely related to the pulse width of the down-counting signal.

The frequency divider is electrically connected to the frequency adjuster to receive the clock frequency signal and generate a feedback frequency signal whose frequency is proportional to the clock frequency signal.

The phase frequency detector includes a first pulse latch circuit, a second pulse latch circuit, a first inverter, a second inverter, a first keeper, a second keeper and a reset circuit.

The first pulse latch circuit receives an inverted reset signal and a reference frequency signal and generates a first storage signal accordingly. When the inverted reset signal and the reference frequency signal are both at a first logic level (high), the first storage signal is at a second logic level (low) inverted to the first logic level.

The second pulse latch circuit receives an inverted reset signal and a feedback frequency signal and generates a second storage signal accordingly. When the inverted reset signal and the feedback frequency signal are both at a first logic level, the second storage signal is at a second logic level inverted to the first logic level.

The first inverter has a first input terminal electrically connected to the first pulse latch circuit to receive the first storage signal, and a first output terminal, and inverts the first storage signal to generate an up-counting signal, and outputs the up-counting signal from the first output terminal.

The second inverter has a second input terminal electrically connected to the second pulse latch circuit to receive the second storage signal, and a second output terminal, and inverts the second storage signal to generate a down signal, and outputs the down signal from the second output terminal.

The first keeper is electrically connected between the first output terminal and the first input terminal of the first inverter and is used for maintaining the potential of the up signal.

The second keeper is electrically connected between the second output terminal and the second input terminal of the second inverter and is used for maintaining the potential of the down-count signal.

The reset circuit is electrically connected to the first pulse latch circuit and the second pulse latch circuit, and is electrically connected to the first output end of the first inverter and the second output end of the second inverter to receive the up-counting signal and the down-counting signal respectively, and generates the inverted reset signal according to the up-counting signal and the down-counting signal. When the up-counting signal and the down-counting signal are both at the first logic level (high), the inverted reset signal is at the second logic level (low).

The utility model has the following advantages: when operating at a high frequency, the maximum operating frequency of the phase frequency detector is twice that of the conventional phase frequency detector with a reset loop, and the first pulse generator and the second pulse generator can be omitted, which is beneficial to reduce power consumption.

Before the present invention is described in detail, it should be noted that similar components are represented by the same reference numerals in the following description.

Referring to FIG. 1 , a first embodiment of the present invention is shown in which a phase-frequency detector with a high-performance minimum blind-zone pulse latching function is applied to a phase-locked loop device with a high pulse frequency, wherein the phase-locked loop device includes a frequency adjuster 1, a frequency divider (FD) 2 and a phase-frequency detector 3.

The frequency adjuster 1 receives an up-counting signal UP and a down-counting signal DN, and generates a clock frequency signal accordingly, wherein an operating frequency of the clock frequency signal is positively related to the pulse width of the up-counting signal, and the operating frequency is inversely related to the pulse width of the down-counting signal. The frequency adjuster 1 includes a charge pump 11, a loop filter 12, and a voltage-controlled oscillator 13. The charge pump 11 receives the up-counting signal UP and the down-counting signal DN, and generates a frequency adjustment signal. The loop filter 12 is electrically connected to the charge pump 11 to receive the frequency adjustment signal, and filters the frequency adjustment signal to generate a filter signal. The voltage controlled oscillator 13 is electrically connected to the loop filter 12 to receive the filter signal, and performs voltage oscillation according to the filter signal to generate the clock frequency signal.

The frequency divider 2 is electrically connected to the frequency adjuster 1 to receive the clock frequency signal and generate a feedback frequency signal (CKFEB) having a frequency proportional to the clock frequency signal.

Referring to FIG. 2 , when half the cycle time (Tck/2) of the reference frequency signal (CKREF) is less than the reset width time (Treset) of the inverted reset signal, the phase frequency detector 3 electrically connects the divider 2 and the frequency adjuster 1, and includes a first pulse latch circuit 31, a second pulse latch circuit 32, a first retainer 41, a second retainer 42, a first inverter 51, a second inverter 52, and a reset circuit 6.

The first pulse latch circuit 31 receives an inverted reset signal and a reference frequency signal and generates a first storage signal accordingly. When the inverted reset signal and the reference frequency signal are both at a first logic level (high), the first storage signal is at a second logic level (low) inverted to the first logic level.

The first pulse latch circuit 31 includes a first pull-down transistor MN1, a second pull-down transistor MN2, and a first pull-up transistor MP1. The first pull-down transistor MN1MP1 has a first end electrically connected to the first input end of the first inverter 51, a second end, and a control end receiving an inverted reset signal. The second pull-down transistor MN2 has a first end electrically connected to the second end of the first pull-down transistor MN1MP1, a second end grounded (GND), and a control end receiving a reference frequency signal. The first pull-up transistor MP1 has a first end electrically connected to the first end of the first pull-down transistor MN1, a second end receiving an operating voltage (VDD), and a control end receiving an inverted reset signal.

The second pulse latch circuit 32 receives the inverted reset signal and the feedback frequency signal, and generates a second storage signal accordingly. When the inverted reset signal and the feedback frequency signal are both at a first logic level, the second storage signal is a second logic level inverted to the first logic level. The second pulse latch circuit 32 includes a third pull-down transistor MN3, a fourth pull-down transistor MN4, and a second pull-up transistor MP2. The third pull-down transistor MN3 has a first end electrically connected to the second input end of the second inverter 52, a second end, and a control end receiving the inverted reset signal. The fourth pull-down transistor MN4 has a first end electrically connected to the second end of the third pull-down transistor MN3, a second end grounded (GND), and a control end receiving the feedback frequency signal. The second pull-up transistor MP2 has a first end electrically connected to the first end of the third pull-down transistor MN3, a second end receiving a working voltage (VDD), and a control end receiving the inverted reset signal. The first pull-up transistor MP1 and the second pull-up transistor MP2 are P-type metal oxide semi-conductor field effect transistors (hereinafter referred to as PMOS), the first end is a drain, the second end is a source, and the control end is a gate. The first pull-down transistor MN1, the second pull-down transistor MN2, the third pull-down transistor MN3 and the fourth pull-down transistor MN4 are N-type metal oxide semiconductor field effect transistors (hereinafter referred to as NMOS), with a first end being a drain, a second end being a source and a control end being a gate.

The first inverter 51 has a first input terminal electrically connected to the first pulse latch circuit 31 to receive the first storage signal, and a first output terminal, and inverts the first storage signal to generate an up signal, and outputs the up signal from the first output terminal.

The second inverter 52 has a second input terminal electrically connected to the second pulse latch circuit 32 to receive the second storage signal, and a second output terminal, and inverts the second storage signal to generate a down-signal, and outputs the down-signal from the second output terminal.

The first retainer 41 is electrically connected between the first output terminal and the first input terminal of the first inverter 51 to retain the potential of the up signal. The first retainer 41 includes a first retaining transistor K1 and a second retaining transistor K2.

The first holding transistor K1 has a first end electrically connected to the first input end of the first inverter 51, a second end receiving a working voltage (VDD), and a control end electrically connected to the first output end of the first inverter 51 to receive the up signal. The second holding transistor K2 has a first end electrically connected to the first end of the second pull-down transistor MN2, a second end grounded, and a control end electrically connected to the first output end of the first inverter 51 to receive the up signal.

The second retainer 42 is electrically connected between the second output terminal and the second input terminal of the second inverter 52 to maintain the potential of the count-down signal. The second retainer 42 includes a third retaining transistor K3 and a fourth retaining transistor K4. The third retaining transistor K3 has a first end electrically connected to the second input terminal of the second inverter 52, a second end receiving a working voltage (VDD), and a control end electrically connected to the second output terminal of the second inverter 52 to receive the count-down signal. The fourth retaining transistor K4 has a first end electrically connected to the first end of the fourth pull-down transistor MN4, a second end grounded, and a control end electrically connected to the second output terminal of the second inverter 52 to receive the count-down signal.

The reset circuit 6 is electrically connected to the first pulse latch circuit 31 and the second pulse latch circuit 32, and is electrically connected to the first output end of the first inverter 51 and the second output end of the second inverter 52 to receive the up-counting signal and the down-counting signal respectively, and generates the inverted reset signal according to the up-counting signal and the down-counting signal. When the up-counting signal and the down-counting signal are both at the first logic level (high), the inverted reset signal is at the second logic level (low). The reset circuit 6 includes a NAND gate having a first end electrically connected to the first output end of the first inverter 51 to receive the up signal, a second end electrically connected to the second output end of the second inverter 52 to receive the down signal, and an output end for outputting the inverted reset signal.

The switching operation of each transistor of the phase frequency detector 3 is described below. When the circuit power (VDD) is turned on, the potentials of all nodes in the circuit are zero, so the first pull-up transistor MP1 and the first holding transistor K1 are turned on, and the first pull-down transistor MN1, the second pull-down transistor MN2, and the second holding transistor K2 are not turned on. The first pull-up transistor MP1 transmits the high potential of VDD to the node q, and the potential of the first storage signal of the node q becomes high. The first storage signal passes through the first inverter 51 to output the up signal UP, and the signal potential of the up signal UP becomes low. The first holding transistor K1 remains turned on and the second holding transistor K2 remains not turned on. When the up signal and the down signal are both low, the NAND gate (NAND gate) The inverted reset signal output by the gate) will become high, controlling the first pull-up transistor MP1 to be non-conductive and the first pull-down transistor MN1 to be conductive, and then waiting for the reference frequency signal (CKREF) or the feedback frequency signal (CKFEB) to become high. If the reference frequency signal (CKREF) or the feedback frequency signal (CKFEB) is low, the second pull-down transistor MN2 is turned off, and the pull-down path composed of the first pull-down transistor MN1 and the second pull-down transistor MN2 is closed, and the signal level of the node q is maintained at the same potential. If the reference frequency signal (CKREF) or the feedback frequency signal (CKFEB) becomes high, the second pull-down transistor MN2 is turned on, and the first pull-down transistor MN1 is turned on. The pull-down path formed by stacking the first pull-down transistor MN2 is turned on, and the potential of the first storage signal of the node q is pulled down to a low potential (or logical 0). At this time, the first storage signal passes through the first inverter 51 to output the up signal UP, and the signal potential of the up signal UP becomes high. The first holding transistor K1 is not turned on and the second holding transistor K2 is turned on. The second holding transistor K2 keeps the node between the source of the first pull-down transistor MN1 and the drain of the second pull-down transistor MN2 at a low potential (or logical 0) to maintain the potential state of the up signal UP. When the up signal UP and the down signal DN both become high, the inverted reset signal output by the NAND gate will become low, thereby resetting the circuit. In other words, the node q The first storage signal becomes high, the up-count signal UP and the down-count signal DN both become low, and then the inverted reset signal output by the NAND gate returns to high, and continues to wait for the next reference frequency signal (CKREF) or feedback frequency signal (CKFEB) to arrive at a high level.

The two input clocks, the reference frequency signal (hereinafter referred to as CKREF) and the feedback frequency signal (hereinafter referred to as CKFEB) are continuous time period signals. The phase frequency detector 3 is used as a frequency detector during the transient response frequency acquisition period. When the two input clocks CKREF and CKFEB When the frequencies are the same, it is used as a phase detector until the frequency and phase are equal. During the frequency acquisition period, if the reference frequency signal CKREF and the feedback frequency signal CKFEB have different clock frequencies, a phase difference equal to the clock frequency difference is detected in each clock cycle. Therefore, the relationship between the clock frequency difference and the phase difference can be expressed as the following formula: , where the parameter is defined as the phase difference per cycle, is defined as the frequency difference between the two input pulses. is defined as the fastest frequency value of the two clock frequencies of the reference frequency signal CKREF and the feedback frequency signal CKFEB or can be expressed as max(f _CKREF , f _CKFEB ). During the frequency acquisition period, the phase difference per cycle is Stepping along the phase frequency detector input/output transfer curve (I/O transfer curve) from 0 to 2π, the phase frequency detector input/output characteristic curve can be expressed by the average of the time difference between the differential output up signal UP and the down signal DN (input phase difference 0 to 2π), as shown in the following formula:

in, is the input pulse frequency of the reference frequency signal CKREF, is the ideal phase frequency detector gain ( ), is the high frequency attenuation factor. The high frequency attenuation factor changes with the input pulse frequency and is inversely proportional to the input pulse frequency, that is, the larger the input pulse frequency, the smaller the high frequency attenuation factor. When , it is the maximum operating frequency of the phase frequency detector. The high frequency attenuation factor of the phase frequency detector is as follows:

when Hour,

Hour,

Among them, the parameters To reset the transmission delay time of the loop, parameter is the input pulse width (CP _REF or CP _FEB ), parameter The blind area size varies with the input pulse frequency and is proportional to the input pulse frequency. That is, the larger the input pulse frequency, the larger the blind area. is the product of the input pulse width and the input pulse frequency. From the above formula, we know that the high-frequency attenuation factor is The size will determine the performance of the phase frequency detector 3.

The definition of the blind area of the phase frequency detector 3 is as follows: when both the up-count signal UP and the down-count signal DN output logic 1 (high level), the inverted reset signal changes to logic 0 (low level). At this time, the phase frequency detector 3 enters the reset state so that the up-count signal UP and the down-count signal DN are reset to logic 0. Regardless of whether the reference frequency signal CKREF or the feedback frequency signal CKFEB changes from logic 0 to logic 1, it cannot trigger the up-count signal UP and the down-count signal DN output by the phase frequency detector 3 to change until the reset state ends, that is, the inverted reset signal returns to logic 1. Therefore, when the phase frequency detector 3 enters the reset state, it is like a blind person who ignores any input transition changes, so the reset loop transmission delay time This will affect the input clock frequency speed and blind area size of the phase frequency detector 3. Therefore, the reset width time (Treset) of the phase frequency detector 3 is as follows: .

in It is the delay time from the up signal UP (or down signal DN) to the inverted reset signal. is the pulse width of the inverting reset signal, is the delay time from the inverted reset signal to the up-count signal UP (or down-count signal DN). The maximum operating frequency of the phase frequency detector 3 of the present invention is as follows:

The formula for the blind zone size is as follows:

Next, we discuss the input clock frequency of the reference frequency signal CKREF. and input pulse width If the half cycle of the input pulse frequency is , and assume When the differential output Reverse the advance to a negative value, i.e. the blind zone Increase, and then assume , the best Value, let's assume , then the differential output There will be oscillations, so Design the following formula:

If the half-cycle of the input clock frequency is , and assume When the differential output Reverse the advance to a negative value, then Increase, and then assume , the best Value, let's assume , then the differential output Reverse the advance to a negative value, Increase, therefore, Design the following formula:

From the above formula, we know that when Hour, , the maximum operating frequency can be rewritten as follows: , which is twice that of the traditional phase frequency detector with reset loop. The maximum operating frequency of the traditional phase frequency detector is and ). Refer to Figure 3 for the input clock frequency, , , ,as well as When the input pulse frequency When, blind spot and gain The magnitude of the attenuation decreases with increasing frequency. When, blind spot and gain The size increases with the frequency and the attenuation slope is larger, so we found that if we reset the loop transmission delay time can be reduced, allowing the input clock frequency to be pushed to a higher operating frequency while maintaining a smaller and larger .

Refer to Figures 4 to 6, which are timing diagrams of the phase frequency detector of the present invention operating in a high frequency band (2.5GHz), wherein Figure 4 shows the frequency lock state when the feedback frequency signal CKFEB and the reference frequency signal CKREF are in phase (phase difference = 0π). Figure 5 shows the state when the feedback frequency signal CKFEB leads the reference frequency signal CKREF in phase (phase difference = 0.5π), and the pulse width of the down-counting signal is greater than the pulse width of the up-counting signal to reduce the frequency of the feedback frequency signal CKFEB. Figure 6 shows that when the phase of the feedback frequency signal CKFEB lags behind the reference frequency signal CKREF (phase difference = 1.0π), the pulse width of the upper signal is greater than the pulse width of the lower signal to increase the frequency of the feedback frequency signal CKFEB.

Referring to FIG. 7 , a second embodiment of the phase frequency detector of the present invention is applied to a phase-locked loop device with a high clock frequency. When half of the cycle time (Tck/2) of the reference frequency signal is greater than or equal to the reset width time (Treset) of the inverted reset signal, the difference from the first embodiment is that the phase frequency detector 3 further includes a first pulse generator 71 and a second pulse generator 72.

The first pulse generator 71 is used to receive a reference frequency signal and shorten the pulse width of the reference frequency signal to generate a shortened pulse width to transmit to the second pull-down transistor MN2 of the first pulse latch circuit 31. Referring to FIG8 , the first pulse generator 71 includes a buffer 711, a pass transistor 712, and a fifth pull-down transistor MN5.

The buffer 711 has an input terminal for receiving the original reference frequency signal and an output terminal. The buffer 711 generates a delayed signal after delaying the original reference frequency signal and outputs it from the output terminal. The buffer 711 is a non-inverting delay element. The transmission transistor 712 has a first terminal electrically connected to the second pull-down transistor MN2, a second terminal outputting the reference frequency signal, and a control terminal electrically connected to the output terminal of the buffer 711. The transmission transistor 712 is a PMOS. The fifth pull-down transistor MN5 has a first end electrically connected to the first end of the transmission transistor 712, a second end grounded, and a control end electrically connected to the output end of the buffer 711. The fifth pull-down transistor MN5 is an NMOS. Referring to FIG. 9 , it is an operation timing diagram of the first pulse generator 71, wherein the parameter CKREF is a reference frequency signal input to the transmission transistor 712, the parameter CKΔ is a delay signal output by the buffer 711, and is used to control the fifth pull-down transistor MN5 and the transmission transistor 712, the parameter CP is a reference frequency signal after the pulse is shortened output by the transmission transistor 712, and the parameter t _PW is the pulse width time after the pulse is shortened. When the level of the delay signal CKΔ is low, the transmission transistor 712 is turned on and the fifth pull-down transistor MN5 is not turned on. The transmission transistor 712 transmits part of the pulse width of the original reference frequency signal until the level of the delay signal CKΔ is high. The transmission transistor 712 turns non-conductive and the fifth pull-down transistor MN5 turns conductive. The fifth pull-down transistor MN5 pulls down the potential of the second end of the transmission transistor 712 to a low level or zero, generating a reference frequency signal with a shortened pulse width.

The second pulse generator 72 is electrically connected to the divider 2 to receive the feedback frequency signal, and shortens the pulse width of the feedback frequency signal to generate a shortened pulse width to be transmitted to the fourth pull-down transistor MN4 of the second pulse latch circuit 32, wherein the reference frequency signal and the shortened pulse width of the feedback frequency signal are close to the reset width time (Treset) of the inverted reset signal. The circuit elements included in the second pulse generator 72 are the same as those of the first pulse generator 71, and thus will not be repeated.

Refer to Figures 10~12, which are timing diagrams of the phase frequency detector 3 of the second embodiment operating in the low frequency band (1GHz), wherein Figure 10 is a frequency locked state when the feedback frequency signal CKFEB is in phase with the reference frequency signal CKREF (phase difference = 0π), wherein the shortened reference pulse is generated by shortening the reference frequency signal CKREF, and the shortened feedback pulse is generated by shortening the feedback frequency signal CKFEB. Figure 11 shows that when the phase of the feedback frequency signal CKFEB leads the reference frequency signal CKREF (phase difference = 0.5π), the pulse width of the down-counting signal is greater than the pulse width of the up-counting signal to reduce the frequency of the feedback frequency signal CKFEB. Figure 12 shows that when the phase of the feedback frequency signal CKFEB lags behind the reference frequency signal CKREF (phase difference = 1.0π), the pulse width of the up-counting signal is greater than the pulse width of the down-counting signal to increase the frequency of the feedback frequency signal CKFEB.

In summary, the above embodiment has the following advantages: 1. The first pulse latch circuit 31 only uses the first pull-down transistor MN1 and the second pull-down transistor MN2, a total of two transistors, as the q-point level pull-down path, which is beneficial to reduce the design area of the first pull-up transistor MP1 (based on the CMOS circuit transistor width design principle). 2. The circuit connection of the first retainer 41 and the first inverter 51 replaces the traditional full latch circuit using two inverters. 3. The path of the inverted reset signal only needs to pass through the first pull-down transistor MN1 and the first pull-up transistor MP1 of the first pulse latch circuit 31, the first inverter 51, and the reset circuit 6. 4. According to 1 to 3, the transmission delay time of the inverted reset signal is effectively reduced, the blind area is reduced, the input pulse frequency speed is increased, the occupied area is reduced, and the chip manufacturing cost is saved. 5. Especially when operating at high frequency, the maximum operating frequency of the phase frequency detector 3 is twice that of the traditional phase frequency detector with reset loop, and the first pulse generator 71 and the second pulse generator 72 can be omitted, which is beneficial to reduce power consumption, reduce the occupied area, and save chip manufacturing cost.

However, the above is only an embodiment of the present invention and should not be used to limit the scope of implementation of the present invention. All simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the content of the patent specification are still within the scope of the present patent.

1: Frequency regulator 11: Charge pump 12: Loop filter 13: Voltage controlled oscillator 2: Frequency divider 3: Phase frequency detector 31: First pulse latch circuit MN1: First pull-down transistor MN2: Second pull-down transistor MP1: First pull-up transistor 32: Second pulse latch circuit MN3: Third pull-down transistor MN4: Fourth pull-down transistor MP2: Second pull-up transistor 41: First retainer K1: First retainer transistor K2: Second retainer transistor 42: Second retainer K3: Third retainer transistor K4: Fourth retainer transistor 51: First inverter 52: Second inverter 6: Reset circuit UP: Up signal DN: Down signal VDD: Operating voltage q: Node 71: First pulse generator 711: Buffer 712: Transmission transistor MN5: Fifth pull-down transistor 72: Second pulse generator

Other features and effects of the present invention will be clearly presented in the implementation method with reference to the drawings, in which: Figure 1 is a system diagram of a first embodiment of the present invention, in which the phase frequency detector with high-performance minimum blind zone pulse latching function is applied to a high-frequency phase-locked loop device; Figure 2 is a circuit diagram of the phase frequency detector of the first embodiment; Figure 3 is a schematic diagram of the relationship between the input pulse frequency and the blind zone; Figure 4 is a timing diagram of the phase frequency detector of the present invention operating in a high frequency band (2.5GHz), illustrating the frequency locking state; Figure 5 is a timing diagram of the phase frequency detector of the present invention operating in a high frequency band (2.5GHz), illustrating the phase leading state of the feedback frequency signal; Figure 6 is a timing diagram of the phase frequency detector of the present invention operating in a high frequency band (2.5GHz), illustrating the phase lagging state of the feedback frequency signal; Figure 7 is a system diagram of a second embodiment of the phase frequency detector of the present invention applied to a phase-locked loop device with a high pulse frequency; Figure 8 is a circuit diagram of the first pulse generator of the second embodiment; Figure 9 is an operation timing diagram of the first pulse generator; FIG. 10 is a timing diagram of the phase frequency detector of the second embodiment operating in a low frequency band (1 GHz), illustrating the frequency lock state; FIG. 11 is a timing diagram of the phase frequency detector of the second embodiment operating in a low frequency band (1 GHz), illustrating the feedback frequency signal phase advance state; and FIG. 12 is a timing diagram of the phase frequency detector of the second embodiment operating in a low frequency band (1 GHz), illustrating the feedback frequency signal phase lag state.

3: Phase frequency detector

31: First pulse latch circuit

MN1: First pull-down transistor

MN2: Second pull-down transistor

MP1: First pull-up transistor

32: Second pulse latch circuit

MN3: The third pull-down transistor

MN4: The fourth pull-down transistor

MP2: Second pull-up transistor

41: First retainer

K1: First holding transistor

K2: Second holding transistor

42: Second retainer

K3: The third holding transistor

K4: The fourth holding transistor

51: First inverter

52: Second inverter

6: Reset the circuit

UP: Upward signal

DN: Down number signal

VDD: operating voltage

q:node

Claims (8)

A phase frequency detector includes: a first pulse latch circuit, receiving an inverted reset signal and a reference frequency signal and generating a first storage signal accordingly; when the inverted reset signal and the reference frequency signal are both at a first logic level, the first storage signal is a second logic level inverted to the first logic level; a second pulse latch circuit, receiving the inverted reset signal and the reference frequency signal; A first inverter is provided, wherein the first input terminal is electrically connected to the first pulse latch circuit to receive the first storage signal, and a second storage signal is generated accordingly. When the inverted reset signal and the feedback frequency signal are both at a first logic level, the second storage signal is at a second logic level inverted to the first logic level. an output terminal, and inverts the first storage signal to generate an up signal, and outputs the up signal from the first output terminal; a second inverter, having a second input terminal electrically connected to the second pulse latch circuit to receive the second storage signal, and a second output terminal, and inverts the second storage signal to generate a down signal, and outputs the down signal from the second output terminal; a first retainer, electrically connected between the first output terminal and the first input terminal of the first inverter, for maintaining the potential of the up signal; a second retainer, electrically connected between the second output terminal and the second input terminal of the second inverter, for maintaining the potential of the down signal; and a reset circuit, electrically connected between the first pulse latch circuit and the second pulse latch circuit The latch circuit is electrically connected to the first output terminal of the first inverter and the second output terminal of the second inverter to receive the up-counting signal and the down-counting signal respectively, and generates the inverted reset signal according to the up-counting signal and the down-counting signal. When the up-counting signal and the down-counting signal are both at the first logic level, the inverted reset signal is at the second logic level. The first pulse latch circuit includes a first pull-down transistor, a second pull-down transistor, and a first pull-up transistor. The first pull-down transistor has a first end electrically connected to the first input terminal of the first inverter, a second end, and a control end for receiving the inverted reset signal. The second pull-down transistor has a first end electrically connected to the second end of the first pull-down transistor and a second end connected to ground. and a control end receiving the reference frequency signal, the first pull-up transistor has a first end electrically connected to the first end of the first pull-down transistor, a second end receiving a working voltage, and a control end receiving the inverted reset signal, the first retainer includes a first retaining transistor and a second retaining transistor, the first retaining transistor has a first end electrically connected to the first input end of the first inverter, a second end receiving a working voltage, and a control end electrically connected to the first output end of the first inverter to receive the count-up signal, the second retaining transistor has a first end electrically connected to the first end of the second pull-down transistor, a second end connected to ground, and a control end electrically connected to the first output end of the first inverter to receive the count-up signal. The phase frequency detector as described in claim 1, wherein the second pulse latch circuit includes a third pull-down transistor, a fourth pull-down transistor, and a second pull-up transistor, the third pull-down transistor having a first end electrically connected to the second input end of the second inverter, a second end, and a control end receiving the inverted reset signal, the fourth pull-down transistor having a first end electrically connected to the second end of the third pull-down transistor, a second end connected to ground, and a control end receiving the feedback frequency signal, and the second pull-up transistor having a first end electrically connected to the first end of the third pull-down transistor, a second end receiving a working voltage, and a control end receiving the inverted reset signal. The phase frequency detector as described in claim 1, wherein the second retainer includes a third retaining transistor and a fourth retaining transistor, the third retaining transistor having a first end electrically connected to the second input end of the second inverter, a second end receiving a working voltage, and a control end electrically connected to the second output end of the second inverter to receive the down signal, and the fourth retaining transistor having a first end electrically connected to the first end of the fourth pull-down transistor, a second end connected to ground, and a control end electrically connected to the second output end of the second inverter to receive the down signal. The phase frequency detector as described in claim 1, wherein the reset circuit includes an NAND gate having a first end electrically connected to the first output end of the first inverter to receive the up signal, a second end electrically connected to the second output end of the second inverter to receive the down signal, and an output end for outputting the inverted reset signal. The phase frequency detector as described in claim 1 further comprises a first pulse generator and a second pulse generator when half of the cycle time of the reference frequency signal is greater than or equal to the reset width of the inverted reset signal. The first pulse generator is used to receive an original reference frequency signal and shorten the pulse width of the original reference frequency signal to generate a shortened pulse. The second pulse generator is used to receive an original feedback frequency signal and shorten the pulse width of the original feedback frequency signal to generate a shortened pulse width as the feedback frequency signal, wherein the reference frequency signal and the shortened pulse width of the feedback frequency signal are close to the reset width of the inverted reset signal. The phase frequency detector as described in claim 5, wherein the first pulse generator includes a buffer, a transmission transistor, and a fifth pull-down transistor. The buffer has an input terminal for receiving the original reference frequency signal and an output terminal. The buffer generates a delayed signal after delaying the original reference frequency signal and outputs it from the output terminal. The transmission transistor has a first terminal electrically connected to the second pull-down transistor, a second terminal electrically connected to the input terminal of the buffer, and a control terminal electrically connected to the output terminal of the buffer. The fifth pull-down transistor has a first terminal electrically connected to the first terminal of the transmission transistor, a second terminal connected to ground, and a control terminal electrically connected to the output terminal of the buffer. A phase frequency detector as described in claim 1, wherein half of the cycle time of the reference frequency signal is less than the reset width of the inverted reset signal. A phase-locked loop device includes: a frequency adjuster, receiving an up-counting signal and a down-counting signal, and generating a clock frequency signal accordingly, wherein an operating frequency of the clock frequency signal is positively correlated to the pulse width of the up-counting signal, and the operating frequency is inversely correlated to the pulse width of the down-counting signal; a frequency divider, electrically connected to the frequency adjuster to receive the clock frequency signal, and generating a feedback frequency whose frequency is proportional to the clock frequency signal. A phase frequency detector includes a first pulse latch circuit, which receives an inverted reset signal and a reference frequency signal and generates a first storage signal accordingly. When the inverted reset signal and the reference frequency signal are both at a first logic level, the first storage signal is a second logic level inverted to the first logic level. A second pulse latch circuit receives the inverted reset signal and the feedback frequency signal and generates a first storage signal accordingly. To generate a second storage signal, when the inverted reset signal and the feedback frequency signal are both at a first logic level, the second storage signal is a second logic level inverted to the first logic level; a first inverter, having a first input terminal electrically connected to the first pulse latch circuit to receive the first storage signal, and a first output terminal, and inverting the first storage signal to generate an up signal, from the first an output terminal outputting the up-counting signal; a second inverter having a second input terminal electrically connected to the second pulse latch circuit to receive the second storage signal, and a second output terminal, and inverting the second storage signal to generate a down-counting signal, and outputting the down-counting signal from the second output terminal; a first retainer electrically connected between the first output terminal and the first input terminal of the first inverter, and used to maintain the potential of the up-counting signal a second retainer electrically connected between the second output terminal and the second input terminal of the second inverter to maintain the potential of the down-counting signal; a reset circuit electrically connected to the first pulse latch circuit and the second pulse latch circuit, and electrically connected to the first output terminal of the first inverter and the second output terminal of the second inverter to receive the up-counting signal and the down-counting signal respectively, and generate the reset circuit according to the up-counting signal and the down-counting signal The inverted reset signal is a first logic level when the up-count signal and the down-count signal are both at the first logic level. The first pulse latch circuit includes a first pull-down transistor, a second pull-down transistor, and a first pull-up transistor. The first pull-down transistor has a first end electrically connected to the first input end of the first inverter, a second end, and a control end for receiving the inverted reset signal. The second pull-down transistor The transistor has a first end electrically connected to the second end of the first pull-down transistor, a second end grounded, and a control end receiving the reference frequency signal. The first pull-up transistor has a first end electrically connected to the first end of the first pull-down transistor, a second end receiving a working voltage, and a control end receiving the inverted reset signal. The first retainer includes a first retaining transistor and a second retaining transistor. The first retaining transistor has a first end electrically connected to the first input end of the first inverter, a second end receiving a working voltage, and a control end electrically connected to the first output end of the first inverter to receive the count-up signal. The second retaining transistor has a first end electrically connected to the first end of the second pull-down transistor, a second end grounded, and a control end electrically connected to the first output end of the first inverter to receive the count-up signal.

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