TWI861963B - Circuit board and method of manufacturing the same - Google Patents

Abstract

A circuit board includes a wiring structure and a capacitive component. The wiring structure includes a plurality of wiring layers and a plurality of insulation layers. The wiring layers and the insulation layers are stacked up alternately in a first direction. The capacitive component is disposed in the wiring structure and passes through the wiring layers and the insulation layers. The capacitive component includes a first electrode, a second electrode and a dielectric material. The first electrode extends in the first direction and through the wiring layers and the insulation layers. The first electrode is connected to at least one of the wiring layers. The second electrodes are arranged in the first direction and separated from each other, where each of the second electrodes is separated from the first electrode. Each of the second electrodes overlaps the first electrode in a second direction, where the second direction is perpendicular to the first direction. Each of the second electrodes is connected to at least one of the wiring layers. The dielectric material is disposed between the first electrode and the second electrode.

Description

Circuit board and manufacturing method thereof

The present invention relates to a circuit board and a manufacturing method thereof, and in particular to a circuit board including a capacitor element and a manufacturing method thereof.

At present, embedded capacitor components in circuit boards are usually composed of two metal layers and a dielectric layer sandwiched between the two metal layers, wherein the two metal layers are electrodes and are arranged in parallel with the circuit layer of the circuit board, and the distance between the two metal layers is equal to the distance between the two adjacent circuit layers. Therefore, the distance between the two metal layers is difficult to change. The capacitance value of the embedded capacitor component is proportional to the overlapping area between the two metal layers (i.e., electrodes), and the metal layer and the circuit layer are arranged in parallel, so that the circuit board needs to have sufficient size, i.e., a certain length and width, to accommodate the embedded capacitor component.

At least one embodiment of the present invention provides a circuit board, which includes a capacitor element and a plurality of circuit layers, wherein the electrodes of the capacitor element extend along the stacking direction of the circuit layers.

Another embodiment of the present invention provides a method for manufacturing the above-mentioned circuit board.

The circuit board provided by at least one embodiment of the present invention includes a circuit structure and a capacitor element. The circuit structure includes a plurality of circuit layers and a plurality of insulating layers, wherein the circuit layers and the insulating layers are stacked along a first direction. The capacitor element is arranged in the circuit structure and passes through the circuit layers and the insulating layers. The capacitor element includes a first electrode, a second electrode and a dielectric material. The first electrode extends along the first direction and passes through the circuit layers and the insulating layers, wherein the first electrode is connected to at least one of the circuit layers. The second electrodes are arranged along the first direction and separated from each other, wherein each of the second electrodes is separated from the first electrode. Each of the second electrodes overlaps with the first electrode along a second direction, wherein the second direction is perpendicular to the first direction. Each of the second electrodes is connected to at least one of the circuit layers. A dielectric material is disposed between the first electrode and the second electrode.

In at least one embodiment of the present invention, the dielectric material includes a plurality of filling materials. The filling materials are arranged along a first direction, wherein each of the filling materials is sandwiched between the first electrode and one of the second electrodes. The filling materials overlap with the second electrodes in a second direction, wherein at least two of the filling materials have different dielectric constants.

In at least one embodiment of the present invention, the distances between the second electrodes and the first electrode in the second direction are equal to each other.

In at least one embodiment of the present invention, the dielectric material has at least one through hole, and the through hole extends along the first direction.

In at least one embodiment of the present invention, the dielectric material has at least one blind hole extending along a first direction, wherein a depth of the blind hole is less than a thickness of the circuit structure.

At least one embodiment of the present invention also provides a method for manufacturing a circuit board, which includes the following steps. A circuit substrate is provided, which includes two core circuit layers and a core insulation layer disposed between the two core circuit layers. Then, two initial trenches parallel to each other are formed on the core insulation layer, wherein the two initial trenches are respectively adjacent to the sides of the core circuit layer. Then, a first initial electrode and a second initial electrode are respectively formed in the two initial trenches. Then, a plurality of build-up circuit layers and a plurality of build-up insulation layers are formed on opposite sides of the core insulation layer, wherein the build-up insulation layer covers the first initial electrode and the second initial electrode. Afterwards, a portion of the build-up insulating layer is removed to form two first trenches and two second trenches on these build-up insulating layers, wherein the two first trenches are respectively located on opposite sides of the first initial electrode and expose the first initial electrode, and the two second trenches are respectively located on opposite sides of the second initial electrode. The depth of the second trench is less than the depth of the first trench. Afterwards, metal material is deposited in the first trench and the second trench to form a first electrode in the first trench, and a plurality of second electrodes are formed in the plurality of second trenches, wherein each of these second electrodes is connected to at least one of these build-up circuit layers.

In at least one embodiment of the present invention, at least one through hole is formed on a portion of the build-up insulating layer between the first electrode and the second electrode, wherein the through hole extends between the build-up insulating layer and the initial insulating layer.

In at least one embodiment of the present invention, at least one blind hole is formed on a portion of the build-up insulating layer between the first electrode and the second electrode, wherein the blind hole at least extends to the build-up insulating layer.

In at least one embodiment of the present invention, a portion of the build-up insulating layer and a portion of the core insulating layer between the first electrode and the second electrode are removed to form a groove, wherein the groove exposes the first electrode, the second electrode and the second initial electrode. Thereafter, a dielectric material is filled in the groove.

In at least one embodiment of the present invention, the step of filling the trench with dielectric material includes sequentially filling a plurality of filling materials in the trench, wherein one of the filling materials is sandwiched between the first electrode and the second initial electrode, and each of the other filling materials is sandwiched between the first electrode and one of the second electrodes.

In at least one embodiment of the present invention, the sidewall of each of the initial trenches is aligned with the side edge of at least one of the core circuit layers.

Based on the above, the electrodes of the above capacitor element (i.e., the first and second electrodes) extend along the stacking direction of the circuit layer (i.e., the first direction). Therefore, compared with the conventional embedded capacitor element, the capacitor element of the present invention will not occupy too much size or area of the circuit board, so as to meet the development trend of current electronic devices (such as mobile devices) towards miniaturization.

In the following text, in order to clearly present the technical features of the present invention, the dimensions (e.g., length, width, thickness, and depth) of the elements (e.g., layers, films, substrates, and regions, etc.) in the drawings will be enlarged in unequal proportions, and the number of some elements will be reduced. Therefore, the description and explanation of the embodiments below are not limited to the number of elements in the drawings and the dimensions and shapes presented by the elements, but should cover the dimensions, shapes, and deviations therefrom caused by actual processes and/or tolerances. For example, the flat surface shown in the drawings may have rough and/or nonlinear features, and the sharp corners shown in the drawings may be rounded. Therefore, the elements presented in the drawings of the present invention are mainly for illustration, and are not intended to accurately depict the actual shapes of the elements, nor are they intended to limit the scope of the patent application of the present invention.

Secondly, the words "approximately", "approximately" or "substantially" used in the present case not only cover the numerical values and numerical ranges clearly recorded, but also cover the permissible deviation range that can be understood by a person of ordinary skill in the art to which the invention belongs, wherein the deviation range can be determined by the error generated during measurement, and the error is caused by, for example, the limitation of the measurement system or the process conditions. In addition, "approximately" can mean within one or more standard deviations of the above numerical values, such as ±30%, ±20%, ±10% or ±5%. The words "approximately", "approximately" or "substantially" used in this text may be used to select acceptable deviation ranges or standard deviations according to the optical, etching, mechanical or other properties, and do not apply a single standard deviation to all the above optical, etching, mechanical and other properties.

FIG. 1A is a schematic top view of a circuit board of at least one embodiment of the present invention, and FIG. 1B is a schematic cross-sectional view taken along line 1B-1B in FIG. 1A. Referring to FIG. 1A and FIG. 1B, the circuit board 100 includes a circuit structure 110, wherein the circuit structure 110 includes a plurality of circuit layers 111a and 111b and a plurality of insulating layers 112a and 112b. These circuit layers 111a and 111b and these insulating layers 112a and 112b are stacked along a first direction D1, that is, the first direction D1 is the stacking direction of the circuit layers 111a, 111b and the insulating layers 112a, 112b. In addition, in FIG. 1B, the first direction D1 is a vertical direction.

The circuit layers 111a and 111b and the insulation layers 112a and 112b may be stacked alternately so that each of the insulation layers 112a and 112b is located between two adjacent circuit layers 111a and 111b. The circuit structure 110 may be formed by building up the opposite sides of a core substrate, wherein the core circuit layer and the core insulation layer of the core substrate are the circuit layer 111a and the insulation layer 112a, respectively.

In addition, the circuit structure 110 may further include at least one conductive connection portion 113, wherein the conductive connection portion 113 connects at least two of the circuit layers 111a and 111b. Taking FIG. 1B as an example, the circuit board 100 includes two conductive connection portions 113, and each conductive connection portion 113 connects adjacent circuit layers 111a and 111b to allow the circuit layers 111a and 111b to be electrically conductive to each other. In addition, the conductive connection portion 113 may be a conductive blind hole, a conductive through hole, or a conductive buried hole, wherein FIG. 1B uses a conductive blind hole as an example, and does not limit the conductive connection portion 113 to only be a conductive blind hole.

The circuit board 100 further includes at least one capacitor 120, wherein the capacitor 120 is disposed in the circuit structure 110 and passes through the circuit layers 111a and 111b and the insulating layers 112a and 112b. The capacitor 120 includes a first electrode 121 and at least two second electrodes 122, wherein the first electrode 121 extends along the first direction D1 and passes through the circuit layers 111a and 111b and the insulating layers 112a and 112b, and the second electrodes 122 are separated from each other and arranged along the first direction D1.

1B , each second electrode 122 also extends along the first direction D1. Therefore, the first electrode 121 and the second electrode 122 of the capacitor 120 extend along the stacking direction of the circuit layers 111a and 111b, and the first electrode 121 and the second electrodes 122 are not arranged parallel to the circuit layers 111a and 111b.

The first electrode 121 is connected to at least one of the wiring layers 111a and 111b, and each of the second electrodes 122 is connected to at least one of the wiring layers 111a and 111b. Taking FIG. 1B as an example, the capacitor element 120 includes a first electrode 121 and three second electrodes 122, wherein the first electrode 121 passes through the wiring layers 111a and 111b and connects all the wiring layers 111a and 111b, and each of the second electrodes 122 is connected to two of the wiring layers 111a and 111b.

It should be noted that in other embodiments, the capacitor element 120 may include two or more than three second electrodes 122, wherein the first electrode 121 may be connected to one, two or more than three of the wiring layers 111a and 111b, and each second electrode 122 may be connected to one or more than three of the wiring layers 111a and 111b. Therefore, the capacitor element 120 shown in FIG. 1B is only provided for example, and does not limit the number of second electrodes 122 included in the capacitor element 120 and the number of wiring layers 111a and 111b connected to each of the first electrode 121 and the second electrode 122.

Each second electrode 122 is separated from the first electrode 121, and each second electrode 122 overlaps with the first electrode 121 along the second direction D2, wherein the second direction D2 is perpendicular to the first direction D1. Taking FIG. 1B as an example, the second direction D2 is a horizontal direction. In addition, from FIG. 1B, the first electrode 121 and the second electrode 122 do not overlap or stack in the first direction D1. The first electrode 121 and the second electrode 122 do not overlap with any circuit layers 111a and 111b in the first direction D1, as shown in FIG. 1B.

The distances W12 between the second electrodes 122 and the first electrode 121 in the second direction D2 are equal to each other. In other words, the second electrodes 122 are coplanar with each other, that is, the sides of the second electrodes 122 are aligned with each other and are located in the same plane, and each second electrode 122 is parallel to the first electrode 121. It should be noted that the second electrodes 122 are substantially coplanar with each other, and each second electrode 122 is substantially parallel to the first electrode 121. In detail, within the allowable error range, the second electrodes 122 may not be coplanar, and each second electrode 122 may not be parallel to the first electrode 121.

The capacitor element 120 further includes a dielectric material 123, wherein the dielectric material 123 is disposed between the first electrode 121 and the second electrode 122. The dielectric material 123 may include a plurality of filling materials F1, F2, and F3. The filling materials F1, F2, and F3 are arranged along a first direction D1, and each of the filling materials F1, F2, and F3 is sandwiched between the first electrode 121 and one of the second electrodes 122, wherein the filling materials F1, F2, and F3 overlap with the second electrodes 122 in the second direction D2, as shown in FIG. 1B .

In the present embodiment, at least two of the filling materials F1, F2 and F3 may be different from each other, so that the dielectric constants of at least two of the filling materials F1, F2 and F3 are different from each other. For example, the filling material F1 may be polyimide (PI), the filling material F2 may be epoxy, such as FR4 or barium titanium filled epoxy, and the filling material F3 may be ceramic, so that the dielectric material 123 may have a plurality of different dielectric constants, so that the capacitor element 120 has a plurality of capacitance values.

It can be seen that in circuit design, the capacitor element 120 is more flexible so that the capacitor element 120 can be applied to more types of circuits. Taking the capacitor element 120 in Figure 1B as an example, when the dielectric constants of the filling materials F1, F2 and F3 are different from each other, the three second electrodes 122 can be electrically connected to three switch elements (not shown) respectively. Through the opening and closing of these three switch elements, the capacitor element 120 can provide eight capacitance values (including zero). In this way, the capacitor element 120 can be widely used in various circuits and electronic components. For example, the capacitor element 120 that can provide multiple capacitance values (e.g., eight) is suitable for application in oscillation frequency modulation circuits, thereby helping to match antennas.

In addition to the filling materials F1, F2 and F3, the sizes (e.g., areas) of the first electrode 121 and each of the second electrodes 122 and the distance W12 between the second electrode 122 and the first electrode 121 in the second direction D2 can determine the capacitance of the capacitor element 120. Compared to conventional embedded capacitor elements, the distance W12 between the second electrode 122 and the first electrode 121 is easier to change, so that the capacitor element 120 can generate a preset capacitance value through the distance W12 and the sizes of the first electrode 121 and the second electrode 122.

It is particularly worth mentioning that in other embodiments, the dielectric material 123 may include only a single filling material. That is, two of the filling materials F1, F2 and F3 in FIG. 1B may be omitted, and the remaining fills the space between the first electrode 121 and the second electrodes 122 completely. Therefore, the dielectric material 123 may have only one dielectric constant. In addition, the dielectric material 123 in this embodiment may be a solid, but in other embodiments, the dielectric material 123 may also be a gas, such as air. Alternatively, at least one of the filling materials F1, F2 and F3 may be a gas (such as air).

FIG. 2A to FIG. 2G are schematic cross-sectional views of the process of manufacturing the circuit board in FIG. 1A. It should be noted that the circuit structure 110 other than the capacitor element 120 can be manufactured using the current circuit board manufacturing process, so FIG. 2A to FIG. 2G mainly depict the manufacturing process of the capacitor element 120, and omit part of the circuit structure 110 other than the capacitor element 120. Referring to FIG. 2A, first, a circuit substrate 10 is provided, which includes a core circuit layer and a core insulation layer, wherein the core insulation layer is disposed between the two core circuit layers.

The circuit substrate 10 is a core substrate, wherein each core circuit layer is a circuit layer 111a, and the core insulation layer is an insulation layer 112a, so the components included in the circuit substrate 10 are the same as some components of the circuit board 100. In addition, the circuit layer 111a may be made of metal, such as copper, and the insulation layer 112a may be made of polymer material, such as epoxy resin.

Please refer to FIG. 2B . Afterwards, two initial trenches R20 are formed in parallel on the insulating layer 112a (i.e., the core insulating layer), wherein the initial trenches R20 can be formed by routing, milling, or laser ablation. These initial trenches R20 are respectively adjacent to the side edges of the circuit layer 111a, wherein each side wall S12 of the initial trenches R20 can be aligned with the side edge S11 of at least one layer of the circuit layer 111a. Taking FIG. 2B as an example, the side wall S12 of each initial trench R20 can be aligned with the side edge S11 of two layers of the circuit layer 111a.

Please refer to FIG. 2C . After the initial trenches R20 are formed, a first initial electrode 121i and a second initial electrode 122i are formed in the two initial trenches R20. The first initial electrode 121i and the second initial electrode 122i can be formed by electroless plating and electric plating. Before the electroless plating and the electric plating, two mask layers 29 can be respectively covered on opposite sides of the insulating layer 112a, wherein the mask layer 29 can be a photoresist layer after development, such as a dry film, and the mask layer 29 will not cover any initial trenches R20 to expose the initial trenches R20. In this way, the mask layers 29 can limit the first initial electrode 121i and the second initial electrode 122i to be formed only in the initial trench R20.

In this embodiment, the first initial electrode 121i and the second initial electrode 122i can be connected to the circuit layer 111a, so that the first initial electrode 121i and the second initial electrode 122i can be electrically connected to the circuit layer 111a. However, in other embodiments, at least one of the first initial electrode 121i and the second initial electrode 122i can be separated from any layer of the circuit layer 111a. For example, at least one of the first initial electrode 121i and the second initial electrode 122i is not connected to any circuit layer 111a. Therefore, the first initial electrode 121i and the second initial electrode 122i are not limited to be connected to the circuit layer 111a.

Please refer to FIG2D. Afterwards, multiple build-up circuit layers and multiple build-up insulation layers are formed on opposite sides of the insulation layer 112a, wherein the build-up circuit layer is the circuit layer 111b, and the build-up insulation layer is the insulation layer 112b. These build-up circuit layers (i.e., the circuit layer 111b) and these build-up insulation layers (i.e., the insulation layer 112b) can be formed by a build-up method, and the insulation layer 112b covers the first initial electrode 121i and the second initial electrode 122i, as shown in FIG2D.

Please refer to FIG. 2D and FIG. 2E. Afterwards, a portion of these insulating layers 112b is removed to form two first trenches R21 and two second trenches R22 on these insulating layers 112b, wherein the two first trenches R21 are respectively located at opposite sides of the first initial electrode 121i and expose the first initial electrode 121i. The two second trenches R22 are respectively located at opposite sides of the second initial electrode 122i. From FIG. 2E, the depth of the second trenches R22 is less than the depth of the first trenches R21, so these second trenches R22 do not expose the second initial electrode 122i. In addition, the forming method of the first trench R21 and the second trench R22 may be the same as the forming method of the initial trench R20 .

Please refer to FIG. 2E and FIG. 2F. Afterwards, metal material is deposited in the first trench R21 and the second trench R22 to form a first electrode 121 in the first trench R21 and a plurality of second electrodes 122 in the second trenches R22. The method of depositing metal material may include electroless plating and electric plating. Before performing electroless plating and electric plating, two mask layers may be used, such as the mask layer 29 shown in FIG. 2C, wherein these mask layers cover the outermost insulating layer 112b respectively and expose the first trenches R21 and the second trenches R22. In this way, the mask layer can limit the first electrode 121 and the second electrode 122 to be formed only in the first trench R21 and the second trench R22, respectively.

Since the first trenches R21 expose the first initial electrode 121i, the first electrode 121 includes the first initial electrode 121i. The second trenches R22 do not expose the second initial electrode 122i, so that the second initial electrode 122i is covered by the insulating layers 112a and 112b. Therefore, the second electrodes 122 are separated from the second initial electrode 122i.

It is worth mentioning that the second initial electrode 122i is one of the second electrodes 122. In detail, in FIG. 1B and FIG. 2F, the second initial electrode 122 in the middle is the second initial electrode 122i in FIG. 2E. In the drawings and descriptions after FIG. 2F, the second initial electrode 122i will be changed to the second electrode 122. In addition, except for the second electrode 122 in the middle (i.e., the original second initial electrode 122i), each second electrode 122 is connected to at least one circuit layer 111b. Taking FIG. 2F as an example, each second electrode 122 is connected to two of these circuit layers 111b.

Please refer to FIG. 2F and FIG. 2G . Afterwards, the insulating layers 112a and 112b between the first electrode 121 and the second electrode 122 (including the original second initial electrode 122i) are partially removed to form a groove (not shown), wherein the groove exposes the first electrode 121 and all the second electrodes 122. Afterwards, the dielectric material 123 is filled in the groove, wherein the dielectric material 123 can directly contact the first electrode 121 and all the second electrodes 122. At this point, the circuit board 100 is basically manufactured.

The dielectric material 123 may include filling materials F1, F2 and F3, and the step of filling the dielectric material 123 in the trench may include sequentially filling the filling materials F1, F2 and F3 in the trench, wherein the filling materials F1, F2 and F3 are respectively sandwiched between the first electrode 121 and the second electrodes 122. Taking FIG. 2G as an example, the filling material F2 is sandwiched between the first electrode 121 and the middle second electrode 122 (i.e., the second initial electrode 122i), and each of the other filling materials F1 and F3 is sandwiched between the first electrode 121 and one of the second electrodes 122. For example, the filling material F1 is interposed between the first electrode 121 and the second electrode 122 below, and the filling material F2 is interposed between the first electrode 121 and the second electrode 122 above.

Please refer to FIG. 2F , and it is particularly noted that in other embodiments, the partial insulating layers 112a and 112b between the first electrode 121 and the second electrodes 122 may not be removed, so that the partial insulating layers 112a and 112b sandwiched between the first electrode 121 and all the second electrodes 122 serve as dielectric materials, thereby forming a capacitor element including the partial insulating layers 112a and 112b, as shown in FIG. 2F . Therefore, the partial insulating layers 112a and 112b may serve as dielectric materials of the capacitor element, which are not limited to include the filling materials F1, F2, and F3.

FIG. 3A is a schematic top view of a circuit board of another embodiment of the present invention, and FIG. 3B is a schematic cross-sectional view taken along line 1B-1B in FIG. 3A. Referring to FIG. 3A and FIG. 3B, the circuit board 300 of this embodiment is similar to the circuit board 100 of the aforementioned embodiment. For example, the circuit board 300 includes a capacitor element 330, a plurality of circuit layers 111a, 111b, and a plurality of insulating layers 112a, 112b, wherein the capacitor element 330 includes a first electrode 121 and a plurality of second electrodes 122. The following mainly describes the differences between the circuit boards 300 and 100, and the same features of the two are basically not repeated.

The capacitor element 330 is different from the capacitor element 120, wherein the dielectric material 323 included in the capacitor element 330 is different from the aforementioned dielectric material 123. Specifically, the dielectric material 323 has at least one through hole T3 and at least one blind hole V3, wherein the through hole T3 and the blind hole V3 can be formed after the first electrode 121 and the second electrodes 122 are formed (please refer to FIG. 2F). In addition, in this embodiment, the dielectric material 323 may have a plurality of through holes T3 and a plurality of blind holes V3, but the present invention does not limit the number of through holes T3 and blind holes V3 of the dielectric material 323, wherein the dielectric material 323 may also have only one of the through hole T3 and the blind hole V3.

That is, after the first electrode 121 and the second electrodes 122 are formed, at least one through hole T3 and at least one blind hole V3 can be formed on a portion of the insulating layer 112b between the first electrode 121 and the second electrodes 122, wherein the through hole T3 extends along the first direction D1 in the insulating layers 112a and 112b, and the blind hole V3 extends along the first direction D1 at least in the insulating layer 112b. Taking FIG. 3B as an example, the blind hole V3 extends in the insulating layer 112a and some insulating layers 112b. From FIG. 3B, it can be seen that the depth of the blind hole V3 is obviously smaller than the thickness of the circuit structure (not shown) of the capacitor element 330, and is also smaller than the depth of the through hole T3.

In addition, the capacitor element 330 may further include a plurality of filling materials 321 and 322, wherein the filling materials 321 and 322 are respectively filled in the through hole T3 and the blind hole V3, and the filling materials 321 and 322 may be the same as the filling materials F1, F2 and F3 in the aforementioned embodiment (please refer to FIG. 1B). For example, the filling materials 321 and 322 may be the same as the filling materials F1 and F2, respectively. In addition, at least one of the filling materials 321 and 322 may be a gas, such as air.

In summary, in the circuit board disclosed in at least one embodiment of the present invention, the electrodes of the capacitor element (i.e., the first and second electrodes) extend along the stacking direction of the circuit layer (i.e., the first direction). Therefore, compared with the conventional embedded capacitor element, the electrodes of the capacitor element in at least one embodiment of the present invention will not be arranged parallel to the circuit layer, that is, the capacitor element will not occupy too much size or area of the circuit board, so that the circuit board of at least one embodiment of the present invention can meet the development trend of current electronic devices (such as mobile devices) towards miniaturization.

Although the present invention has been disclosed as above by way of embodiments, they are not intended to limit the present invention. A person having ordinary knowledge in the technical field to which the present invention belongs may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined in the attached patent application.

10: Circuit substrate 29: Mask layer 100, 300: Circuit board 110: Circuit structure 111a, 111b: Circuit layer 112a, 112b: Insulation layer 113: Conductive connection part 120, 330: Capacitor element 121: First electrode 121i: First initial electrode 122: Second electrode 122i: Second initial electrode 123, 323: Dielectric material 321, 322, F1, F2, F3: Filling material D1: First direction D2: Second direction R20: Initial trench R21: First trench R22: Second trench S11: Side S12: Sidewall T3:Through hole V3:Blind hole W12:Distance

FIG. 1A is a schematic diagram of a circuit board of at least one embodiment of the present invention from above. FIG. 1B is a schematic diagram of a cross section taken along line 1B-1B in FIG. 1A. FIG. 2A to FIG. 2G are schematic diagrams of a cross section of a process for manufacturing the circuit board in FIG. 1A. FIG. 3A is a schematic diagram of a circuit board of another embodiment of the present invention from above. FIG. 3B is a schematic diagram of a cross section taken along line 3B-3B in FIG. 3A.

100: Circuit board

110: Circuit structure

111a, 111b: Circuit layer

112a, 112b: Insulating layer

113: Conductive connection part

120: Capacitor components

121: First electrode

122: Second electrode

123: Dielectric materials

F1, F2, F3: filling materials

D1: First direction

D2: Second direction

W12: Distance

Claims (11)

A circuit board, comprising: A circuit structure, comprising a plurality of circuit layers and a plurality of insulating layers, wherein the circuit layers and the insulating layers are stacked alternately along a first direction; A capacitor element, disposed in the circuit structure and passing through the plurality of circuit layers and the plurality of insulating layers, wherein the capacitor element comprises: A first electrode, extending along the first direction and passing through the plurality of circuit layers and the plurality of insulating layers, wherein the first electrode is connected to at least one of the circuit layers; A plurality of second electrodes are arranged along the first direction and separated from each other, wherein each of the second electrodes is separated from the first electrode, and each of the second electrodes overlaps with the first electrode along a second direction, wherein the second direction is perpendicular to the first direction, and each of the second electrodes is connected to at least one layer of the circuit layer; and a dielectric material is disposed between the first electrode and the second electrode. A circuit board as described in claim 1, wherein the dielectric material comprises: A plurality of filling materials arranged along the first direction, wherein each of the filling materials is sandwiched between the first electrode and one of the second electrodes, and the plurality of filling materials overlap with the plurality of second electrodes respectively in the second direction, wherein the dielectric constants of at least two of the filling materials are different from each other. A circuit board as described in claim 1, wherein the distances between the multiple second electrodes and the first electrode in the second direction are equal to each other. A circuit board as described in claim 1, wherein the dielectric material has at least one through hole, and the through hole extends along the first direction. A circuit board as described in claim 1, wherein the dielectric material has at least one blind hole, and the blind hole extends along the first direction, wherein the depth of the blind hole is less than the thickness of the circuit structure. A method for manufacturing a circuit board, comprising: Providing a circuit substrate, comprising two core circuit layers and a core insulation layer disposed between the two core circuit layers; Forming two initial trenches parallel to each other on the core insulation layer, wherein the two initial trenches are respectively adjacent to the sides of the core circuit layer; Forming a first initial electrode and a second initial electrode in the two initial trenches respectively; Forming a plurality of build-up circuit layers and a plurality of build-up insulation layers on opposite sides of the core insulation layer, wherein the build-up insulation layer covers the first initial electrode and the second initial electrode; Removing part of the build-up insulating layer to form two first trenches and two second trenches on the multiple build-up insulating layers, wherein the two first trenches are respectively located on opposite sides of the first initial electrode and expose the first initial electrode, and the two second trenches are respectively located on opposite sides of the second initial electrode, wherein the depth of the second trench is less than the depth of the first trench; and Depositing metal material in the first trench and the second trench to form a first electrode in the first trench, and forming multiple second electrodes in the multiple second trenches, wherein each of the second electrodes is connected to at least one of the build-up circuit layers. The method for manufacturing a circuit board as described in claim 6 further comprises: Forming at least one through hole on a portion of the build-up insulating layer between the first electrode and the second electrode, wherein the through hole extends between the build-up insulating layer and the initial insulating layer. The method for manufacturing a circuit board as described in claim 6 further comprises: Forming at least one blind hole on a portion of the build-up insulating layer between the first electrode and the second electrode, wherein the blind hole at least extends to the build-up insulating layer. The method for manufacturing a circuit board as described in claim 6 further comprises: Removing a portion of the build-up insulating layer and a portion of the core insulating layer between the first electrode and the second electrode to form a groove, wherein the groove exposes the first electrode, the second electrode and the second initial electrode; and Filling a dielectric material in the groove. The method for manufacturing a circuit board as described in claim 9, wherein the step of filling the dielectric material in the groove comprises: Sequentially filling a plurality of filling materials in the groove, wherein one of the filling materials is sandwiched between the first electrode and the second initial electrode, and each of the other filling materials is sandwiched between the first electrode and one of the second electrodes. A method for manufacturing a circuit board as described in claim 6, wherein the side wall of each of the initial trenches is aligned with the side edge of at least one of the core circuit layers.

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