TWI861253B - PROCESS FOR MANUFACTURING A COMPOSITE STRUCTURE COMPRISING A THIN LAYER OF MONOCRYSTALLINE SiC ON A CARRIER SUBSTRATE MADE OF SiC - Google Patents

Abstract

The invention relates to a process for manufacturing a composite structure comprising a thin layer of monocrystalline silicon carbide arranged on a carrier substrate made of silicon carbide, the process comprising: a) a step of providing an initial substrate made of monocrystalline silicon carbide, b) a step of epitaxial growth of a monocrystalline silicon carbide donor layer on the initial substrate, to form a donor substrate 111, c) a step of ion implantation of light species into the donor layer, to form a buried brittle plane delimiting the thin layer between said buried brittle plane and a free surface of said donor layer, d) a step of direct liquid injection-chemical vapour deposition, at a temperature below 1000°C, to form a carrier layer directly on the free surface of the donor layer, said carrier layer being formed by an at least partially amorphous SiC matrix, e) a step of separating along the buried brittle plane to form, on the one hand, an intermediate composite structure comprising the thin layer on the carrier layer and, on the other hand, the rest of the donor substrate, f) a step of heat treatment at a temperature of between 1000°C and 1800°C, applied to the intermediate composite structure, to crystallize the carrier layer and to form the polycrystalline carrier substrate, g) a step of mechanical and/or chemical treatment(s) of the composite structure.

Description

A method for making a composite structure comprising a single crystal SiC thin layer on a SiC carrier substrate

The invention relates to the field of semiconductor materials for microelectronic components. In detail, the invention relates to a method for making a composite structure comprising a single-crystal silicon carbide layer disposed on a carrier substrate made of silicon carbide.

Interest in silicon carbide (SiC) has grown significantly over the past few years as this semiconductor material offers the potential to improve power handling capabilities. SiC is increasingly being used to create innovative power components to meet the needs of emerging electronics sectors, such as electric vehicles.

Compared to traditional silicon homologues, power components and integrated supply systems based on monocrystalline silicon carbide are able to manage much higher power densities and do so with smaller active area sizes. To further limit the size of power components on SiC, it is advantageous to make vertical components rather than horizontal components. To do this, it is necessary to enable vertical electrical conduction between the electrodes arranged on the front and the back of the SiC structure.

However, single-crystal SiC substrates used in the microelectronics industry are currently still quite expensive and difficult to provide in large sizes. Therefore, it is advantageous to use thin-layer transfer methods to produce composite structures, which usually include a single-crystal SiC thin layer arranged on a cheaper carrier substrate. A well-known thin-layer transfer method is the Smart Cut ^TM method, which is based on light ion implantation and direct bonding. This method allows the production of composite structures comprising a single-crystal SiC (hereinafter referred to as c-SiC) thin layer, which is taken from a c-SiC donor substrate and is in direct contact with a carrier substrate made of polycrystalline SiC (hereinafter referred to as p-SiC), allowing vertical conduction. However, achieving high-quality direct bonding via molecular adhesion between c-SiC and p-SiC substrates remains difficult because managing the surface state and roughness of these substrates is quite complex.

There are also various treatment methods derived from the above method in the prior art. For example, F. Mu et al. (ECS Transactions, 86(5)3-21, 2018) performed direct bonding (SAB is the abbreviation for "surface activated bonding") after activating the surfaces to be bonded by argon bombardment: this pre-bonding treatment will produce a very high density of side bonds, which promote the formation of covalent bonds at the bonding interface, thus having a high bonding energy. However, the disadvantage of this method is that it will produce an amorphous layer on the surface of the single-crystalline SiC donor substrate, which has a negative impact on the vertical conduction between the c-SiC thin layer and the p-SiC carrier substrate.

Many solutions to this problem have been proposed, especially document EP3168862, which uses dopant species to be implanted into the amorphous layer to restore its electrical properties. The biggest disadvantage of this method is that it is complicated and costly.

Document US8436363 discloses a method for making a composite structure comprising a c-SiC thin layer disposed on a metal carrier substrate, the thermal expansion coefficient of the carrier substrate matching the thermal expansion coefficient of the thin layer. This manufacturing method comprises the following steps: - forming a buried brittle plane in the c-SiC donor substrate, thereby defining a thin layer between the buried brittle plane and the front surface of the donor substrate; - depositing a layer of metal, such as tungsten or molybdenum, on the front surface of the donor substrate to form a carrier substrate with sufficient thickness to perform the function of a stiffener; - separating along the buried brittle plane to form a composite structure comprising a metal carrier substrate and a c-SiC thin layer on the one hand, and forming the remaining part of the c-SiC donor substrate on the other hand.

However, this method of fabrication is incompatible when the material forming the carrier substrate is p-SiC, since p-SiC needs to be deposited at temperatures above 1200°C (the temperature usually used for its fabrication). In detail, at such high temperatures, the growth kinetics of the cavities present in the buried brittle planes are faster than those of the p-SiC layer and it is not possible to achieve the thickness required for the strengthening effect before blistering begins to occur, which is associated with deformations of the layer perpendicular to the cavities.

Regardless of the method used to transfer the layer, another problem arises with regard to providing a composite structure comprising a c-SiC thin layer of ultra-high quality, more specifically one that does not contain (or has a very low density of) extensional defects that could easily affect the performance quality and reliability of the power devices to be formed on said thin layer.

The present invention relates to a solution to replace the prior art, the purpose of which is to overcome all or part of the above-mentioned shortcomings. In detail, the present invention relates to a method for making a composite structure, which comprises a high-quality c-SiC thin layer arranged on a crystalline SiC carrier substrate.

The present invention relates to a method for manufacturing a composite structure, which comprises a single-crystal silicon carbide thin layer arranged on a carrier substrate made of silicon carbide. The method comprises: a) providing an initial substrate made of single crystal silicon carbide, b) epitaxially growing a donor layer of single crystal silicon carbide on the initial substrate to form a donor substrate, wherein the crystal defect density of the donor layer is lower than that of the initial substrate, c) implanting light species ions into the donor layer to form a buried brittle plane to define the thin layer between the buried brittle plane and the free surface of the donor layer, d) performing direct injection liquid chemical vapor deposition at a temperature below 1100°C to directly form a carrier layer on the free surface of the donor layer, wherein the carrier layer is composed of at least a partially amorphous SiC matrix. e) a step of separating along the buried brittle plane, thereby forming an intermediate composite structure comprising the thin layer on the carrier layer on the one hand and the remainder of the donor substrate on the other hand, f) a step of subjecting the intermediate composite structure to a heat treatment at a temperature between 1000°C and 1800°C, so as to crystallize the carrier layer and form a polycrystalline carrier substrate, g) a step of subjecting the composite structure to a mechanical and/or chemical treatment, the treatment being applied to the free face of the carrier substrate (i.e. the back face of the composite structure) and/or the free face of the thin layer (i.e. the front face of the composite structure).

According to other advantageous and non-limiting features of the invention, which can be implemented individually or in any technically feasible combination: . the deposition step d) is carried out at a temperature between 100° C. and 700° C., or even preferably at a temperature between 200° C. and 600° C.; . the deposition step d) is carried out at a pressure between 1 Torr and 500 Torr; . the precursor used during the deposition step d) is selected from polysilylethylene and disilabutane; . at the end of the deposition step d), the carrier layer has a thickness greater than or equal to 10 microns, or even greater than or equal to 50 microns, or even greater than or equal to 100 microns, or even greater than or equal to 200 microns; . Chemical etching, mechanical grinding and/or chemical mechanical polishing are applied to the free surface of the carrier layer between step d) and step e);. Step a) comprises forming a single-crystalline conversion layer on the initial substrate to convert the basal plane dislocation defects of the initial substrate into threading edge dislocation defects;. The epitaxial growth step b) is carried out at a temperature higher than 1200°C, preferably between 1500°C and 1650°C;. The separation step e) is carried out at a temperature higher than the deposition temperature of step d);. The separation step e) occurs during the deposition step d), preferably at the end of step d);. The separation step e) and the crystallization step f) occur during the same heat treatment;. Step g) includes chemically mechanically polishing the front and back sides of the composite structure simultaneously;. The method further includes a step of trimming the remaining portion of the donor substrate for the purpose of reusing it as an initial substrate or a donor substrate.

In the following description, the same numbers in the figures represent the same type of components. For the sake of convenience, the figures are schematic diagrams that are not drawn to scale. In particular, the thickness of the layers along the z-axis is not to scale relative to the lateral dimensions along the x-axis and y-axis; in addition, the relative thickness relationship between the layers may not be accurately presented in the figures.

The present invention relates to a method for manufacturing a composite structure 1, which comprises a single-crystal silicon carbide thin layer 10 disposed on a carrier substrate 20 made of silicon carbide (Figure 1). The carrier substrate 20 is preferably polycrystalline (polycrystalline SiC will be referred to as "p-SiC" hereinafter).

The method first includes step a) of providing an initial substrate 11 made of single-crystal silicon carbide (Fig. 2a). In the following description, single-crystal silicon carbide will be referred to as "c-SiC".

The initial substrate 11 is preferably a wafer having a diameter of 100 mm, 150 mm, 200 mm, or even 300 mm, or even 450 mm, and a thickness typically between 300 microns and 800 microns. The initial substrate 11 has a front side 11a and a back side 11b. The surface roughness of the front side 11a can advantageously be selected to be less than 1 nm Ra (average roughness), which is measured by scanning 20 microns x 20 microns with an atomic force microscope (AFM).

The method then includes a step b) of epitaxially growing a donor layer 110 of single-crystal silicon carbide on the initial substrate 11 to form a donor substrate 111 (Fig. 2b). The operation of the epitaxial growth step makes the crystal defect density of the donor layer 110 lower than the crystal defect density of the initial substrate 11.

The c-SiC starting substrate 11 is typically of 4H or 6H polytype, exhibiting an offcut of less than 4.0°±0.5° relative to the <11-20> crystallographic axis, and a micropipe density of less than or equal to 5/cm ² or even less than 1/cm ^2. For example, when the starting substrate 11 is N-type (nitrogen) doped, its resistivity is preferably between 0.015 ohm.cm and 0.030 ohm.cm. The selected starting substrate 11 may have a low basal plane dislocation (BPD) defect density, typically less than or equal to 3000/cm ^2. c-SiC substrates with a BPD density of about 1500/cm ² are reasonably available and therefore easily available.

At the end of the method of the present invention, the c-Si thin layer 10 of the composite structure 1 will be formed by the donor layer 110. In order to meet the specifications required for the vertical component to be made on the thin layer 10, it is expected that the crystal quality of the donor layer 110 is higher than that of the initial substrate 11. There are different types of extensional defects in the layer or substrate of c-SiC. These extensional defects may affect the performance and reliability of the component. In particular, BPD defects are fatal to bipolar components: because when the recombination energy of electron-hole pairs exists, Shockley stacking faults (SFF) will expand from the difference. The expansion of SFF inside the active region of the component will cause the passing state resistance of the component to increase.

Therefore, the c-SiC donor layer 110 is fabricated so that the BPD defect density is less than or equal to 1/cm ² .

To this end, the epitaxial growth step b) is carried out at a temperature above 1200°C, preferably between 1500°C and 1650°C. The precursor is silane (SiH4), propane (C3H8) or ethylene (C2H4); the carrier gas can be hydrogen with or without argon.

The low BPD defect rate in the donor layer 110 can be obtained by promoting the conversion of BPD defects existing in the initial substrate 11 into through-edge dislocations (TEDs).

According to a specific embodiment, step a) comprises forming a single-crystalline conversion layer 13, preferably made of c-SiC, so that the BPD defects in the initial substrate 11 are converted into TED defects to the greatest extent (Figure 3a). For this purpose, it is advantageous to select a low off-angle of close to 4° for the c-SiC initial substrate 11, increase in-situ etching before epitaxial growth, target a high growth rate (usually greater than 5μm/h), and select the growth conditions of the single-crystalline conversion layer 13 so that the C/Si ratio in the precursor flow is close to 1.

Step b) then consists in epitaxially growing a donor layer 110 on the conversion layer 13 ( FIG. 3 b ). According to this particular embodiment, it is also possible to obtain a c-SiC donor layer 110 with a BPD defect density lower than or equal to 1/cm ² , or even lower than 0.1/cm ^{2 .} Moreover, the probability of bipolar degradation (the probability of holes reaching below the BPD/TED transition point) at the end of the method of the invention is extremely small (<0.1%), since the single-crystalline conversion layer 13 is not transferred to the composite structure 1 . The known technique aimed at reducing bipolar degradation involves introducing a recombination layer (doped with nitrogen exceeding 1 ^E 18 at/cm ³ ) between the conversion layer and the active layer. At the expense of a thickness of 10 μm and a concentration of more than 5 ^E 18 / cm ³ , the recombination layer can reduce the probability of holes appearing to 0.1% compared to the basic structure without the recombination layer. In the present invention, since the single crystal conversion layer 13 is not transferred, the probability of holes reaching the bipolar degenerate nucleation point (BPD-TED conversion point or any BPD point) is at least less than 0.1% or even close to 0%.

It should be noted that prior to the epitaxial growth in step b), a conventional cleaning or etching process of the initial substrate 11 may be performed to remove part or all of the particle contaminants, metal contaminants or organic contaminants, or the native oxide layer that may be present on the front surface 11a.

The manufacturing method according to the present invention further comprises a step c) of implanting light ion species into the donor layer 110 to a predetermined depth, which represents the ideal thickness of the thin layer 10, and the implantation will not touch the initial substrate 11 (and/or the conversion layer 13, if any) under any circumstances. The implantation forms a buried brittle plane 12 in the donor layer 110, which defines a thin layer 10 between the buried brittle plane 12 and the free front surface 11a of the donor layer 110 (Figure 2c).

The implanted light species is preferably hydrogen, helium, or hydrogen and helium. As is known from the Smart Cut ^™ method, the light species will form microcavities near a given depth, distributed in a thin layer parallel to the free front surface 11a of the donor layer 110, i.e. parallel to the plane (x, y) in the figure. For simplicity, this thin layer is called the buried brittle plane 12.

The implantation energy of the lightweight species is selected to reach a predetermined depth in the donor layer 110.

Hydrogen ions are typically implanted at an energy between 10 keV and 250 keV and a dose between 5 ^E 16 /cm ² and 1 ^E 17 /cm ² to define a thin layer 10 with a thickness of about 100 nm to 1500 nm.

It should be noted that before the ion implantation step, a protective layer may be deposited on the free surface of the donor layer 110. This protective layer may be composed of materials such as silicon oxide or silicon nitride.

The method of the invention then comprises a step d) (FIG. 2d) of forming a carrier layer 20' directly on the free surface of the donor layer 110 by direct liquid chemical vapor deposition (DLI-CVD) at a temperature below 1000°C, preferably below 900°C. The deposition step d) can be carried out at a temperature between 100°C and 800°C, between 100°C and 700°C, or even advantageously between 200°C and 600°C. The pressure in the deposition chamber is preferably limited to between 1 Torr and 500 Torr.

The DLI-CVD deposition technique provides good yield between the material provided (precursor) and the deposition thickness achieved without the use of chlorinated precursors, thus limiting costs and environmental constraints.

DLI-CVD deposition is best performed using pure or diluted disilanebutane or polysilylethylene precursors. Other precursors such as methyltrichlorosilane, ethylenetrichlorosilane, dichloromethylvinylsilane, tetraethylsilane, tetramethylsilane, diethylmethylsilane, bistrimethylsilylmethane, or hexamethyldisilane may also be used as needed.

This technology, described in the paper by Guilhaume Boisselier (2013, “Dépôt chimique en phase vapeur de carbures de chrome, de silicium et d'hafnium assisté par injection liquide pulsée [Pulsed liquid injection-chemical vapour deposition of chromium,silicon and hafnium carbides]”), is used to deposit ceramic coatings on parts (such as metal parts made of steel or alloys) to protect them during very high temperature processing.

The applicant in this case proposed a deposition step d) based on DLI-CVD that can be used for completely different applications, namely forming a carrier layer 20' on the c-SiC donor layer 110, so as to obtain a composite structure 1 for use in the field of microelectronics at the end of the manufacturing method.

The deposited carrier layer 20' forms a SiC matrix, which includes amorphous SiC and reaction byproducts derived from the precursors used in the deposition process and formed from carbon chains. In addition, the SiC matrix may optionally include crystallized SiC grains.

The DLI-CVD technique can provide a deposition rate greater than or equal to 10 microns/hour, or even greater than 50 microns/hour, or even greater than 100 microns/hour. At a given average deposition temperature, the deposition rate does not need to be very high (except for obvious economic reasons) because within the temperature range, the thermally activated growth of the cavity of the buried brittle plane 12 maintains a slow rate, so that the thickness of the carrier layer 20' can be easily achieved to ensure a strong effect relative to the buried brittle plane 12.

At the end of step d), the carrier layer 20' may have a thickness greater than or equal to 10 microns, greater than or equal to 50 microns, 100 microns, or even greater than or equal to 200 microns. The stack 211 produced in step d) includes the carrier layer 20' disposed on the donor layer 110, and the donor layer 110 disposed on the initial substrate 11.

The method of the invention then comprises a step e) of separation along the embedded brittle plane 12 to form, on the one hand, the intermediate composite structure 1' and, on the other hand, the remainder 111' of the donor substrate (Fig. 2e).

According to an advantageous embodiment, the separation step e) is to apply a heat treatment to the stack 211 at a separation temperature higher than the deposition temperature of step d). In detail, the microcavities present in the embedded brittle plane 12 follow the growth dynamics until the initiation of a fracture wave, which will propagate throughout the entire extent of the embedded brittle plane 12 and cause the intermediate composite structure 1' to separate from the remainder 111' of the initial substrate. In operation, the temperature can be between 950°C and 1200°C, preferably between 1000°C and 1200°C, depending on the implantation conditions of step c).

According to an alternative embodiment, the separation step e) is performed by applying mechanical pressure to the stack 211, followed by, if necessary, embrittlement of the embedded brittle plane 12 by heat treatment. The pressure can be applied, for example, by inserting a tool (such as a blade) close to the embedded brittle plane 12. For example, the separation pressure can be of the order of several GPa, preferably greater than 2 GPa.

According to yet another embodiment, the separation step e) along the buried brittle plane 12 occurs during or just after the DLI-CVD deposition step d), more specifically when the deposition temperature reaches a range of 900°C to 1000°C.

The manufacturing method of the present invention then includes a step f) of applying a heat treatment to the intermediate composite structure 1' at a temperature between 1000°C and 1800°C to crystallize the carrier layer 20' and form a polycrystalline carrier substrate 20.

The tempering atmosphere may in particular contain, for example, argon, nitrogen, hydrogen, helium or a mixture of these gases.

The tempering has the effect of removing hydrogen from the carrier layer 20' and causing the SiC matrix to crystallize in the form of polycrystalline SiC.

The crystallization heat treatment can be carried out using known furnaces for treating multiple structures simultaneously (batch tempering). The typical duration of the crystallization heat treatment is between a few minutes and a few hours.

Optionally, a crystallization heat treatment can be performed in situ in the DLI deposition chamber, which typically lasts for a few minutes.

The present invention is advantageous in that the temperature ramp is limited, for example, less than 20°/min, less than 5°/min or even less than 1°/min, so as to limit the occurrence of cracks or structural defects in the crystal layer.

After step f), a composite structure 1 can be obtained, which comprises a thin layer 10 of single-crystal silicon carbide disposed on a carrier substrate 20 made of polycrystalline silicon carbide.

The deposition parameters (step d) and the crystallization tempering parameters (step f) are determined so that the carrier substrate 20 has: - good electrical conductivity, i.e. lower than or equal to 0.03 ohm.cm, or even lower than or equal to 0.01 ohm.cm, - high thermal conductivity, i.e. greater than or equal to 150 W.m ^-1 .K ^-1 , or even greater than or equal to 200 W.m ^-1 .K ^-1 , - and a thermal expansion coefficient similar to that of the thin layer 10, i.e. between 3.8 ^E -6/K and 4.2 ^E -6/K at room temperature.

To achieve these properties, the carrier substrate 20 preferably has structural features such as: polycrystalline structure, 3C SiC grains, [111] orientation, an average size of 1 to 50 μm in the main plane of the substrate, and N-type doping so that the final resistivity is less than or equal to 0.03 ohm.cm, or even less than or equal to 0.01 ohm.cm.

Furthermore, it is preferred to define a non-insulating interface between the donor layer 110 and the carrier substrate 20. The resistivity of the non-insulating interface is generally expected to be below 1 mohm.cm ² . In order to ensure the conductivity of the interface, the native oxide present on the free face of the donor layer 110 can be removed by deoxidation with HF (hydrofluoric acid) by a wet or dry method before the deposition step d). As an alternative, the first few nanometers deposited on the carrier layer 20 ′ can be overdoped by introducing doping species during the DLI-CVD deposition step d). It should be noted that, in general, during the deposition step d), the doping species may be introduced in different doses depending on the degree of doping and the target conductivity of the carrier substrate 20 that will take effect at the end of the crystallization annealing in step f).

The present invention is also advantageous in that, prior to the deoxidation and/or formation of the carrier layer 20', a cleaning process may be applied to the donor substrate 111 to remove some or all of the particulate contaminants, metal contaminants or organic contaminants that may be present on the free surface of the substrate.

As is known, at the completion of separation step e), the surface roughness of the free face 10a of the thin layer 10 of the composite structure 1 is between 5 and 100 nm RMS (measured by scanning 20 microns x 20 microns with an atomic force microscope (AFM)).

Then, a step g) of mechanically and/or chemically treating the composite structure 1 is performed to smooth the free surface 10a of the thin layer 10 and correct the thickness uniformity of the composite structure 1 (Fig. 2f).

Step g) may include chemical mechanical polishing (MCP) of the free surface 10a of the thin layer 10, which can typically remove about 50 to 1000 nanometers of material to obtain a final roughness of less than 0.5nm RMS (20 x 20μm scanned by AFM) or even less than 0.3nm. Step g) may also include chemical or plasma treatment (cleaning or etching), such as SC1/SC2 cleaning (standard cleaning 1, standard cleaning 2) and/or HF (hydrofluoric acid) cleaning, and/or N2, Ar, CF4 and other plasmas, to further improve the quality of the free surface 10a of the thin layer 10.

It should be noted that the crystallization of the carrier layer 20' often causes cracks or structural defects in the crystallized layer (forming the carrier substrate 20), thereby affecting its mechanical and electrical qualities.

Therefore, step g) may include chemical mechanical polishing (MCP) and/or chemical treatment (etching or cleaning) and/or mechanical treatment (trimming) of the back side 20b of the carrier substrate 20 to remove all or part of the aforementioned cracks and structural defects, thereby improving the thickness uniformity of the carrier substrate 20 and the roughness of the back side 20b. The thickness removed from the back side may be between about 100 microns and several microns.

The ideal roughness is less than 0.5nm RMS (measured by scanning an area of 20 microns x 20 microns with an atomic force microscope (AFM)) in order to make a vertical component where at least one metal electrode will be present on the back side 20b of the composite substrate 1.

During step g), the edges of the composite structure 1 may also be ground or trimmed so that the shape of its circular profile and the cutting edge waste are compatible with the requirements of the microelectronics process.

It should be noted that the treatment applied to the back side 20b of the carrier substrate 20 can be applied to the free side of the carrier layer 20' as required before the separation step e), i.e. before the front free side 10a of the composite structure 1 is exposed, in order to limit its contamination level, especially during contaminating or restrictive treatments, such as chemical etching or mechanical grinding (trimming).

According to an advantageous embodiment, the chemical mechanical treatment step g) comprises simultaneously grinding (MCP) the front free surface 10a and the back surface 20b of the composite structure 1 to smooth and improve the thickness uniformity of the composite structure 1. The grinding parameters of the front and back surfaces may be different, because the smoothing of c-SiC surfaces and p-SiC surfaces usually requires the use of different consumables. When the carrier substrate 20 is made of p-SiC, the focus is particularly on the mechanical grinding part of the back surface 20b to limit the preferential attack of the chemical grinding part on the grain boundaries. For example, the grinding parameters, such as the rotation speed (of the grinding head and the grinding disk), the pressure, the concentration of the abrasive and the physical properties (i.e. the diameter of the diamond nanoparticles is about 10nm and 1μm), etc., can be adjusted to strengthen the mechanical grinding part.

After step g), a heat treatment step g') may be carried out, if necessary, at a temperature between 1000°C and 1800°C for about one hour to a maximum of several hours. The purpose of this step is to stabilize the composite structure 1 by ensuring that structural or organizational defects still exist in and/or on the thin layer 10 and, where appropriate, by significantly developing the crystal structure of the carrier substrate 20, thereby making the composite structure 1 compatible with the high-temperature heat treatment required for the subsequent production of components on the thin layer 10.

The method of the invention may include a second step h) of epitaxially growing an additional layer 10' of single-crystalline silicon carbide on the thin layer 10 of the composite structure 1 (FIG. 2g). Such a step may be implemented when a relatively thick useful layer 100 (usually about 5 to 50 microns) is required for the production of a component.

The temperature applied in step h) can be chosen so as to limit the stresses induced by the composite structure 1 in the useful layer 100 (which corresponds to the combination of the thin layer 10 and the additional layer 10').

Finally, the manufacturing method may include a step of trimming the remaining portion 111' of the donor substrate for the purpose of reusing it as an initial substrate 11 or a donor substrate 111. Such a trimming step is based on one or more treatments of the surface 110'a (FIG. 2e), such as surface or edge chemical mechanical polishing, and/or mechanical trimming, and/or dry or wet chemical etching.

The thickness of the donor layer 110 formed in step b) is preferably defined so that the remaining portion 111' of the donor substrate 111 can be reused as the donor substrate 111 at least twice.

When the conversion layer 13 is present, care should be taken to keep the layer intact, in other words, always keep a portion of the donor layer 110 on the remaining portion 111' of the donor substrate. In this way, when this portion of the donor layer 110 is not enough to make the composite structure 1, only the step of epitaxially growing the donor layer 110 is required, and the previous step of growing the conversion layer 13 is not required.

Example: According to a non-limiting and exemplary embodiment, the initial substrate 11 provided in step a) of the manufacturing method is a 4H polytype c-SiC wafer, which has an orientation of 4.0°±0.5° relative to the <11-20> axis, a diameter of 150 mm, and a thickness of 350 μm.

Prior to step b) of epitaxially growing the c-SiC donor layer 110, a conventional RCA cleaning procedure (standard cleaning 1 + standard cleaning 2) can be performed on the initial substrate 11, followed by peroxysulfuric acid (a mixture of sulfuric acid and hydrogen peroxide), and then HF (hydrofluoric acid).

The epitaxial growth is performed at a temperature of 1650°C in an epitaxial chamber, and the precursor may be, for example, silane (SiH4), propane (C3H8) or ethylene (C2H4), and the grown c-SiC donor layer 110 has a thickness of 30 microns (growth rate: 10 microns/hour). The donor layer has a BPD defect density of about 1/ ^cm2 .

Hydrogen ions are implanted through the free surface of the donor layer 110 at an energy of 150 keV and a dose of 6 ^E 16 H+/cm ² , thereby forming a buried brittle plane 12 at a depth of about 800 nm in the initial substrate 11.

An RCA cleaning process + peroxysulfuric acid is performed on the donor substrate 111 to remove potential contaminants from the free surface of the donor layer 110.

DLI-CVD deposition is performed on the donor layer 110 at a temperature of 800°C for 60 minutes with a disiloxane (DSB) precursor at a pressure of 50 Torr to achieve a carrier layer 20' having a thickness of at least 150 microns. Under the conditions, the carrier layer 20' is deposited in the form of an amorphous SiC matrix and includes reaction byproducts from the deposited precursor.

The stack 211 is then subjected to tempering at a temperature of 1000°C for 50 minutes, during which the separation takes place at the buried brittle planes. At the completion of this separation step e), the intermediate composite structure 1' formed by the thin layer 10 and the carrier layer 20' is separated from the remaining part 111' of the donor substrate.

Then, the intermediate composite structure 1' is subjected to a crystallization heat treatment at 1200°C for 1 hour in an argon atmosphere to form a p-SiC carrier substrate 20 of the composite structure 1.

Alternatively, the separation step and the crystallization step can be carried out during the same heat treatment, for example at a temperature of 1200°C in a neutral atmosphere.

The back side of the carrier substrate 20 is mechanically trimmed to remove about 15 to 30 microns, which can remove cracks and structural defects caused by the crystallization of the SiC matrix.

One or more chemical mechanical polishing operations are then performed to restore the surface roughness of the thin layer 10 and the surface roughness of the back side of the carrier substrate 20, followed by a conventional cleaning procedure.

Of course, the present invention is not limited to the implementation methods and examples described above, and all changes made to the implementation examples fall within the scope defined by the scope of the patent application in this case.

1: Composite structure

1’: Middle composite structure

10: Thin layer

10’: Extra layer

10a: Free surface

11: Initial substrate

11’: Remaining part of the initial substrate

11a: Front

11b: Back

12: Embedded brittle plane

13: Single crystal conversion layer

20: Carrier substrate

20’: Carrier layer

20b: Back

21: Middle layer

22: Extra layer

100: Useful layer

110: Donor layer

110'a: Surface

111: Donor substrate

111’: Remainder

211: Stack

The following section on the implementation of the present invention will more clearly explain other features and advantages of the present invention. The implementation is provided with reference to the attached drawings, wherein: FIG1 shows a composite structure made according to the manufacturing method of the present invention; FIG2a to FIG2g show the steps of a manufacturing method according to the present invention; FIG3a and FIG3b show the steps of a manufacturing method according to the present invention.

Claims (13)

A method for manufacturing a composite structure (1), wherein the composite structure (1) comprises a thin layer (10) of single-crystal silicon carbide disposed on a carrier substrate (20) of silicon carbide, the method comprising: a) providing an initial substrate (11) of single-crystal silicon carbide, b) epitaxially growing a donor layer (110) of single-crystal silicon carbide on the initial substrate (11) to form a donor substrate (111), wherein the donor layer (110 ) has a crystal defect density lower than that of the initial substrate (11), c) implanting light species ions into the donor layer (110) to form a buried brittle plane (12), wherein the buried brittle plane (12) defines the thin layer (10) between the buried brittle plane (12) and the free surface of the donor layer (110), d) performing direct injection liquid chemical vapor deposition at a temperature lower than 1100° C. to directly implant the thin layer (10) in the donor layer (110) ), the carrier layer (20') being formed of an at least partially amorphous SiC matrix, e) a separation step along the buried brittle plane (12) to form an intermediate composite structure (1') comprising the thin layer (10) on the carrier layer (20') on the one hand and the remainder (111') of the donor substrate on the other hand, f) heating the substrate at 1000°C and 1800°C g) a step of subjecting the intermediate composite structure (1') to heat treatment at a temperature between 20 and 50°C to crystallize the carrier layer (20') and form a polycrystalline carrier substrate (20); g) a step of subjecting the composite structure (1) to mechanical and/or chemical treatment, wherein the treatment is applied to the free surface of the carrier substrate (20), i.e., the back surface of the composite structure (1), and/or the free surface of the thin layer (10), i.e., the front surface of the composite structure (1). A method as claimed in claim 1, wherein the deposition step d) is carried out at a temperature between 100°C and 700°C, or even preferably at a temperature between 200°C and 600°C. A method as claimed in claim 1 or 2, wherein the deposition step d) is carried out at a pressure between 1 Torr and 500 Torr. A method as claimed in claim 1 or 2, wherein the precursor used during the deposition step d) is selected from polysilylethylene and disilabutane. A method as claimed in claim 1, wherein at the end of the deposition step d), the carrier layer (20') has a thickness greater than or equal to 10 microns, or even greater than or equal to 50 microns, or even greater than or equal to 100 microns, or even greater than or equal to 200 microns. A method as claimed in claim 1, wherein chemical etching, mechanical grinding and/or chemical mechanical polishing are applied to the free surface of the carrier layer (20') between step d) and step e). The method of claim 1, wherein step a) includes forming a single crystal conversion layer (13) on the initial substrate (11) to convert the basal plane dislocation defect of the initial substrate (11) into a threading edge dislocation defect. The method of claim 1, wherein the epitaxial growth step b) is carried out at a temperature higher than 1200°C, preferably at a temperature between 1500°C and 1650°C. The method of claim 1, wherein the separation step e) is carried out at a temperature higher than the deposition temperature of step d). The method of claim 1, wherein the separation step e) occurs during the deposition step d), preferably at the end of step d). The method of claim 1, wherein the separation step e) and the crystallization step f) are performed during the same heat treatment period. The method of claim 1, wherein step g) comprises simultaneously chemically mechanically polishing the front and back sides of the composite structure (1). The method of claim 1 further includes the step of trimming the remaining portion (111') of the donor substrate for the purpose of reusing it as an initial substrate or a donor substrate.