TWI860894B - Estimation method for connection of chip - Google Patents

Abstract

The present invention provides an estimation method for connection of chip, which includes: providing a chip having a plurality of contacts, in which a projection area defined by orthogonally projecting end surfaces of the contacts onto a plane has an area that is defined as a predetermined area; using an optical module to detect a three-dimensional (3D) information from the end surfaces of the chip and to transmit corresponding signals to a processing module for obtaining a 3D surface corresponding in shape to the end surfaces; using the processing module to obtain a cross section of the 3D surface at a connection depth, in which an area of the cross section is defined as an estimation soldering area; and an estimation connection value is obtained through the processing module by dividing the estimation soldering area by the predetermined area.

Description

Wafer Bonding Prediction Method

The present invention relates to a chip measurement method, and more particularly to a chip bonding estimation method.

The existing chip coplanarity measurement method adopts the specifications of the Solid State Technology Association (JEDEC) (such as JEDEC22-B108B), which is mainly built on the measurement of Ball Grid Array (BGA) packaged or Pin Grid Array (PGA) packaged chips to evaluate the chip welding effect. However, with the evolution of chip technology, the existing chip coplanarity measurement method has gradually become difficult to accurately evaluate the welding effect of all chip types, such as: Land Grid Array (LGA) packaged chips.

Therefore, the inventor believes that the above defects can be improved, so he conducted intensive research and applied scientific principles, and finally proposed an invention with a reasonable design and effective improvement of the above defects.

The present invention provides a chip bonding prediction method, which can effectively improve the defects that may be caused by the existing chip coplanarity measurement method.

The present invention discloses a chip bonding prediction method, which includes: a pre-step: providing a chip having a plurality of contacts; wherein, when the end faces of the plurality of contacts are orthographically projected onto a plane, the sum of their areas is defined as a preset area; wherein, the plurality of contacts of the chip can be used to be respectively disposed on a plurality of solders located on a circuit board, so that the plurality of end faces have a bonding area contacting the plurality of solders; wherein, the chip bonding prediction method defines a bonding value, which is the bonding area divided by the predetermined area. a ratio of the preset area to the end surface of the chip; an imaging step: using an optical module to stereoscopically image the end surfaces of the multiple contacts of the chip and transmit signals to a processing module to obtain a stereoscopic plane corresponding to the multiple end surfaces; an estimation step: using the processing module to obtain a cross-section at an estimated depth based on the stereoscopic plane, and its area is defined as an estimated welding area; and a judgment step: using the processing module to divide the estimated welding area by the preset area to obtain an estimated bonding value.

The present invention also discloses a chip bonding estimation method, which includes: a pre-step: providing a chip having multiple contacts; wherein, when the end faces of the multiple contacts are orthographically projected onto a plane, the sum of their areas is defined as a preset area; an imaging step: using an optical module to stereoscopically image the end faces of the multiple contacts of the chip, and transmitting signals to a processing module to obtain a stereoscopic configuration plane corresponding to the multiple end faces; an estimation step: using the processing module to obtain a cross-section at an estimated depth based on the stereoscopic configuration plane, and its area is defined as an estimated welding area; and a judgment step: using the processing module to divide the estimated welding area by the preset area to obtain a bonding estimation value.

In summary, the chip bonding estimation method disclosed in the embodiment of the present invention can estimate the bonding estimation value of the chip by obtaining the three-dimensional configuration planes corresponding to the multiple end faces before the chip is welded, and then evaluate whether the chip continues the subsequent welding operation, so as to improve the product yield after the welding operation is performed.

Furthermore, the chip bonding estimation method disclosed in the embodiment of the present invention obtains the bonding estimation value of the chip, which is not constrained by the coplanarity standard of the Solid State Technology Association and can effectively evaluate the welding effect of all chip types.

To further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, such description and drawings are only used to illustrate the present invention and do not limit the scope of protection of the present invention.

The following is a specific embodiment to illustrate the implementation of the "chip bonding estimation method" disclosed in the present invention. The technical personnel in this field can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed based on different viewpoints and applications without deviating from the concept of the present invention. In addition, the attached drawings of the present invention are only for simple schematic illustrations and are not depicted according to actual sizes. Please note in advance. The following implementation will further explain the relevant technical content of the present invention in detail, but the disclosed content is not used to limit the scope of protection of the present invention.

It should be understood that although the terms "first", "second", "third" and so on may be used in this article to describe various components or signals, these components or signals should not be limited by these terms. These terms are mainly used to distinguish one component from another component, or one signal from another signal. In addition, the term "or" used in this article may include any one or more combinations of the related listed items depending on the actual situation.

Please refer to Figures 1 to 9, which are an embodiment of the present invention. This embodiment discloses a chip bonding estimation method S100, which sequentially includes a pre-step S110, an imaging step S120, an estimation step S130, and a judgment step S140, but the present invention is not limited thereto. For example, in other embodiments not shown in the present invention, any of the above steps S110~S140 can be adjusted and changed according to actual needs. The following is a sequential description of each of the steps of the chip bonding estimation method S100.

The pre-step S110: As shown in FIG. 1 to FIG. 5, a chip 200 and a chip measuring device 100 for measuring the chip 200 are provided. In this embodiment, the number of the chip 200 is one to introduce the connection relationship between it and the chip measuring device 100, and the chip bonding estimation method S100 is to implement the remaining steps (such as: the imaging step S120, the estimation step S130, and the judgment step S140) through the chip measuring device 100, so as to estimate the bonding value of the chip 200 before the chip 200 is soldered to a circuit board 300, but the present invention is not limited thereto.

For example, in other embodiments not shown in the present invention, the chip bonding estimation method S100 (or the chip measurement device 100) can be used to simultaneously estimate the bonding values of multiple chips 200; or, the chip bonding estimation method S100 can be implemented by a device different from the chip measurement device 100; or, the chip measurement device 100 can also be used alone (e.g., sold).

It should be further explained that the coplanarity specification (e.g., JEDEC22-B108B) of the Solid State Technology Association (SSE) is actually irrelevant to the bonding condition between the chip and the solder. Therefore, the definition of the bonding value used in this embodiment is different from the above coplanarity specification of the Solid State Technology Association. This is to more accurately present the soldering condition of the chip 200. Specifically, the chip 200 has a plurality of contacts 201, and when the end faces 2011 of the plurality of contacts 201 are orthographically projected onto a plane, the sum of their areas is defined as a preset area. The plurality of contacts 201 of the chip 200 can be used to be respectively arranged on the plurality of solders 400 located on the circuit board 300, so that the plurality of end faces 2011 have a welding area in contact with the plurality of solders 400. Furthermore, the chip bonding estimation method S100 defines the bonding value, which is a ratio of the welding area divided by the preset area.

It should be further explained that the package structure of the chip 200 can be further defined as a Land Grid Array (LGA) package, and each of the contacts 201 is a pad. In more detail, the chip 200 has a package body 202 covering a plurality of the contacts 201, and the end surfaces 2011 of the plurality of the contacts 201 are exposed from the package body 202 but do not protrude from the bottom edge of the package body 202, but the present invention is not limited thereto. For example, in other embodiments not shown in the present invention, the chip 200 may also adopt other types of packaging structures, such as: a ball grid array (BGA) packaging structure, in which the contact 201 is a solder ball; or a pin grid array (PGA) packaging structure, in which the contact 201 is a pin.

To facilitate understanding of this embodiment, the wafer measurement device 100 is described below, which includes a support frame 1, two supporting modules 2 respectively mounted at the two ends of the support frame 1, a lateral transfer mechanism 3 located on the inner side of the support frame 1, an optical module 4 mounted on the lateral transfer mechanism 3 and located on the inner side of the support frame 1, and a processing module 5 (such as a processor or a computer) electrically coupled to the optical module 4.

It should be noted that, although the wafer measuring device 100 is described in this embodiment as including the above-mentioned components, the present invention is not limited thereto. For example, in other embodiments not shown in the present invention, the wafer measuring device 100 may include at least one supporting module 2, and the supporting frame 1 is correspondingly adjusted to an L shape; or, the wafer measuring device 100 may omit the lateral transfer mechanism 3 so that the optical module 4 does not move; or, the wafer measuring device 100 may omit the supporting frame 1 and the lateral transfer mechanism 3, and at least one supporting module 2 and the optical module 4 are installed on other components.

In addition, since the two supporting modules 2 in this embodiment adopt substantially the same structure, and the two supporting modules 2 are also installed substantially symmetrically (e.g., the two supporting modules 2 are arranged facing each other), for the convenience of explaining this embodiment, the structure of a single supporting module 2 will be described below, but the present invention is not limited thereto. For example, in other embodiments not shown in the present invention, the chip measurement device 100 may also include a plurality of supporting modules 2 with slightly different structures.

The support module 2 in this embodiment includes a plate-shaped support platform 21 (also regarded as a support plate), a longitudinal transfer mechanism 22 connected to the support platform 21 and mounted on the support frame 1, an optical glass 23 mounted on the support platform 21, and a chip fixture 24 detachably mounted on the support platform 21, but the present invention is not limited thereto. For example, in other embodiments not shown in the present invention, the longitudinal transfer mechanism 22 and/or the chip fixture 24 of the support module 2 can be omitted or replaced by other components; or, the support module 2 can also adopt a non-plate-shaped support platform 21.

In this embodiment, the support platform 21 includes a first surface 211 and a second surface 212 located on opposite sides, and the support platform 21 is formed with a through hole 213 penetrating from the first surface 211 to the second surface 212. The through hole 213 of the support platform 21 is elongated in this embodiment and defines a length direction D, and the through hole 213 is preferably formed by recessing from one end of the support platform 21 away from the longitudinal transfer mechanism 22. More specifically, the support platform 21 is formed by recessing the first surface 211 to form a ring-shaped receiving groove 214 surrounding the through hole 213 in this embodiment.

Furthermore, the support platform 21 is installed on the longitudinal transfer mechanism 22, and the longitudinal transfer mechanism 22 can move the support platform 21 along a translation direction H perpendicular to the longitudinal direction D (and the hammer direction V). The support platform 21 is installed on the longitudinal transfer mechanism 22 at a portion where the through hole 213 is not formed, so that the portion of the support platform 21 where the through hole 213 is formed is suspended.

It should be noted that, since the support platform 21 is non-translucent in this embodiment, the support platform 21 is formed with the through hole 213 to facilitate the combination with other components to jointly realize the measurement of the chip 200, but the present invention is not limited to this. For example, in other embodiments not shown in the present invention, the support platform 21 may also be translucent and not have the through hole 213.

The optical glass 23 is a transparent flat plate structure in this embodiment, and the optical glass 23 has a supporting plane 231 and a light incident surface 232 located on opposite sides. The light incident surface 232 is also planar in this embodiment, and the shape of the light incident surface 232 is the same as the shape of the supporting plane 231, but the present invention is not limited thereto.

The position of the optical glass 23 corresponds to the through hole 213 (e.g., the optical glass 23 is disposed in the receiving groove 214 of the support platform 21), and the optical glass 23 preferably completely covers one side of the through hole 213 (e.g., the top side of the through hole 213 in FIG. 3), but the present invention is not limited thereto. For example, in other embodiments not shown in the present invention, the optical glass 23 may also only cover a portion of the through hole 213.

Furthermore, the supporting plane 231 can be used to provide multiple contacts 201 of at least one chip 200, so that the end surface 2011 of each contact 201 faces the supporting plane 231. In this embodiment, the supporting plane 231 of the optical glass 23 is perpendicular to the hammer direction V, and the optical glass 23 is a long strip structure parallel to (or defines) the length direction D, so that the supporting plane 231 can provide multiple chips 200 for setting along the length direction D.

It should be further explained that, although the optical glass 23 is described as a flat plate in this embodiment, in other embodiments not shown in the present invention, the supporting plane 231 may only occupy a partial surface of the optical glass 23, and the area of the optical glass 23 outside the supporting plane 231 may be non-planar.

The chip fixture 24 is mounted on the first surface 211 of the carrier 21 so that the optical glass 23 is clamped between the carrier 21 and the chip fixture 24. The chip fixture 24 includes two movable plates 241, and the relative positions of the two movable plates 241 can be changed relative to the carrier 21 to form at least one holding groove 242 for accommodating at least one chip 200.

In this embodiment, the relative moving directions of the two movable sheets 241 are perpendicular to the length direction D and the hammer direction V, and the number of the holding grooves 242 formed by the two movable sheets 241 being assembled together is multiple, and their positions correspond to the supporting plane 231. In other words, the multiple chips 200 arranged on the supporting plane 231 along the length direction D can be clamped by the two movable sheets 241 and positioned in the multiple holding grooves 242 respectively.

The above is a structural description of a single carrier module 2. The following will introduce other structures of the chip measurement equipment 100 and the connection relationship between the two carrier modules 2. The optical module 4 is installed on the lateral transfer mechanism 3 and is arranged corresponding to the light incident surface 232 of the optical glass 23, and the lateral transfer mechanism 3 can make the optical module 4 face the light incident surface 232 of the optical glass 23 and move along the longitudinal direction D.

That is, the optical module 4 can selectively move to the bottom of any chip 200 carried by any of the carrying modules 2 through the lateral transfer mechanism 3. Accordingly, the optical module 4 can measure the multiple contacts 201 of at least one chip 200 disposed on the carrying plane 231 through the through hole 213.

In this embodiment, the optical module 4 includes a positioning bracket 41 mounted on the lateral transfer mechanism 3, and a light projector 42 and a plurality of light receivers 43 mounted and fixed on the positioning bracket 41. The light projector 42 and the plurality of light receivers 43 are arranged in a row along the length direction D. That is, the arrangement direction of the plurality of light receivers 43 is parallel to the length direction D of the optical glass 23, and the relative movement direction of the two movable sheets 241 is perpendicular to the arrangement direction of the plurality of light receivers 43.

The above content is an explanation of the pre-step S110. The following is an introduction to other steps of the chip bonding estimation method S100. The imaging step S120: As shown in Figures 1, 6 and 7 (please refer to Figures 2 and 3), the optical module 4 is used to stereoscopically image the end faces 2011 of the multiple contacts 201 of the chip 200, and transmit the signal to the processing module 5 to obtain the three-dimensional surface S corresponding to the multiple end faces 2011.

Furthermore, the light projector 42 (in the imaging step S120) emits a structured light L based on interference fringes toward the multiple contacts 201 of at least one chip 200, and the multiple light receivers 43 (in the imaging step S120) receive the structured light L reflected by at least one chip 200 to obtain the signal; the processing module 5 presents the three-dimensional surface S (such as FIG. 8 ) in the form of point cloud data, which can be displayed on a screen (not shown), but the present invention is not limited to the above. That is to say, in other embodiments not shown in the present invention, the imaging step S120 can obtain the three-dimensional surface S through various imaging methods according to actual needs.

The estimation step S130: As shown in FIG. 1, FIG. 8 and FIG. 9 (please refer to FIG. 2 and FIG. 3), the processing module 5 obtains a cross-section S1 at an estimated depth according to the three-dimensional plane S, and its area is defined as an estimated welding area. In this embodiment, the estimated depth refers to the depth at which the contact 201 of the chip 200 may be connected to the corresponding solder 400 (such as FIG. 5).

In addition, the definition of the preset area can also be adjusted according to design requirements; for example, the preset area can be the total surface area corresponding to the plurality of end faces 2011 obtained by the processing module 5 through the three-dimensional surface S.

The judgment step S140: As shown in Figures 1 to 5, the processing module 5 divides the estimated welding area by the preset area to obtain an estimated bonding value, which is used to preliminarily evaluate whether the chip 200 is qualified. In this embodiment, the estimated bonding value refers to: the estimated ratio of the multiple contacts 201 of the chip 200 connected to the multiple solders 400 after the chip 200 is soldered to the circuit board 300.

Furthermore, the qualified standard of the estimated value of the joint can be adjusted according to actual needs; for example, for automotive products, the qualified standard of the estimated value of the joint is preferably not less than 90%, while for general products, the qualified standard of the estimated value of the joint can be not less than 70%.

Accordingly, the chip bonding estimation method S100 in this embodiment can estimate the bonding estimation value of the chip 200 by obtaining the three-dimensional structure S corresponding to the multiple end faces 2011 before the chip 200 is soldered to the multiple solders 400 of the circuit board 300, and then evaluate whether the chip 200 continues the subsequent soldering operation, so as to improve the product yield after the soldering operation is performed.

Furthermore, the bonding estimation value of the chip 200 obtained by the chip bonding estimation method S100 in this embodiment is not constrained by the coplanarity standard of the Solid State Technology Association and can effectively evaluate the welding effect of all chip types.

In addition, the chip measurement device 100 in this embodiment can be used to obtain the three-dimensional surface S corresponding to the multiple end faces 2011 through the mutual matching of multiple components (such as: the corresponding configuration between the light projector 42, the multiple light receivers 43, and the optical glass 23), so as to make the chip measurement device 100 suitable for various types of chip measurement. Among them, the chip measurement device 100 in this embodiment can also be further provided with the chip fixture 24 so that the chip 200 can be measured in a stable state, so as to effectively improve the accuracy of the three-dimensional surface S.

It should be further explained that the chip bonding estimation method S100 of this embodiment can be further implemented as follows in the estimation step S130: the processing module 5 obtains the depression P with the largest depth in each of the contacts 201 according to the three-dimensional structure S (such as: Figure 9). Furthermore, the judgment step S140 is further implemented as follows: the processing module 5 defines the distance between the depression P with the largest depth in multiple contacts 201 and the cross-section S1 located at the estimated depth as a coplanarity estimation value.

In addition, the estimated bonding value in this embodiment can be obtained by first obtaining the estimated coplanarity value and then calculating and inferring, but it is not limited to this. For example, the estimated bonding value can also be obtained without the estimated coplanarity value; or in other words, the method of obtaining the estimated bonding value can be adjusted according to the design requirements.

Accordingly, the chip bonding estimation method S100 can also provide the coplanarity estimation value that is more familiar to those who are accustomed to using the coplanarity specification of the Solid State Technology Association. Furthermore, the chip bonding estimation method S100 can also reflect the defects that may be generated in the production process of each contact 201 of the chip 200 based on the obtained recess P of each contact 201, thereby helping to improve the production yield of the chip 200.

The above disclosed contents are only the preferred feasible embodiments of the present invention, and do not limit the patent scope of the present invention. Therefore, all equivalent technical changes made by using the contents of the specification and drawings of the present invention are included in the patent scope of the present invention.

100: Chip measurement equipment

1: Support frame

2: Carrier module

21: Carrier platform

211: First surface

212: Second surface

213:Piercing

214: Storage tank

22: Longitudinal transfer mechanism

23: Optical glass

231: Loading plane

232: Light-entering surface

24: Wafer fixture

241:Activity video

242: Retaining groove

3: Horizontal transfer mechanism

4: Optical module

41: Positioning bracket

42: Light projector

43: Optical receiver

5: Processing module

200: Chip

201:Touch point

2011: End face

202:Package

300: Circuit board

400: Solder

V: hammer direction

D: Length direction

H: Translation direction

L:Structured light

S: three-dimensional structure

S1: Cross section

P: Depression

S100: Wafer bonding estimation method

S110: Preliminary steps

S120: Imaging step

S130: Estimation step

S140: Judgment step

Figure 1 is a schematic diagram of the steps of the chip bonding estimation method of an embodiment of the present invention.

Figure 2 is a three-dimensional schematic diagram of the pre-step in Figure 1.

Figure 3 is a partial exploded schematic diagram of Figure 2.

Figure 4 is a schematic diagram (I) illustrating the bonding value of an embodiment of the present invention.

Figure 5 is a schematic diagram (II) illustrating the bonding value of an embodiment of the present invention.

Figure 6 is a schematic diagram of the imaging step in Figure 1.

Figure 7 is an enlarged schematic diagram of area VII in Figure 6.

Figure 8 is a schematic diagram of the estimation step in Figure 1.

Figure 9 is a partial schematic diagram of Figure 8.

100: Chip measurement equipment

1: Support frame

2: Carrier module

21: Carrier platform

22: Longitudinal transfer mechanism

23: Optical glass

24: Wafer fixture

241:Activity video

242: Retaining groove

3: Horizontal transfer mechanism

4: Optical module

41: Positioning bracket

42: Light projector

43: Optical receiver

5: Processing module

200: Chip

V: hammer direction

D: Length direction

L:Structured light

S120: Imaging step

Claims (10)

A chip bonding prediction method comprises: a pre-step: providing a chip having a plurality of contacts; wherein, when the end faces of the plurality of contacts are orthographically projected onto a plane, the sum of their areas is defined as a preset area; wherein, the plurality of contacts of the chip can be used to be respectively disposed on a plurality of solders located on a circuit board, so that the plurality of end faces have a bonding area contacting the plurality of solders; wherein the chip bonding prediction method defines a bonding value, which is the bonding area divided by the preset area. an imaging step: using an optical module to stereoscopically image the end faces of the plurality of contact points of the chip and transmit signals to a processing module to obtain a three-dimensional plane corresponding to the plurality of end faces; an estimation step: using the processing module to obtain a cross section at an estimated depth based on the three-dimensional plane, and its area is defined as an estimated welding area; and a judgment step: using the processing module to divide the estimated welding area by the preset area to obtain an estimated bonding value. The chip bonding prediction method as described in claim 1, wherein the processing module presents the three-dimensional surface in the form of point cloud data. The chip bonding estimation method as described in claim 2, wherein the optical module comprises: a light projector, which emits a structured light based on interference fringes toward the plurality of contact points of the chip in the imaging step; and a plurality of light receivers, which receive the structured light reflected by the chip in the imaging step to obtain the signal. The chip bonding estimation method as described in claim 1, wherein the packaging structure of the chip is further defined as a land grid array (LGA) package; wherein the estimation step is further implemented by the processing module obtaining the depression with the largest depth in each of the contacts according to the three-dimensional structure; the determination step is further implemented by the processing module defining the distance between the depression with the largest depth in the plurality of contacts and the cross section located at the estimated depth as a coplanarity estimation value. The chip bonding estimation method as described in claim 4, wherein the chip has a package body covering a plurality of the contacts, and the end faces of the plurality of the contacts are exposed from the package body but do not protrude from the bottom edge of the package body. The chip bonding estimation method as described in claim 1, wherein the chip bonding estimation method further comprises in the pre-step: providing a chip measurement device, which comprises the optical module, the processing module, and at least one supporting module; wherein at least one of the supporting modules comprises: a supporting platform; and an optical glass mounted on the supporting platform, and the optical glass has a supporting plane and a light incident surface located on opposite sides; wherein the supporting plane can be used for arranging the plurality of contacts of the chip so that the end surface of each contact faces the supporting plane; wherein the optical module is arranged corresponding to the light incident surface of the optical glass. The chip bonding estimation method as described in claim 6, wherein at least one of the supporting modules includes a chip fixture detachably mounted on the supporting platform, which includes two movable plates; wherein the relative positions of the two movable plates can be changed relative to the supporting platform to form a holding groove for accommodating the chip. The chip bonding estimation method as described in claim 6, wherein the optical glass defines a length direction, and the supporting plane can accommodate multiple chips along the length direction. A chip bonding estimation method includes: a pre-step: providing a chip having a plurality of contacts, wherein when the end faces of the plurality of contacts are orthographically projected onto a plane, the sum of their areas is defined as a preset area; an imaging step: using an optical module to stereoscopically image the end faces of the plurality of contacts of the chip, and transmitting signals to a processing module to obtain a three-dimensional plane having a shape corresponding to the plurality of end faces; an estimation step: using the processing module to obtain a cross-section at an estimated depth according to the three-dimensional plane, and the area thereof is defined as an estimated bonding area; and a judgment step: using the processing module to divide the estimated bonding area by the preset area to obtain a bonding estimation value. The chip bonding prediction method as described in claim 9, wherein the processing module presents the three-dimensional structure surface in the form of point cloud data; wherein the optical module includes: a light projector, which emits a structured light based on interference fringes toward the multiple contact points of the chip in the imaging step; and multiple light receivers, which receive the structured light reflected by the chip in the imaging step to obtain the signal.