TWI860853B - Semiconductor device - Google Patents

Abstract

Provided is a semiconductor device suitable for manufacturing a three-dimensional (3D) NAND flash memory with high capacity and high performance. The semiconductor device includes a substrate, a first device structure layer, an interconnect structure layer, a second device structure layer, a pattern structure, a first seal ring and a second seal ring. The first device structure layer is disposed on the substrate. The interconnect structure layer is disposed on the first device structure layer, and is electrically connected to the first device structure layer. The interconnect structure layer includes a plurality of first pads located at a surface of the interconnect structure layer. The second device structure layer is disposed on the interconnect structure layer. The second device structure layer includes a plurality of second pads located at a surface of the second device structure layer. The pattern structure is disposed at a first interface between the interconnect structure layer and the second device structure layer. The first seal ring is disposed at the surface of the interconnect structure layer and surrounds the pattern structure. The second seal ring is disposed at the surface of the second device structure layer and surrounds the pattern structure. Each of the first pads is connected to a corresponding second pad, and the first seal ring is connected to the second seal ring.

Description

Semiconductor components

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a hybrid bonding structure.

In a general hybrid bonding process, two chips are bonded together with their active surfaces facing each other to form a bonding structure, wherein a dielectric layer of one chip is bonded to a dielectric layer of another chip, and a pad of one chip is bonded to a pad of another chip.

However, in addition to the pads, there are usually larger components, such as various mark structures, on the surface of the chip. After the two chips are bonded, when the bonding structure is subjected to high temperature or external force, the film peeling is likely to occur around the larger components at the bonding interface, and the film peeling may even spread to the entire chip, causing damage to the chip.

The present invention provides a semiconductor device having a hybrid bonding structure, wherein a pattern structure having a large width at a bonding interface is surrounded by a seal ring.

The semiconductor element of the present invention includes a substrate, a first element structure layer, an internal connection structure layer, a second element structure layer, a pattern structure, a first guard ring and a second guard ring. The first element structure layer is arranged on the substrate. The internal connection structure layer is arranged on the first element structure layer and is electrically connected to the first element structure layer. The internal connection structure layer includes a plurality of first pads located at the surface of the internal connection structure layer. The second element structure layer is arranged on the internal connection structure layer. The second element structure layer includes a plurality of second pads located at the surface of the second element structure layer. The pattern structure is arranged at a first interface between the internal connection structure layer and the second element structure layer. The first protection ring is disposed on the surface of the inner connection structure layer and surrounds the pattern structure. The second protection ring is disposed on the surface of the second device structure layer and surrounds the pattern structure. Each of the first pads is connected to the corresponding second pad, and the first protection ring is connected to the second protection ring.

In an embodiment of the semiconductor device of the present invention, the width of the pattern structure is greater than the width of the first pad and greater than the width of the second pad.

In an embodiment of the semiconductor device of the present invention, the width of the first guard ring is greater than or equal to half of the width of the first pad, and less than or equal to 3 times the width of the first pad.

In an embodiment of the semiconductor device of the present invention, the width of the second guard ring is greater than or equal to half of the width of the second pad, and less than or equal to 3 times the width of the second pad.

In an embodiment of the semiconductor device of the present invention, the width of the pattern structure is greater than or equal to 4 times the width of the first pad, and greater than or equal to 4 times the width of the second pad.

In an embodiment of the semiconductor device of the present invention, the pattern structure is not electrically connected to the inner connection structure layer, and is not electrically connected to the second device structure layer.

In an embodiment of the semiconductor device of the present invention, the pattern structure includes a marking mark or an alignment mark.

In an embodiment of the semiconductor device of the present invention, the pattern structure is located in the interconnect structure layer.

In an embodiment of the semiconductor device of the present invention, the distance between the first guard ring and the pattern structure is greater than or equal to twice the width of the first pad.

In an embodiment of the semiconductor device of the present invention, the pattern structure is located in the second device structure layer.

In an embodiment of the semiconductor device of the present invention, the distance between the second guard ring and the pattern structure is greater than or equal to twice the width of the second pad.

In an embodiment of the semiconductor device of the present invention, the plurality of first pads include at least one first electrical connection pad and at least one first dummy pad, the plurality of second pads include at least one second electrical connection pad and at least one second dummy pad, each of the first electrical connection pads is connected to the corresponding second electrical connection pad, and each of the first dummy pads is connected to the corresponding second dummy pad.

In an embodiment of the semiconductor device of the present invention, the first electrical connection pad is electrically connected to the first device structure layer.

In an embodiment of the semiconductor device of the present invention, the second electrical connection pad is electrically connected to the second device structure layer.

In an embodiment of the semiconductor device of the present invention, there is no first pad between the first guard ring and the pattern structure, and there is no second pad between the second guard ring and the pattern structure.

In an embodiment of the semiconductor device of the present invention, the width of the first guard ring is the same as the width of the second guard ring.

In an embodiment of the semiconductor device of the present invention, the width of the first guard ring is different from the width of the second guard ring.

In an embodiment of the semiconductor device of the present invention, a second interface is provided between the first pad and the second pad.

In an embodiment of the semiconductor device of the present invention, the second device structure layer includes a memory structure layer.

In an embodiment of the semiconductor device of the present invention, the memory structure layer includes a three-dimensional flash memory structure.

Based on the above, in the semiconductor device of the present invention, the first protective ring and the second protective ring surround the pattern structure. Therefore, when the semiconductor device is subjected to high temperature or external force in the subsequent manufacturing process, the first protective ring and the second protective ring can effectively limit the area where film separation occurs.

The following is a detailed description of the embodiments and accompanying drawings, but the embodiments provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustration purposes only and are not drawn in their original size. For ease of understanding, the same components will be indicated by the same symbols in the following description.

The terms "include", "including", "have", etc. used in this document are open terms, which means "including but not limited to".

When using the terms "first", "second", etc. to describe an element, it is only used to distinguish these elements from each other, and does not limit the order or importance of these elements. Therefore, in some cases, the first element can also be called the second element, and the second element can also be called the first element, and this does not deviate from the scope of the present invention.

In addition, the directional terms mentioned herein, such as "upper", "lower", etc., are only used to refer to the directions of the drawings and are not used to limit the present invention. Therefore, it should be understood that "upper" can be used interchangeably with "lower", and when an element such as a layer or film is placed "on" another element, the element can be placed directly on the other element, or there can be an intermediate element. On the other hand, when an element is said to be placed "directly" on another element, there is no intermediate element between the two.

In addition, in this article, the range expressed by "a numerical value to another numerical value" is a summary expression method to avoid listing all numerical values in the range one by one in the specification. Therefore, the description of a specific numerical range covers any numerical value in the numerical range, and covers a smaller numerical range defined by any numerical value in the numerical range.

FIG1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention.

1, the semiconductor device 10 of the present embodiment includes a first substrate 100, a second substrate 102, a first device structure layer 104, an internal connection structure layer 106, a pattern structure 110, a first protection ring 112, a second device structure layer 114, and a second protection ring 118. Depending on the types of the first device structure layer 104 and the second device structure layer 114, the semiconductor device 10 can be applied to various semiconductor devices, and the present invention is not limited thereto. For example, the semiconductor device 10 can be applied to a three-dimensional NAND flash memory with high capacity and high performance. The semiconductor device 10 applied to a three-dimensional flash memory will be described below as an example.

In this embodiment, the second substrate 102 is disposed on the first substrate 100. In this embodiment, the active surface of the first substrate 100 and the active surface of the second substrate 102 are opposite to each other. The first substrate 100 and the second substrate 102 can each be a silicon substrate or a silicon on insulator (SOI) substrate.

The first device structure layer 104 is disposed on the active surface of the first substrate 100 and is located between the first substrate 100 and the second substrate 102. In the present embodiment, the first device structure layer 104 may include a transistor, a device isolation structure, a contact window, a dielectric layer covering the above-mentioned devices, etc., but the present invention is not limited thereto. In FIG. 1 , the first device structure layer 104 is simply illustrated as an example. The detailed structure of the first device structure layer 104 is well known to those skilled in the art and will not be further described herein.

The interconnect structure layer 106 is disposed on the first device structure layer 104 and is located between the first device structure layer 104 and the second substrate 102. The interconnect structure layer 106 is electrically connected to the first device structure layer 104. In this embodiment, the interconnect structure layer 106 may include multiple circuit layers, multiple vias, a dielectric layer covering the above-mentioned devices, etc. In the interconnect structure layer 106, the bottommost circuit layer may be connected to the contact window in the first device structure layer 104, and the via may connect two adjacent circuit layers. In FIG. 1, the interconnect structure layer 106 is simply shown as an example. The detailed structure of the interconnect structure layer 106 is well known to those skilled in the art, and thus will not be described further.

In addition, the inner connection structure layer 106 includes a plurality of first pads 108. The first pads 108 are disposed on the surface of the inner connection structure layer 106. Specifically, in the present embodiment, the first pads 108 are embedded in the inner connection structure layer 106 and include first electrical connection pads 108a and first dummy pads 108b. In FIG. 1 , the number of the first electrical connection pads 108a and the first dummy pads 108b is only used as an example, and the present invention is not limited thereto. The first electrical connection pads 108a can be electrically connected to the topmost wiring layer in the inner connection structure layer 106 to provide the function of electrical signal transmission and the bonding function. The first dummy pad 108b is not electrically connected to the device in the interconnect structure layer 106 and only provides a bonding function.

The pattern structure 110 and the first guard ring 112 are disposed on the surface of the inner connection structure layer 106. Specifically, in this embodiment, the pattern structure 110 and the first guard ring 112 are buried in the inner connection structure layer 106, and the first guard ring 112 surrounds the pattern structure 110. The pattern structure 110 and the first guard ring 112 are not electrically connected to the inner connection structure layer 106. The pattern structure 110 can be a marking mark, an alignment mark, or any other mark, and the present invention is not limited thereto.

FIG. 2A is a schematic top view of the inner connection structure layer 106. As shown in FIG. 2A, in the present embodiment, the first pads 108 are disposed on the surface of the inner connection structure layer 106 and are arranged in an array, but the present invention is not limited thereto. In addition, the pattern structure 110 and the first guard ring 112 are located outside the array area. The first guard ring 112 surrounds the pattern structure 110 and is not connected to the pattern structure 110. In the present embodiment, the distance between the first guard ring 112 and the pattern structure 110 is, for example, greater than or equal to twice the width of the first pad 108. There is no first pad 108 between the first guard ring 112 and the pattern structure 110.

The pattern structure 110 has a larger size than the first pad 108. Since the pattern structure 110 has a larger size, a depression is generated at the surface of the pattern structure 110 during the process of forming the pattern structure 110. In the present embodiment, the width of the pattern structure 110 is greater than the width of the first pad 108. For example, the width of the pattern structure 110 may be greater than or equal to 4 times the width of the first pad 108. In addition, the width of the first protection ring 112 is greater than or equal to half the width of the first pad 108 and less than or equal to 3 times the width of the first pad 108. In FIG. 2A , the shapes of the first pad 108 , the pattern structure 110 , and the first protection ring 112 are merely examples, and the present invention is not limited thereto.

The first substrate 100, the first device structure layer 104, the interconnect structure layer 106, the first pad 108, the pattern structure 110 and the first protection ring 112 may constitute the first chip CP1 in this embodiment. In other words, FIG2A may be viewed as a top view of the first chip CP1.

Please continue to refer to FIG. 1 , the second device structure layer 114 is disposed on the active surface of the second substrate 102 and is located between the internal connection structure layer 106 and the second substrate 102. In this embodiment, when the semiconductor device 10 is applied to a three-dimensional NAND flash memory, the second device structure layer 114 is a memory structure layer, which may at least include a stacking structure composed of multiple insulating layers and multiple conductive layers, a vertical channel (VC) structure penetrating the stacking structure, a contact window, a dielectric layer covering the above-mentioned device, etc., but the present invention is not limited thereto. In FIG. 1 , the second device structure layer 114 is simply illustrated as an example. The detailed structure of the second device structure layer 114 is well known to those skilled in the art and will not be further described herein.

In other embodiments, when the semiconductor device 10 is applied to other semiconductor devices, the second device structure layer 114 may have a desired structure. For example, the second device structure layer may include a structure similar to the first device structure layer 104 and the interconnect structure layer 106, but the present invention is not limited thereto.

In addition, the second device structure layer 114 includes a plurality of second pads 116. The second pads 116 are disposed on the surface of the second device structure layer 114. Specifically, in the present embodiment, the second pads 116 are embedded in the second device structure layer 114 and include second electrical connection pads 116a and second dummy pads 116b. The second electrical connection pads 116a can be electrically connected to the contact window or the conductive layer in the second device structure layer 114 to provide the function of electrical signal transmission and the bonding function. The second dummy pads 116b are not electrically connected to the device in the second device structure layer 114 and only provide the bonding function.

The position and quantity of the second electrical connection pad 116a correspond to the position and quantity of the first electrical connection pad 108a, and the position and quantity of the second dummy pad 116b correspond to the position and quantity of the first dummy pad 108b. The second electrical connection pad 116a is connected to the corresponding first electrical connection pad 108a with an interface therebetween, and the second dummy pad 116b is connected to the corresponding second dummy pad 108b with an interface therebetween. In this embodiment, the second electrical connection pad 116a is aligned with the corresponding first electrical connection pad 108a, and the second dummy pad 116b is aligned with the corresponding second dummy pad 108b, but the present invention is not limited thereto. In other embodiments, there may be an alignment offset between the second electrical connection pad 116a and the corresponding first electrical connection pad 108a, and there may be an alignment offset between the second dummy pad 116b and the corresponding second dummy pad 108b.

The second protection ring 118 is disposed at the surface of the second device structure layer 114. Specifically, in the present embodiment, the second protection ring 118 is embedded in the second device structure layer 114. The second protection ring 118 is connected to the first protection ring 112, and an interface is provided between the two. In addition, the position of the second protection ring 118 corresponds to the position of the first protection ring 112 to surround the pattern structure 110. The second protection ring 118 is not electrically connected to the second device structure layer 114. In the present embodiment, the second protection ring 118 is aligned with the first protection ring 112, but the present invention is not limited thereto. In other embodiments, there may be an alignment offset between the second protection ring 118 and the first protection ring 112.

FIG2B is a schematic top view of the interconnect structure layer 106. As shown in FIG2B, in this embodiment, the second pads 116 are disposed on the surface of the second device structure layer 114 and are arranged in an array corresponding to the first pads 116. In addition, the second guard ring 112 is located outside the array region corresponding to the first guard ring 112. The region surrounded by the second guard ring 118 does not have the second pad 116.

In this embodiment, the width of the second protective ring 112 is the same as the width of the first protective ring 112, but the present invention is not limited thereto. In other embodiments, the width of the second protective ring 112 may be different from the width of the first protective ring 112. In addition, the width of the second protective ring 112 is greater than or equal to half the width of the second pad 116, and less than or equal to 3 times the width of the second pad 116. In FIG. 2B, the shapes of the second pad 116 and the second protective ring 118 are only examples, and the present invention is not limited thereto. The shapes of the second pad 116 and the second protective ring 118 may be the same as or different from the shapes of the first pad 108 and the first protective ring 112, and the present invention is not limited thereto.

The second substrate 102, the second device structure layer 114, the second pad 116 and the second protective ring 118 may constitute the second chip CP2 in this embodiment. In other words, FIG2B may be viewed as a top view of the second chip CP2.

As can be seen from the above, the semiconductor element 10 of this embodiment includes a hybrid bonding structure formed by bonding the first chip CP1 and the second chip CP2 by hybrid bonding, and therefore there is an interface between the internal connection structure layer 106 of the first chip CP1 and the second element structure layer 114 of the second chip CP2, and the pattern structure 110 is located at the interface. In this embodiment, the active surface of the first substrate 100 in the first chip CP1 and the active surface of the second substrate 102 in the second chip CP2 are opposite to each other, so the process of bonding the chips in this embodiment is a face-to-face bonding process.

After the above-mentioned bonding process, the second substrate 102 in the second chip CP2 can be processed. In one embodiment, the second substrate 102 can be thinned from the back side of the second substrate 102 by grinding, polishing or etching to form the semiconductor device 10 as shown in FIG. 1. In another embodiment, the second substrate 102 in the second chip CP2 can be completely removed. That is, in this case, in the semiconductor device 10, the second chip CP2 bonded to the inner connection structure layer 106 in the first chip CP1 will only include the second device structure layer 114.

In the semiconductor device 10, the first guard ring 112 surrounds the pattern structure 110, and the second guard ring 118 also surrounds the pattern structure 110. Therefore, when the semiconductor device 10 is subjected to high temperature or external force in a subsequent manufacturing process, since the pattern structure 110 is surrounded by the first guard ring 112 and the second guard ring 118, even if film separation occurs around the air cavity AG, the film separation phenomenon is limited to the area surrounded by the first guard ring 112 and the area surrounded by the second guard ring 118, and will not affect the area outside the first guard ring 112 and the area outside the second guard ring 118. That is to say, in this embodiment, the influence of the air pocket AG on the device can be greatly reduced or even avoided by providing the first protection ring 112 and the second protection ring 118.

In particular, in the present embodiment, the width of the first guard ring 112 is greater than or equal to half of the width of the first pad 108 and less than or equal to three times the width of the first pad 108, and the width of the second guard ring 118 is greater than or equal to half of the width of the second pad 116 and less than or equal to three times the width of the second pad 116. Therefore, the first guard ring 112 and the second guard ring 118 can effectively reduce or even avoid the influence of air pockets AG on the components.

When the width of the first guard ring 112 is less than half the width of the first pad 108, the first guard ring 112 cannot be effectively connected to the second guard ring 118, and the phenomenon of film separation cannot be effectively limited to the area surrounded by the first guard ring 112. When the width of the second guard ring 118 is less than half the width of the second pad 116, the second guard ring 118 cannot be effectively connected to the first guard ring 112, and the phenomenon of film separation cannot be effectively limited to the area surrounded by the second guard ring 118.

In addition, when the width of the first guard ring 112 is greater than 3 times the width of the first pad 108, the first guard ring 112 may have a depression at the surface like the pattern structure 110, resulting in air pockets in the semiconductor device 10. When the width of the second guard ring 118 is greater than 3 times the width of the second pad 116, the second guard ring 118 may have a depression at the surface like the pattern structure 110, resulting in air pockets in the semiconductor device 10.

Fig. 3 is a cross-sectional schematic diagram of a semiconductor device of the second embodiment of the present invention. Fig. 4A is a top view schematic diagram of the interconnect structure layer in Fig. 3. Fig. 4B is a top view schematic diagram of the second device structure layer in Fig. 3. In this embodiment, the same components as those in the first embodiment are represented by the same reference symbols and will not be described again.

Please refer to Figures 3, 4A and 4B at the same time. The difference between the semiconductor device 20 of this embodiment and the semiconductor device 10 of the first embodiment is that: in the semiconductor device 20, the pattern structure 110 is located at the interface between the internal connection structure layer 106 of the first chip CP1 and the second device structure layer 114 of the second chip CP2, and is located on the surface of the second device structure layer 114.

Specifically, in this embodiment, the pattern structure 110 is embedded in the second device structure layer 114, and the second protection ring 118 surrounds the pattern structure 110. The pattern structure 110 is not electrically connected to the second device structure layer 114. The distance between the second protection ring 118 and the pattern structure 110 is, for example, greater than or equal to twice the width of the second pad 116. There is no second pad 116 between the second protection ring 118 and the pattern structure 110.

The pattern structure 110 has a larger size than the second pad 116. In the present embodiment, the width of the pattern structure 110 is greater than the width of the second pad 116. For example, the width of the pattern structure 110 may be greater than or equal to 4 times the width of the second pad 116. In addition, the width of the first protection ring 112 is greater than or equal to half the width of the first pad 108 and less than or equal to 3 times the width of the first pad 108, and the width of the second protection ring 118 is greater than or equal to half the width of the second pad 116 and less than or equal to 3 times the width of the second pad 116.

In this way, when the semiconductor device 20 is subjected to high temperature or external force in the subsequent manufacturing process, since the pattern structure 110 is surrounded by the first protective ring 112 and the second protective ring 118, even if film separation occurs around the air cavity AG, the film separation phenomenon will only be limited to the area surrounded by the first protective ring 112 and the area surrounded by the second protective ring 118, and will not affect the area outside the first protective ring 112 and the area outside the second protective ring 118.

Although the present invention has been disclosed as above by way of embodiments, they are not intended to limit the present invention. Any person having ordinary knowledge in the relevant technical field may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

10, 20: semiconductor element 100: first substrate 102: second substrate 104: first element structure layer 106: internal connection structure layer 108: first pad 108a: first electrical connection pad 108b: first dummy pad 110: pattern structure 112: first protective ring 114: second element structure layer 116: second pad 116a: second electrical connection pad 116b: second dummy pad 118: second protective ring AG: air cavity CP1: first chip CP2: second chip

FIG1 is a cross-sectional schematic diagram of a semiconductor element of the first embodiment of the present invention. FIG2A is a top view schematic diagram of the interconnect structure layer in FIG1. FIG2B is a top view schematic diagram of the second element structure layer in FIG1. FIG3 is a cross-sectional schematic diagram of a semiconductor element of the second embodiment of the present invention. FIG4A is a top view schematic diagram of the interconnect structure layer in FIG3. FIG4B is a top view schematic diagram of the second element structure layer in FIG3.

10: Semiconductor components

100: First base

102: Second base

104: First element structure layer

106: Internal connection structure layer

108: First pad

108a: first electrical connection pad

108b: First dummy pad

110: Pattern structure

112: First protection ring

114: Second component structure layer

116: Second pad

116a: second electrical connection pad

116b: Second dummy pad

118: Second protection ring

AG: air pocket

CP1: First chip

CP2: Second chip

Claims (20)

A semiconductor device comprises: a substrate; a first device structure layer disposed on the substrate; an internal connection structure layer disposed on the first device structure layer and electrically connected to the first device structure layer, wherein the internal connection structure layer comprises a plurality of first pads located on the surface of the internal connection structure layer; a second device structure layer disposed on the internal connection structure layer, wherein the second device structure layer comprises a plurality of second pads located on the surface of the second device structure layer; a pattern structure disposed on the first device structure layer; A first protection ring is disposed at a first interface between the inner connection structure layer and the second element structure layer; a first protection ring is disposed at a surface of the inner connection structure layer and surrounds the pattern structure; and a second protection ring is disposed at a surface of the second element structure layer and surrounds the pattern structure, wherein each of the first pads is connected to a corresponding second pad, and the first protection ring is connected to the second protection ring, and wherein the pattern structure does not contact the first protection ring and the second protection ring. A semiconductor device as described in claim 1, wherein the width of the pattern structure is greater than the width of the first pad and greater than the width of the second pad. A semiconductor device as described in claim 1, wherein the width of the first guard ring is greater than or equal to half the width of the first pad, and less than or equal to 3 times the width of the first pad. A semiconductor device as described in claim 1, wherein the width of the second guard ring is greater than or equal to half the width of the second pad, and less than or equal to 3 times the width of the second pad. A semiconductor device as described in claim 1, wherein the width of the pattern structure is greater than or equal to 4 times the width of the first pad, and greater than or equal to 4 times the width of the second pad. A semiconductor device as described in claim 1, wherein the pattern structure is not electrically connected to the internal connection structure layer and is not electrically connected to the second device structure layer. A semiconductor device as described in claim 6, wherein the pattern structure includes a marking mark or an alignment mark. A semiconductor device as described in claim 1, wherein the pattern structure is located in the interconnect structure layer. A semiconductor device as described in claim 8, wherein the distance between the first guard ring and the pattern structure is greater than or equal to twice the width of the first pad. A semiconductor device as described in claim 1, wherein the pattern structure is located in the second device structure layer. A semiconductor device as described in claim 10, wherein the distance between the second guard ring and the pattern structure is greater than or equal to twice the width of the second pad. The semiconductor device as described in claim 1, wherein the plurality of first pads include at least one first electrical connection pad and at least one first dummy pad, the plurality of second pads include at least one second electrical connection pad and at least one second dummy pad, each of the first electrical connection pads is connected to the corresponding second electrical connection pad, and each of the first dummy pads is connected to the corresponding second dummy pad. A semiconductor device as described in claim 12, wherein the first electrical connection pad is electrically connected to the first device structure layer. A semiconductor device as described in claim 12, wherein the second electrical connection pad is electrically connected to the second device structure layer. A semiconductor device as described in claim 1, wherein the first pad is not provided between the first guard ring and the pattern structure, and the second pad is not provided between the second guard ring and the pattern structure. A semiconductor element as described in claim 1, wherein the width of the first guard ring is the same as the width of the second guard ring. A semiconductor element as described in claim 1, wherein the width of the first guard ring is different from the width of the second guard ring. A semiconductor element as described in claim 1, wherein there is a second interface between the first pad and the second pad. A semiconductor device as described in claim 1, wherein the second device structure layer includes a memory structure layer. A semiconductor device as described in claim 19, wherein the memory structure layer includes a three-dimensional flash memory structure.