TWI860173B - Composite substrate and method thereof, and semiconductor laminate structure - Google Patents

Abstract

A method for manufacturing a composite substrate includes steps as follows: an initial substrate is provided; a van der Waals material layer is formed on the initial substrate; a plasma treatment process is applied on the van der Waals material layer, wherein the plasma treatment process includes bombarding the van der Waals material layer with an reactive gas plasma; and a nitride based epitaxial layer is formed on the van der Waals material layer.

Description

Composite substrate, manufacturing method thereof and semiconductor stacking structure

This disclosure relates to a composite substrate, its manufacturing method and semiconductor stacked structure, and in particular, can integrate low-voltage operation and fast computing two-dimensional material field effect transistors and high-voltage gallium nitride field-effect transistors. It also discloses a gas plasma process for reducing mismatch stress, its manufacturing method and a semiconductor stacked structure comprising the composite substrate.

Gallium nitride materials have the characteristics of wide bandgap, high critical electric field, high thermal conductivity, high saturated electron velocity, high frequency transmission capability and small component volume, which makes gallium nitride the main material of high-frequency transistor components or high-voltage transistor components, and is widely used in solid-state lighting, display, 5G communication and many other fields.

Due to the high cost of gallium nitride substrates, gallium nitride semiconductor components currently mainly use heterogeneous substrates with materials different from gallium nitride, such as sapphire, silicon carbide and silicon, and grow gallium nitride epitaxial layers on the substrates by epitaxial growth. However, in the process of growing gallium nitride epitaxial layers on heterogeneous substrates, there are large lattice mismatch and thermal mismatch problems between gallium nitride epitaxial layers and heterogeneous substrates, resulting in high-density dislocations and large mismatch stresses in gallium nitride epitaxial layers, which seriously affect the performance of gallium nitride semiconductor components.

One purpose of the present disclosure is to provide a composite substrate, a manufacturing method thereof, and a semiconductor stacking structure to solve the above-mentioned problems.

According to one embodiment of the present disclosure, a method for manufacturing a composite substrate is provided, comprising the following steps: providing an initial substrate; forming a Van der Waals material layer on the initial substrate; performing a plasma treatment process on the Van der Waals material layer, wherein the plasma treatment process comprises bombarding the Van der Waals material layer with a reactive gas plasma; and forming a nitride epitaxial layer on the Van der Waals material layer.

Another embodiment of the present disclosure is to provide a composite substrate, comprising a substrate, a Van der Waals material layer and a nitride epitaxial layer, wherein the Van der Waals material layer is disposed on the substrate, and the nitride epitaxial layer is disposed on the Van der Waals material layer, wherein the material of the substrate is different from that of the nitride epitaxial layer.

According to another embodiment of the present disclosure, a semiconductor stacked structure is provided, which includes the aforementioned composite substrate, a nucleation layer, a buffer layer, a high resistance layer, a barrier layer, an intrinsic gallium nitride layer, an electron supply layer, and a capping layer. The nucleation layer is disposed on the composite substrate, the buffer layer is disposed on the nucleation layer, the high resistance layer is disposed on the buffer layer, the barrier layer is disposed on the high resistance layer, the intrinsic gallium nitride layer is disposed on the barrier layer, the electron supply layer is disposed on the intrinsic gallium nitride layer, and the capping layer is disposed on the electron supply layer.

Compared with the prior art, the present invention forms a Van der Waals material layer on the initial substrate before forming the nitride epitaxial layer. After being treated with gas plasma, the Van der Waals material will have a compatible bonding energy with the nitride, which is conducive to the epitaxial growth of the nitride along the crystal axis direction of the initial substrate. In addition, the Van der Waals material layer is conducive to designing a logic circuit with a low conduction voltage and integrating it with a gallium nitride power device.

100: Manufacturing method of composite substrate

110,120,121,122,130,135,140,150,151,152,160,170,180: Steps

200,200a,410: Composite substrate

210: Initial base

220,412: Van der Waals material layer

225: Seed layer

230,413: Nitride epitaxial layer

240: Stress layer

250: Supporting base

260: Reactive gas plasma

400:Semiconductor stacked structure

411,411a: base

414: Bond strengthening layer

415a: Aluminum-carbon-nitrogen interface

420,420a: Nucleation layer

430: Buffer layer

440: High resistance layer

450: Barrier layer

451: The first barrier layer

452: Second barrier layer

453: The third barrier layer

460: Intrinsic gallium nitride layer

470: Electronic supply layer

480: Covering layer

500:HEMT

510: Gate electrode

520: Source electrode

530: Drain electrode

540:2DEG

Figure 1 is a flow chart of the steps of a method for manufacturing a composite substrate according to an embodiment of the present disclosure.

Figure 2 is a schematic diagram of the steps of the manufacturing method of the composite substrate in Figure 1.

Figure 3 is a flow chart of the steps of forming a two-dimensional graphene layer on a silicon carbide substrate according to an embodiment of the present disclosure.

Figure 4 is a flow chart of the steps of forming a stress layer on a nitride epitaxial layer according to an implementation method disclosed herein.

Figure 5 is a schematic cross-sectional view of a semiconductor stacked structure according to an embodiment of the present disclosure.

Figure 6 is a schematic cross-sectional view of a high electron mobility transistor (HEMT) according to an embodiment of the present disclosure.

Figure 7 is a local transmission electron microscope (TEM) result diagram of the high electron mobility transistor according to Example 1 of the present disclosure.

Figure 8 is an energy-dispersive X-ray spectroscopy (EDX) result diagram according to Example 1 of the present disclosure.

The above-mentioned and other technical contents, features and effects of this disclosure will be clearly presented in the detailed description of the preferred embodiments with reference to the drawings below. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front, back, bottom, top, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are for explanation rather than limitation of this disclosure. In addition, in the following embodiments, the same or similar components will be labeled with the same or similar numbers.

The description below of "the first feature is formed on or above the second feature" may refer to "the first feature is in direct contact with the second feature" or "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact.

Although the present disclosure uses the terms first, second, third, etc. to describe various elements, components, regions, layers, and/or sections, it should be understood that these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are only used to distinguish a certain element, component, region, layer, and/or section from another element, component, region, layer, and/or section, and they do not imply or represent any previous sequence of the element, nor do they represent the arrangement order of a certain element and another element, or the order of the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present disclosure, the first element, component, region, layer, or section discussed below can also be referred to as the second element, component, region, layer, or section.

The numerical ranges and parameters described below are all approximate values. Here, "approximately" generally refers to the actual value within plus or minus 10%, 5%, 1% or 0.5% of a specific value or range. It should be understood that all ranges, quantities, values, ratios and percentages used herein are modified by "approximately". Therefore, unless otherwise stated to the contrary, the numerical parameters disclosed in this specification and the attached patent application are approximate values and can be changed as needed.

Please refer to Figure 1 and Figure 2 at the same time. Figure 1 is a step flow chart of a method 100 for manufacturing a composite substrate according to an embodiment of the present disclosure, and Figure 2 is a step schematic diagram of the method 100 for manufacturing a composite substrate in Figure 1. The method 100 for manufacturing a composite substrate includes steps 110 to 140.

Step 110 is to provide an initial substrate 210. The initial substrate 210 can be used to form a Van der Waals material layer 220 thereon. The thickness of the initial substrate 210 can be 350 μm to 1500 μm. The initial substrate 210 can be a silicon substrate, a silicon-on-insulator (SOI) substrate, a sapphire substrate, an oxynitride substrate, a III-V substrate or a silicon carbide (SiC) substrate, and the crystal structure of the silicon carbide substrate can be a 3C, 4H or 6H crystal type.

Step 120 is to form a Van Der Waals material layer 220 on the initial substrate 210. The thickness of the Van Der Waals material layer 220 can be 1nm to 200nm.

The Van der Waals material layer 220 includes 2D graphene, hexagonal boron nitride (h-BN) or transition metal dichalcogenides. Transition metal dichalcogenides include but are not limited to molybdenum disulfide (MoS ₂ ), tungsten disulfide (WS ₂ ), molybdenum diselenide (MoSe ₂ ) or tungsten diselenide (WSe ₂ ).

The Van der Waals material layer 220 can be formed on the initial substrate 210 by, but not limited to, chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), ion implantation, plasma-assisted selective reaction (PSR), etc.

In the present disclosure, two-dimensional graphene (or simply graphene) refers to a planar sheet with a single-atom thickness, which is composed of ^sp2 -bonded carbon atoms, and the bonded carbon atoms are arranged in a honeycomb lattice. In the present disclosure, the term two-dimensional graphene also refers to a sheet with a layered structure of more than one layer but less than 10 layers. The number of layers can be 1 to 10 layers, or any number of layers therein. Generally speaking, when the surface area of two-dimensional graphene (whether a single-layer structure or a multi-layer structure) exceeds 0.005 square micrometers ( ^μm2 , preferably 0.006 to 0.038 square micrometers), the graphene exists in the form of nanosheets. Alternatively, when the surface area of graphene is less than 0.005 square micrometers, the two-dimensional graphene exists in the form of nanodots. Unless otherwise specified, the term graphene includes pure graphene and graphene with a small amount of graphene oxide.

Taking the Van der Waals material layer 220 as a two-dimensional graphene (2D graphene) and the initial substrate 210 as a silicon carbide substrate as an example, the method of forming the two-dimensional graphene layer can be, for example, plasma-assisted selective reaction (PSR). FIG. 3 is a flow chart of the steps of forming a two-dimensional graphene layer on a silicon carbide substrate according to an embodiment of the present disclosure. Please refer to FIG. 3, FIG. 3 adopts PSR to form a two-dimensional graphene layer on a silicon carbide substrate, wherein step 121 is to perform a plasma treatment process on the silicon carbide substrate, and the plasma treatment process includes bombarding the silicon carbide substrate with nitrogen plasma ( _N2 plasma) to generate carbon-silicon nitrogen bonds (Si-CN). The plasma treatment process may be performed at a power of 200 watts (W) to 1000 W and for a time of 1 minute to 60 minutes. After completing step 121, step 122 may be performed. Step 122 is to perform a heat treatment process, which includes heating the silicon carbide substrate in a nitrogen and hydrogen ( _N2 / _H2 ) atmosphere. The volume ratio of _N2 / _H2 may be, for example, but not limited to, 95/5, 90/10 or 50/50, so that the hydrogen can react with the residual oxygen in the vacuum furnace, thereby preventing the residual oxygen from contaminating the finished product. The heat treatment process may be an annealing process, and the heat treatment process may be performed at 1000° C. to 1200° C. for 5 minutes to 60 minutes. In this way, the silicon that is no longer bound by the carbon-silicon bond due to the breaking of the carbon-silicon bond can be combined with nitrogen to form silicon nitride (Si ₃ N ₄ ), and the carbon that is no longer bound by the carbon-silicon bond due to the breaking of the carbon-silicon bond can be combined with each other to form a two-dimensional graphene layer. In addition, the two-dimensional graphene layer is doped with nitrogen ions to form a nitrided two-dimensional graphene layer, and the nitrogen ions are provided by nitrogen plasma in the plasma treatment process and/or nitrogen in the heat treatment process. In other words, when PSR is used to form a nitride two-dimensional graphene layer, a silicon nitride layer can be formed at the same time. The silicon nitride layer is located between the silicon carbide substrate and the nitride two-dimensional graphene layer. In addition, the nitride two-dimensional graphene layer is an N-type graphene layer.

In other embodiments, chemical vapor deposition (CVD) may be used to form a two-dimensional graphene layer on the initial substrate 210. For example, the initial substrate 210 may be exposed to a graphene precursor (such as methane) to form a two-dimensional graphene layer on the initial substrate 210.

Step 130 is to perform a plasma treatment process on the Van der Waals material layer 220, which is to bombard the Van der Waals material layer 220 with a reactive gas plasma 260 to generate a dangling bond on the surface of the Van der Waals material layer 220. In this way, the damaged area of the Van der Waals material layer 220 is conducive to the subsequent formation of the nitride epitaxial layer 230, so that the growth orientation of the nitride can continue to grow in the direction of the crystal axis of the initial substrate 210. The nitride epitaxial layer 230 can be, for example, a gallium nitride epitaxial layer. In step 130, the power of the plasma treatment process can be 200W to 1000W, and the execution time can be 1 minute to 60 minutes. The reactive gas plasma 260 may be a gas plasma containing elements such as C, H, O, N and/or F. For example, the reactive gas plasma 260 may include nitrogen plasma, oxygen plasma, ammonia plasma, hydrogen plasma, tetrafluoromethane (CF ₄ ) plasma, sulfur hexafluoride (SF ₆ ) plasma, nitrous oxide (N ₂ O) plasma or a combination thereof.

Step 140 is to form a nitride epitaxial layer 230 on the Van der Waals material layer 220. The thickness of the nitride epitaxial layer 230 can be 0.5 μm to 10 μm. In this way, a composite substrate 200 can be obtained. The composite substrate 200 includes an initial substrate 210, a Van der Waals material layer 220 and a nitride epitaxial layer 230. The Van der Waals material layer 220 is disposed on the initial substrate 210, and the nitride epitaxial layer 230 is disposed on the Van der Waals material layer 220. The material of the initial substrate 210 is different from that of the nitride epitaxial layer 230.

The manufacturing method 100 of the composite substrate may optionally include step 135, wherein a seed layer 225 is formed on the van der Waals material layer 220, and then step 140 is performed. In other words, the nitride epitaxial layer 230 is disposed on the van der Waals material layer 220 through the seed layer 225. When the manufacturing method 100 of the composite substrate includes step 135, the composite substrate 200 includes an initial substrate 210, a van der Waals material layer 220, a seed layer 225, and a nitride epitaxial layer 230, wherein the seed layer 225 is disposed between the van der Waals material layer 220 and the nitride epitaxial layer 230. The thickness of the nitride epitaxial layer 230 may be 0.5 μm to 8 μm. The seed layer 225 may be a group IIIA nitride, such as aluminum nitride, gallium nitride, indium nitride, aluminum-gallium nitride, aluminum-indium nitride, or gallium-aluminum-indium nitride. The thickness of the seed layer 225 may be 0.1 μm to 1 μm.

The manufacturing method 100 of the composite substrate may optionally include steps 150 to 180. Step 150 is to form a stress layer 240 on the nitride epitaxial layer 230. Please also refer to FIG. 4, which is a flow chart of the steps of forming a stress layer 240 on the nitride epitaxial layer 230 according to an embodiment of the present disclosure. Step 151 is to coat a glass photoresist layer (not shown) on the nitride epitaxial layer 230, and the thickness of the glass photoresist layer may be 50 μm to 100 μm. Step 152 is to perform a sintering process, which can be performed at 300°C to 700°C for 1 minute to 12 hours, or at 500°C to 700°C for 30 minutes to 360 minutes, so that the glass photoresist layer is transformed into the stress layer 240. The time of the aforementioned sintering process can be adjusted according to the temperature, and the present invention is not limited thereto. In addition to protecting the nitride epitaxial layer 230, the stress layer 240 can also serve as a submount to support the nitride epitaxial layer 230 and the Van der Waals material layer 220 when the initial substrate 210 is subsequently removed.

Referring back to FIG. 1, step 160 is to remove the initial substrate 210 to expose the Van der Waals material layer 220. For example, an attach film (not shown) can be attached to the top surface of the stress layer 240, and force is applied to the attach film to peel off the stress layer 240, the nitride epitaxial layer 230, and the Van der Waals material layer 220 from the initial substrate 210 to expose the bottom surface of the Van der Waals material layer 220.

Step 170 is to combine the Van der Waals material layer 220 with the carrier substrate 250, specifically, to transfer the stacked layer consisting of the Van der Waals material layer 220 and the nitride epitaxial layer 230 to the carrier substrate 250, so that the Van der Waals material layer 220 is disposed between the nitride epitaxial layer 230 and the carrier substrate 250. The carrier substrate 250 can be selected according to actual needs, and the carrier substrate 250 can be but not limited to a silicon-on-insulator substrate, a high-resistivity silicon (HR-Si) substrate, an aluminum nitride (AlN) substrate, a silicon (100) substrate, a copper foil substrate, a ceramic substrate or a gallium oxide (Ga ₂ O ₃ ) substrate. When the initial substrate 210 is not a silicon carbide substrate, the supporting substrate 250 may also be a silicon carbide substrate. Afterwards, the adhesive film bonded to the top surface of the stress layer 240 is removed.

Step 180 is to remove the stress layer 240 to expose the top surface of the nitride epitaxial layer 230. In this way, a composite substrate 200a can be obtained. The difference between the composite substrate 200a and the composite substrate 200 is that the substrate is different. In other words, through steps 150 to 180, the initial substrate 210 can be replaced with another substrate. The thermal conductivity, electrical insulation or mechanical properties of the replaced substrate can be different from the initial substrate 210 to meet subsequent applications, which is beneficial to expand the application range. In addition, the replaced initial substrate 210 can be reused, which is beneficial to reduce material costs.

FIG. 5 is a cross-sectional schematic diagram of a semiconductor stack structure 400 according to an embodiment of the present disclosure. The semiconductor stack structure 400 includes, from bottom to top, a composite substrate 410, a nucleation layer 420, a buffer layer 430, a high resistance layer 440, a barrier layer 450, an intrinsic gallium nitride layer 460, an electron supply layer 470, and a capping layer 480.

The composite substrate 410 includes a substrate 411, a Van der Waals material layer 412, and a nitride epitaxial layer 413 from bottom to top, and may optionally include a seed layer (not shown) disposed between the Van der Waals material layer 412 and the nitride epitaxial layer 413, and may optionally include a bonding strengthening layer 414 disposed above the nitride epitaxial layer 413. The substrate 411 may be the aforementioned initial substrate 210 or the supporting substrate 250. The details of the composite substrate 410 may refer to the composite substrates 200 and 200a, and will not be repeated here.

After the composite substrate 410 is fabricated and before the nucleation layer 420 is formed, trimethylaluminum (TMAl) may be periodically introduced into the process chamber, whereby the trimethylaluminum reacts with nitrogen ions on the nitride epitaxial layer 413. For example, the trimethylaluminum may remove one of the methyl groups and form a bond with the nitrogen ions, thereby optimizing the surface of the nitride epitaxial layer 413 and improving the epitaxial quality of the nitride epitaxial layer 413. In other words, a bonding strengthening layer 414 may be further included between the nitride epitaxial layer 413 and the nucleation layer 420, which is formed by the reaction of trimethylaluminum and nitrogen ions.

x1

1；0

y1

1；以及x1+y1

1。或者，可滿足下列條件：0

x1<0.01；以及0.9<y1

1。在形成成核層420時，製程溫度可採取漸進升溫的方式，例如可以每分鐘提高10℃至15℃。成核層420的厚度可為5nm至500nm。藉此，可提升複合基板410與其他層之間的接合性，降低龜裂(crack)、捲曲發生的機率。 The nucleation layer 420 is disposed on the composite substrate 410. The material of the nucleation layer 420 can be aluminum nitride (AlN) or In _x1 Al _y1 Ga _1-x1-y1 N, and meets the following conditions:

x1

1;0

y1

1; and x1+y1

1. Alternatively, the following conditions may be met: 0

x1<0.01; and 0.9<y1

1. When forming the nucleation layer 420, the process temperature can be gradually increased, for example, by 10°C to 15°C per minute. The thickness of the nucleation layer 420 can be 5nm to 500nm. This can improve the bonding between the composite substrate 410 and other layers and reduce the probability of cracks and curling.

The buffer layer 430 is disposed on the nucleation layer 420 and is used to buffer the stress from the composite substrate 410. The material of the buffer layer 430 may be Al _x2 Ga _1-x2 N and meet the following conditions: 0.7<x2<0.95. The thickness of the buffer layer 430 may be 50nm to 200nm. In addition, the buffer layer 430 may also be a super lattice structure composed of multiple semiconductor layers.

The high resistance layer 440 is disposed on the buffer layer 430, and the resistivity of the high resistance layer 440 is higher than that of the buffer layer 430. The material of the high resistance layer 440 may be doped gallium nitride (GaN), the doping element may be carbon, iron, magnesium, zinc or a combination thereof, and the doping amount may be 2E19/cm ³ . The thickness of the high resistance layer 440 may be 0.2 μm to 5.5 μm.

x3

1.0；0

x4

0.1；0.15

y2

0.20；以及0.80

x5

0.85。第一阻障層451作為排斥層(exclusion layer)，可減少合金無序和界面散射，當半導體層疊結構400應用於HEMT，有利於提高二維電子氣(two-dimensional electron gas)2DEG的遷移率。第二阻障層452作為中間層(interlayer)，可保護第一阻障層451，避免第一阻障層451受到熱及/或化學蝕刻的影響。在形成阻障層450，可進行前置流(pre-flow)步驟，前置流依據阻障層450的材質可包含銦、鋁、鎵、氮等前導物及載體氣流，而可以氣體的形式進入反應爐，例如，銦、鋁、鎵或氮前導物舉例可為三甲基鋁(TMAl)、三乙基鋁(TEAl)、三甲基鎵(TMGa)、三乙基鎵(TEGa)、三甲基銦(TMIn)、三乙基銦(TEIn)，載體氣流舉例可為N₂、H₂，其中調整前置流的時間及流量，使前置流不足以提供完整的氮化物單層，例如，使前置流提供少於80%的氮化物單層，或者，少於60%的氮化物單層，或者，少於40%的氮化物單層，或者，少於20%的氮化物單層。阻障層450的厚度可為90nm至1500nm，其中第一阻障層451的厚度可為30nm至500nm，第二阻障層452的厚度可為30nm至500nm，第三阻障層453的厚度可為30nm至500nm。 The barrier layer 450 is disposed on the high resistance layer 440. The barrier layer 450 includes a first barrier layer 451, a second barrier layer 452, and a third barrier layer 453 in order from the composite substrate 410 to the direction away from the composite substrate 410. The material of the first barrier layer 451 is Al _x3 Ga _1-x3 N, the material of the second barrier layer 452 is Al _x4 Ga _1-x4 N, and the material of the third barrier layer 453 is In _y2 Al _x5 Ga _1-x5-y2 N, and the following conditions are met: 0.7

x3

1.0;0

x4

0.1; 0.15

y2

0.20; and 0.80

x5

0.85. The first barrier layer 451 acts as an exclusion layer to reduce alloy disorder and interface scattering. When the semiconductor stack structure 400 is applied to HEMT, it is beneficial to improve the mobility of two-dimensional electron gas 2DEG. The second barrier layer 452 acts as an interlayer to protect the first barrier layer 451 and prevent the first barrier layer 451 from being affected by heat and/or chemical etching. After forming the barrier layer 450, a pre-flow step may be performed. The pre-flow may include precursors such as indium, aluminum, gallium, and nitrogen, and a carrier gas flow according to the material of the barrier layer 450, and may enter the reaction furnace in the form of gas. For example, examples of indium, aluminum, gallium, or nitrogen precursors may be trimethylaluminum (TMAl), triethylaluminum (TEAl), trimethylgallium (TMGa), triethylgallium (TEGa), trimethylindium (TMIn), and triethylindium (TEIn). Examples of carrier gas flow may be _N2 , _H2 , wherein the time and flow rate of the pre-flow are adjusted so that the pre-flow is insufficient to provide a complete nitride monolayer, for example, the pre-flow provides less than 80% of the nitride monolayer, or less than 60% of the nitride monolayer, or less than 40% of the nitride monolayer, or less than 20% of the nitride monolayer. The thickness of the barrier layer 450 may be 90nm to 1500nm, wherein the thickness of the first barrier layer 451 may be 30nm to 500nm, the thickness of the second barrier layer 452 may be 30nm to 500nm, and the thickness of the third barrier layer 453 may be 30nm to 500nm.

The intrinsic gallium nitride layer 460 is disposed on the barrier layer 450. The thickness of the intrinsic gallium nitride layer 460 may be 0.1 μm to 1.5 μm.

The electron supply layer 470 is disposed on the intrinsic gallium nitride layer 460. The material of the electron supply layer 470 may be InAl _x6 Ga _1-x6 N or Al _x7 Ga _1-x7 N, and may satisfy the following conditions: 0.1<x6<1;0<x7<1. The thickness of the electron supply layer 470 may be 8nm to 45nm.

The capping layer 480 is disposed on the electron supply layer 470. The material of the capping layer 480 may be P-type gallium nitride (GaN) or P-type Al _x8 Ga _1-x8 N, and satisfy the following condition: 0<x8<1. The thickness of the capping layer 480 may be 10 nm to 100 nm.

The nucleation layer 420, buffer layer 430, high resistance layer 440, barrier layer 450, intrinsic gallium nitride layer 460, electron supply layer 470 and capping layer 480 of the semiconductor stack structure 400 can all be formed by epitaxial growth through metal-organic chemical vapor deposition (MOCVD). The semiconductor stack structure 400 can be subsequently processed to manufacture the desired semiconductor element or device.

Please refer to FIG. 6 for a cross-sectional view of a HEMT 500 according to an embodiment of the present disclosure. The HEMT 500 can be processed from the semiconductor stack structure 400. In detail, compared with the semiconductor stack structure 400, the HEMT 500 further includes a gate electrode 510, a source electrode 520, and a drain electrode 530. The gate electrode 510 is disposed on the capping layer 480, and the source electrode 520 and the drain electrode 530 are disposed on both sides of the gate electrode 510 and are located on the intrinsic gallium nitride layer 460. The source electrode 520 and the drain electrode 530 can pass through the electron supply layer 470 to reach the top surface of the intrinsic gallium nitride layer 460, or reach a depth of the intrinsic gallium nitride layer 460. As shown in FIG. 8, the region not covered by the capping layer 480 forms a 2DEG 540 due to the piezoelectric effect generated between the intrinsic gallium nitride layer 460 and the electron supply layer 470. By applying a bias voltage to the P-type capping layer 480 using the gate electrode 510, the concentration of the 2DEG 540 in the intrinsic gallium nitride layer 460 located below the P-type capping layer 480 can be adjusted, thereby adjusting the switching of the HEMT 500. Compared with silicon power transistors, the HEMT 500 has a wider energy band gap, and therefore has the characteristics of low on-state resistance (RON) and low switching loss. The HEMT 500 can be used as a power switching transistor for voltage converter applications or telecommunication high power applications, but the present disclosure is not limited thereto. How to form the gate electrode 510, the source electrode 520 and the drain electrode 530 in the semiconductor stacked structure 400 is well known in the art and will not be further described here.

Please refer to Figures 7 and 8, Figure 7 is a local TEM result image of the high electron mobility transistor according to Example 1 of the present disclosure, and Figure 8 is an EDX result image according to Example 1 of the present disclosure, wherein Part A is a local scanning transmission electron microscope (STEM) result image of the high electron mobility transistor of Example 1, Part B shows the distribution of aluminum atoms (Al) of Example 1, Part C shows the distribution of carbon atoms (C) of Example 1, Part D shows the distribution of nitrogen atoms (N) of Example 1, and Part E shows the distribution of silicon atoms (Si) of Example 1. In Figure 7, from bottom to top, it includes a substrate 411a, a Van der Waals material layer (not otherwise labeled), a nitride epitaxial layer (not otherwise labeled), a bond strengthening layer (not otherwise labeled) and a nucleation layer 420a, wherein the substrate 411a is a silicon substrate, the Van der Waals material layer is a nitride two-dimensional graphene layer, the bond strengthening layer is formed by the reaction of trimethyl aluminum and nitrogen ions, the nucleation layer 420a is aluminum nitride, and the Van der Waals material layer, the nitride epitaxial layer and the bond strengthening layer form an aluminum-carbon-nitrogen interface (Al-C-N interface) 415a. From the lattice arrangement observed in FIG. 7 and the EDX component analysis results in FIG. 8, it can be seen that the present disclosure can successfully form an aluminum-carbon-nitrogen interface 415a between the substrate 411a and the nucleation layer 420a, which is beneficial to enhance the bonding ability between the substrate 411a and the nucleation layer 420a, and is beneficial to reduce the mismatch stress between the two.

Compared to the prior art, the present invention forms a Van der Waals material layer on the initial substrate before forming the nitride epitaxial layer. After being treated with gas plasma, the Van der Waals material layer will have a compatible bonding energy with the nitride, which is conducive to the epitaxial growth of the nitride along the crystal axis direction of the initial substrate. In addition, the Van der Waals material layer is conducive to designing a logic circuit with a low conduction voltage and integrating it with a gallium nitride power device.

The above is only the preferred embodiment of this disclosure. All equivalent changes and modifications made according to the scope of patent application of this disclosure should be within the scope of this disclosure.

100: Manufacturing method of composite substrate

110,120,130,135,140,150,160,170,180: Steps

Claims (20)

A method for manufacturing a composite substrate comprises: providing an initial substrate; forming a Van der Waals material layer on the initial substrate, wherein the material of the initial substrate is different from the material of the Van der Waals material layer; performing a plasma treatment process on the Van der Waals material layer, wherein the plasma treatment process comprises bombarding the Van der Waals material layer with a reactive gas plasma; and forming a nitride epitaxial layer on the Van der Waals material layer, wherein the Van der Waals material layer has a compatible bonding energy with the nitride epitaxial layer after the plasma treatment process. A method for manufacturing a composite substrate as described in claim 1, wherein the Van der Waals material layer comprises two-dimensional graphene, hexagonal boron nitride or transition metal dichalcogenide. The method for manufacturing a composite substrate as described in claim 2, wherein the transition metal dichalcogenide comprises molybdenum disulfide (MoS ₂ ), tungsten disulfide (WS ₂ ), molybdenum diselenide (MoSe ₂ ) or tungsten diselenide (WSe ₂ ). The method for manufacturing a composite substrate as described in claim 1, wherein the reactive gas plasma comprises nitrogen plasma, oxygen plasma, ammonia plasma, hydrogen plasma, tetrafluoromethane (CF ₄ ) plasma, sulfur hexafluoride (SF ₆ ) plasma, nitrous oxide (N ₂ O) plasma or a combination thereof. The manufacturing method of the composite substrate as described in claim 1 further comprises: forming a seed layer on the van der Waals material layer, wherein the seed layer is disposed between the van der Waals material layer and the nitride epitaxial layer. The manufacturing method of the composite substrate as described in claim 1, wherein the Van der Waals material layer is a two-dimensional graphene layer, the initial substrate is a silicon carbide substrate, and forming the two-dimensional graphene layer on the silicon carbide substrate includes: performing another plasma treatment process on the silicon carbide substrate, wherein the another plasma treatment process is bombarding the silicon carbide substrate with nitrogen plasma; and performing a heat treatment process, wherein the heat treatment process includes heating the silicon carbide substrate in a nitrogen and hydrogen atmosphere. The manufacturing method of the composite substrate as described in claim 6, wherein: the power of the plasma treatment process applied to the silicon carbide substrate is 200 watts to 1000 watts, and the application time is 1 minute to 60 minutes; and the heat treatment process is performed at 1000°C to 1200°C for 5 minutes to 60 minutes. The manufacturing method of the composite substrate as described in claim 1 further comprises: forming a stress layer on the nitride epitaxial layer; removing the initial substrate to expose the van der Waals material layer; combining the van der Waals material layer with a supporting substrate; and removing the stress layer. The manufacturing method of the composite substrate as described in claim 8, wherein forming the stress layer on the nitride epitaxial layer comprises: coating a glass photoresist layer on the nitride epitaxial layer; and performing a sintering process, wherein the sintering process is performed at 300°C to 700°C for 1 minute to 12 hours to transform the glass photoresist layer into the stress layer. A method for manufacturing a composite substrate as described in claim 8, wherein the supporting substrate is a silicon-on-insulator (SOI) substrate, a high-resistivity silicon (HR-Si) substrate, an aluminum nitride (AlN) substrate, a silicon (100) substrate, a silicon carbide substrate, a copper foil substrate, a ceramic substrate or a gallium oxide (Ga ₂ O ₃ ) substrate. A composite substrate is manufactured by the manufacturing method of the composite substrate as described in claim 1, comprising: a substrate; a Van der Waals material layer disposed on the substrate; and a nitride epitaxial layer disposed on the Van der Waals material layer; wherein the material of the substrate is different from that of the nitride epitaxial layer, and the material of the substrate is different from that of the Van der Waals material layer. A composite substrate as described in claim 11, wherein the Van der Waals material layer comprises two-dimensional graphene, hexagonal boron nitride or transition metal dichalcogenide. The composite substrate as described in claim 12, wherein the transition metal dichalcogenide comprises molybdenum disulfide (MoS ₂ ), tungsten disulfide (WS ₂ ), molybdenum diselenide (MoSe ₂ ) or tungsten diselenide (WSe ₂ ). The composite substrate as described in claim 11 further comprises: a sublayer disposed between the Van der Waals material layer and the nitride epitaxial layer. The composite substrate as described in claim 11, wherein the substrate is a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a high-resistivity silicon (HR-Si) substrate, an aluminum nitride (AlN) substrate, a silicon (100) substrate or a gallium oxide (Ga ₂ O ₃ ) substrate. A semiconductor stacked structure, comprising: a composite substrate as described in claim 11; a nucleation layer disposed on the composite substrate; a buffer layer disposed on the nucleation layer; a high resistance layer disposed on the buffer layer; a barrier layer disposed on the high resistance layer; an intrinsic gallium nitride layer disposed on the barrier layer; an electron supply layer disposed on the intrinsic gallium nitride layer; and a capping layer disposed on the electron supply layer. The semiconductor stack structure as claimed in claim 16, wherein the material of the nucleation layer is aluminum nitride or In _x1 Al _y1 Ga _1-x1-y1 N, and satisfies the following conditions:

x1

1;0

y1

1; and x1+y1

1. A semiconductor stacked structure as described in claim 16, wherein the material of the buffer layer is Al _x2 Ga _1-x2 N and satisfies the following conditions: 0.7<x2<0.95; the material of the high resistance layer is doped gallium nitride, and the doping element of the high resistance layer is carbon, iron, magnesium, zinc or a combination thereof. The semiconductor stacked structure as claimed in claim 16, wherein the barrier layer comprises a first barrier layer, a second barrier layer and a third barrier layer in order from the composite substrate to the direction away from the composite substrate, the material of the first barrier layer is Al _x3 Ga _1-x3 N, the material of the second barrier layer is Al _x4 Ga _1-x4 N, the material of the third barrier layer is In _y2 Al _x5 Ga _1-x5-y2 N, and the following conditions are met: 0.7

x3

1.0;0

x4

0.1; 0.15

y2

0.20; and 0.80

x5

0.85. A semiconductor stack structure as described in claim 16, wherein the material of the electron supply layer is InAl _x6 Ga _1-x6 N or Al _x7 Ga _1-x7 N, and satisfies the following conditions: 0.1<x6<1;0<x7<1; the material of the covering layer is P-type gallium nitride or P-type Al _x8 Ga _1-x8 N, and satisfies the following conditions: 0<x8<1.