TWI858926B - Functional testing device - Google Patents
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Description
本發明係關於一種功能測試裝置。The present invention relates to a functional testing device.
在伺服器產品製造中,執行功能板測試(function board test,FBT)之測試功能站是最後一道的產品驗證站台,透過測試功能站可確認生產工藝及產品功能的情況。測試功能站的作業主要由作業員負責將伺服器主機板或周邊功能卡上所需的各種元件連接至測試功能站的連接器以進行測試。In server product manufacturing, the test station that performs function board test (FBT) is the last product verification station. The production process and product function can be confirmed through the test station. The operation of the test station is mainly responsible for connecting the various components required on the server motherboard or peripheral function card to the connector of the test station for testing.
現行的測試機台需使用真實的主機板進行測試,需開機進到作業系統才能進行測試,且一次只能對一個伺服器主機板或周邊功能卡進行測試,不僅測試時間及成本高,對於伺服器主機板或周邊功能卡需求日益增大的未來而言,這將使得供給與需求之間無法達到平衡。Current test machines require real motherboards for testing, and they must be powered on to the operating system before testing. Moreover, they can only test one server motherboard or peripheral function card at a time. This not only increases the testing time and cost, but also makes it impossible to achieve a balance between supply and demand in the future as the demand for server motherboards or peripheral function cards continues to increase.
鑒於上述,本發明提供一種以滿足上述需求的功能測試裝置。In view of the above, the present invention provides a functional testing device to meet the above requirements.
依據本發明一實施例的功能測試裝置,包含:基板、輸入輸出模組、多個功能測試模組基板管理控制模組以及電力模組。輸入輸出模組設置於基板上,用於接收測試腳本。該些功能測試模組可插拔地設置於基板上。基板管理控制模組設置於基板上且連接於輸入輸出模組及該些功能測試模組,基板管理控制模組用於根據測試腳本控制該些功能測試模組輸出多個測試訊號。電力模組設置於基板上,用於接收並傳輸電力至該些功能測試模組及基板管理控制模組。According to an embodiment of the present invention, a functional test device includes: a substrate, an input-output module, a plurality of functional test modules, a substrate management control module, and a power module. The input-output module is arranged on the substrate for receiving a test script. The functional test modules are pluggably arranged on the substrate. The substrate management control module is arranged on the substrate and connected to the input-output module and the functional test modules. The substrate management control module is used to control the functional test modules to output a plurality of test signals according to the test script. The power module is arranged on the substrate for receiving and transmitting power to the functional test modules and the substrate management control module.
根據以上一或多個實施例的功能測試裝置,可同時對一或多個待測物進行多種測試,進而減少測試時間。此外,由於以上實施例的功能測試裝置可以不需透過主機板,故可減少測試成本。According to the functional test device of one or more embodiments above, multiple tests can be performed on one or more DUTs at the same time, thereby reducing the test time. In addition, since the functional test device of the above embodiments does not need to pass through the motherboard, the test cost can be reduced.
以上之關於本揭露內容之說明及以下之實施方式之說明係用以示範與解釋本發明之精神與原理,並且提供本發明之專利申請範圍更進一步之解釋。The above description of the disclosed content and the following description of the implementation methods are used to demonstrate and explain the spirit and principle of the present invention, and provide a further explanation of the scope of the patent application of the present invention.
以下在實施方式中詳細敘述本發明之詳細特徵以及優點,其內容足以使任何熟習相關技藝者了解本發明之技術內容並據以實施,且根據本說明書所揭露之內容、申請專利範圍及圖式,任何熟習相關技藝者可輕易地理解本發明相關之目的及優點。以下之實施例係進一步詳細說明本發明之觀點,但非以任何觀點限制本發明之範疇。The following detailed description of the features and advantages of the present invention is provided in the implementation mode, and the content is sufficient to enable any person skilled in the relevant art to understand the technical content of the present invention and implement it accordingly. Moreover, according to the content disclosed in this specification, the scope of the patent application and the drawings, any person skilled in the relevant art can easily understand the relevant purposes and advantages of the present invention. The following embodiments are to further explain the viewpoints of the present invention in detail, but are not to limit the scope of the present invention by any viewpoint.
本發明以下一或多個實施例所揭露之功能測試裝置、系統及方法可適用於功能板測試(function board test,FBT)之站台,用於對主機板或周邊功能卡進行測試,特別是伺服器的主機板或周邊功能卡。The function test device, system and method disclosed in one or more of the following embodiments of the present invention can be applied to a function board test (FBT) station for testing a motherboard or a peripheral function card, especially a motherboard or a peripheral function card of a server.
請參考圖1,圖1係依據本發明一實施例所繪示的功能測試裝置的方塊圖。如圖1所示,功能測試裝置11包括基板110、輸入輸出模組111、多個功能測試模組112a及112b、基板管理控制模組113以及電力模組114。圖1示例性呈現兩個功能測試模組,然本發明不限制功能測試模組的數量。輸入輸出模組111、基板管理控制模組113以及電力模組114設置於基板110上,功能測試模組112a及112b可插拔地設置於基板110上。功能測試模組112a及112b可以具有不同的測試功能,且各可以執行一或多個測試項目。舉例而言,功能測試模組112a及112b可透過快捷周邊組件互連(peripheral component interconnect express,PCIe)連接埠設置於基板110上。功能測試模組112a及112b各自的規格可為高度、寬度、長度半高半長(half-height half-length,HHHL)或高度、寬度、長度全高半長(full-height half-length,FHHL)。基板管理控制模組113連接於輸入輸出模組111、功能測試模組112a及112b以及電力模組114。Please refer to FIG. 1 , which is a block diagram of a functional test device according to an embodiment of the present invention. As shown in FIG. 1 , the
輸入輸出模組111可以包括用於存取測試腳本(script)的一或多個通訊埠。換言之,輸入輸出模組111用於接收測試腳本。具體而言,輸入輸出模組111可以通訊連接於使用者介面以接收使用者輸入的測試腳本,或/及通訊連接於資料庫伺服器(database server)以取得測試腳本,其中通訊連接可透過有線或無線的方式。測試腳本可以指示測試項目以及對應的測試流程,包含功能測試模組112a及112b的多個測試項目的執行順序。電力模組114用於接收並傳輸電力至功能測試模組112a及112b及基板管理控制模組113。進一步來說,電力模組114更可以傳輸電力至待測物。The input-
基板管理控制模組113可以包括基板管理控制器(baseboard management controller,BMC)及記憶體,其中基板管理控制器的內嵌記憶體可以預存功能測試模組112a及112b的測試項目所對應的測試指令(command),記憶體可用於儲存測試腳本。具體而言,所述內嵌記憶體可為嵌入式多媒體卡(embedded multimedia card,eMMC)等非揮發性記憶體,記憶體可為雙倍資料率第四代隨機存取記憶體等揮發性記憶體(double data rate fourth generation synchronous dynamic random-access memory,DDR4)。基板管理控制模組113用於根據測試腳本控制功能測試模組112a及112b輸出多個測試訊號,其中測試訊號可以輸出至待測物。基板管理控制模組113更可以透過功能測試模組112a及112b取得待測物對於測試訊號的回應訊號,並據以產生通過(pass)或不通過(fail)的測試結果。The baseboard
在輸入輸出模組111接收測試腳本後,基板管理控制模組113的基板管理控制器可以將測試腳本存入基板管理控制器的記憶體,及在要執行測試時,讀取記憶體中的測試腳本,及根據讀取的測試腳本使用基板管理控制器的內嵌記憶體儲存的該些測試指令的至少一部分以控制功能測試模組112a及112b輸出測試訊號。After the input-
舉例而言,測試項目可以包括快捷周邊組件互連的測試項目。快捷周邊組件互連的測試項目可以包括連結(link)傳輸速度及寬度(width)、連結速度變化(link speed change)測試、資料傳輸性能、接收端通道邊界(receiver lane margin)測試、接收端眼圖(eye diagram)、封包產生器及錯誤注入(error injection)的一或多者。基板管理控制模組113可以透過功能測試模組112a及112b取得快捷周邊組件互連對於以上測試項目的回應訊號,並據以產生測試結果。For example, the test items may include test items for the interconnection of the quick peripheral components. The test items for the interconnection of the quick peripheral components may include one or more of link transmission speed and width, link speed change test, data transmission performance, receiver lane margin test, receiver eye diagram, packet generator and error injection. The baseboard
此外,輸入輸出模組111可更用於取得待測物的識別資訊,基板管理控制模組113的基板管理控制器透過輸入輸出模組111向資料庫伺服器索取對應於識別資訊的測試腳本,再將測試腳本存入基板管理控制器的記憶體。待測物的唯讀記憶體(read-only memory,ROM)可存有待測物的識別資訊,輸入輸出模組111可透過直接讀取待測物的唯讀記憶體而取得識別資訊。識別資訊可為待測物的名稱及/或序列號等,本發明不予以限制。In addition, the input-
請一併參考圖1及圖2,其中圖2係依據本發明一實施例所繪示的基板管理控制模組的方塊圖。如圖2所示,基板管理控制模組113可以包含擴充板1130、第一記憶元件1131、第二記憶元件1132、控制晶片1133以及連接埠1134,其中第一記憶元件1131、第二記憶元件1132、控制晶片1133以及連接埠1134設置於擴充板1130。具體來說,第一記憶元件1131可為前述用於儲存測試腳本的記憶體,第二記憶元件1132可為前述用於儲存對應於多個測試項目的測試指令的記憶體,控制晶片1133可為執行基板管理控制的晶片(RunBMC)。控制晶片1133可以透過連接埠1134連接基板110上的電路,連接埠1134例如為雙線記憶體模組(dual in-line memory module,DIMM)介面。換言之,基板管理控制模組113可以可插拔地連接於基板110,然於另一實施例中,基板管理控制模組113可以包含直接設置於基板110的第一記憶元件1131、第二記憶元件1132以及控制晶片1133。Please refer to FIG. 1 and FIG. 2 , wherein FIG. 2 is a block diagram of a baseboard management control module according to an embodiment of the present invention. As shown in FIG. 2 , the baseboard
請一併參考圖1到圖3,其中圖3係依據本發明一實施例所繪示的輸入輸出模組的方塊圖。如圖3所示,輸入輸出模組111可以包括第一通訊埠1111、第二通訊埠1112以及第三通訊埠1113。第一通訊埠1111用於連接資料庫伺服器A1,第二通訊埠1112用於連接掃描裝置A2,第三通訊埠1113用於連接使用者介面A3。舉例來說,第一通訊埠1111可為RJ45,第二通訊埠1112可為通用序列匯流排(universal serial bus,USB)介面。第三通訊埠1113可為通用序列匯流排介面、RS232、RS485中的一者。圖3實施例僅示例性地說明三種通訊埠,於其他實施例中,功能測試裝置11可以包含三種通訊埠中的一或兩種通訊埠,且各種通訊埠的數量亦不受限制。Please refer to Figures 1 to 3, wherein Figure 3 is a block diagram of an input-output module according to an embodiment of the present invention. As shown in Figure 3, the input-
資料庫伺服器A1可為雲端資料庫伺服器,儲存分別對應於不同待測物的多個測試腳本。掃描裝置A2可為條碼掃描裝置,掃描裝置A2可用於掃描待測物上的條碼以取得前述的識別資訊。使用者介面A3可為鍵盤、滑鼠、觸控式螢幕等,用於接收使用者輸入的資訊。The database server A1 may be a cloud database server, storing multiple test scripts corresponding to different objects to be tested. The scanning device A2 may be a barcode scanning device, which may be used to scan the barcode on the object to be tested to obtain the aforementioned identification information. The user interface A3 may be a keyboard, a mouse, a touch screen, etc., for receiving information input by the user.
基板管理控制模組113可根據識別資訊透過第一通訊埠1111向資料庫伺服器A1索取對應於識別資訊(即對應於待測物)的測試腳本。此外, 第三通訊埠1113亦可用於自使用者介面A3接收測試腳本。換言之,輸入輸出模組111可同時包括第一通訊埠1111以及第三通訊埠1113,亦可僅包括其中一者。The baseboard
請一併參考圖4及圖5,圖4係依據本發明一實施例所繪示的功能測試裝置的立體示意圖,圖5係繪示圖4的功能測試裝置的俯視圖。圖1到圖3所示的基板110、輸入輸出模組111、功能測試模組112a及112b、基板管理控制模組113及電力模組114的設置方式可如圖4及圖5所示。此外,電力模組114可包括電力輸入埠1141及電力輸出埠1142。電力輸入埠1141用於自外部電力源接收電力,以供應電力至基板110上的各模組,以及將電力透過電力輸出埠1142輸出至待測物。Please refer to FIG. 4 and FIG. 5 together. FIG. 4 is a three-dimensional schematic diagram of a functional test device according to an embodiment of the present invention, and FIG. 5 is a top view of the functional test device of FIG. 4. The
請參考圖6,圖6係依據本發明一實施例所繪示的功能測試系統的方塊圖。如圖6所示,功能測試系統1包括如圖1所示的功能測試裝置11及待測物12。功能測試模組112a及112b可插拔地設置於基板110上,且可插拔地連接至待測物12。待測物12連接於電力模組114,電力模組114用於接收及輸出電力至待測物12。輸入輸出模組111用於接收對應於待測物12的多個測試腳本。基板管理控制模組113用於根據該些測試腳本透過功能測試模組112a及112b對待測物12進行測試。換言之,基板管理控制模組113根據該些測試腳本控制功能測試模組112a及112b輸出測試訊號至待測物12。Please refer to FIG6 , which is a block diagram of a functional test system according to an embodiment of the present invention. As shown in FIG6 , the
請參考圖7,圖7係依據本發明另一實施例所繪示的功能測試系統的方塊圖。如圖7所示,功能測試系統1’包括如圖1所示的功能測試裝置11、多個待測物12a到12c以及介面卡13。圖7所示的功能測試模組的數量及待測物的數量僅為示例,功能測試模組的數量可為大於2,待測物的數量可介於1到3之間,亦可為大於3。舉例而言,待測物12a到12c的每一者可包括儲存識別資訊的非揮發性記憶體。介面卡13用於將功能測試模組112a及112b連接至待測物12a到12c。功能測試模組112a及112b可以是透過迷你冷邊輸入輸出(mini cool edge I/O,MCIO)傳輸線連接於介面卡13。具體而言,在圖3的架構中,介面卡13可用於將電力模組114輸出的電力及功能測試模組112a及112b輸出的測試訊號傳送至待測物12a到12c。Please refer to FIG. 7, which is a block diagram of a functional test system according to another embodiment of the present invention. As shown in FIG. 7, the functional test system 1' includes the
請一併參考圖7、圖8A及8B,其中圖8A係依據本發明一實施例所繪示的介面卡的殼體、電力訊號輸入埠及測試訊號輸入埠的方塊圖,圖8B係依據本發明一實施例所繪示的介面卡的訊號輸出埠的方塊圖。如圖8A及圖8B所示,介面卡13具有殼體130、電力訊號輸入埠131、一或多個測試訊號輸入埠132及一或多個訊號輸出埠133。訊號輸出埠133包含對應於電力訊號輸入埠131的電力訊號子埠1331及對應於測試訊號輸入埠132的一或多個測試訊號子埠1332。電力訊號輸入埠131電性連接於電力模組114及電力訊號子埠1331。測試訊號輸入埠132電性連接於測試訊號子埠1332以及功能測試模組112a及112b。具體而言,電力訊號輸入埠131及測試訊號輸入埠132可設置於殼體130的第一面1301,訊號輸出埠133可設置於介面卡13的第二面1302。更具體而言,第二面1302可與第一面1301相對。訊號輸出埠133可透過排線連接於待測物。圖8A及8B示例性地呈現介面卡的電力訊號輸入埠131、測試訊號輸入埠132及訊號輸出埠133的設置位置,然本發明的電力訊號輸入埠131、測試訊號輸入埠132及訊號輸出埠133的設置方式不限於此。Please refer to FIG. 7, FIG. 8A and FIG. 8B together, wherein FIG. 8A is a block diagram of a housing, a power signal input port and a test signal input port of an interface card according to an embodiment of the present invention, and FIG. 8B is a block diagram of a signal output port of an interface card according to an embodiment of the present invention. As shown in FIG. 8A and FIG. 8B, the
電力訊號輸入埠131用於自電力模組114接收電力,及將所述電力經由電力訊號子埠1331輸出至待測物12a到12c。測試訊號輸入埠132用於自功能測試模組112a及112b接收測試訊號,及將所述測試訊號經由測試訊號子埠1332輸出至待測物12a到12c。在圖8A及圖8B的實施例中,一個測試訊號輸入埠132可用於接收功能測試模組112a及112b中的一者的測試訊號,或一個測試訊號輸入埠132可用於接收功能測試模組112a及112b兩者的測試訊號;一個訊號輸出埠133可用於將電力及測試訊號輸出至待測物12a到12c中的一者,或一個訊號輸出埠133可用於將電力及測試訊號輸出至待測物12a到12c的每一者。The power
請參考圖9,圖9係依據本發明另一實施例所繪示的功能測試裝置的方塊圖。如圖9所示,功能測試裝置21包括基板210、輸入輸出模組211、多個連接埠212a及212b、主控模組213以及電力模組214。圖9示例性呈現兩個連接埠,然本發明不限制連接埠的數量。功能測試裝置21的基板210及輸入輸出模組211可與圖1到圖8的實施例的基板110及輸入輸出模組111相同,故不於此贅述。Please refer to FIG. 9, which is a block diagram of a functional test device according to another embodiment of the present invention. As shown in FIG. 9, the
連接埠212a及212b及主控模組213設置於基板210上,且主控模組213連接於連接埠212a及212b。主控模組213用於根據輸入輸出模組211接收的測試腳本輸出多個測試訊號至連接埠212a及212b。進一步而言,連接埠212a及212b可為快捷周邊組件互連連接埠,分別用於連接待測物。The
請一併參考圖9及圖10,其中圖10係依據本發明一實施例所繪示的主控模組的方塊圖。如圖10所示,主控模組213包括處理器2131、第一連接埠2132及第二連接埠2133。處理器2131連接於第一連接埠2132及第二連接埠2133。圖10示例性呈現兩個連接埠,然本發明不限制連接埠的數量。第一連接埠2132可為快捷周邊組件互連連接埠,第二連接埠2133可為RJ45。Please refer to FIG. 9 and FIG. 10 , where FIG. 10 is a block diagram of a main control module according to an embodiment of the present invention. As shown in FIG. 10 , the
請一併參考圖9到圖11,其中圖11係繪示圖9的功能測試裝置的示意圖。如圖11所示,輸入輸出模組211包括第一通訊埠2111、第二通訊埠2112以及第三通訊埠2113,電力模組214包括電力輸入埠2141及電力輸出埠2142,其中第一通訊埠2111、第二通訊埠2112以及第三通訊埠2113可分別與圖3到圖5的第一通訊埠1111、第二通訊埠1112以及第三通訊埠1113相同,電力輸入埠2141及電力輸出埠2142可分別與圖4及圖5的電力輸入埠1141及電力輸出埠1142相同。Please refer to FIG. 9 to FIG. 11 , where FIG. 11 is a schematic diagram of the functional test device of FIG. 9 . As shown in FIG. 11 , the input-
進一步而言,電力模組214可包括電力輸入埠2141,電力輸入埠用2141於自外部接收電力,將電力供應至主控模組213,及經由連接埠212a及212b將電力供應至待測物。Furthermore, the
此外,功能測試裝置21亦可依如圖6到圖8的一或多個實施例的方式連接於待測物。在此實施方式中,連接埠212a及212b用於連接功能測試模組,電力模組214更包括電力輸出埠2142,用於輸出電力至待測物。In addition, the
在功能測試裝置21中,主控模組213可為以中央處理單元(central processing unit,CPU)為主要運算元件的模組,透過快捷周邊組件互連連接埠(第一連接埠2132)連接於基板210的電路。於一實施例中,主控模組213可為以基板管理控制器為主要運算元件的模組,透過快捷周邊組件互連連接埠(第一連接埠2132)連接於基板210的電路。此外,功能測試裝置21可更包括從屬模組215,設置於基板210上,從屬模組215可為基板管理控制模組。基板管理控制模組的實現方式可與圖2的實施方式相同。In the
此外,主控模組213可具第一連接埠2132,從屬模組215可具有另一通訊埠,用於取得測試腳本,其中從屬模組215的通訊埠亦可為RJ45。主控模組213可根據測試腳本的一部分輸出測試訊號至連接埠212a及212b中的一者,及從屬模組215可根據測試腳本的另一部分輸出測試訊號至連接埠212a及212b中的另一者。換言之,測試腳本可指示主控模組213及從屬模組215各自需執行的測試內容,主控模組213及從屬模組215可取得同一測試腳本,主控模組213及從屬模組215根據測試腳本判斷各自需經由連接埠212a及212b輸出的測試訊號。In addition, the
請參考圖12,圖12係依據本發明又一實施例所繪示的功能測試系統的方塊圖。如圖12所示,功能測試系統3包括基板310、輸入輸出模組311、多個連接埠312a及312b、主控模組313以及多個待測物32a及32b。功能測試系統3的基板310、輸入輸出模組311、連接埠312a及312b及主控模組313可與圖9到圖11的實施例的基板210、輸入輸出模組211、連接埠212a及212b及主控模組213相同,故不於此贅述。此外,功能測試系統3可更包括從屬模組,其實現方式可與圖11的實施例相同。Please refer to FIG. 12, which is a block diagram of a functional test system according to another embodiment of the present invention. As shown in FIG. 12, the functional test system 3 includes a
如圖12所示,待測物32a連接於連接埠312a,待測物32b連接於連接埠312b,其中待測物32a及待測物32b可彼此相同或相異。如前所述,主控模組313可為中央處理單元,用於根據測試腳本輸出測試訊號至連接埠312a及312b,以由連接埠312a及312b分別輸出測試訊號至待測物32a及32b。As shown in FIG12 , the DUT 32a is connected to the
功能測試系統3包括還可包括從屬模組,所述從屬模組可與圖11的從屬模組215相同。換言之,功能測試系統3的從屬模組可為基板管理控制模組,主控模組313及從屬模組各自對應於輸入輸出模組311的一通訊埠(例如,RJ45),用於取得測試腳本;及主控模組313及從屬模組可各自根據測試腳本輸出測試訊號至連接埠312a及312b。The functional test system 3 may further include a slave module, which may be the same as the
此外,主控模組313測試的待測物可為網路介面卡(network interface card,NIC)及繪圖處理器卡中的一或多個;從屬模組測試的待測物可為不具主動元件的待測物,例如擴充卡(riser card)。換言之,主控模組313用於測試待測物32a,從屬模組用於測試待測物32b,且待測物32b不具主動元件。In addition, the DUT tested by the
請接著參考圖13,其中圖13係依據本發明一實施例所繪示的功能測試方法的流程圖。圖13所示的功能測試方法適用於待測物,可由連接於功能測試模組的設備執行,亦可由直接連接待測物的設備執行。換言之,功能測試方法可以上一或多個實施例的基板管理控制模組、主控模組及從屬模組執行,且適用於以上所有實施例的功能測試裝置及功能測試系統。以下以圖12的功能測試系統3為例說明功能測試方法。所述功能測試方法包括:步驟S101:根據待測物的識別資訊從雲端資料庫伺服器索取測試腳本,其中測試腳本包含不同類型的多個測試項目;以及步驟S103:根據測試腳本對待測物進行測試。Please refer to FIG. 13, which is a flow chart of a functional test method according to an embodiment of the present invention. The functional test method shown in FIG. 13 is applicable to an object to be tested, and can be executed by a device connected to a functional test module, or can be executed by a device directly connected to the object to be tested. In other words, the functional test method can be executed by the baseboard management control module, the main control module, and the slave module of one or more embodiments, and is applicable to the functional test devices and functional test systems of all the above embodiments. The functional test method is explained below using the functional test system 3 of FIG. 12 as an example. The functional testing method comprises: step S101: obtaining a test script from a cloud database server according to identification information of the object to be tested, wherein the test script comprises a plurality of test items of different types; and step S103: testing the object to be tested according to the test script.
於步驟S101,主控模組313根據待測物的識別資訊,經由輸入輸出模組311從雲端資料庫伺服器(例如,圖3的資料庫伺服器A1)索取測試腳本。如上所述,主控模組313取得待測物的識別資訊的方法可以是經由掃描裝置或透過讀取待測物的唯讀記憶體得到。測試腳本包含不同類型的多個測試項目,例如快速周邊元件互連介面類型的測試項目、電源類型的測試項目、網路連接類型的測試項目等。In step S101, the
於步驟S103,主控模組313根據測試腳本對待測物32a及32b進行測試。以待測物32a為例,主控模組313可根據測試腳本輸出對應的測試訊號至連接埠312a,以輸出測試訊號至待測物32a。In step S103, the
進一步而言,同樣以待測物32a為例,步驟S103的實現方式亦可包括主控模組313根據測試腳本的該些測試項目控制功能測試模組(例如,圖1的功能測試模組112a及112b)對待測物32a進行測試,其中該些功能測試模組中的每一者能夠執行該些測試項目中的至少一者。此外,主控模組313可以是將該些測試項目所對應的多個控制訊號以分時多工的方式傳送至該些功能測試模組,以控制功能測試模組對待測物32a進行測試。換言之,主控模組313可以控制功能測試模組以分時多工的方式對待測物32a進行測試。Furthermore, taking the object to be tested 32a as an example, the implementation method of step S103 may also include the
請接著參考圖14,其中圖14係依據本發明一實施例所繪示的對待測物進行測試的方法的流程圖。圖14可視為圖13之步驟S103的一實施例的細部流程圖。以下同樣以圖12的功能測試系統3及其待測物32a為例進行說明。所述對待測物進行測試的方法包括:步驟S201:產生第一封包;步驟S203:經由快速周邊元件互連介面輸出第一封包至待測物,其中第一封包包含第一檢驗碼;步驟S205:經由快速周邊元件互連介面從待測物接收第二封包,其中第二封包包含第二檢驗碼;步驟S207:判斷第一檢驗碼與第二檢驗碼是否一致;若步驟S207的判斷結果為「是」,執行步驟S209:產生關於待測物的正面測試結果;以及若步驟S207的判斷結果為「否」,執行步驟S211:產生關於待測物的負面測試結果。Please refer to FIG. 14, which is a flow chart of a method for testing a DUT according to an embodiment of the present invention. FIG. 14 can be regarded as a detailed flow chart of an embodiment of step S103 of FIG. 13. The following is also described by taking the functional test system 3 and the DUT 32a of FIG. 12 as an example. The method for testing the DUT includes: step S201: generating a first packet; step S203: outputting the first packet to the DUT via the rapid peripheral component interconnect interface, wherein the first packet includes a first check code; step S205: receiving a second packet from the DUT via the rapid peripheral component interconnect interface, wherein the second packet includes a second check code; step S207: determining whether the first check code is consistent with the second check code; if the determination result of step S207 is "yes", executing step S209: generating a positive test result about the DUT; and if the determination result of step S207 is "no", executing step S211: generating a negative test result about the DUT.
於步驟S201,主控模組313產生的第一封包可包括在測試訊號內。第一封包包括第一校驗碼,其中第一校驗碼可為循環冗餘校驗(cyclic redundancy check, CRC)的函數。此外,第一封包還可包括封包序列號碼等資料,本發明不予以限制。In step S201, the first packet generated by the
於步驟S203,主控模組313經由快速周邊元件互連介面(連接埠312a)輸出第一封包至待測物32a,其中快速周邊元件互連介面可為連接埠312a。步驟S203相當於前述透過連接埠/功能測試模組輸出測試訊號至待測物。In step S203, the
於步驟S205,主控模組313經由同樣的快速周邊元件互連介面從待測物32a接收第二封包。第二封包包括第二校驗碼,其中第二校驗碼可為循環冗餘校驗的函數。此外,第二封包還可包括封包序列號碼等資料,本發明不予以限制。In step S205, the
於步驟S207,主控模組313判斷第一校驗碼與第二校驗碼是否一致。若第一校驗碼與第二校驗碼一致,主控模組313判斷對待測物32a的測試成功,故執行步驟S209以產生關於待測物32a的正面測試結果。反之,若第一校驗碼與第二校驗碼不一致,主控模組313判斷對待測物32a的測試不成功,故執行步驟S211以產生關於待測物32a的負面測試結果。In step S207, the
請接著一併參考圖15及圖16,其中圖15係依據本發明一實施例所繪示的產生第一封包的方法的流程圖,圖16係依據本發明一實施例所繪示的功能測試方法的示意圖。圖15可視為圖14之步驟S201的一實施例的細部流程圖。以下同樣以圖12的功能測試系統3及其待測物32a為例進行說明。所述產生第一封包的方法包括:步驟S301:由資料鏈路層產生第一校驗碼;步驟S303:由資料鏈路層基於傳輸層封包及第一校驗碼產生鏈路層封包;以及步驟S305:由實體層基於鏈路層封包產生第一封包。Please refer to FIG. 15 and FIG. 16 together, wherein FIG. 15 is a flow chart of a method for generating a first packet according to an embodiment of the present invention, and FIG. 16 is a schematic diagram of a functional test method according to an embodiment of the present invention. FIG. 15 can be regarded as a detailed flow chart of an embodiment of step S201 of FIG. 14. The following is also explained by taking the functional test system 3 and its DUT 32a of FIG. 12 as an example. The method for generating a first packet includes: step S301: generating a first checksum from a data link layer; step S303: generating a link layer packet from a data link layer based on a transport layer packet and the first checksum; and step S305: generating a first packet from a physical layer based on a link layer packet.
於步驟S301,主控模組313的資料鏈路層(data link layer)產生第一校驗碼。於步驟S303,主控模組313的資料鏈路層基於傳輸層(transaction layer)封包及第一校驗碼產生鏈路層封包,其中傳輸層封包係由主控模組313的傳輸層產生。換言之,於步驟S303,主控模組313在傳輸層封包的尾端加上第一校驗碼而產生鏈路層封包,且可在傳輸層封包的頭端加上封包序列號碼。In step S301, the data link layer of the
於步驟S305,主控模組313的實體層(physical layer)基於鏈路層封包產生第一封包。進一步而言,主控模組313的實體層可以是在鏈路層封包的頭幀加上開始(start)及在鏈路層封包的尾幀加上結束(end),以產生第一封包。In step S305, the physical layer of the
以上多個實施例所述的待測物可以是伺服器的主機板、電源板、快捷周邊組件互連(Peripheral Component Interconnect Express,PCIe)介面、網路介面卡(network interface card,NIC)、繪圖處理器卡或轉接卡等各種元件,本發明不予以限制。The DUT described in the above embodiments may be a server motherboard, a power board, a peripheral component interconnect express (PCIe) interface, a network interface card (NIC), a graphics processor card or an adapter card, etc., and the present invention is not limited thereto.
根據以上一或多個實施例的功能測試裝置、系統及方法,可同時對一或多個待測物進行多種測試,進而減少測試時間。此外,由於根據以上一或多個實施例的功能測試裝置、系統及方法可以不需透過主機板,故可減少測試成本。According to the functional test device, system and method of one or more embodiments, multiple tests can be performed on one or more DUTs at the same time, thereby reducing the test time. In addition, since the functional test device, system and method of one or more embodiments do not need to pass through the motherboard, the test cost can be reduced.
雖然本發明以前述之實施例揭露如上,然其並非用以限定本發明。在不脫離本發明之精神和範圍內,所為之更動與潤飾,均屬本發明之專利保護範圍。關於本發明所界定之保護範圍請參考所附之申請專利範圍。Although the present invention is disclosed as above with the aforementioned embodiments, it is not intended to limit the present invention. Any changes and modifications made without departing from the spirit and scope of the present invention are within the scope of patent protection of the present invention. Please refer to the attached patent application for the scope of protection defined by the present invention.
1,1’,3:功能測試系統
11,21:功能測試裝置
110,210:基板
111,211,311:輸入輸出模組
1111,2111:第一通訊埠
1112,2112:第二通訊埠
1113,2113:第三通訊埠
112a,112b:功能測試模組
113:基板管理控制模組
1130:擴充板
1131:第一記憶元件
1132:第二記憶元件
1133:控制晶片
1134,212a,212b,312a,312b:連接埠
114,214,314:電力模組
1141,2141:電力輸入埠
1142,2142:電力輸出埠
12,12a,12b,12c,32a,32b:待測物
13:介面卡
130:殼體
1301:第一面
1302:第二面
131:電力訊號輸入埠
132:測試訊號輸入埠
133:訊號輸出埠
1331:電力訊號子埠
1332:測試訊號子埠
213,313:主控模組
2131:處理器
2132:第一連接埠
2133:第二連接埠
215:從屬模組
A1:資料庫伺服器
A2:掃描裝置
A3:使用者介面
S101,S103,S201,S203,S205,S207,S209,S211,S301,S303,S305:步驟1,1’,3:
圖1係依據本發明一實施例所繪示的功能測試裝置的方塊圖。 圖2係依據本發明一實施例所繪示的基板管理控制模組的方塊圖。 圖3係依據本發明一實施例所繪示的輸入輸出模組的方塊圖。 圖4係依據本發明一實施例所繪示的功能測試裝置的立體示意圖。 圖5係繪示圖4的功能測試裝置的俯視圖。 圖6係依據本發明一實施例所繪示的功能測試系統的方塊圖。 圖7係依據本發明另一實施例所繪示的功能測試系統的方塊圖。 圖8A係依據本發明一實施例所繪示的介面卡的殼體、電力訊號輸入埠及測試訊號輸入埠的方塊圖,圖8B係依據本發明一實施例所繪示的介面卡的訊號輸出埠的方塊圖。 圖9係依據本發明另一實施例所繪示的功能測試裝置的方塊圖。 圖10係依據本發明一實施例所繪示的主控模組的方塊圖。 圖11係繪示圖9的功能測試裝置的示意圖。 圖12係依據本發明又一實施例所繪示的功能測試系統的方塊圖。 圖13係依據本發明一實施例所繪示的功能測試方法的流程圖。 圖14係依據本發明一實施例所繪示的對待測物進行測試的方法的流程圖。 圖15係依據本發明一實施例所繪示的產生第一封包的方法的流程圖。 圖16係依據本發明一實施例所繪示的功能測試方法的示意圖。 FIG. 1 is a block diagram of a functional test device according to an embodiment of the present invention. FIG. 2 is a block diagram of a baseboard management control module according to an embodiment of the present invention. FIG. 3 is a block diagram of an input/output module according to an embodiment of the present invention. FIG. 4 is a three-dimensional schematic diagram of a functional test device according to an embodiment of the present invention. FIG. 5 is a top view of the functional test device of FIG. 4. FIG. 6 is a block diagram of a functional test system according to an embodiment of the present invention. FIG. 7 is a block diagram of a functional test system according to another embodiment of the present invention. FIG8A is a block diagram of a housing, a power signal input port, and a test signal input port of an interface card according to an embodiment of the present invention, and FIG8B is a block diagram of a signal output port of an interface card according to an embodiment of the present invention. FIG9 is a block diagram of a functional test device according to another embodiment of the present invention. FIG10 is a block diagram of a main control module according to an embodiment of the present invention. FIG11 is a schematic diagram of the functional test device of FIG9. FIG12 is a block diagram of a functional test system according to another embodiment of the present invention. FIG13 is a flow chart of a functional test method according to an embodiment of the present invention. FIG. 14 is a flow chart of a method for testing an object to be tested according to an embodiment of the present invention. FIG. 15 is a flow chart of a method for generating a first packet according to an embodiment of the present invention. FIG. 16 is a schematic diagram of a functional testing method according to an embodiment of the present invention.
11:功能測試裝置 11: Functional test equipment
110:基板 110: Substrate
111:輸入輸出模組 111: Input and output module
112a,112b:功能測試模組 112a,112b: Functional test module
113:基板管理控制模組 113: Baseboard management control module
114:電力模組 114: Power module
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103257910A (en) * | 2013-04-26 | 2013-08-21 | 北京航空航天大学 | LX I embedded type reconfigurable general test platform capable of being used for on-site test |
| CN111505481A (en) * | 2020-04-17 | 2020-08-07 | 苏州浪潮智能科技有限公司 | Mainboard test system, method, equipment and medium |
| CN116089199A (en) * | 2023-03-30 | 2023-05-09 | 湖南华自信息技术有限公司 | IO port testing method and server |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103257910A (en) * | 2013-04-26 | 2013-08-21 | 北京航空航天大学 | LX I embedded type reconfigurable general test platform capable of being used for on-site test |
| CN111505481A (en) * | 2020-04-17 | 2020-08-07 | 苏州浪潮智能科技有限公司 | Mainboard test system, method, equipment and medium |
| CN116089199A (en) * | 2023-03-30 | 2023-05-09 | 湖南华自信息技术有限公司 | IO port testing method and server |
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