TWI858980B - Memory block and manufacturing method thereof, and memory cell - Google Patents

Abstract

The present application provides a memory block and its manufacturing method, and a memory cell. The method includes: providing a semiconductor substrate; defining multiple word line holes on the semiconductor substrate to divide each memory subarray layer into multiple columns of drain region semiconductor strips, channel semiconductor strips, and source region semiconductor strips along a row direction; forming a floating gate storage structure through at least one side of a part of each word line hole that exposes a corresponding channel semiconductor strip; filling the gate material in each word line hole to form a gate strip. The memory block produced by the manufacturing method has a high storage density.

Description

Storage block and its manufacturing method, storage unit

The present invention relates to the field of semiconductor device technology, and in particular to a storage block and its manufacturing method, and a storage unit.

This invention claims priority to the following application: Chinese mainland patent application number 2022113433049 filed on October 27, 2022. The application is hereby incorporated by reference in its entirety.

Two-dimensional (2D) storage blocks are ubiquitous in electronic devices and may include, for example, NOR flash storage arrays, NAND flash storage arrays, and DRAM arrays. However, 2D storage arrays have reached their scaling limits and storage density cannot be further increased.

The storage block and its manufacturing method, as well as the storage unit provided by the present invention are intended to solve the problem that the existing 2D storage array has reached its scaling limit and the storage density cannot be further improved.

In order to solve the above technical problems, a technical solution adopted by the present invention is to provide a method for manufacturing a storage block. The method comprises: providing a semiconductor substrate, wherein the semiconductor substrate comprises a substrate and a plurality of storage sub-array layers formed on the substrate, the plurality of storage sub-array layers are stacked in sequence along a height direction perpendicular to the substrate, and each of the storage sub-array layers comprises a drain semiconductor layer, a channel semiconductor layer and a source semiconductor layer stacked along the height direction; a plurality of word line holes are opened on the semiconductor substrate to connect each word line hole to the source semiconductor layer; The storage sub-array layer is divided into a plurality of columns of drain semiconductor strips, channel semiconductor strips and source semiconductor strips along the row direction, wherein the plurality of word line holes are arranged in a matrix in the row direction and the column direction, each of the word line holes extends along the height direction, and at least one side of each of the word line holes exposes a portion of at least one column of the drain semiconductor strips, channel semiconductor strips and source semiconductor strips of the plurality of storage sub-array layers. ; forming a storage structure on at least one side of each word line hole where the drain semiconductor strip, the channel semiconductor strip and the source semiconductor strip are exposed, wherein the storage structure is a charge trap storage structure; filling each word line hole with a gate material to form a plurality of gate strips, wherein at least a portion of each gate strip is aligned with a portion of the channel semiconductor strip corresponding to one of the storage sub-array layers; The projections on the projection plane overlap, the projection plane extends along the height direction and the column direction, and the portion of the gate bar, the corresponding portion of the channel semiconductor bar, the portion of the charge energy trap storage structure sandwiched between the portion of the gate bar and the corresponding portion of the channel semiconductor bar, the portion of the drain semiconductor bar adjacent to the corresponding portion of the channel semiconductor bar, and the portion of the source semiconductor bar form a storage unit.

In one embodiment, a semiconductor substrate is provided, comprising:

Providing the lining;

A plurality of storage sub-array layers are sequentially formed on the substrate along the height direction;

A first hard mask layer is formed on a plurality of the storage array layers, and a plurality of isolation barrier holes are opened in the first hard mask layer and the plurality of the storage array layers, and an isolator is filled in the isolation barrier holes to form a plurality of isolation walls to form the semiconductor substrate, wherein the isolation barrier holes are arranged in a matrix in the row direction and the column direction, and each of the isolation barrier holes extends along the height direction to the substrate.

In one embodiment, the substrate is a single crystal substrate;

A plurality of storage sub-array layers are sequentially formed on the substrate along the height direction, including:

Forming a first single crystal sacrificial semiconductor layer or a virtual memory array layer on the substrate by epitaxial growth;

Two layers of storage sub-array layers and a second single crystal sacrificial semiconductor layer are sequentially and alternately formed on the first single crystal sacrificial semiconductor layer by epitaxial growth until the top two layers of the storage sub-array layer are formed; or, a second single crystal sacrificial semiconductor layer and two layers of storage sub-array layers are sequentially and alternately formed on the virtual storage sub-array layer by epitaxial growth.

In one embodiment, two adjacent storage array layers share a source region, and the formation method of each two storage array layers sharing the source region includes:

On the first single crystal sacrificial semiconductor layer or the second single crystal sacrificial semiconductor layer at the lower layer, a first single crystal semiconductor layer of a first doping type is formed by epitaxial growth;

Forming a second single crystal semiconductor layer of a second doping type on the first single crystal semiconductor layer by epitaxial growth;

Forming a third single crystal semiconductor layer of the first doping type on the second single crystal semiconductor layer by epitaxial growth;

Forming a fourth single crystal semiconductor layer of a second doping type on the third single crystal semiconductor layer by epitaxial growth;

Forming a fifth single crystal semiconductor layer of the first doping type on the fourth single crystal semiconductor layer by epitaxial growth;

Wherein, the first single crystal semiconductor layer and the fifth single crystal semiconductor layer of the first doping type are used as the drain semiconductor layer, the second single crystal semiconductor layer and the fourth single crystal semiconductor layer of the second doping type are used as the channel semiconductor layer, and the third single crystal semiconductor layer of the first doping type is used as the source semiconductor layer;

The first single crystal semiconductor layer, the second single crystal semiconductor layer and the third single crystal semiconductor layer constitute one storage sub-array layer; the third single crystal semiconductor layer, the fourth single crystal semiconductor layer and the fifth single crystal semiconductor layer constitute another storage sub-array layer; the two storage sub-array layers share the third single crystal semiconductor layer as the shared source region semiconductor layer.

In one embodiment, a plurality of word line holes are opened on the semiconductor substrate, including:

Forming a plurality of word line openings on the first hard mask layer, wherein the plurality of word line openings are arranged in a matrix in the row direction and the column direction;

The first hard mask layer with the word line opening is used as a photomask to etch the plurality of storage sub-array layers under the first hard mask layer to form a plurality of word line holes, wherein the plurality of word line holes cooperate with the plurality of isolation walls to divide each layer of the storage sub-array layer into a plurality of rows of drain semiconductor strips, channel semiconductor strips and source semiconductor strips along the row direction.

In one embodiment, further comprising:

Using the word line hole, the first single crystal sacrificial semiconductor layer and the second single crystal sacrificial semiconductor layer are removed;

Deposition is performed in the area where the first single crystal sacrificial semiconductor layer and the second single crystal sacrificial semiconductor layer are removed, so as to fill the area where the first single crystal sacrificial semiconductor layer and the second single crystal sacrificial semiconductor layer are removed with insulating material, thereby replacing the first single crystal sacrificial semiconductor layer and the second single crystal sacrificial semiconductor layer with insulating isolation layers.

In one embodiment, a charge energy trap storage structure is formed on both sides of the portion of each word line hole that exposes the drain semiconductor strip, the channel semiconductor strip, and the source semiconductor strip, respectively, including:

Depositing a first dielectric layer on the surface of the semiconductor substrate having the word line hole, wherein the first dielectric layer covers the portions of the drain semiconductor strip, the channel semiconductor strip, and the source semiconductor strip exposed on both sides of the word line hole;

Depositing a charge storage layer on the first dielectric layer;

A second dielectric layer is deposited on the charge storage layer.

In one embodiment, the gate material is filled in each word line hole, including:

The gate material is filled in each word line hole to form a plurality of gate bars, wherein the charge energy trap storage structure is arranged between each gate bar and the drain semiconductor bars, channel semiconductor bars and source semiconductor bars in the plurality of storage sub-array layers.

To solve the above technical problem, another technical solution adopted by the present invention is to provide a storage block. The storage block includes: a storage array, including a plurality of storage units arranged in a three-dimensional array, wherein the storage array includes a plurality of stacking structures arranged along a row direction, each stacking structure extends along a column direction, and each stacking structure includes a drain semiconductor strip, a channel semiconductor strip, and a source semiconductor strip stacked along a height direction, each of the drain semiconductor strip, the channel semiconductor strip, and the source semiconductor strip extends along the column direction; a plurality of gate strips arranged along the column direction are arranged on both sides of the stacking structure, each of the gate strips extends along the height direction; Upward, at least a portion of each gate bar overlaps with a projection of a portion of a corresponding channel semiconductor bar on a projection plane, and the projection plane extends along the height direction and the column direction; a portion of the gate bar, a corresponding portion of the channel semiconductor bar, a portion of the drain semiconductor bar and a portion of the source semiconductor bar that are adjacent to the corresponding portion of the channel semiconductor bar are used to form a storage unit; a charge energy trap storage structure is provided between each gate bar and the drain semiconductor bar, the channel semiconductor bar and the source semiconductor bar in a plurality of the storage array layers.

In one embodiment, each of the drain semiconductor strip, channel semiconductor strip, and source semiconductor strip is a single crystal semiconductor strip.

In one embodiment, each column of the stacked structure includes multiple groups of stacked substructures, and each group of stacked substructures includes a drain semiconductor strip, a channel semiconductor strip, a source semiconductor strip, a channel semiconductor strip, and a drain semiconductor strip stacked in sequence along the height direction to share the same source semiconductor strip.

In one embodiment, a layer of isolation strips is provided between two adjacent groups of the stacked substructures to isolate them from each other.

In one embodiment, a plurality of isolation walls distributed along the column direction are respectively disposed on both sides of the stacking structure, and each isolation wall extends along the height direction and the row direction to separate at least a portion of two adjacent columns of the stacking structure.

In one embodiment, in the row direction, the gate strip is filled between two adjacent isolation walls in the same row;

Two adjacent columns of the stacked structure share the same gate strip.

In one embodiment, the isolation wall near the row-direction edge of the storage block extends in the row direction to the row-direction edge of the storage block to completely isolate two adjacent rows of the stacking structure.

In one embodiment, the charge energy trap storage structure includes a first dielectric layer, a charge storage layer and a second dielectric layer, wherein the first dielectric layer is located between the charge storage layer and the adjacent stack structure, the charge storage layer is located between the first dielectric layer and the second dielectric layer, and the second dielectric layer is located between the charge storage layer and the gate strip.

In order to solve the above technical problems, a technical solution adopted by the present invention is: to provide a storage unit. The storage unit includes: a drain part, a channel part, a source part and a gate part, wherein the drain part, the channel part and the source part are stacked in the height direction, and the gate part is located on one side of the drain part, the channel part and the source part, and extends along the height direction; wherein, in the height direction, the projections of the gate part and the channel part on a projection plane at least partially overlap, and the projection plane extends along the height direction and the extension direction of the drain part, the channel part and the source part, and a charge energy trap storage structure part is arranged between the gate part and the drain part, the channel part and the source part.

In one embodiment, the drain region, the channel region and the source region are single crystal semiconductors.

In one embodiment, the charge energy trap storage structure includes a first dielectric part, a charge storage part and a second dielectric part, wherein the first dielectric part is located between the charge storage part and the adjacent drain region part, channel part and source region part, the charge storage part is located between the first dielectric part and the second dielectric part, and the second dielectric part is located between the charge storage part and the gate strip part.

The beneficial effects of the present invention are different from those of the prior art: the present invention provides a method for manufacturing a storage block. The method comprises: providing a semiconductor substrate, wherein the semiconductor substrate comprises a substrate and a plurality of storage sub-array layers formed on the substrate, the plurality of storage sub-array layers are stacked in sequence along a height direction perpendicular to the substrate, and each of the storage sub-array layers comprises a drain semiconductor layer, a channel semiconductor layer and a source semiconductor layer stacked along the height direction; a plurality of word line holes are opened on the semiconductor substrate to connect each word line hole to the source semiconductor layer; The storage sub-array layer is divided into a plurality of columns of drain semiconductor strips, channel semiconductor strips and source semiconductor strips along a row direction, wherein the plurality of word line holes are arranged in a matrix in the row direction and the column direction, each of the word line holes extends along the height direction, and at least one side of each of the word line holes exposes a portion of at least one column of the drain semiconductor strips, channel semiconductor strips and source semiconductor strips of the plurality of storage sub-array layers; A storage structure is formed on at least one side of each word line hole where the drain semiconductor strip, the channel semiconductor strip and the source semiconductor strip are exposed, wherein the storage structure is a charge trap storage structure; a gate material is filled in each word line hole to form a plurality of gate strips, wherein at least a portion of each gate strip is aligned with a portion of the channel semiconductor strip corresponding to one of the storage sub-array layers. The projections on the projection plane overlap, the projection plane extends along the height direction and the column direction, the portion of the gate bar, the corresponding portion of the channel semiconductor bar, the portion of the charge energy trap storage structure sandwiched between the portion of the gate bar and the corresponding portion of the channel semiconductor bar, the portion of the drain semiconductor bar and the portion of the source semiconductor bar adjacent to the corresponding portion of the channel semiconductor bar, constitute a storage unit. The storage block manufactured by the method has a higher storage density.

1: Storage array

10: Storage block

11: Drain semiconductor strip

11’: Drainage area

11a: Bit line connection line

11c, D: Drain semiconductor layer

12: Channel semiconductor strip (or well semiconductor)

12’: Channel section

12a: Well area connection line

12b: Common well line (or well semiconductor)

12c: Common well area lead wire

12c’,CH: channel semiconductor layer

13: Source region semiconductor strip

13’: Source area

13a: Source connection line

13b: Common source line

13c: Common source lead

13c’,S: source semiconductor layer

14: Second single crystal sacrificial semiconductor layer

14’: Insulation isolation layer

14a: Interlayer isolation strips

15a: Body structure

15a’: Main body

15b, 15b’: raised part

16: Support column

1a: Storage subarray layer

1b: Semiconductor strip structure (stacked structure)

2,G: Gate bar

2’: Gate part

3: Isolation wall

31: Isolation wall holes

4: Word line holes

5: Storage structure

5’: Storage structure part

51: First dielectric layer (first dielectric part)

52: Charge storage layer (charge storage part)

53: Second dielectric layer (second dielectric part)

54: Floating gate

56: First insulating medium layer

6a, 6b: word line lead-out line

7: Word line connection line

81: Lining

82: First single crystal sacrificial semiconductor layer

83: First hard mask layer

831: Word line opening

8a,WL-a,WL-1-a: odd word lines

8b,WL-b,WL-1-b: even word lines

BL-1-1, BL-1-2, BL-1-3, BL-1-4, BL-1-5, BL-1-6: bit lines

E,F: Direction

S21,S211a,S212a,S213a,S211b,S212b,S213b,S214b,S22,S221,S222,S223,S224,S23,S231,S232,S23,S24,a,b,b1,b2,b3,b4,b5: method

X: row direction

Y: column direction

Z: height direction

In order to more clearly explain the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without making any progressive efforts.

Figure 1 is a simplified structural diagram of the memory device provided in an embodiment of the present invention.

Figures 2a to 4 are schematic diagrams of the three-dimensional structure of the storage array provided by the present invention.

Figure 5 is a schematic diagram of the three-dimensional structure of a storage unit provided in an embodiment of the present invention.

Figure 6 shows a schematic diagram of a three-dimensional structure in which two storage cells share the same column of drain semiconductor strips, channel semiconductor strips, and source semiconductor strips.

Figure 7 is a schematic diagram of the three-dimensional structure of a storage unit provided in another embodiment of the present invention.

Figure 8 is a schematic diagram of the three-dimensional structure of a storage unit provided in another embodiment of the present invention.

Figure 9 is a partial schematic diagram of the three-dimensional structure of a storage block provided in another embodiment of the present invention.

Figure 10 is a schematic diagram of the three-dimensional structure of a storage unit provided in yet another embodiment of the present invention.

Figure 11 is a schematic diagram of the three-dimensional structure of a storage block provided in yet another embodiment of the present invention.

Figure 12 is a schematic diagram of the circuit connection of some storage units of a storage block shown in an embodiment of the present invention.

FIG13 is a schematic diagram of the circuit of the storage block shown in FIG11.

FIG14 is a schematic plan view of the storage block shown in FIG11.

Figure 15 is a schematic diagram of the storage unit corresponding to each layer of bit lines.

Figure 16 is a schematic diagram of the three-dimensional distribution of word lines and bit lines.

Figure 17 is a flow chart of a storage block manufacturing method provided in an embodiment of the present invention.

Figures 18-27 are schematic structural diagrams of the specific process flow of the storage block manufacturing method shown in an embodiment of the present invention.

The following will combine the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by the ordinary knowledge in this field without making progressive labor are within the scope of protection of the present invention.

The terms "first", "second", and "third" in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second", and "third" can explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus comprising a series of steps or units is not limited to the listed steps or units, but may optionally also include steps or units not listed, or may optionally also include other steps or units inherent to these processes, methods, products or apparatuses.

Reference to "embodiments" herein means that the specific features, structures, or characteristics described in conjunction with the embodiments may be included in at least one embodiment of the invention. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those of ordinary skill in the art that the embodiments described herein may be combined with other embodiments.

The present invention is described in detail below with reference to the drawings and embodiments.

In this embodiment, refer to FIG. 1, which is a simplified structural diagram of a storage device provided by an embodiment of the present invention. A storage device is provided, and the storage device can be specifically a non-dynamic storage device. The storage device can include one or more storage blocks 10. The specific structure and function of the storage block 10 can refer to the relevant description of the storage block 10 provided in any of the following embodiments. It can be understood by those skilled in the art that the storage array 1 includes a structure in which a plurality of storage units are arranged in a three-dimensional array; and the storage block 10 includes not only the storage array 1 formed by a plurality of storage units arranged in an array, but also other components, such as various types of wires (or connecting wires), etc., so that the storage block 10 can realize various memory operations.

Please refer to Figures 2a to 3, which are schematic diagrams of the three-dimensional structure of the storage array provided in the embodiment of the present invention; a storage block 10 is provided, and the storage block 10 includes a storage array 1. The storage array 1 includes a plurality of storage units distributed in a three-dimensional array.

As shown in FIG. 2a, the storage array 1 includes a plurality of storage sub-array layers 1a stacked in sequence along the height direction Z, and each storage sub-array layer 1a includes a drain semiconductor layer, a channel semiconductor layer, and a source semiconductor layer stacked in the height direction Z. The drain semiconductor layer, the channel semiconductor layer, and the source semiconductor layer may be single crystal semiconductor layers grown by epitaxy. The height direction Z is a direction perpendicular to the substrate (such as the substrate 81 in FIG. 9). Stacking in sequence means arranging in sequence from bottom to top on the substrate, and stacking represents arrangement, and does not indicate or imply the structure or the upper and lower relationship of each layer.

In each storage array layer 1a, the drain semiconductor layer (D) includes a plurality of drain semiconductor strips 11 spaced apart along the row direction X, and each drain semiconductor strip 11 extends along the column direction Y; the channel semiconductor layer (CH) includes a plurality of channel semiconductor strips 12 spaced apart along the row direction X, and each channel semiconductor strip 12 extends along the column direction Y. The source semiconductor layer (S) includes a plurality of source semiconductor strips 13 spaced apart along the row direction X, and each source semiconductor strip 13 extends along the column direction Y. Each of the drain semiconductor strips 11, the channel semiconductor strip 12, and the source semiconductor strip 13 is a single crystal semiconductor strip. It is understood by those skilled in the art that each of the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13 can be a single crystal semiconductor strip formed by processing the drain semiconductor layer, the channel semiconductor layer and the source semiconductor layer formed by epitaxial growth. As shown in Figure 2a-3, multiple gate strips 2 (G) are respectively arranged on both sides of each column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13. The multiple gate strips 2 distributed on one side of each column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 are spaced along the column direction Y, and each gate strip 2 extends along the height direction Z, so that the corresponding parts of the multiple drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 in the same column of the multiple storage array layers 1a share the same gate strip 2.

As shown in FIG2b, among the multiple columns of gate strips 2, each gate strip 2 in the same column and a corresponding gate strip 2 in the adjacent column corresponding to the row direction X are staggered in the column direction Y. For example, each gate strip 2 in the first column of gate strips 2 and each gate strip 2 in the second column are staggered in the column direction Y. Of course, as shown in FIG2a, each gate strip 2 in the same column and a corresponding gate strip 2 in the adjacent column corresponding to the row direction X can also be aligned with each other in the column direction Y. Among them, the staggered setting can reduce the influence of the electric field between the corresponding two gate strips 2 in the adjacent columns.

In the height direction Z, at least a portion of each gate strip 2 overlaps with a projection of a portion of a corresponding channel semiconductor strip 12 in each storage array layer 1a on a projection plane. The projection plane is a plane defined by the height direction Z and the column direction Y, that is, the projection plane extends along the height direction Z and the column direction Y. As shown in FIG. 2a-3, for the convenience of description, it is defined below that a row of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13 in each storage array layer 1a constitute a semiconductor strip structure; two adjacent storage array layers 1a can adopt a common source design, that is, the two adjacent storage array layers 1a share the same source semiconductor layer (S), as follows. Therefore, the two adjacent storage array layers 1a The corresponding two semiconductor strip-shaped structures share the same source region semiconductor strip 13; of course, those with ordinary knowledge in the art can understand that the two adjacent storage sub-array layers 1a can also adopt a non-common source design, that is, each storage sub-array layer 1a has an independent source region semiconductor layer. Therefore, the two semiconductor strip-shaped structures 1b corresponding to the two adjacent storage sub-array layers 1a respectively have independent source region semiconductor strips 13. A plurality of drain region semiconductor strips 11, channel semiconductor strips 12 and source region semiconductor strips 13 in the same column in the plurality of layers of memory subarray layer 1a form a column of semiconductor strip structures 1b, which is also a stacked structure 1b. Among them, a row of semiconductor strip structures 1b includes a plurality of semiconductor strip structures, and the number of semiconductor strip structures in a row of semiconductor strip structures 1b is the same as the number of storage array layers 1a. As shown in Figures 2a-3, a row of semiconductor strip structures 1b includes two semiconductor strip structures, but a person skilled in the art should know that a row of semiconductor strip structures 1b may include a plurality of stacked semiconductor strip structures, as shown in Figure 4, which is a three-dimensional structural diagram of a storage array provided by another embodiment of the present invention, and a row of semiconductor strip structures 1b includes three semiconductor strip structures.

In other words, it can be understood by a person skilled in the art that the storage array 1 includes a plurality of stacked structures 1b distributed along the row direction X, each stacked structure 1b extends along the column direction Y; and each stacked structure 1b includes a drain semiconductor strip 11, a channel semiconductor strip 12, and a source semiconductor strip 13 stacked along the height direction, each drain semiconductor strip 11, channel semiconductor strip 12, and source semiconductor strip 13 extends along the column direction Y; and a plurality of gate strips 2 distributed along the column direction Y are arranged on both sides of each stacked structure 1b, each gate strip 2 extends along the height direction Z.

A portion of each semiconductor strip structure overlaps with a projection of a corresponding portion of a corresponding gate strip 2 on the projection plane. In particular, a portion of the channel semiconductor strip 12 in each semiconductor strip structure overlaps with a projection of a portion of a corresponding gate strip 2 on the projection plane. Therefore, a portion of the gate strip 2, a corresponding portion of the channel semiconductor strip 12, a portion of the drain semiconductor strip 11 adjacent to the corresponding portion of the channel semiconductor strip 12, and a portion of the source semiconductor strip 13 constitute a storage unit. For example, as shown in FIG. 2a-3, a portion of the gate strip 2 in the first row along the row direction X and the first row along the column direction Y is connected to a corresponding portion of the channel semiconductor strip 12 in the first row of the drain semiconductor strip 11, the channel semiconductor strip 12, and the source semiconductor strip 13 (a semiconductor strip structure of a D/CH/S structure) of the first storage array layer 1a in the height direction Z along the row direction X in the projection plane. If the projections on the plane overlap, the portion of the gate strip 2 in the first column and the first row, the corresponding portion of the first column channel semiconductor strip 12 in the first storage array layer 1a in the height direction Z, and the portion of the drain semiconductor strip 11 and the portion of the source semiconductor strip 13 in the first storage array layer 1a in the height direction Z that match the corresponding portion of the first column channel semiconductor strip 12 are used to form a storage unit.

It is understood by those skilled in the art that in a semiconductor device, a channel needs to be formed in the semiconductor region between the semiconductor drain region and the semiconductor source region; and the gate is arranged on one side of the semiconductor region between the semiconductor drain region and the semiconductor source region to form a semiconductor device. Therefore, as shown in Fig. 2a-3, the portion of each gate strip 2 that overlaps with a channel semiconductor strip 12 in an adjacent stacked structure 1b on the above projection plane is used as a gate, i.e., the control gate of the corresponding storage unit; the portion of the channel semiconductor strip 12 that overlaps with the gate strip 2 on the above projection plane is the corresponding portion of the channel semiconductor strip 12, which serves as a channel region (well region) for forming a channel therein; and The drain region semiconductor strip 11 and the source region semiconductor strip 13 adjacent to the channel semiconductor strip 12 are respectively partially arranged just above or below the corresponding part of the channel semiconductor strip 12. That is to say, they exactly match the corresponding parts of the channel semiconductor strip 12. As the semiconductor drain region and the semiconductor source region, the corresponding parts of the channel semiconductor strip 12 are sandwiched in between, and cooperate with the part of the gate strip 2 used as the control gate, thereby forming a memory unit.

Therefore, as shown in FIGS. 2a-3 , the memory array 1 of the present invention comprises a plurality of memory cells arranged in an array through the drain semiconductor strips 11 , the channel semiconductor strips 12 , the source semiconductor strips 13 and the gate strips 2 . In particular, the storage array 1 of the present invention includes a plurality of storage sub-array layers 1a stacked in sequence along the height direction Z, each storage sub-array layer 1a includes a layer of drain semiconductor strips 11, channel semiconductor strips 12, source semiconductor strips 13, and a portion of the gate strips 2 matching the layer, so each layer of storage sub-array layer 1a includes a layer of array-arranged storage cells, and the plurality of storage sub-array layers 1a stacked along the height direction Z constitute a plurality of layers of array-arranged storage cells along the height direction Z.

In the present invention, each drain region semiconductor strip 11 is a semiconductor strip of the first doping type, such as an N-type doped semiconductor strip; in a specific embodiment, each drain region semiconductor strip 11 serves as a bitline (BL) of a storage block.

Each channel semiconductor strip 12 is a semiconductor strip of the second doping type, such as a P-type doped semiconductor strip; in a specific embodiment, each channel semiconductor strip 12 serves as a well region of a storage unit.

Each source region semiconductor strip 13 is also a semiconductor strip of the first doping type, such as an N-type doped semiconductor strip; in a specific embodiment, each source region semiconductor strip 13 serves as a source line (SL) of a storage block.

Of course, those skilled in the art can understand that in other types of storage devices, each drain semiconductor strip and each source semiconductor strip can also be a P-type doped semiconductor strip, while each channel semiconductor strip 12 is an N-type doped semiconductor strip. The present invention is not limited to this.

Please continue to refer to FIG. 2a-3. In the height direction Z, two adjacent storage array layers 1a include a drain semiconductor layer, a channel semiconductor layer, a source semiconductor layer, a channel semiconductor layer and a drain semiconductor layer stacked in sequence to share the same source semiconductor layer. As shown in FIG. 2a-3, in the height direction Z, a common source semiconductor strip 13 is arranged between two adjacent channel semiconductor strips 12 in the same column, and a drain semiconductor strip 11 is arranged on both sides of the two adjacent channel semiconductor strips 12. That is to say, in the height direction Z, the same row of semiconductor strip structures 1b of two adjacent memory subarray layers 1a includes sequentially stacked drain semiconductor strips 11, channel semiconductor strips 12, source semiconductors 13, channel semiconductor strips 12 and drain semiconductor strips 11, thus forming two semiconductor strip structures, and the two semiconductor strip structures share the same source semiconductor strip 13. In this way, the storage density of the memory block 10 can be further improved while reducing costs and processes.

Please refer to 4 together. The storage array 1 includes a plurality of storage sub-array layers 1a stacked in sequence along the height direction Z. Each storage sub-array layer 1a includes a drain semiconductor layer, a channel semiconductor layer, and a source semiconductor layer stacked along the height direction Z.

In each storage array layer 1a, the drain semiconductor layer, the channel semiconductor layer and the source semiconductor layer respectively include a plurality of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 spaced apart along the row direction X.

Two adjacent storage array layers 1a include a drain semiconductor layer, a channel semiconductor layer, a source semiconductor layer, a channel semiconductor layer and a drain semiconductor layer stacked in sequence to share the same source semiconductor layer.

An interlayer isolation layer is provided between every two storage array layers 1a to isolate the storage array layers 1a from the other two storage array layers 1a. For example, in the height direction Z, one interlayer isolation layer is set between the first storage sub-array layer 1a and the second storage sub-array layer 1a and the third storage sub-array layer 1a and the fourth storage sub-array layer 1a; another interlayer isolation layer is set between the third storage sub-array layer 1a and the fourth storage sub-array layer 1a and the fifth storage sub-array layer 1a and the sixth storage sub-array layer 1a, and the layers can be stacked continuously in this way. It can be understood that one of the interlayer isolation layers is located between the second storage sub-array layer 1a and the third storage sub-array layer 1a; the other interlayer isolation layer is located between the fourth storage sub-array layer 1a and the fifth storage sub-array layer 1a.

Specifically, as shown in FIG4 , in the height direction Z, in the same row of semiconductor strip structures, an interlayer isolation strip 14a is provided between every two semiconductor strip structures. Similarly, in other rows of semiconductor strip structures, an interlayer isolation strip 14a is also provided between every two semiconductor strip structures. It can be understood by those skilled in the art that a plurality of interlayer isolation strips 14a on the same horizontal plane constitute an interlayer isolation layer to isolate the semiconductor strip structures in the other two layers of the storage array layer 1a from each other.

In other words, in the present invention, each stacking structure 1b may include a plurality of stacking substructures, each stacking substructure includes a drain semiconductor strip 11, a channel semiconductor strip 12, a source semiconductor strip 13, a channel semiconductor strip 12, and a drain semiconductor strip 11 stacked in sequence along the height direction Z, thereby sharing the same source semiconductor strip 13. In the stacking structure 1b, an interlayer isolation strip 14a is provided between two adjacent stacking substructures to isolate them from each other. That is to say, the drain semiconductor strips 11, channel semiconductor strips 12, source semiconductor strips 13, channel semiconductor strips 12 and drain semiconductor strips 11 in the same column in two adjacent memory sub-array layers 1a form a stacked substructure, so the two adjacent memory sub-array layers 1a share a source semiconductor strip 13.

Please continue to refer to FIG. 4 or FIG. 2a , the storage array 1 is further provided with a plurality of isolation walls 3, which are arranged in a matrix in the row direction X and the column direction Y. As shown in FIG. 2a , a plurality of isolation walls 3 distributed along the column direction Y are respectively arranged on both sides of each column of the drain semiconductor strips 11, the channel semiconductor strips 12, and the source semiconductor strips 13, and each isolation wall 3 extends adjacent to each other in the height direction Z and the row direction X to separate at least parts of two adjacent columns of the drain semiconductor strips 11, the channel semiconductor strips 12, and the source semiconductor strips 13. That is to say, a plurality of isolation walls 3 distributed along the column direction Y are respectively provided on both sides of each stacked structure 1b to separate at least part of two adjacent columns of stacked structures 1b. In specific embodiments, especially during the manufacturing process of the memory block 10 , the isolation wall 3 can further serve as a supporting structure, and can be used to support two adjacent rows of stacked structures 1 b during and/or after the manufacturing process. In addition, supporting columns (not shown, described in detail below) are provided on partial areas on both sides of each stacking structure 1b, so that during and/or after the manufacturing process of the storage array 1, the supporting columns are used to support two adjacent rows of stacking structures 1b.

In the column direction Y, the area between two adjacent isolation walls 3 in the same column is used to form word line holes 4. That is to say, any two adjacent isolation walls 3 in the same column, combined with the two columns of semiconductor strip structures 1b on both sides (ie, the stacked structure 1b), can define a plurality of areas for forming word line holes 4. These areas are processed so that corresponding word line holes 4 can be formed. That is, a plurality of drain region semiconductor strips 11, channel semiconductor strips 12 and source region semiconductor strips 13 extending along the column direction Y are arranged along the A plurality of row isolation walls 3 extending in the row direction X cooperate with the plurality of isolation walls 3 to define a plurality of word line holes 4 . Each word line hole 4 extends along the height direction Z.

Each word line hole 4 is filled with gate material to form a gate strip 2 . That is to say, in the column direction Y, the gate strips 2 are filled between two adjacent isolation walls 3 in the same column.

Please refer to FIG. 5, where FIG. 5 is a schematic diagram of the three-dimensional structure of a storage unit provided by an embodiment of the present invention. As shown in FIG. 5, the storage unit includes a drain region 11', a channel region 12', a source region 13' and a gate region 2', wherein the drain region 11', the channel region 12', and the source region 13' are stacked along the height direction Z, respectively, the channel region 12' is located between the drain region 11' and the source region 13', and the gate region 2' is located on one side of the drain region 11', the channel region 12', the source region 13' and the gate region 2', and extends along the height direction Z. The drain region 11', the channel region 12' and the source region 13' are single crystal semiconductors, respectively.

In addition, in the height direction Z, the projections of the gate portion 2' and the channel portion 12' on a projection plane at least partially overlap. The projection plane is located on one side of the drain portion 11', the channel portion 12', and the source portion 13' and extends along the height direction Z and the extension direction of the drain portion 11', the channel portion 12', and the source portion 13'.

As shown in FIG5, it is easy for a person skilled in the art to understand that the drain region portion 11' is a portion of a drain region semiconductor strip 11 shown in FIG2a-4, the channel portion 12' is a portion of a channel semiconductor strip 12 shown in FIG2a-4, the source region portion 13' is a portion of a source region semiconductor strip 13 shown in FIG2a-4, and the gate portion 2' is a portion of a gate strip shown in FIG2a-4. Therefore, in the height direction Z, the plurality of storage subarray layers 1a include a plurality of storage cells.

In addition, as shown in FIG5 , a storage structure portion 5’ is disposed between the gate portion 2’ and the drain portion 11’, the channel portion 12’, and the source portion 13’, wherein the storage structure portion 5’ can be used to store charges; the gate portion 2’ and the drain portion 11’, the channel portion 12’, the source portion 13’, and the storage structure portion 5’ sandwiched between the gate portion 2’ and the channel portion 12’ constitute a storage unit. The storage unit can represent logic data 1 or logic data 0 by the state of whether there is a stored charge in the storage structure portion 5’, thereby realizing data storage. The storage structure portion 5' may include a charge energy trap storage structure portion, a floating gate storage structure portion, or other types of capacitive storage structure portions.

Therefore, it can be understood by those skilled in the art that in the storage array 1 shown in FIG. 2a-4, a storage structure 5 is also provided between the gate strip 2 and the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13, so that each storage unit can use its corresponding storage structure part 5' to store charge.

In addition, it should be pointed out that, in order to facilitate the diagrammatic representation of the storage structure portion 5', the sizes of the drain portion 11', the channel portion 12', the source portion 13', the gate portion 2' and the storage structure portion 5' shown in FIG. 5 are only for illustration and do not represent the actual size or proportion.

It can be understood by those skilled in the art that, as mentioned above, the portion of the gate strip 2 and the adjacent channel semiconductor strip 12 whose projections overlap on the above projection plane is used as the control gate of the storage unit. Therefore, the gate portion 2' of the gate strip 2 is the portion of the gate strip 2 that overlaps with the channel semiconductor 12 whose projections overlap on the projection plane; the portion of the channel semiconductor strip 12 that overlaps with the gate strip 2 whose projections overlap on the above projection plane is the control gate of the channel semiconductor strip. The corresponding part of the channel semiconductor strip 12 is used as the well region. Therefore, the channel part 12' in the channel semiconductor strip 12 is the part that overlaps with the projection of the gate strip 2 on the projection plane; the drain semiconductor strip 11 and the source semiconductor strip 13 are used as the drain part 11' and the source part 13', that is, the part of the drain semiconductor strip 11 and the source semiconductor strip 13 that is arranged above or below the channel part 12, as the semiconductor drain region and the semiconductor source region.

Similarly, the storage structure portion 5' is the portion of the storage structure 5 located between the channel portion 12' and the gate portion 2'.

Please continue to refer to Figures 2a to 4. Two columns of adjacent drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 are distributed on both sides of a gate strip 2; therefore, the two columns of adjacent drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 share the same gate strip 2. That is to say, for a gate strip 2, in a memory subarray layer 1a, it cooperates with the corresponding parts of the drain region semiconductor strip 11, the channel semiconductor strip 12 and the source region semiconductor strip 13 on the left to form a memory unit, and it cooperates with the corresponding parts of the drain region semiconductor strip 11, the channel semiconductor strip 12 and the source region semiconductor strip 13 on the right to form another memory unit. In other words, in the same row, there are two gate strips 2 on the left and right sides of a column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 in a memory sub-array layer 1a. Therefore, the part of it combined with the gate strip 2 on the left side forms a memory unit. , the part that cooperates with the gate strip 2 on the right side forms a memory unit. That is to say, in the same row, a column of drain region semiconductor strips 11, channel semiconductor strips 12 and source region semiconductor strips 13 in a memory subarray layer 1a are shared by the two gate strips 2 on the left and right sides.

Specifically, please refer to FIG. 6, which is a schematic diagram of a three-dimensional structure in which two storage units share the same row of drain semiconductor strips, channel semiconductor strips and source semiconductor strips; as shown in FIG. 6, the source region portion 13', the channel portion 12', and the drain region portion 11' stacked in the height direction Z cooperate with the gate portion 2' on the left and the storage structure portion 5' between the two to form a storage unit; similarly, the drain region portion 11', the channel portion 12', and the source region portion 13' cooperate with the gate portion 2' on the right and the storage structure portion 5' between the two to form another storage unit, so the two storage units share the same drain region portion 11', the channel portion 12', and the source region portion 13'.

For ease of understanding, it can be considered that the drain region 11', the channel region 12', the source region 13' cooperate with the gate region 2' on the left and the storage structure 5' between them to form a storage unit (bit); the drain region 11', the channel region 12', the source region 13' cooperate with the gate region 2' on the right and the storage structure 5' between them to form another storage unit (bit).

Therefore, returning to Figures 2a-4, a person skilled in the art can understand that a storage structure 5 is first arranged on the left and right sides of each word line hole 4, and then a gate material is filled in the word line hole 4 to form a gate strip 2, that is, two adjacent rows of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 cooperate with the storage structure 5 to share the same gate strip 2.

In conjunction with Figures 2a-3 and 5-6, in one embodiment, each of the above-mentioned drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13 is a standard strip structure. That is, the cross-section of each position of each drain semiconductor strip 11, channel semiconductor strip 12, and source semiconductor strip 13 along their respective extension directions is a standard rectangular cross-section. The storage unit corresponding to this embodiment can be specifically referred to Figures 5 and 6.

In another embodiment, in combination with FIG. 4 and FIG. 7 , FIG. 7 is a schematic diagram of a three-dimensional structure of a storage unit provided by another embodiment of the present invention; each of the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13 respectively includes a body structure 15a and a plurality of protrusions 15b. The body structure 15a extends along the column direction Y and is in a strip shape. The plurality of protrusions 15b are distributed in two rows on both sides of the body, and each row includes a plurality of protrusions 15b arranged at intervals, and each protrusion 15b extends from the body structure 15a along the row direction X in a direction away from the body structure 15a toward the corresponding gate strip 2 (word line hole 4). That is to say, in each row of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13, two rows of protrusions 15b respectively extend from the strip-shaped body structure 15a toward the gate strips 2 (word line holes 4) on both sides. Therefore, one of ordinary skill in the art can understand that the memory structure formed in the word line hole 4 The surfaces of the structure 5 and the gate strip 2 close to the drain region semiconductor strip 11, the channel semiconductor strip 12 and the source region semiconductor strip 13 are curved concave surfaces.

As shown in FIG7 , for the storage unit, the drain region 11’, the channel region 12’, and the source region 13’ have a body portion 15a’ and a protrusion 15b’, and the storage structure portion 5’ and the gate portion 2’ have a concave surface corresponding to the protrusion 15b’ to wrap the protrusion 15b away from the surface of the body structure 15a.

In the present invention, by making each of the drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 include protrusions 15b protruding toward both sides, the surface area of each of the drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 can be increased to increase the area of the corresponding region between the channel portion 12' and the gate portion 2' in each storage cell, thereby enhancing the performance of the storage block 10.

Specifically, the convex surface of the protrusion 15b away from the main structure 15a can be a curved surface or other forms of convex surface, wherein the curved surface can include a cylindrical semicircular surface, and the protrusion 15b of each column of the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13 constitutes a cylindrical semicircular column. The gate strip 2 arranged corresponding to the protrusion 15b has a concave surface facing the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13, and the concave surface is a curved surface corresponding to the convex surface of the protrusion 15b, so as to ensure that the gate strip 2 matches the channel semiconductor strip 12 at the corresponding position.

In a specific embodiment, as shown in FIG. 4 , the storage structure 5 extends in the height direction Z in the word line hole 4 and is disposed between the gate strip 2 and the adjacent drain semiconductor strip 11, channel semiconductor strip 12 and source semiconductor strip 13 to form a plurality of storage units with the corresponding portions of the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13. In the present invention, the storage structure 5 can be a charge energy trap storage structure, a floating gate storage structure or other types of capacitive dielectric structures.

Refer to FIG8 , which is a three-dimensional structural schematic diagram of a storage unit provided by another embodiment of the present invention; in this embodiment, the storage structure 5 adopts a charge energy trap storage structure. As shown in FIG8 , the storage structure part 5′ of the storage unit includes a first dielectric part 51, a charge storage part 52 and a second dielectric part 53. Among them, the first dielectric part 51 is located between the charge storage part 52 and the stacked drain part 11′, the channel part 12′ and the source part 13′, the charge storage part 52 is located between the first dielectric part 51 and the second dielectric part 53, and the second dielectric part 53 is located between the charge storage part 52 and the gate part 2′. Among them, the charge storage part 52 is used to store charge so that the storage unit can realize data storage.

Therefore, referring to FIG8 , a person skilled in the art can understand that the storage structure 5 in the storage array shown in FIG2a-4 of the present invention includes a first dielectric layer, a charge storage layer and a second dielectric layer, the first dielectric layer is located between the charge storage layer and the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13, the charge storage layer is located between the first dielectric layer and the second dielectric layer, and the second dielectric layer is located between the charge storage layer and the gate strip 2.

Among them, the first dielectric layer (first dielectric part 51) and the second dielectric layer (second dielectric part 53) can be made of insulating materials, such as silicon oxide materials. The charge storage layer (charge storage part 52) can be made of a storage material with charge energy trapping characteristics, and in particular, the charge storage layer is made of silicon nitride material. Therefore, the first dielectric layer (first dielectric part 51), the charge storage layer (charge storage part 52) and the second dielectric layer (second dielectric part 53) constitute an ONO storage structure. Specifically, you can also refer to the following process method for the storage block of the charge energy trap storage structure.

In another specific embodiment, see FIG. 9, which is a partial schematic diagram of the three-dimensional structure of a storage block 10 provided in another embodiment of the present invention. In this embodiment, the storage structure 5 is a floating gate storage structure, at least part of which extends in the word line hole 4 along the height direction Z, and is disposed between the gate strip 2 and the drain semiconductor strip 11, the channel semiconductor strip 12, and the source semiconductor strip 13.

Specifically, in conjunction with FIG. 9 and FIG. 10 , FIG. 10 is a schematic diagram of a three-dimensional structure of a storage unit provided by another embodiment of the present invention; for each storage unit, the floating gate storage structure includes a plurality of floating gates 54 and an insulating medium encapsulating the plurality of floating gates 54. As shown in FIG. 9 , it can be seen through the word line hole 4 that the plurality of floating gates 54 are arranged at intervals along the height direction Z, and each floating gate 54 is arranged on one side of the channel semiconductor strip 12 along the row direction X, and corresponds to a corresponding portion of the channel semiconductor strip 12. As shown in FIG. 10 , the insulating medium surrounding the floating gate 54 includes a first insulating dielectric layer 56 between the channel semiconductor strip 12 and the floating gate 54 , and a second insulating dielectric layer covering several other surfaces of the floating gate 54 . That is to say, there is an insulating medium between the floating gate 54 and the corresponding part of the channel semiconductor strip 12 , between two adjacent floating gates 54 , and between the floating gate 54 and the gate strip 2 . The insulating medium wraps any surface of the floating gate 54 to completely isolate the floating gate 54 from other structures.

Among them, the floating gate 54 is made of polycrystalline silicon material. The insulating medium can be made of insulating materials such as silicon oxide material. Specifically, please refer to the following process method for the storage block of the floating gate storage structure.

In the storage unit of the charge energy trap storage structure shown in FIG8 and FIG2a-4, the storage structure 5 uses a first dielectric layer (first dielectric part 51), a charge storage layer (charge storage part 52) and a second dielectric layer (second dielectric part 53) to form an ONO storage structure.

Since the characteristic of the ONO storage structure is that the implanted charge can be fixed near the implantation point, and the characteristic of the floating gate storage structure (for example, FIG. 9-11 uses polysilicon (poly) as the floating gate) is that the implanted charge can be evenly distributed on the entire floating gate 54. That is to say, in the ONO storage structure, the charge can only move in the implantation/removal direction, that is, the stored charge can only be fixed near the implantation point, and it cannot move arbitrarily in the charge storage layer, especially in the extension direction of the charge storage layer. Therefore, for the ONO storage structure, the charge storage layer only needs to be provided with insulating media on its front and back sides, and the charge stored in each storage unit will be fixed in the charge storage part 52. The charge is near the implantation point and will not move along the charge storage layer of the same layer to the charge storage part 52 in other storage cells; whereas in the floating gate storage structure, the charge can not only move in the implantation/removal direction but also move arbitrarily in the floating gate 54. Therefore, if the floating gate 54 is a continuous whole, the stored charge can move along the extension direction of the floating gate 54 and thus move to the floating gate 54 in other storage cells. Therefore, for the floating gate memory structure, the floating gate 54 of each memory unit is independent, and each surface of each floating gate needs to be covered by an insulating medium and isolated from each other to prevent the charges stored on the floating gate 54 in one memory unit from moving to the floating gates 54 in other memory units.

That is to say, for the memory cells and memory blocks of the charge energy trap memory structure shown in Figures 8 and 2a-4, the memory structure 5 can extend from top to bottom in the word line hole 4, with both sides of the charge storage layer Just set the first dielectric layer and the second dielectric layer.

In the floating gate storage structure shown in Figure 9-11, the floating gate 54 of each storage unit is independent, and each surface of each floating gate 54 needs to be covered by an insulating medium and isolated from each other. Charge stored on the floating gate 54 in one memory cell is prevented from moving to floating gates in other memory cells.

It can be understood by those skilled in the art that some portions of the insulating medium are interconnected, as long as it can be ensured that the floating gate 54 of each storage unit is independent of each other and the surface of each floating gate 54 is wrapped by the insulating medium. Therefore, in the word line hole 4, the insulating medium that wraps the floating gate 54 can extend roughly in the height direction, wrapping the floating gate 54 of each storage unit. Specifically, the storage block 10 having a floating gate storage structure can refer to the process method of the storage block having a floating gate storage structure described below.

In addition, it is understood by those skilled in the art that the storage structure 5 may also adopt other types of storage structures, such as ferroelectric or variable resistor or other types of capacitive storage structures.

In one embodiment, refer to FIG. 11, which is a three-dimensional structural schematic diagram of a storage block 10 provided in another embodiment of the present invention. FIG. 11 only shows three layers of storage subarray layers 1a, which is only for illustration. It can be understood by those skilled in the art that the storage block 10 includes a plurality of layers of storage subarray layers 1a, and every two layers of storage subarray layers 1a are separated from each other by a layer of interlayer isolation layer (composed of a plurality of interlayer isolation strips 14a). The storage block 10 also includes a plurality of word lines (WL) and a plurality of word line connection lines 7.

As mentioned above, the overlapping portion of the gate strip 2 and a channel semiconductor strip 12 in an adjacent stacked structure 1b on the above projection plane is used as the control gate of the corresponding storage cell; therefore, each gate strip 2 is used to form the control gate (CG) of a plurality of storage cells. As is known to all, the control gate of a row of storage cells needs to be connected to a corresponding word line, and a voltage is applied to the control gate of the storage cells in this row through the word line, thereby controlling the storage cells to perform various memory operations.

In the present invention, as shown in FIG. 11 , a plurality of word lines are arranged on a plurality of storage subarray layers 1a and are spaced apart in the column direction Y, and each word line extends in the row direction X. And each word line is connected to a plurality of word line connection lines 7. The plurality of word line connection lines 7 connected to the same word line extend in the height direction Z respectively, and extend to the gate bars 2 in the plurality of word line holes 4 in the same row respectively, so as to connect to the gate bars 2 in the corresponding word line holes 4, thereby realizing the connection between the current word line and the control gates of the plurality of storage cells in the same row in the plurality of storage subarray layers 1a. It can be understood that the plurality of word line holes 4 and the plurality of word line connection lines 7 are arranged in one-to-one correspondence.

Specifically, the word line of the same row can be a single word line, connecting the gate strip 2 in each word line hole 4 of the same row. Of course, the word line of the same row can also include multiple types of word lines; the gate strips 2 in the multiple word line holes 4 on the same row can be respectively connected to different types of word lines of the corresponding row. In a specific embodiment, as shown in FIG. 11, the multiple gate strips 2 of the same row are respectively used to connect two corresponding word lines, that is, each row of word lines includes two types of an odd word line 8a and an even word line 8b. It should be noted that in the present invention, an odd word line 8a and an even word line 8b connected to the multiple gate strips 2 of the same row are defined as a row of word lines, corresponding to a row of gate strips 2.

Specifically, in the plurality of storage sub-array layers 1a, a portion of the storage cells in the same row are connected to the odd word lines 8a of the corresponding row through the odd word line holes 4 of the same row; and the remaining storage cells in the same row in the plurality of storage sub-array layers 1a are connected to the even word lines 8b of the corresponding row through the even word line holes 4 of the same row. For example, the first part of the storage cells in the first row are connected to the odd word lines 8a in the first row through the first word line hole 4, the third word line hole 4, the fifth word line hole 4 ... the n-1th word line hole 4 in the first row; the second part of the storage cells in the first row are connected to the even word lines 8b in the first row through the second word line hole 4, the fourth word line hole 4, the sixth word line hole 4 ... the nth word line hole 4 in the first row, wherein n is an even number greater than 1. That is to say, the odd number lines 8a of the same row of word lines are connected to a plurality of memory cells (the first part of the memory cells) in the plurality of storage sub-array layers 1a corresponding to the odd number line holes 4 of this row; the even number lines 8b of the same row of word lines are connected to the plurality of memory cells (the second part of the memory cells) in the plurality of plurality of storage subarray layers 1a corresponding to the even number line holes 4 of this row.

As described above, since odd-numbered word line holes 4 are distributed on one side of each column of the drain semiconductor strip 11, channel semiconductor strip 12, and source semiconductor strip 13, and even-numbered word line holes 4 are distributed on the other side thereof, each of the drain semiconductor strip 11, channel semiconductor strip 12, and source semiconductor strip 13 in each storage array layer 1a can cooperate with the odd-numbered gate strip 2 in the odd-numbered word line holes 4 on one side thereof, so as to achieve the desired storage device. and the storage structure 5 disposed therebetween, are used to form a storage unit, namely the first storage unit; each drain semiconductor strip 11, channel semiconductor strip 12, and source semiconductor strip 13 in each storage array layer 1a can cooperate with the even gate strip 2 in the even word line hole 4 on the other side thereof, and the storage structure 5 disposed therebetween, to form another storage unit, namely the second storage unit.

In other words, the gate strip 2 filled in each word line hole 4 can be used to form a storage unit (bit) together with the drain semiconductor strip 11, channel semiconductor strip 12, source semiconductor strip 13 and storage structure 5 on the left side of each storage array layer 1a; or it can be used to form another storage unit (bit) together with the drain semiconductor strip 11, channel semiconductor strip 12, source semiconductor strip 13 and storage structure 5 on the right side of each storage array layer 1a.

Therefore, for the odd word line holes 4, the left half or right half of each drain semiconductor strip 11, channel semiconductor strip 12 and source semiconductor strip 13 in each storage array layer 1a is combined with the gate strip 2 in the corresponding odd word line hole 4 to form a first storage unit. Specifically, in each storage array layer 1a, each column of the drain semiconductor strip 11, the channel semiconductor strip 12, and the source semiconductor strip 13, for example, the word line hole 4 on the left side of the first column of the drain semiconductor strip 11, the channel semiconductor strip 12, and the source semiconductor strip 13 from left to right is an odd-numbered word line hole, and the drain semiconductor strip 11, the channel semiconductor strip 12, and the source semiconductor strip 13 of the column cooperate with the gate strip 2 in the odd-numbered word line hole 4 on the left side thereof to form a first storage unit. The word line hole 4 on the right side of the second row of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 from left to right is an odd word line hole. The drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 in this row cooperate with the gate strips 2 in the odd word line holes 4 on one side thereof, and are also used to form a first storage unit.

Similarly, for the even word line holes 4, each of the drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 in each storage array layer 1a cooperates with the gate strips 2 in the even word line holes 4 on the other side thereof to form a second storage unit. Specifically, in each storage array layer 1a, each column of the drain semiconductor strip 11, the channel semiconductor strip 12, and the source semiconductor strip 13, for example, the word line holes on the right side of the first column of the drain semiconductor strip 11, the channel semiconductor strip 12, and the source semiconductor strip 13 from left to right are even-numbered word line holes 4, and the drain semiconductor strip 11, the channel semiconductor strip 12, and the source semiconductor strip 13 of the column cooperate with the gate strip 2 in the even-numbered word line holes 4 on the right side thereof to form a second storage unit. The word line holes on the left side of the second column of the drain semiconductor strip 11, the channel semiconductor strip 12, and the source semiconductor strip 13 from left to right are even-numbered word line holes 4. The drain semiconductor strip 11, channel semiconductor strip 12 and source semiconductor strip 13 of the column cooperate with the gate strip 2 in the even-numbered word line hole 4 on its left side to form a second storage unit.

Therefore, in the present invention, the gate bars 2 in the memory array 1 are respectively connected to the corresponding word lines, and the gate bars 2 in the same row are connected to the corresponding word lines in the same row. Among them, in the same row, the gate bars 2 arranged in the odd word line holes 4 are connected to the odd word lines 8a in the word lines in the row; the gate bars 2 arranged in the even word line holes 4 are connected to the even word lines 8b in the word lines in the row. That is to say, all the first memory cells in the same row in the plurality of storage sub-array layers 1a are connected to the odd number lines 8a of the corresponding row through the odd gate strips 2 in the odd number line holes 4 of the same row; all the second memory cells in the same row in the plurality of storage subarray layers 1a are connected to the even number lines 8b of the corresponding row through the even gate strips 2 in the even number line holes 4 of the same row.

Of course, in other embodiments, three, four or five adjacent word line holes 4 on the same row are connected as a group, and each row of word lines includes three, four or five different types of word lines, and the gate bars 2 in each word line hole 4 in each group are connected to different types of word lines.

In addition, as shown in FIG. 11 , in the present invention, it can be defined that the number of rows of word lines is consistent with the number of rows of word line holes 4 . That is to say, as shown in Figure 11, although the gate strips 2 in the word line holes 4 of the same row are connected to a corresponding odd number line 8a and a corresponding even number line 8b, however, the gate strips 2 corresponding to the same row are connected to a corresponding odd number line 8a and a corresponding even number line 8b. An odd number line 8a and an even number line 8b of the word line hole 4 can be defined as a row of word lines, corresponding to a row of gate strips 2 (word line holes 4). That is, each row of word lines includes two types: an odd number line 8a and an even number line 8b. Then the number of rows of word lines is consistent with the number of rows of word line holes 4. In addition, it should be noted that, as shown in FIG. 11 , in each row, the left and right sides of the non-head and non-end word line holes 4 correspond to a row of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13. However, from left to right, for the word line hole 4 at the head end, only the right side corresponds to a row of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13; for the word line hole 4 at the end, only The left side corresponds to a row of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13. Therefore, it can be understood by those skilled in the art that in each row, the word line holes 4 at the head and the word line holes at the end are 4Functionally constitutes a complete word line hole.

As shown in FIG. 11 , in this embodiment, a plurality of word lines 8a or 8b may be disposed on a plurality of storage subarray layers 1a in a storage block 10, which are connected to corresponding word line holes 4 via word line connection lines 7.

Of course, it is understood by those skilled in the art that a plurality of word lines 8a or 8b can also be arranged on another stacked chip, and the stacked chip can be stacked together with the chip where the storage block 10 is located in a stacked manner and electrically connected. For example, hybrid bonding can be used to stack the stacked chip and the chip where the storage block 10 is located. The end of the word line connection line 7 in the storage block 10 away from the gate strip 2 serves as the word line connection end of the storage block 10, and is used to connect to the stacked chips stacked together with the storage block 10 in the height direction Z.

In addition, as shown in FIG. 11 , in another embodiment, the memory block 10 may further include a plurality of word line lead lines 6a or 6b, each word line 8a or 8b is further connected to a corresponding word line lead line 6a or 6b, the word line lead line 6a or 6b extends in the height direction Z and is away from the gate bar 2 relative to the word line connection line 7, and one end of the word line lead line 6a or 6b away from the word line 8a or 8b serves as a word line connection end for connecting to stacked chips stacked together in the height direction Z of the memory block 10, that is, the word line is set on a memory array chip, and the control circuit is set on another chip. Of course, those skilled in the art can understand that each word line 8a or 8b can also be connected to the control circuit on the chip where the storage block 10 is located through the corresponding word line lead 6a or 6b, that is, the related lines, storage arrays and control circuits are set on the same chip.

Please continue to refer to FIG. 12, which is a schematic diagram of the circuit connection of a portion of the memory cells of a memory block according to an embodiment of the present invention. As shown in FIG. 12, for each column of the drain semiconductor strips 11, the channel semiconductor strips 12, and the source semiconductor strips 13 of the plurality of storage array layers 1a, at the end thereof, the plurality of drain semiconductor strips 11 of the same column are respectively led out through different bit line connection lines 11a, as shown in FIG. 12, the bit line connection lines 11a extend in the height direction Z. For example, the first row of the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13, the drain semiconductor strip 11 in the first storage array layer 1a is led out at its end through a bit line connection line 11a, wherein the end of the bit line connection line 11a far from the drain semiconductor strip 11 can be used as a bit line connection end; the drain semiconductor strip 11 in the second storage array layer 1a is led out at its end through another bit line connection line 11a, and another end of the bit line connection line 11a far from the corresponding drain semiconductor strip 11 is used as another bit line connection end; ..., and so on. Therefore, each drain semiconductor strip 11 can be used as a bit line, and receives a bit line voltage through the bit line connection end.

It is understood by those skilled in the art that the memory block 10 can also be connected to other stacked chips stacked together in the height direction Z through the bit line connection terminal, and the other stacked chips are used to provide the bit line voltage to each of the semiconductor strips 11 in the drain area of the memory block 10 as the bit line through the bit line connection terminal. Of course, the bit line connection terminal can also be used to connect to the control circuit on the chip where the memory block 10 is located, that is, the related lines, the memory array 1 and the control circuit are set on the same chip.

Similarly, for each column of the drain semiconductor strip 11, channel semiconductor strip 12, and source semiconductor strip 13 of the multiple layers of storage array layers 1a, at the end thereof, the multiple source semiconductor strips 13 of the same column are led out through corresponding source connection lines 13a, and the source connection lines 13a extend in the height direction Z.

As shown in FIG. 12 , all source connection lines 13a in the memory block 10 can be respectively connected to the same common source line 13b, and a source voltage is applied to the source semiconductor strip 13 in the memory block 10 through the common source line 13b and the source connection line 13a.

Of course, it can be understood by those skilled in the art that in other embodiments, the memory block 10 may also include a plurality of common source lines 13b, such as a preset number of common source lines 13b, and the source semiconductor strips 13 in the plurality of storage array layers 1a may be connected to different plurality of common source lines 13b through corresponding source connection lines 13a according to preset rules. In addition, similar to the bit line connection line 11a corresponding to the drain semiconductor strip 11, the end of the source connection line 13a corresponding to each source semiconductor strip 13, which is far from the source semiconductor strip 13, may be used as a source connection end to receive the source voltage respectively.

Please continue to refer to FIG. 12 , the memory block 10 may further include a common source lead line 13c, which is connected to the common source line 13b, wherein the common source line 13b is connected to all source connection lines 13a in the memory block 10. The common source lead line 13c is away from the memory array 1 in the memory block 10 and extends in the height direction Z, wherein one end of the common source lead line 13c away from the common source line 13b may serve as a common source connection end for connecting with other stacked chips stacked together in the height direction Z of the memory block 10. Of course, the common source connection terminal can also be used to connect to the control circuit on the chip where the storage block 10 is located, that is, the related lines, storage arrays and control circuits are set on the same chip.

Of course, a person of ordinary skill in the art can understand that the common source line 13 b may also be provided in other stacked wafers stacked together with the memory block 10 in the height direction Z. That is to say, one end of the source connection line 13a away from the corresponding source region semiconductor strip 13 can be used as a source connection end for connection with other stacked wafers stacked together in the height direction Z of the memory block 10, so that Common source lines 13b are provided in other stacked wafers.

Similarly, for each row of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13 of the multiple layers of storage array layers 1a, at their ends, multiple channel semiconductor strips 12 in the same row are led out through corresponding well region connection lines 12a, and the well region connection lines 12a extend in the height direction Z.

As shown in FIG12 , all the well connection lines 12a in the storage block 10 are respectively connected to the same common well line 12b, so that the well voltage can be uniformly applied to all the channel semiconductor strips 12 in the storage block 10 through the common well line 12b.

Of course, it can be understood by those skilled in the art that the well region connection line 12a corresponding to each channel semiconductor strip 12 in the storage block 10 can be respectively connected to a plurality of common well region lines (or well region voltage lines) 12b to apply a well region voltage to each channel semiconductor strip 12. For example, similar to the above, the well region connection line 12a corresponding to each channel semiconductor strip 12 is far from the end of the channel semiconductor strip 12 as a well region connection terminal, which is used to receive a separate well region voltage.

Please continue to refer to FIG. 12 . All the well connection lines 12a in the memory block 10 are respectively connected to the same common well line 12b. The memory block 10 may further include a common well lead line 12c, which is connected to the common well line 12b. The common well lead line 12c is far away from the memory array 1 in the memory block 10 and extends in the height direction Z. One end of the common well lead line 12c far away from the common well line 12b may be used as a common well connection end for connecting other stacked chips stacked together in the height direction Z of the memory block 10. Of course, the common well area connection end can also be used to connect with the control circuit on the wafer where the memory block 10 is located, that is, the relevant circuits, the memory array 1 and the control circuit are arranged on the same wafer. That is to say, all the channel semiconductor strips 12 in the memory block 10 can be connected together through the common well area line 12b to jointly receive the same well area voltage. In this embodiment, the channel semiconductor strips 12 are p-type semiconductor strips, forming a p-well. All channel semiconductor strips 12 in the memory block 10 are connected together through the common well area line 12b, and receive the same well area voltage through the common well area line 12b. In addition, in this embodiment, the memory block 10 reads signals through the same common source line 13b.

Of course, a person of ordinary skill in the art can understand that the common well region line 12 b may also be provided in other stacked wafers stacked together with the memory block 10 in the height direction Z. That is to say, one end of the well connection line 12a away from the corresponding channel semiconductor strip 12 can be used as a well connection end for connecting with other stacked wafers stacked together in the height direction Z of the memory block 10, so as to Common well area lines 12b are provided in other stacked wafers.

In addition, it should be noted that, as shown in FIGS. 11 and 13 , in the present invention, various wires, such as word lines 8a or 8b, word line connection lines 7, word line lead lines 6a or 6b, common source lines 13b, common well lines 12b, etc., are all arranged on the same side of the storage array 1 in the storage block 10, that is, arranged above the storage array 1. Therefore, it is ensured that the drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13 in the storage array 1 can be formed by epitaxial growth of single crystal semiconductor strips, while deposition can only form polycrystalline semiconductor strips. Compared with polycrystalline semiconductor strips formed by deposition, the drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 formed by epitaxial growth in the present invention can obtain superior device performance and greatly improve the performance of related storage devices. Specifically, compared with the storage cell using polycrystalline semiconductor, the storage cell using single crystal semiconductor (single crystal drain semiconductor strip 11, channel semiconductor strip 12 and source semiconductor strip 13) has more interfaces. When electrons pass through polycrystalline semiconductor, they move along the interface, that is, the distance of electron movement increases and the current decreases significantly. According to actual experience, the current of the storage cell of polycrystalline semiconductor is only 1/10 of the current of the storage cell of single crystal semiconductor. Therefore, the storage block 10 of the present invention uses the storage cell of single crystal semiconductor, which can greatly improve the performance of the storage device. In addition, the storage unit current of polycrystalline semiconductors is small, which will affect the read window (Read window) between the read and write operations (PGM) and the erase operation (ERS) of the storage unit, and have a great impact on the reliability of the storage device, especially the reliability of NOR storage devices. In addition, for NOR storage devices, if hot carrier injection (HCI) is used for read and write operations, single crystal semiconductors must be used to complete it.

In addition, since the various wires in the present invention are arranged on the same side of the storage array 1 in the storage block 10, it is more convenient to perform three-dimensional bonding stacking processing with stacked chips, thereby improving the performance of related storage devices, and manufacturing chips separately, which is conducive to optimizing the process and reducing the manufacturing time.

It is understood by those skilled in the art that in some embodiments, in order to obtain better performance of the memory block 10, the most peripheral memory cells can generally be used as dummy cells and do not perform actual storage operations. For example, the memory cells included in the bottom memory array layer 1a can be used as dummy cells. In some embodiments, in the memory block 10, a row of drain semiconductor strips 11, a channel semiconductor strip 12, and a source semiconductor strip 13 are respectively disposed on the leftmost side and the rightmost side. The row of drain semiconductor strips 11, the channel semiconductor strips 12, and the source semiconductor strips 13 on the leftmost side cooperate with the gate strips 2 in the word line holes 4 on the right side thereof and the gate strips 2 and the gate strips 2 on the leftmost side and the gate strips 2 on the rightmost side ... The storage unit formed by the storage structure 5 between them, the rightmost row of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 cooperate with the gate strip 2 in the word line hole 4 on the left side and the storage structure 5 between them, and the storage unit formed by them is also a virtual storage unit and does not participate in the actual storage work.

Therefore, in the present invention, unless otherwise specified, the storage array layer 1a mentioned in the full text does not include the bottom storage array layer involved in the dummy cell; the drain semiconductor strip 11, channel semiconductor strip 12 and source semiconductor strip 13 do not include the leftmost column of drain semiconductor strip 11, channel semiconductor strip 12 and source semiconductor strip 13 and the rightmost column of drain semiconductor strip 11, channel semiconductor strip 12 and source semiconductor strip 13 involved in the dummy cell.

Therefore, as mentioned above, in one row, from left to right, for the word line hole 4 at the head end, only the right side thereof corresponds to a column of the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13; for the word line hole 4 at the end, only the left side thereof corresponds to a column of the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13. Therefore, it can be understood by a person of ordinary skill in the art that, in one row, the word line hole 4 at the head end and the word line hole 4 at the end functionally constitute a complete word line hole.

Please refer to Figures 13 to 16 together. Figure 13 is a schematic diagram of the circuit of the storage block 10 shown in Figure 11; Figure 14 is a schematic diagram of the plane of the storage block 10 shown in Figure 11; Figure 15 is a schematic diagram of the storage unit corresponding to each layer of bit lines; Figure 16 is a schematic diagram of the three-dimensional distribution of word lines and bit lines.

As shown in FIG. 13 , the memory block 10 includes a plurality of memory array layers 1a ( FIG. 13 shows six layers), and the drain semiconductor strips 11 in the plurality of memory array layers 1a serve as bit lines, such as BL-1-1, BL-1-2, BL-1-3, BL-1-4, BL-1-5, and BL-1-6; the plurality of rows in each memory array layer 1a The drain semiconductor strips 11 form a plurality of bit lines, such as BL-1-1, BL-2-1, ...; the source semiconductor strips 13 in the plurality of storage array layers 1a in the memory block 10 are connected to a common source line 13b; the well semiconductors 12 in the plurality of storage array layers 1a in the memory block 10 are connected to a common well line 12b. In addition, a gate strip 2 in the same word line hole 4 and the drain semiconductor layers 11c, channel semiconductor layers 12c' and source semiconductor layers 13c' on the left and right sides respectively form two columns of memory cells (as shown in the middle two columns of memory cells). The gate strip 2 corresponding to the odd word hole 4 is connected to the odd word line WL-a, such as the first and fourth columns of storage cells, which correspond to the first and third word line holes; the gate strip 2 corresponding to the even word hole 4 is connected to the even word line WL-b, such as the second and third columns of storage cells, which correspond to the second word line hole.

As shown in Figures 14-16, in each storage array layer 1a, the drain semiconductor strip 11, channel semiconductor strip 12 and source semiconductor strip 13 extending along the column direction, the semiconductor strip structure 1b in the same column and the gate strip 2 in the left word line hole 4 form a storage unit (bit), and form another storage unit (bit) with the gate strip 2 in the right word line hole 4. The first row of odd word line holes 4, such as hole-1, hole-3, ..., connect the first row of odd word lines WL-1-a, and the first row of even word line holes, such as hole-2, hole-4, ..., connect the first row of even word lines WL-1-b.

As shown in FIG16 , it is assumed that the storage block 10 includes a P-layer storage array layer 1a, M rows of word lines and N columns of bit lines. Each storage array layer 1a includes N columns of drain semiconductor strips 11 as bit lines, such as BL-1-1, ..., BL-N-1; for the P-layer storage array layer 1a, such as BL-1-1, ..., BL-N-P, the storage block 10 includes N*P drain semiconductor strips 11 as bit lines. M rows of word lines, such as WL-1-a/b, ..., WL-M-a/b, respectively intersect with the projections of N columns of bit lines on the projection plane defined by the row direction X and the column direction Y, forming a plurality of storage units. Among them, P, M, and N are all natural numbers greater than 0.

According to the above conditions, it can be understood by a person skilled in the art that in the same row direction X, the memory block 10 includes (N+1) word line holes 4, such as WL-hole-1-1, ..., WL-hole-1-(N+1); in the same column direction Y, the memory block 10 includes M word line holes 4, such as WL-hole-1-(N+1), ..., WL-hole-M-(N+1). One side of each column of the drain semiconductor strip 11, the channel semiconductor strip 12, and the source semiconductor strip 13 corresponds to M word line holes 4. Each row of word lines (one odd word line 8a and one even word line 8b) corresponds to (N+1) word line holes 4. As mentioned above, in the same row, the leading and trailing word line holes 4 correspond to only one storage cell in each storage sub-array layer 1a, so they can be functionally considered as a complete word line hole 4; and the other word line holes 4 correspond to two storage cells (one storage cell on each side) in each storage sub-array layer 1a. Therefore, each row of word lines corresponds to N*2*P storage cells. When N is an even number, an odd number line 8a corresponds to (N/2+1) word line holes, including the first and last word line holes 4 in the same row. That is to say, the odd number line 8a also corresponds to N/2 complete word line holes 4, corresponding to (N/2)*P*2 memory cells; an even number line 8b corresponds to N/2 word line holes 4, corresponding to (N/2)*P*2 memory cells. That is to say, the number of memory cells corresponding to the odd number line 8a and the even number line 8b are the same.

In a specific embodiment, if the storage block 10 specifically includes 8 storage array layers 1a and 1024 word lines, each word line row includes an odd word line 8a and an even word line 8b, each storage array layer 1a includes 2048 columns of drain semiconductor strips 11 as bit lines, and the storage block 10 includes 2048*8 drain semiconductor strips 11 as bit lines.

In the same row direction X, the memory block 10 includes (2048+1=2049) word line holes 4; in the same column direction Y, the memory block 10 includes 1024 word line holes 4. Each drain semiconductor strip 11 as a bit line corresponds to 1024 word line holes 4, corresponding to 1024*2 storage cells. Each row of word lines corresponds to (2048+1=2049) word line holes 4, and the word line holes 4 at the head and the end correspond to only one storage cell in each storage array layer 1a, so they functionally constitute a complete word line hole 4, which corresponds to 2048*2*8=32K storage cells. N is an even number 2048, then an odd number line 8a corresponds to (2048/2+1=1025) word line holes, which includes the first and last word line holes 4 in the same row. In other words, the odd number line 8a also corresponds to 1024 complete word line holes 4, corresponding to (2048/2)*8*2 Memory unit; an even word line 8b corresponds to 2048/2 word line holes 4, corresponding to (2048/2)*8*2 memory cells.

Storage block 10 can define 1024*2 storage cells corresponding to 1/8 word line as a storage page (128 complete word line holes 4). Storage block 10 can define 32K storage cells corresponding to a row of word lines as a sector. It can be understood that a sector corresponds to 2 word lines, (2048+1) word line holes 4 (2048 complete word line holes 4), and 2048*2*8 storage cell bits.

The storage block 10 can define 16 magnetic regions to form a sub-storage block 10 (eblk), including 0.5M storage cells (2048*2*8*16=1024*2*2*8*16=1024*1024*0.5). In a specific embodiment, the storage block 10 includes 64 sub-storage blocks 10, including 32M storage cells. Each storage block 10 shares a common source line 13b and a common well line 12b.

The storage block 10 provided in this embodiment includes a storage array 1, and the storage array 1 includes a plurality of storage units distributed in a three-dimensional array, wherein the storage array 1 includes a plurality of storage sub-array layers 1a stacked in sequence along a height direction Z, and each storage sub-array layer 1a includes a drain semiconductor layer, a channel semiconductor layer, and a source semiconductor layer stacked in the height direction Z. The drain semiconductor layer, the channel semiconductor layer, and the source semiconductor layer in each storage array layer 1a include a plurality of drain semiconductor strips 11, a channel semiconductor strip 12, and a source semiconductor strip 13 respectively distributed along the row direction X, and each of the drain semiconductor strips 11, the channel semiconductor strip 12, and the source semiconductor strip 13 is respectively distributed along the column direction X. A plurality of gate strips 2 distributed along the column direction Y are respectively arranged on both sides of each column of the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13, and each gate strip 2 extends along the height direction Z; in the height direction Z, at least a portion of each gate strip 2 coincides with a projection of a portion of the channel semiconductor strip 12 corresponding to one of the storage array layers 1a on a projection plane, and the projection plane extends along the height direction Z and the column direction Y, and a portion of the gate strip 2, a corresponding portion of the channel semiconductor strip 12, a portion of the drain semiconductor strip 11 adjacent to the corresponding portion of the channel semiconductor strip 12, and a portion of the source semiconductor strip 13 are used to form a storage unit. Compared to a two-dimensional storage array, the storage block 10 has a higher storage density.

As mentioned above, the memory block 10 of the present invention includes two types of memory cells. In one embodiment, in combination with FIG. 5, FIG. 7, FIG. 8 and FIG. 10, a memory cell is provided, which includes a drain region portion 11', a channel region portion 12', a source region portion 13' and a gate portion 2'. The drain region portion 11', the channel region portion 12' and the source region portion 13' are stacked along the height direction Z, and the gate portion 2' is located on one side of the drain region portion 11', the channel region portion 12' and the source region portion 13', and extends along the height direction Z. In the height direction Z, the projections of the gate part 2' and the channel part 12' on the projection plane extending along the height direction Z at least partially overlap, and a storage structure part 5' is arranged between the gate part 2' and the drain area part 11', the channel part 12', and the source area part 13'.

Among them, the drain area part 11' is part of the drain area semiconductor layer of the storage block 10 provided in the above embodiment, the channel part 12' is part of the channel semiconductor layer, and the source area part 13' is part of the source area semiconductor layer. The specific structure, function and stacking method of the drain area part 11', the channel part 12', the source area part 13' and the storage structure part 5' can refer to the specific structure, function and stacking method of the drain area semiconductor layer, the channel semiconductor layer, the source area semiconductor layer and the storage structure 5 in each of the above storage array layers 1a, and can achieve the same or similar technical effects, which will not be repeated here.

Wherein, when the drain region 11', the channel 12', and the source region 13' are strip structures, and the storage structure 5' is a charge energy trap storage structure, the specific structure of the storage unit can be seen in FIG5, and the other structures of the storage unit can be seen in the above description of FIG5. When the drain region 11', the channel 12', and the source region 13' all include a body structure 15a and a plurality of protrusions 15b, and the storage structure 5' is a charge energy trap storage structure, the specific structure of the storage unit can be seen in FIG7, and the other structures of the storage unit can be seen in the above description of FIG7. When the storage structure part 5' is a floating gate storage structure part, the specific structure of the storage unit can be found in Figures 10 and 11, and the other structures of the storage unit can be found in the above-mentioned descriptions of Figures 10 and 11.

See Figure 17, which is a flow chart of a storage block manufacturing method provided in an embodiment of the present invention. In this embodiment, a storage block manufacturing method is provided, which can be used to prepare the storage block 10 provided in Figures 2a to 4 of the above-mentioned embodiment to obtain a storage block 10 with a higher storage density; wherein the storage structure 5 of the storage block 10 is a charge energy trap storage structure. Specifically, the method includes:

Method S21: Provide a semiconductor substrate.

See FIG. 18, which is a side view of a semiconductor substrate provided by an embodiment of the present invention. The semiconductor substrate includes a substrate 81, a first single crystal sacrificial semiconductor layer 82 disposed on the substrate 81, two layers of storage array layers 1a and second single crystal sacrificial semiconductor layers 14 formed on the first single crystal sacrificial semiconductor layer 82 and alternating in sequence, until the top two layers of storage array layers 1a are formed.

The substrate 81 may be a single crystal substrate 81; specifically, it may be a single crystal silicon material. The first single crystal sacrificial semiconductor layer 82 and/or the second single crystal sacrificial semiconductor layer 14 may be silicon germanium (SiGe). A plurality of storage sub-array layers 1a are stacked in sequence along the height direction Z perpendicular to the substrate 81. Each storage sub-array layer 1a includes a drain semiconductor layer 11c, a channel semiconductor layer 12c' and a source semiconductor layer 13c' stacked along the height direction Z. Moreover, in the height direction Z, two adjacent storage array layers 1a can share the source region, including the sequentially stacked drain semiconductor layer 11c, channel semiconductor layer 12c', source semiconductor layer 13c', channel semiconductor layer 12c' and drain semiconductor layer 11c, to share the same source semiconductor layer 13c'. Therefore, for the storage array layers 1a with a common source, a second single crystal sacrificial semiconductor layer 14 is provided on every two layers of storage array layers 1a to isolate them from the other two layers of storage array layers 1a. The second single crystal sacrificial semiconductor layer 14 can be made of silicon germanium (SiGe) semiconductor material.

It should be noted that the structure shown in FIG. 18 is only an exemplary depiction of a portion of the structure of the semiconductor substrate; those skilled in the art can understand that what is actually arranged between the first single crystal sacrificial semiconductor layer 82 and the second single crystal sacrificial semiconductor layer 14 shown in FIG. 18 are two storage sub-array layers 1a having a shared source region semiconductor layer 13c'. For the sake of simplicity, the figure only schematically shows one layer of storage sub-array layer 1a for illustration only.

In a specific implementation, method S21 may specifically include:

Method S211a: Providing a substrate 81.

Among them, the substrate 81 can be a single crystal substrate 81; specifically, it can be a single crystal silicon material.

Method S212a: sequentially forming a plurality of storage sub-array layers 1a on the substrate 81 along the height direction Z.

Among them, method S212a specifically includes:

Method a: Form a first single crystal sacrificial semiconductor layer 82 on the substrate 81 by epitaxial growth.

Among them, the first single crystal sacrificial semiconductor layer 82 can be silicon germanium (SiGe).

Method b: Two layers of storage array layers 1a and second single crystal sacrificial semiconductor layers 14 are alternately formed on the first single crystal sacrificial semiconductor layer 82 by epitaxial growth. Then, two layers of storage array layers 1a are formed, and the second single crystal sacrificial semiconductor layer 14 and two layers of storage array layers 1a with a common source can be repeatedly stacked until the top two layers of storage array layers with a common source are formed.

The material of the second single crystal sacrificial semiconductor layer 14 is the same as that of the first single crystal sacrificial semiconductor layer 82, and can also be silicon germanium (SiGe).

It is understood by those skilled in the art that the purpose of first arranging the first single crystal sacrificial semiconductor layer 82 on the substrate 81 is to prevent the plurality of storage array layers 1a thereon from directly contacting the substrate 81 and causing leakage. However, as mentioned above, the device performance of the bottom storage array layer 1a in the memory block of the present invention is poor, and therefore, the memory cells in the bottom storage array layer 1a are generally used as virtual memory cells and do not participate in the actual memory operation. Therefore, it can be understood by those skilled in the art that the first single crystal sacrificial semiconductor layer 82 may not be disposed on the substrate 81, and a single-layer storage array layer 1a or a two-layer storage array layer 1a with a common source as a virtual storage unit may be directly formed on the substrate 81, and then the first single crystal sacrificial semiconductor layer 82 and the two-layer storage array layer 1a with a common source are alternately formed thereon by epitaxial growth until the top two-layer storage array layer 1a with a common source is formed. That is to say, the lowermost storage sub-array layer 1a of the virtual memory unit or the two common-source storage sub-array layers 1a will not participate in the actual memory operation. Therefore, it can also prevent leakage to the substrate 81.

Among them, two adjacent storage array layers 1a share a source region, and the formation method of each two storage array layers 1a sharing a source region includes:

Method b1: Form a first doped type first single crystal semiconductor layer on the lower first single crystal sacrificial semiconductor layer 82 or the second single crystal sacrificial semiconductor layer 14 by epitaxial growth.

Specifically, semiconductor material gas and first type doping ion gas can be introduced simultaneously to form a first doping type first single crystal semiconductor layer by epitaxial growth on the lower first single crystal sacrificial semiconductor layer 82 or the second single crystal sacrificial semiconductor layer 14. The first single crystal semiconductor layer serves as the drain semiconductor layer 11c (or source semiconductor layer 13c'). The first doping ions can be arsenic ions. The semiconductor material can be an existing semiconductor material for forming the drain region (or source region).

Method b2: Forming a second single crystal semiconductor layer of a second doping type on the first single crystal semiconductor layer by epitaxial growth.

Specifically, a semiconductor material gas and a second type of doping ion gas may be introduced simultaneously to form a second single crystal semiconductor layer of a second doping type on the first single crystal semiconductor layer by epitaxial growth. The second single crystal semiconductor layer serves as the channel semiconductor layer 12c'. The second doping ions may be BF2 ⁺ ions. The semiconductor material may be an existing semiconductor material for forming a well region.

Method b3: Forming a third single crystal semiconductor layer of the first doping type on the second single crystal semiconductor layer by epitaxial growth.

Specifically, semiconductor material gas and first type doping ion gas can be introduced simultaneously to form a third single crystal semiconductor layer of the first doping type on the second single crystal semiconductor layer by epitaxial growth. The third single crystal semiconductor layer serves as the source semiconductor layer 13c' (or the drain semiconductor layer 11c). Wherein, the first doping ion can be arsenic ion. The semiconductor material can be an existing semiconductor material for forming a source region (or a drain region).

In the specific implementation process of method S212a, a second single crystal sacrificial semiconductor layer 14 is further generated between every two storage array layers 1a. Moreover, in the height direction Z, each adjacent two storage array layers 1a separated by the second single crystal sacrificial semiconductor layer 14 include a drain semiconductor layer 11c, a channel semiconductor layer 12c', a source semiconductor layer 13c', a channel semiconductor layer 12c' and a drain semiconductor layer 11c stacked in sequence to share the same source semiconductor layer 13c'.

Method b4: Forming a fourth single crystal semiconductor layer of the second doping type on the third single crystal semiconductor layer by epitaxial growth.

The specific implementation of method b4 is similar to method b2. The fourth single crystal semiconductor layer is used as a channel semiconductor layer 12c'.

Method b5: Form a fifth single crystal semiconductor layer of the first doping type on the fourth single crystal semiconductor layer by epitaxial growth.

The specific implementation of method b5 is similar to method b1. The fifth single crystal semiconductor layer is used as the drain semiconductor layer 11c (or source semiconductor layer 13c').

Among them, the first single crystal semiconductor layer, the second single crystal semiconductor layer and the third single crystal semiconductor layer constitute a storage sub-array layer 1a; the third single crystal semiconductor layer, the fourth single crystal semiconductor layer and the fifth single crystal semiconductor layer constitute another storage sub-array layer 1a; the two storage sub-array layers 1a share the third single crystal semiconductor layer as a common source region semiconductor layer 13c'.

It can be understood that in the specific implementation process, after method b5, a second single crystal sacrificial semiconductor layer 14 is formed on the fifth single crystal semiconductor layer. Afterwards, methods b1-b5 are continued to be performed on the second single crystal sacrificial semiconductor layer 14 until a preset number of storage array layers 1a are formed.

That is to say, a second single crystal sacrificial semiconductor layer 14 is formed between every two memory subarray layers 1a. Moreover, in the height direction Z, each adjacent two memory subarray layers 1a separated by the second single crystal sacrificial semiconductor layer 14 include a drain region semiconductor layer 11c, a channel semiconductor layer 12c', and a source region semiconductor layer stacked in sequence. 13c', the channel semiconductor layer 12c' and the drain region semiconductor layer 11c, so as to share the same source region semiconductor layer 13c'.

Method S213a: forming a first hard mask layer 83 on a plurality of storage array layers 1a, and opening a plurality of isolation barrier holes 31 in the first hard mask layer 83 and a plurality of storage array layers 1a, and filling the isolation barrier holes 31 with isolators to form a plurality of isolation walls 3, so as to form a semiconductor substrate.

Among them, the first hard mask layer 83 can be made of silicon dioxide material or silicon nitride material.

Specifically, see FIG. 19 , which is a top view of a plurality of isolation barrier holes 31 formed on the storage array layer 1a. The plurality of isolation barrier holes 31 may be formed by etching. The isolation barrier holes 31 are arranged in a matrix in the row direction X and the column direction Y, and each isolation barrier hole 31 extends along the height direction Z to the surface of the substrate 81. The specific structure of the isolation wall 3 formed in the isolation barrier hole 31 can be seen in FIG. 20 , which is a top view of a plurality of isolation walls 3 formed in the isolation barrier hole 31 shown in FIG. 19 . Specifically, the isolation wall 3 near the edge of the memory block 10 in the column direction Y is further extended in the column direction Y to the edge of the memory block 10 in the column direction Y to ensure that the isolation wall 3 at the edge of the column direction Y can completely isolate two adjacent columns of stacking structures 1b. Specifically, in some embodiments, the isolation wall 3 near the Y edge of the column direction of the storage block 10 is a T-shaped isolation wall 3, that is, it includes a transverse portion and a protruding portion toward the Y edge of the column direction of the storage block 10, and the protruding portion is connected to the Y edge of the column direction of the storage block 10 to completely isolate the two adjacent columns of stacked structures 1b to prevent short circuits between the two columns of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13. The isolation wall 3 and the first hard mask layer 83 can be made of the same material.

In another implementation, method S21 specifically includes:

Method S211b: Providing a substrate 81.

Method S212b: forming a plurality of isolation walls 3 on the substrate 81, wherein the plurality of isolation walls 3 are arranged in a matrix in the row direction X and the column direction Y, and each isolation wall 3 extends along a height direction Z perpendicular to the substrate 81.

Method S213b: Form multiple storage array layers 1a in sequence on the substrate 81 and between the isolation wall 3 along the height direction Z.

Among them, the specific implementation process of forming a plurality of storage sub-array layers 1a is the same or similar to the specific implementation process of forming a plurality of storage sub-array layers 1a in the above method S212a, and can achieve the same or similar technical effects, which can be specifically referred to above.

Method S214b: Form a first hard mask layer 83 on the above structure to form a semiconductor substrate.

Specifically, a first hard mask layer 83 can be formed on the product structure after being processed by method S213b, and the first hard mask layer 83 is located on a side surface of the plurality of storage sub-array layers 1a away from the substrate 81.

Method S22: A plurality of word line holes are opened on the semiconductor substrate to divide each storage array layer into a plurality of columns of drain semiconductor strips, channel semiconductor strips and source semiconductor strips along the row direction.

In the specific implementation process, method S22 specifically includes:

Method S221: Form a plurality of word line openings 831 on the first hard mask layer 83.

See FIG. 21 , which is a top view of forming a plurality of word line openings 831 and word line holes 4 on a semiconductor substrate; a plurality of word line openings 831 may be formed on the first hard mask layer 83 by etching. The plurality of word line openings 831 are arranged in a matrix in the row direction X and the column direction Y.

Method S222: Using the word line opening 831 as a mask, the plurality of storage sub-array layers 1a under the first hard mask layer 83 are etched to form a plurality of word line holes 4.

See FIG. 21 to FIG. 23 , FIG. 22 is a cross-sectional view of the product corresponding to FIG. 21 in the E direction; FIG. 23 is a cross-sectional view of the product corresponding to FIG. 21 in the F direction. Specifically, the word line holes 4 can be processed by etching. As shown in FIG. 21 , a plurality of word line holes 4 are arranged at intervals at positions different from the isolation wall 3; and a plurality of word line holes 4 are arranged in a matrix in the row direction X and the column direction Y, and each storage array layer 1a is divided into a plurality of columns of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 along the row direction X. As shown in FIG. 22 , each word line hole 4 extends along the height direction Z, and the left and right sides (such as the left and right sides in the orientation of FIG. 22 ) of each word line hole 4 at the non-edge part respectively expose two columns of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13 of a plurality of storage array layers 1a. Among them, the left and right opposite sides of each word line hole 4 are the drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13; the front and rear opposite sides are the isolation walls 3. In this step, an etching liquid with a high etching ratio for semiconductor materials and a low etching ratio for isolation walls 3 can be used to process and form the word line hole 4. In addition, as shown in FIG. 2a-4, the leftmost edge word line hole 4 has only one row of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13 on the right side; similarly, the rightmost edge word line hole 4 has only one row of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13 on the left side. However, it can be understood by those skilled in the art that the leftmost edge word line hole 4 and the rightmost edge word line hole 4 can be considered to be combined to form a complete word line hole, and the difference between the edge word line holes 4 will not be specifically pointed out in the following.

As shown in FIG2 and FIG4 , a plurality of word line holes 4 cooperate with a plurality of isolation walls 3 to divide the drain semiconductor layer 11c in each storage array layer 1a into a plurality of drain semiconductor strips 11 spaced apart along the row direction X; divide the channel semiconductor layer 12c' into a plurality of channel semiconductor strips 12 spaced apart along the row direction X; and divide the source semiconductor layer 13c' into a plurality of source semiconductor strips 13 spaced apart along the row direction X. The other specific structures and functions of each of the drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13 can be found in the above related descriptions, and will not be repeated here. In addition, as shown in FIG. 23 , the interior of the isolation wall 3 can be made of silicon oxide, and the outside is wrapped with a layer of silicon nitride material, and the silicon nitride material wrapped outside is the same as the material of the first hard mask layer 83.

In the specific implementation process, refer to Figures 24a-24b, Figure 24a is a schematic diagram of the structure shown in Figure 21 after being processed by method S223; Figure 24b is a schematic diagram of the structure shown in Figure 24a after being filled with insulating material; after method S222, it also includes:

Method S223: Using the word line hole 4, remove the first single crystal sacrificial semiconductor layer 82 and the second single crystal sacrificial semiconductor layer 14.

Specifically, the first single crystal sacrificial semiconductor layer 82 and the second single crystal sacrificial semiconductor layer 14 can be removed by etching.

Method S224: Deposition is performed in the area where the first single crystal sacrificial semiconductor layer 82 and the second single crystal sacrificial semiconductor layer 14 are removed, so as to fill the area where the first single crystal sacrificial semiconductor layer 82 and the second single crystal sacrificial semiconductor layer 14 are removed with insulating material, thereby replacing the insulating isolation layer 14' with the first single crystal sacrificial semiconductor layer 82 and the second single crystal sacrificial semiconductor layer 14.

Among them, the insulating material can be filled by atomic layer deposition. The insulating material can be specifically silicon oxide. It can be understood by those skilled in the art that after the first single crystal sacrificial semiconductor layer 82 and the second single crystal sacrificial semiconductor layer 14 are removed in method S223, the isolation wall 3 can fully support the adjacent stacking structure 1b, so as to facilitate the subsequent execution of method S224.

In addition, it can be understood by those skilled in the art that in some embodiments, the storage array 1 further includes a support column 16. Specifically, see Figure 25a and Figure 25b, Figure 25a is a three-dimensional structural schematic diagram of a storage array provided in an embodiment of the present invention; Figure 25b is a partial plan schematic diagram of a storage array provided in an embodiment of the present invention.

As shown in Figures 25a and 25b, the storage array 1 also includes a plurality of support columns 16, and the support columns 16 extend along the height direction Z of the storage array 1.

As described above, the first single crystal sacrificial semiconductor layer 82 and the second single crystal sacrificial semiconductor layer 14 need to be replaced with the insulating isolation layer 14'. In this step, the first single crystal sacrificial semiconductor layer 82 and the second single crystal sacrificial semiconductor layer 14 are partially replaced with the insulating isolation layer 14', but in the subsequent steps, according to the need for electrical isolation, all of the first single crystal sacrificial semiconductor layer 82 and the second single crystal sacrificial semiconductor layer 14 will be replaced with the insulating isolation layer 14'. That is to say, during the manufacturing process of the memory array 1, after the first single crystal sacrificial semiconductor layer 82 and/or the second single crystal sacrificial semiconductor layer 14 is etched away, the storage sub-array layer 1a in the relevant areas is suspended. In these relevant areas, if isolation walls 3 are provided, the isolation walls 3 can fully support the suspended storage sub-array layers 1a in these areas and prevent the storage sub-array layer 1a from collapsing.

However, in some areas, there may be no isolation wall 3. For example, in the drain/source lead-out area, the storage array layer 1a in this area does not need to manufacture storage cells. The drain semiconductor strip 11, the source semiconductor strip 13 and/or the channel semiconductor strip 12 in the storage array layer 1a in this area need to be led out and connected to the corresponding various types of wires. Therefore, in these areas, a plurality of isolation walls 3 need to be set between two rows of stacked structures 1b. In this way, during the manufacturing process of the storage array 1, after etching the first single crystal sacrificial semiconductor layer 82 and/or the second single crystal sacrificial semiconductor layer 14 in the stacked structure 1b in these regions, the support pillars 16 can fully support the suspended storage sub-array layer 1a, prevent the storage sub-array layer 1a from collapsing, support the frame of the storage array 1, and maintain the structural stability of the storage array 1.

A person of ordinary skill in the art can understand that the support column 16 and the isolation wall 3 can be made of the same material and made in the same process steps. That is to say, the isolation wall 3 and the support column 16 are similar in nature, except that the isolation wall 3 is set in the area of the storage array 1 where the storage unit needs to be manufactured, and it plays a supporting and forming role in the manufacturing process of the storage array 1. The function of the word line holes 4; and the support pillars 16 are formed in other areas of the memory array 1 that do not require the production of memory cells, such as the sink/source lead-out area, and play a supporting role during the manufacturing process of the memory array 1 . Of course, in some other embodiments, the support column 16 can also be arranged in the area of the storage array 1 where the storage unit needs to be manufactured. For example, when the distance between two adjacent isolation walls 3 is far, the isolation walls 3 cannot provide enough space. When the supporting function is needed, a supporting column 16 can be set in this area as needed to assist the isolation wall 3 in providing supporting force. The supporting column 16 can be set according to actual needs, and the present invention does not limit this.

The material of the supporting column 16 can be silicon oxide or silicon nitride.

Method S23: Forming storage structures on at least one side of each word line hole that exposes the drain semiconductor strip, the channel semiconductor strip, and the source semiconductor strip, respectively, wherein the storage structure is a charge trap storage structure.

The product structure after being processed by method S23 can be specifically seen in Figure 26, which is a schematic diagram of the structure shown in Figure 24b after being processed by method S23. In the specific implementation process, method S23 specifically includes:

Method S231: Depositing a first dielectric layer on a semiconductor substrate having a word line hole 4.

Specifically, a first dielectric layer is deposited in each word line hole 4 and on the surface of the first hard mask layer 83 away from the substrate 81. The first dielectric layer in each word line hole 4 covers the surface of the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13 exposed on both sides of the word line hole 4. For example, in conjunction with FIG. 4, the first stacked structure 1b and the second stacked structure 1b are partially exposed through the word line hole 4 of the first row and the second column (hereinafter referred to as the first word line hole 4), and the first dielectric layer in the first word line hole 4 covers the portion of the first column storage structure 5 exposed through the first word line hole 4, and covers the portion of the second column semiconductor strip structure 1b exposed through the first word line hole 4.

Method S232: Depositing a charge storage layer on the first dielectric layer.

The charge storage layer is located on a surface of the first dielectric layer that is away from the semiconductor strip structure 1b.

Method S233: Depositing a second dielectric layer on the charge storage layer.

The second dielectric layer is located on the side of the charge storage layer facing away from the first dielectric layer.

Method S24: Fill each word line hole with a gate material to form a plurality of gate strips.

The product structure after being processed by method S24 is specifically shown in FIG5 and FIG27. FIG27 is a schematic diagram of the structure shown in FIG26 after being processed by method S24. As shown in FIG5, at least a portion of each gate strip 2 overlaps with a portion of a channel semiconductor strip 12 corresponding to one of each storage array layer 1a on a projection plane, and the projection plane extends along the height direction Z and the column direction Y. The portion of the gate strip 2, the corresponding portion of the channel semiconductor strip 12, the portion of the drain semiconductor strip 11 and the portion of the source semiconductor strip 13 adjacent to the corresponding portion of the channel semiconductor strip 12, and the portion of the charge energy trap storage structure constitute a storage unit.

As mentioned above, in this embodiment, the storage structure 5 is a charge trap storage structure, such as an ONO type charge trap storage structure, so that the implanted charge can be fixed near the implantation point, and the charge can only move in the implantation/removal direction (roughly perpendicular to the extension direction of the charge storage layer 52), and cannot move freely in the charge storage layer 52, especially cannot move in the direction of the implantation/removal direction. Move in the extension direction of the charge storage layer 52. For the charge energy trap storage structure, the charge storage layer 52 only needs to be provided with an insulating medium on its front and back sides. The charge stored in each storage unit will be fixed near the implantation point of the charge storage part, and will not move along the charge storage layer 52 of the same layer to the charge storage part in other storage units. Therefore, in the corresponding process method, it is only necessary to form a first dielectric layer 51 and a second dielectric layer 53 on both sides of the charge storage layer 52 to separate the charge storage layer 52 from the drain semiconductor strip 11, the channel semiconductor strip 12, the source semiconductor strip 13 and the gate strip 2, and the process is relatively simple.

Specifically, the manufacturing method of the memory block 10 can be used to prepare the memory blocks involved in the following embodiments. Referring to FIG. 2 to FIG. 4 , the memory block 10 includes a memory array 1 . The storage array 1 includes a plurality of storage units arranged in a three-dimensional array, wherein the storage array 1 includes a plurality of stacked structures 1b arranged along a row direction X, each stacked structure 1b extends along a column direction Y, and each stacked structure 1b includes a drain semiconductor strip 11, a channel semiconductor strip 12, and a source semiconductor strip 13 stacked along a height direction Z, each drain semiconductor strip 11, channel semiconductor strip 12, and source semiconductor strip 13 extends along the column direction Y, and each drain semiconductor strip 11, channel semiconductor strip 12, and source semiconductor strip 13 is a single crystal semiconductor strip.

A plurality of gate strips 2 distributed along the column direction Y are respectively arranged on both sides of each stacked structure 1b, and each gate strip 2 extends along the height direction Z. In the height direction Z, at least a portion of each gate strip 2 overlaps with a projection of a portion of a corresponding channel semiconductor strip 12 on a projection plane, and the projection plane extends along the height direction Z and the column direction Y; a portion of the gate strip 2, a corresponding portion of the channel semiconductor strip 12, a portion of the drain semiconductor strip 11 adjacent to the corresponding portion of the channel semiconductor strip 12, and a portion of the source semiconductor strip 13 are used to form a storage unit. Specifically, a charge energy trap storage structure is provided between each gate strip 2 and the drain semiconductor strip 11, channel semiconductor strip 12 and source semiconductor strip 13 in the plurality of storage array layers 1a. The specific structure and function of the charge energy trap storage structure, as well as the positional relationship between the charge energy trap storage structure and the storage array 1, can be found in the above-mentioned related description.

Specifically, each stacking structure 1b includes multiple stacking substructures, and each stacking substructure includes a drain semiconductor strip 11, a channel semiconductor strip 12, a source semiconductor strip 13, a channel semiconductor strip 12, and a drain semiconductor strip 11 stacked in sequence along the height direction Z to share the same source semiconductor strip 13. Specifically, an isolation layer (i.e., the above-mentioned insulating isolation layer 14') is provided between two adjacent stacking substructures to isolate them from each other.

A plurality of isolation walls 3 distributed along the column direction Y are respectively arranged on both sides of the stacking structure 1b, and each isolation wall 3 extends along the height direction Z and the row direction X to isolate at least part of two adjacent columns of stacking structures 1b, wherein, in the manufacturing process shown above, the isolation wall 3 further serves as a supporting structure to support the two adjacent columns of stacking structures 1b, facilitating the subsequent manufacturing process. Of course, after the manufacturing process, the isolation wall 3 can also serve as a supporting structure to support the two adjacent columns of stacking structures 1b. The isolation wall 3 near the edge of the memory block 10 in the column direction Y is a T-shaped isolation wall to completely isolate the two adjacent columns of stacked structures 1b. Of course, the isolation wall 3 at the edge of the column direction Y can also be in other forms, such as extending in the column direction Y to the edge of the memory block 10 in the column direction Y, etc., as long as it can completely isolate the two adjacent columns of stacked structures 1b at the edge of the column direction Y.

In the row direction Y, a gate strip 2 is filled between two adjacent isolation walls 3 in the same row; parts of two adjacent rows of stacked structures 1b share the same gate strip 2.

The other structures and functions of the storage block 10 provided in this embodiment can be found in the specific description of the storage block 10 provided in any of the above embodiments where the storage structure is a charge energy trap storage structure, which will not be elaborated here.

The storage unit corresponding to the above process method includes: a drain area 11', a channel area 12', a source area 13' and a gate area 2', wherein the drain area 11', the channel area 12' and the source area 13' are stacked along the height direction Z, and the gate area 2' is located on one side of the drain area 11', the channel area 12' and the source area 13', and extends along the height direction Z; wherein, in the height direction Z, the projections of the gate area 2' and the channel area 12' on a projection plane at least partially overlap, and the projection plane extends along the height direction Z and the extension direction of the drain area 11', the channel area 12' and the source area 13', and a charge energy trap storage structure portion is arranged between the gate area 2' and the drain area 11', the channel area 12' and the source area 13'.

The specific structure and position relationship of the charge energy trap storage structure part can be found in the above-mentioned related description. The other structures and functions of the storage unit can be found in the related description of the storage unit in which the storage structure part 5' involved in the above-mentioned embodiment is the charge energy trap storage structure part, which will not be repeated here.

The above is only the implementation method of the present invention, and is not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process change made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

S21,S22,S23,S24:Methods

Claims (18)

A manufacturing method of a storage block, characterized in that it includes: providing a semiconductor substrate, wherein the semiconductor substrate includes a substrate and a plurality of storage sub-array layers formed on the substrate, the plurality of storage sub-array layers are stacked in sequence along a height direction perpendicular to the substrate, each of the storage sub-array layers includes a drain semiconductor layer, a channel semiconductor layer and a source semiconductor layer stacked in the height direction, wherein the drain semiconductor layer, the channel semiconductor layer and the source semiconductor layer are stacked in the height direction. The source semiconductor layer is a single crystal semiconductor layer; a plurality of word line holes are opened on the semiconductor substrate to divide each storage sub-array layer into a plurality of drain semiconductor strips, channel semiconductor strips and source semiconductor strips along the row direction, wherein the plurality of word line holes are arranged in a matrix in the row direction and the column direction, each of the word line holes extends along the height direction, and at least one side of each of the word line holes exposes at least one column of the plurality of storage sub-array layers. The drain semiconductor strip, the channel semiconductor strip and the source semiconductor strip are exposed in each word line hole to form a storage structure, wherein the storage structure is a charge trap storage structure; a gate material is filled in each word line hole to form a plurality of gate strips, wherein each gate strip has at least a portion corresponding to one of each storage sub-array layer. The projections of the channel semiconductor strip on a projection plane overlap, and the projection plane extends along the height direction and the column direction. The gate strip, the corresponding part of the channel semiconductor strip, the charge energy trap storage structure sandwiched between the gate strip and the corresponding part of the channel semiconductor strip, the drain semiconductor strip and the source semiconductor strip adjacent to the corresponding part of the channel semiconductor strip form a storage unit. The process method as described in claim 1, wherein the semiconductor substrate is provided, including: providing the substrate; sequentially forming a plurality of the storage array layers on the substrate along the height direction; forming a first hard mask layer on the plurality of the storage array layers, and opening a plurality of isolation barrier holes in the first hard mask layer and the plurality of the storage array layers, filling the isolation barrier holes with isolators to form a plurality of isolation walls, so as to form the semiconductor substrate, wherein the isolation barrier holes are arranged in a matrix in the row direction and the column direction, and each of the isolation barrier holes extends along the height direction to the substrate. The process method as described in claim 2, wherein the substrate is a single crystal substrate; the plurality of storage array layers are sequentially formed on the substrate along the height direction, including: forming a first single crystal sacrificial semiconductor layer or a virtual storage array layer on the substrate by epitaxial growth; Two layers of storage sub-array layers and a second single crystal sacrificial semiconductor layer are alternately formed on the virtual storage sub-array layer by epitaxial growth until the top two layers of the storage sub-array layer are formed; or, a second single crystal sacrificial semiconductor layer and two layers of storage sub-array layers are alternately formed on the virtual storage sub-array layer by epitaxial growth. The process method as described in claim 3, wherein two adjacent storage array layers share a source region, and each of the two storage array layers sharing the source region is formed by: forming a first single crystal semiconductor layer of a first doping type by epitaxial growth on the first single crystal sacrificial semiconductor layer or the second single crystal sacrificial semiconductor layer; and forming a first single crystal semiconductor layer of a first doping type by epitaxial growth on the first single crystal semiconductor layer. A second single crystal semiconductor layer of a second doping type is formed by epitaxial growth; a third single crystal semiconductor layer of a first doping type is formed by epitaxial growth on the second single crystal semiconductor layer; a fourth single crystal semiconductor layer of a second doping type is formed by epitaxial growth on the third single crystal semiconductor layer; a fourth single crystal semiconductor layer of a second doping type is formed by epitaxial growth on the fourth single crystal semiconductor layer; a fifth single crystal semiconductor layer of the first doping type; wherein the first single crystal semiconductor layer and the fifth single crystal semiconductor layer of the first doping type are used as the draw region semiconductor layer, the second single crystal semiconductor layer and the fourth single crystal semiconductor layer of the second doping type are used as the channel semiconductor layer, and the third single crystal semiconductor layer of the first doping type is used as the source region semiconductor layer The first single crystal semiconductor layer, the second single crystal semiconductor layer and the third single crystal semiconductor layer constitute a storage sub-array layer; the third single crystal semiconductor layer, the fourth single crystal semiconductor layer and the fifth single crystal semiconductor layer constitute another storage sub-array layer; the two storage sub-array layers share the third single crystal semiconductor layer as the shared source region semiconductor layer. The process method as described in claim 3, wherein the opening of a plurality of word line holes on the semiconductor substrate comprises: forming a plurality of word line openings on the first hard mask layer, wherein the plurality of word line openings are arranged in a matrix in the row direction and the column direction; using the first hard mask layer having the word line openings as a photomask, etching the plurality of storage sub-array layers under the first hard mask layer to form a plurality of word line holes, wherein the plurality of word line holes cooperate with the plurality of isolation walls to divide each layer of the storage sub-array layer into a plurality of rows of drain semiconductor strips, channel semiconductor strips and source semiconductor strips along the row direction. The process method as described in claim 5 further comprises: using the word line hole to remove the first single crystal sacrificial semiconductor layer and the second single crystal sacrificial semiconductor layer; depositing in the area where the removed first single crystal sacrificial semiconductor layer and the second single crystal sacrificial semiconductor layer are located, so as to fill the area where the removed first single crystal sacrificial semiconductor layer and the second single crystal sacrificial semiconductor layer are located with insulating material, thereby replacing the first single crystal sacrificial semiconductor layer and the second single crystal sacrificial semiconductor layer with an insulating isolation layer. The process method as described in claim 1, wherein the charge energy trap storage structure is formed on both sides of the portion of the drain semiconductor strip, the channel semiconductor strip and the source semiconductor strip exposed in each word line hole, comprising: depositing a first dielectric layer on the surface of the semiconductor substrate having the word line hole, wherein the first dielectric layer covers the portions of the drain semiconductor strip, the channel semiconductor strip and the source semiconductor strip exposed on both sides of the word line hole; depositing a charge storage layer on the first dielectric layer; and depositing a second dielectric layer on the charge storage layer. The process method as described in claim 7, wherein the gate material is filled in each word line hole, including: the gate material is filled in each word line hole to form a plurality of gate strips, wherein the charge energy trap storage structure is arranged between each gate strip and the drain semiconductor strip, channel semiconductor strip and source semiconductor strip in the plurality of storage sub-array layers. A storage block is characterized in that it comprises: a storage array, comprising a plurality of storage units arranged in a three-dimensional array, wherein the storage array comprises a plurality of stacking structures arranged along a row direction, each stacking structure extends along a column direction, and each stacking structure comprises a drain semiconductor strip, a channel semiconductor strip, and a source semiconductor strip stacked along a height direction, each of the drain semiconductor strip, the channel semiconductor strip, and the source semiconductor strip extends along the column direction; a plurality of gate strips arranged along the column direction are arranged on both sides of the stacking structure, each of the gate strips extends along the height direction; in the height direction, each of the gate strips has at least The projection of a portion of the gate bar and a portion of the corresponding channel semiconductor bar on a projection plane overlaps, and the projection plane extends along the height direction and the column direction; the portion of the gate bar, the corresponding portion of the channel semiconductor bar, the portion of the drain semiconductor bar and the portion of the source semiconductor bar adjacent to the corresponding portion of the channel semiconductor bar are used to form a storage unit; a charge energy trap storage structure is provided between each gate bar and each of the drain semiconductor bars, channel semiconductor bars and source semiconductor bars in the stacked structure; wherein each of the drain semiconductor bars, channel semiconductor bars and source semiconductor bars are single crystal semiconductor bars. A storage block as described in claim 9, wherein each row of the stacking structure includes a plurality of stacking substructures, and each stacking substructure includes a drain semiconductor strip, a channel semiconductor strip, a source semiconductor strip, a channel semiconductor strip, and a drain semiconductor strip stacked in sequence along the height direction to share the same source semiconductor strip. A storage block as described in claim 10, wherein an interlayer isolation strip is provided between two adjacent groups of the stacked substructures to isolate them from each other. A storage block as described in claim 9, wherein a plurality of isolation walls distributed along the column direction are respectively provided on both sides of the stacking structure, and each of the isolation walls extends along the height direction and the row direction to separate at least a portion of two adjacent columns of the stacking structure. A storage block as described in claim 12, wherein, in the row direction, the gate strip is filled between two adjacent isolation walls in the same row; Parts of the stacking structure in two adjacent rows share the same gate strip. A storage block as described in claim 12, wherein the isolation wall near the row-direction edge of the storage block extends in the row direction to the row-direction edge of the storage block to completely isolate two adjacent rows of the stacking structure. A storage block as described in claim 9, wherein the charge energy trap storage structure includes a first dielectric layer, a charge storage layer and a second dielectric layer, wherein the first dielectric layer is located between the charge storage layer and the adjacent stacking structure, the charge storage layer is located between the first dielectric layer and the second dielectric layer, and the second dielectric layer is located between the charge storage layer and the gate strip. A storage block as described in claim 9, wherein the gate bars of two adjacent columns are staggered in the row direction; or the gate bars of two adjacent columns are aligned in the row direction. A storage unit is characterized in that it includes: a drain region, a channel region, a source region and a gate region, wherein the drain region, the channel region and the source region are stacked in a height direction, and the gate region is located on one side of the drain region, the channel region and the source region and extends in the height direction; wherein in the height direction, the projections of the gate region and the channel region on a projection plane at least partially overlap, and the projection plane extends along the height direction and the extension direction of the drain region, the channel region and the source region, and a charge energy trap storage structure portion is arranged between the gate region and the drain region, the channel region and the source region; wherein the drain region, the channel region and the source region are single crystal semiconductors, respectively. The storage unit as described in claim 17, wherein the charge energy trap storage structure portion includes a first dielectric portion, a charge storage portion and a second dielectric portion, wherein the first dielectric portion is located between the charge storage portion and the adjacent drain region portion, channel portion and source region portion, the charge storage portion is located between the first dielectric portion and the second dielectric portion, and the second dielectric portion is located between the charge storage portion and the gate strip portion.

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