TWI858954B - Integrated cmos source drain formation with advanced control - Google Patents

Abstract

A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

Description

Integrated CMOS source-drain formation using advanced control methods

Embodiments of the present disclosure relate generally to the fabrication of integrated circuits and, more particularly, to apparatus and methods for forming source-drain extensions in finFETs using selective epitaxial growth (SEG).

Transistors are key components of most integrated circuits. Since the drive current, and thus the speed, of a transistor is proportional to the gate width of the transistor, faster transistors generally require larger gate widths. Therefore, there is a tradeoff between transistor size and speed, and "fin" field-effect transistors (finFETs) have been developed to address the conflicting goals of transistors with maximum drive current and minimum size. FinFETs are characterized by a fin-shaped channel region that greatly increases the size of the transistor without significantly increasing the transistor's footprint, and FinFETs are currently used in many integrated circuits. However, finFETs have their own drawbacks.

Forming horizontal source/drain extensions becomes increasingly difficult for narrow and tall finFETs because the fin-shaped channel region can simply be amorphized or otherwise damaged by conventional ion implantation techniques (such as beam-line ion implantation). Specifically, in some finFET architectures (e.g., horizontal gate all around, hGAA), ion implantation can result in severe intermixing between the silicon channel and the adjacent sacrificial layer of germanium silicon (SiGe). Such intermixing is highly undesirable due to the subsequent reduction in the ability to selectively remove the sacrificial SiGe layer. Furthermore, repairing such implant damage via thermal annealing increases the thermal budget of the finFET device.

Furthermore, since the source/drain extensions in a finFET can be covered by other structures, precise placement of a desired dopant in the horizontal source/drain extension regions of a finFET is difficult at best. For example, (inner) sidewall spacers on a sacrificial SiGe superlattice (SL) layer typically cover the source/drain extension regions when doping is performed. Therefore, known line-of-sight ion implantation techniques cannot uniformly deposit dopants directly into the finFET source/drain extension regions.

Additionally, the time that the substrate is exposed to the atmosphere (also known as the Q-time) can have a significant impact on the defectivity of the epitaxial film. Thus, there is a need for processing equipment and techniques for accurately doping the source/drain regions in finFET devices currently available or under development.

One or more embodiments of the present disclosure relate to a method of forming a semiconductor device. An anisotropic etching process is performed on a semiconductor material on a semiconductor substrate to expose a surface in the semiconductor material. The surface is disposed between an existing structure of the semiconductor device and a main semiconductor portion of the semiconductor substrate on which the semiconductor material is formed. An isotropic etching process is performed on the exposed sidewalls to recess the semiconductor material disposed between the existing structure and the main semiconductor portion of the semiconductor substrate by a distance to form a cavity. A layer of deposited material is formed on the cavity surface by a selective epitaxial growth (SEG) process. Between forming the cavity and SEG, the substrate does not undergo a pre-cleaning process.

Additional embodiments of the present disclosure relate to methods of forming a semiconductor element. A semiconductor substrate is positioned within a semiconductor material thereon in a first processing chamber. An anisotropic etching process is performed on the semiconductor material to expose a surface in the semiconductor material. The surface is disposed between an existing structure of the semiconductor element and a main semiconductor portion of the semiconductor substrate on which the semiconductor material is formed. An isotropic etching process is performed on the exposed sidewalls to recess the semiconductor material disposed between the existing structure and the main semiconductor portion of the semiconductor substrate a distance to form a cavity. The semiconductor substrate is moved from the first processing chamber to a second processing chamber without exposing the semiconductor substrate to oxidizing conditions. A distance by which the semiconductor material has been recessed after the isotropic etching is determined. A layer of deposited material is formed on the cavity surface in a second processing chamber using a selective epitaxial growth (SEG) process. The semiconductor substrate does not undergo a pre-cleaning process between the cavity formation and the SEG process. The SEG process takes into account the distance that the semiconductor material has been recessed after the isotropic etching.

Further embodiments of the present disclosure relate to a processing tool for forming semiconductor devices. A central transfer station has a plurality of processing chambers disposed about the central transfer station. A robot is within the central transfer station and is configured to move substrates between the plurality of processing chambers. A first processing chamber is connected to the central transfer station. The first processing chamber is configured to perform an isotropic etch process. A metrology station is within the processing tool and is accessible to the robot. The metrology station is configured to determine a recess distance of semiconductor material on the substrate from the isotropic etch process. A second processing chamber is connected to the central transfer station. The second processing chamber is configured to perform a selective epitaxial growth (SEG) process. The controller is connected to one or more of the central transfer station, the robot, the first processing chamber, the metrology station, or the second processing chamber. The controller has one or more configurations selected from: a first configuration for moving a substrate on the robot between the plurality of processing chambers and the metrology station; a second configuration for performing an isotropic etch process on the substrate in the first processing chamber; a third configuration for performing an analysis to determine recess of the semiconductor material in the metrology station; or a fourth configuration for performing a selective epitaxial growth process in the second processing chamber, the selective epitaxial growth process being adjusted for recess of the semiconductor material.

Before describing several exemplary embodiments of the present disclosure, it will be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

As used in this specification and the accompanying patent applications, the term "substrate" refers to a surface, or a portion of a surface, on which a process acts. As will also be understood by those skilled in the art, reference to a substrate may also refer to only a portion of a substrate unless the context clearly indicates otherwise. In addition, reference to deposition on a substrate may mean both a bare substrate and a substrate on which one or more films or features are deposited or formed.

As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, depending on the application, substrate surfaces on which treatments may be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. The substrate may be exposed to pre-treatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam cure, and/or bake the substrate surface. In addition to processing directly on the surface of the substrate itself, in the present disclosure, as disclosed in more detail below, any of the disclosed film processing steps may also be performed on an underlying layer formed on the substrate, and the term "substrate surface" is intended to include such underlying layers as indicated by the context. Thus, for example, where a film/layer or portion of a film/layer has been deposited onto the substrate surface, the exposed surface of the newly deposited film/layer becomes the substrate surface.

Embodiments of the present disclosure relate to semiconductor devices, processing tools, and processing methods that include a doped semiconductor material formed in a region disposed between an existing structure of the semiconductor device and a bulk semiconductor portion of a semiconductor substrate. In one or more embodiments, the semiconductor device comprises a finFET device. In such embodiments, an n-doped silicon-containing material forms an n-doped source or drain extension disposed between a gate spacer layer of the finFET and a bulk semiconductor portion of a semiconductor substrate on which the n-doped source or drain extension is disposed. Although the embodiments of the present disclosure are described with respect to forming nMOS (n-type metal oxide semiconductor) and n-doped films, those skilled in the art will recognize that p-doped films can also be formed by similar processes. References to "nMOS" or "n-doped" throughout the present disclosure are for ease of description only, and the present disclosure should not be considered limited to nMOS or n-doped structures. In some embodiments, the method involves forming pMOS (p-type metal oxide semiconductor) or p-doped films. Some embodiments of the present disclosure relate to a process for forming a PMOS device, wherein the source/drain (SD) comprises multiple layers of SiGe and boron. In one or more embodiments, the SD material provides a compressive stress of the PMOS device that increases the hole mobility. Controlling the amount of lateral push in conjunction with the epitaxial SD layer formation can affect the overall performance.

FIG. 1 is a perspective view of a fin-field-effect transistor (finFET) 100 according to an embodiment of the present disclosure. The FinFET 100 includes a semiconductor substrate 101, an insulating region 102 formed on a surface of the semiconductor substrate 101, a fin structure 120 formed on the surface of the semiconductor substrate 101, and a gate electrode structure 130 formed on the insulating region 102 and on the fin structure 120. A top portion of the fin structure 120 is exposed and electrically coupled to a source contact (not shown) of the finFET 100, another top portion of the fin structure 120 is exposed and electrically coupled to a drain contact (not shown) of the finFET 100, and a central portion of the semiconductor fin 121 includes a channel region of the finFET 100. The gate electrode structure 130 serves as a gate of the finFET 100.

The semiconductor substrate 101 may be a bulk silicon (Si) substrate, a bulk germanium (Ge) substrate, a bulk silicon germanium (SiGe) substrate, or the like. The insulating region 102 (or referred to as shallow trench isolation (STI)) may include one or more dielectric materials, such as silicon dioxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), or multiple layers thereof. The insulating region 102 may be formed by high-density plasma (HDP), flowable chemical vapor deposition (FCVD), or the like.

The fin structure 120 includes a semiconductor fin 121 and a fin spacer layer (not shown for clarity) formed on the sidewall of the semiconductor fin 121. The semiconductor fin 121 may be formed from the semiconductor substrate 101 or from a different semiconductor material deposited on the semiconductor substrate 101. In the latter case, the different semiconductor material may include germanium silicon, a III-V compound semiconductor material, or the like.

The gate electrode structure 130 includes a gate electrode layer 131, a gate dielectric layer 132, a gate spacer layer 133, and a mask layer 136. In some embodiments, the gate electrode layer 131 includes a polysilicon layer or a metal layer covered with a polysilicon layer. In other embodiments, the gate electrode layer 131 includes a material selected from the following: metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN) and molybdenum nitride ( _MoNx )), metal carbides (such as tantalum carbide (TaC) and helium carbide (HfC)), metal-nitride-carbides (such as TaCN), metal oxides (such as molybdenum oxide ( _MoOx )), metal oxynitrides (such as molybdenum oxynitride ( _{MoOxNy )} ), metal silicides (such as nickel silicide), and combinations thereof. The gate electrode layer 131 may also be a metal layer covered with a polysilicon layer.

The gate dielectric layer 132 may include silicon oxide (SiO _x ), which may be formed by thermal oxidation of the semiconductor fin 121. In other embodiments, the gate dielectric layer 132 is formed by a deposition process. Suitable materials for forming the gate dielectric layer 132 include silicon oxide, silicon nitride, oxynitride, metal oxide (such as HfO ₂ , HfZrO _x , HfSiO _x , HfTiO _x , HfAlO _x ), and combinations and multiple layers thereof. The gate spacers 133 are formed on the sidewalls of the gate electrode layer 131, and each may include a nitride portion 134 and/or an oxide portion 135 as shown. In some embodiments, the mask layer 136 may be formed on the gate electrode layer 131 as shown, and may include silicon nitride.

FIG. 2 is a cross-sectional view of a finFET 100 according to an embodiment of the present disclosure. The cross-sectional view shown in FIG. 2 is taken at section A-A in FIG. 1. As shown, the finFET 100 includes a semiconductor fin 121 having a heavily doped region 201, a doped extension region 202, and a channel region 205. Although the embodiments herein are described with respect to the formation of nMOS, those skilled in the art will recognize that the heavily doped region 201 and the doped extension region 202 may be p-doped regions.

Heavily doped region 201 forms the source and drain regions of finFET 100 and includes a relatively high concentration of an n-dopant such as phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), lithium (Li) or a p-dopant such as boron (B), aluminum (Al), gallium (Ga), or indium (In). Although region 201 may be referred to as heavily n-doped, those skilled in the art will recognize that this region may be a p-doped region and may include a relatively high concentration of a p-dopant such as boron (B). For example, in some embodiments, the dopant concentration in the heavily doped region 201 can be as high as ^5x1021 atoms/ ^cm3 . In some embodiments, the heavily doped region 201 has a dopant concentration in a range of about ^1x1020 atoms/ ^cm3 to about ^1x1022 atoms/ ^cm3 . The heavily doped region 201 can be produced by any suitable doping technique. Because the heavily doped region 201 is generally not covered by the central structure of the finFET 100 when doped, line-of-sight doping techniques such as beamline ion implantation can be used. Alternatively, since a major portion of each heavily doped region 201 is typically exposed during doping, conformal doping techniques such as plasma doping (PLAD) may be used to form the heavily doped regions 201.

The doped extension region 202 forms the source and drain extensions of the finFET 100 and includes one or more n-doping agents. One skilled in the art will recognize that the extension region may be a p-doped region. According to an embodiment of the present disclosure, the doped extension region 202 includes one or more n-doping agents that act as a diffusion barrier for the n-doping agents in the heavily doped region 201. Therefore, because the doped extension region 202 is disposed between the channel region 205 and the heavily doped region 201, n dopants (such as phosphorus) located in the heavily doped region 201 cannot diffuse into the channel region 205. With the small geometries associated with modern finFET devices, the width 133A of the gate spacer 133 (which is also close to the distance between the heavily doped regions 201) can be only a few nanometers. Thus, such n dopant diffusion can be a severe challenge in nMOS devices such as the finFET 100. In some embodiments, the doped extension region 202 includes one or more heavier mass atoms (e.g., Ge, Sn, etc.) that increase the compressive stress in the channel region 205.

In some embodiments, the n-dopant in the heavily doped region 201 may include phosphorus. In such embodiments, the n-dopant included in the doped extension region 202 may include arsenic (As), which may serve as a primary diffusion barrier to phosphorus diffusion or only as a spatial (geometric) offset. Alternatively or additionally, in such embodiments, the n-dopant included in the doped extension region 202 may include antimony (Sb), which may also serve as a partial barrier to phosphorus diffusion. In some embodiments, the p-dopants included in the region 201 and the region 202 may independently include one or more of boron (B), aluminum (Al), gallium (Ga), or indium (In).

In some embodiments, the doped extension region 202 is formed to have a thickness 202A that is less than the width 133A of the gate spacer layer 133. For example, in such an embodiment, the thickness 202A of the doped extension region 202 may be approximately 1 nanometer less than the width 133A. Therefore, in such an embodiment, the doped extension region 202 does not extend into the channel region 205.

Furthermore, according to an embodiment of the present disclosure, the doped extension region 202 is formed by a (SEG) process. Specifically, a cavity is formed in a portion of the semiconductor fin 121 that is disposed between the gate spacer 133 and the bulk semiconductor portion of the semiconductor substrate 101. The cavity is then filled with an n- or p-doped semiconductor material, such as a silicon material doped with arsenic (As) (e.g., also referred to herein as Si:As) or a silicon material doped with boron (B) (e.g., also referred to herein as Si:B). Thus, source-drain extensions for the finFET 100 are formed in a region of the semiconductor fin 121 that is between an existing structure of the semiconductor fin 121 and the bulk semiconductor portion of the semiconductor substrate 101. Additionally, the n-dopant included in the doped extension region 202 may be selected to act as a diffusion barrier for the n-dopant located in the heavily doped region 201. Note that the doped extension region 202 cannot be formed by beam-line ion implantation or PLAD due to the presence of the gate spacer 133. Various embodiments of how the doped extension region 202 may be formed in the finFET 100 are described below in conjunction with FIG. 3 and FIGS. 4A to 4E.

FIG. 3 is a flow chart of a fabrication process 300 for forming an nMOS finFET according to various embodiments of the present disclosure. One skilled in the art will recognize that a pMOS finFET may be formed by a similar fabrication process. FIGS. 4A-4E are schematic cross-sectional views of a semiconductor device (such as finFET 100 in FIG. 1 ) at various stages of process 300 according to various embodiments of the present disclosure. Although process 300 is shown as being used to form doped extension regions, process 300 may also be used to form other structures on a substrate.

The process 300 begins at operation 301, as shown in FIG. 4A, where a gate electrode structure 130 and a gate spacer 133 are formed on a semiconductor fin 121. In the embodiment shown in FIG. 4A, the semiconductor fin 121 is formed from a portion of a semiconductor substrate 101.

In operation 302, an anisotropic etch process is performed on a portion of the semiconductor fin 121 that is disposed between the gate spacer layer 133 and a bulk semiconductor portion of the semiconductor substrate 101. Thus, as shown in FIG. 4B, one or more sidewall surfaces 401 in the semiconductor material of the semiconductor fin 121 are exposed. As shown, the sidewall surface 401 is disposed between the existing structure of the finFET 100 and the bulk semiconductor portion of the semiconductor substrate 101. That is, the sidewall surface 401 is disposed between the gate spacer layer 133 and the semiconductor substrate 101. Thus, the sidewall surface 401 is in a region of the semiconductor fin 121 that is not accessible by conventional, surface-standard line-of-sight ion implantation techniques.

The anisotropic etching process of operation 302 may be selected to remove sufficient material from the semiconductor fin 121 so that the sidewall surface 401 has any suitable target length 401A. For example, in some embodiments, the anisotropic etching process of operation 302 is performed so that the sidewall surface 401 has a target length 401A of about 5 nm to about 10 nm. In other embodiments, the sidewall surface 401 may have a target length 401A greater than 10 nm or less than 5 nm, depending on the geometry of the gate spacer layer 133, the concentration of the n-dopant in the heavily doped region 201, the size of the channel region 205, and other factors. The anisotropic etching process of operation 302 may be, for example, a deep reactive-ion etch (DRIE) process, during which the gate spacer layer 133 and other portions of the finFET 100 are masked.

In operation 303, as shown in FIG. 4C , an isotropic etching process is performed on sidewall surface 401 to form one or more cavities 402 in the material of semiconductor fin 121. As shown, each cavity 402 has a surface 403. In addition, each cavity 402 is disposed between an existing structure of finFET 100 (i.e., one of gate spacer layers 133) and a bulk semiconductor portion of semiconductor substrate 101. Thus, portions of cavities 402 are each in regions of semiconductor fin 121 that are inaccessible to line-of-sight ion implantation techniques.

The isotropic etching process of operation 303 may be selected to remove sufficient material from the semiconductor fin 121 so that the cavity 402 has any suitable target width 402A. For example, in some embodiments, the isotropic etching process of operation 303 is performed so that the cavity 402 has a target width 402A of about 2 nm to about 10 nm. In other embodiments, the sidewall surface 401 may have a target width 402A greater than 10 nm or less than 2 nm, depending on the geometry of the gate spacer layer 133, the concentration of the n-dopant or p-dopant in the heavily doped region 201, and other factors. For example, in some embodiments, the target width 402A may be selected such that the cavity 402 has a target width 402A that is no more than about 1 nm smaller than the width 133A of the gate spacer layer 133 .

The isotropic etching process of operation 303 may include any suitable etching process that is selective to the semiconductor material of the semiconductor fin 121. For example, when the semiconductor fin 121 includes silicon (Si), the isotropic etching process of operation 303 may include one or more of a HCl-based chemical vapor etch (CVE) process, a HCl and _GeH4 -based CVE process, and/or a _Cl2 -based CVE process. In some embodiments, the isotropic etching process of operation 303 includes one or more of a wet etching process or a dry etching process. In some embodiments, the isotropic etching process of operation 303 includes a dry etching process.

In some embodiments, an optional operation 304 is performed in which a pre-deposition cleaning process or other surface preparation process is performed on the surface 403 of the cavity 402. The surface preparation process may be performed to remove native oxide on the surface 403 and otherwise prepare the surface 403 prior to the (SEG) process performed in operation 305. The surface preparation process includes a dry etching process, a wet etching process, or a combination of the two.

In such an embodiment, the dry etching process may include a known plasma etching, or a remote plasma assisted dry etching process, such as the SiCoNi ^™ etching process available from Applied Materials, Inc., Santa Clara, California. In the SiCoNi ^™ etching process, the surface 403 is exposed to _H2 , _NF3 , and/or _NH3 plasma species, such as plasma excited hydrogen and fluorine species. For example, in some embodiments, the surface 403 may be simultaneously exposed to _H2 , _NF3 , and _NH3 plasmas. The SiCoNi ^TM etch process of operation 304 may be performed in a SiCoNi pre-clean chamber that may be integrated into one of a variety of multi-processing platforms, including the Centura ^TM , Dual ACP, Producer ^TM GT, and Endura platforms available from Applied Materials. The wet etch process may include a hydrofluoric (HF) acid post process, i.e., a so-called "HF post" process, in which the HF etch of the surface 403 with the surface 403 terminated by hydrogen is performed. Alternatively, any other liquid-based pre-epitaxial pre-clean process may be employed in operation 304. In some embodiments, the process includes sublimation etching for native oxide removal. The etching process may be plasma-based or thermal. The plasma process can be any suitable plasma (eg, conductively coupled plasma, inductively coupled plasma, microwave plasma).

In some embodiments, the apparatus or processing tool is configured to maintain the substrate under vacuum conditions to prevent the formation of an oxide layer and does not use a pre-epitaxy pre-cleaning process. In such embodiments, the processing tool is configured to move the substrate from the etch processing chamber to the epitaxial chamber without exposing the substrate to atmospheric conditions.

In operation 305, as shown in FIG. 4D, a selective epitaxial growth (SEG) process is performed on surface 403 to grow a layer of deposited material 406, thereby forming doped extension region 202. Specifically, the deposited material includes a semiconductor material (such as silicon), and an n-type dopant. For example, in some embodiments, deposited material 406 includes Si:As, wherein the arsenic concentration in deposited material 406 is selected based on the electrical needs of finFET 100. Note that Si:As can be deposited via (SEG) with an electrically active dopant concentration of arsenic up to about ^5x1021 atoms/ ^cm3 . However, such high arsenic concentration present in the doped extension region 202 may result in increased resistivity due to undesired formation of As V (arsenic-vacancy) complexes and arsenic diffusion into the channel region 205. Additionally, AsP V (arsenic-phosphorus-vacancy) complexes may form in the doped extension region 202, resulting in increased phosphorus diffusion into the channel region 205. Therefore, in some embodiments, the deposited material 406 includes an arsenic electroactive dopant concentration of no greater than about 5× ^{10 20} atoms/cm ³ .

In some embodiments, deposited material 406 may have a deposition thickness 406A of about 2 nm to about 10 nm. In other embodiments, deposited material 406 may have a deposition thickness 406A that is thicker than 10 nm for certain configurations of finFET 100. In some embodiments, as shown in FIG. 4D , deposition thickness 406A is selected such that deposition material 406 completely fills cavity 402. In other embodiments, deposition thickness 406A is selected such that deposition material 406 partially fills cavity 402 and covers exposed surfaces of semiconductor fin 121 that form cavity 402.

The appropriate SEG process in operation 305 may include specific processing temperatures and pressures, processing gases, and gas flows selected to promote selective growth of a particular n-doped or p-doped semiconductor material. In embodiments where the particular n-doped semiconductor material includes Si:As, the doping gas used in the SEG process in operation 305 may include AsH ₃ , As(SiH ₃ ) ₃ , AsCl ₃ , or tertiarybutylarsine (TBA). Other gases used in the SEG process may include dichlorosilane (DCS), HCl, SiH ₄ , Si ₂ H ₆ , and/or Si ₄ H ₁₀ . In such an embodiment, the SEG process of operation 305 may be performed in an atmospheric or sub-atmospheric pressure chamber that has a low _H2 carrier gas flow. For example, in such an embodiment, the process pressure in the process chamber in which the SEG process is performed may be on the order of about 20-700 F. In such an embodiment, the high reactor pressure and low dilution (due to the low carrier gas flow) may produce high arsenic and high dichlorosilane ( _H2SiCl2 or _DCS ) partial pressures, thereby facilitating the removal of chlorine (Cl) and excess arsenic from the surface 403 during the SEG process. Thus, high film growth rates and associated high arsenic integration rates are achieved, and good crystal quality may be obtained. In some embodiments, the doping gas used provides a p-doped semiconductor material. In some embodiments, the p-doped semiconductor material includes one or more of boron (B), aluminum (Al), gallium (Ga), or indium (In). In some embodiments, the doping precursor includes one or more of borane, diborane, or plasmas thereof.

The SEG process of operation 305 may be performed in any suitable processing chamber, such as a processing chamber integrated into one of various multi-processing platforms, including the Producer ^™ GT, Centura ^™ AP, and Endura platforms available from Applied Materials, Inc. In such an embodiment, the SiCoNi ^™ etch process of operation 304 may be performed in another chamber of the same multi-processing platform.

In operation 306, as shown in FIG. 4E, a second SEG process is performed in which a heavily doped region 201 is formed. The heavily doped region 201 is formed on the doped extension region 202. The heavily doped region 201 can be formed of any suitable semiconductor material, including doped silicon, germanium doped silicon, carbon doped silicon, or the like. The one or more dopants can include any suitable n-dopant, such as phosphorus. For example, in some embodiments, the heavily doped region 201 can include phosphorus-doped silicon (Si:P). Any suitable SEG process can be used to form the heavily doped region 201. The thickness and other film properties of heavily doped region 201 may be selected based on the electrical requirements of finFET 100 , the size of finFET 100 , and other factors.

In some embodiments, the second SEG process is performed in the same processing chamber as the SEG process of operation 305. Therefore, the doped extension region 202 can actually be formed in the preliminary deposition step during the formation of the heavily doped region 201. Therefore, in such embodiments, a dedicated processing chamber is not required to form the doped extension region 202, and additional time for transferring the substrate from the first processing chamber (for performing SEG of the doped extension region 202) to the second processing chamber (for performing SEG of the heavily doped region 201) is avoided. In addition, in such embodiments, the deposited material 406 is not exposed to air. Alternatively, in some embodiments, the second SEG process is performed in a different processing chamber than the SEG process of operation 305, thereby reducing the amount of processing chambers exposed to harmful dopants such as arsenic. In such embodiments, both chambers may be integrated into the same multi-process platform, thereby avoiding vacuum break and exposure of the deposited material 406 to air.

After operation 306, the remaining components of finFET 100 may be completed using known manufacturing techniques.

Embodiments of the process 300 enable the formation of the doped extension regions 202 in precisely defined locations (i.e., in regions of the semiconductor fin 121 that are difficult to reach using conventional ion implantation techniques). Furthermore, the process of forming the doped extension regions 202 can be integrated into an existing selective epitaxial growth step already employed in the fabrication of finFETs, thereby minimizing or eliminating disturbances to the process flow used to form the finFETs. Additionally, implant damage (i.e., defects from heavy mass ion implants, such as silicon interstices or even silicon amorphization) is avoided, as well as any deleterious interactions between such crystalline defects and high concentrations of arsenic and/or phosphorus. Thus, no post-implantation anneal or associated additional thermal budget that impacts the process is required. Furthermore, since no vacuum break occurs between the deposition of the doped extension regions 202 and the heavily doped regions 201, additional pre-clean-related material loss is also avoided when the SEG process of operation 305 is performed in the same processing chamber as the SEG process of operation 306 or in a different processing chamber on the same multi-processing platform.

As is well known in the art, introducing tensile strain into the channel region of an nMOS finFET can increase charge mobility in the nMOS finFET. Additionally, as described herein, forming an epitaxially grown Si:As material adjacent to the channel region 205 of the semiconductor fin 121 can introduce significant tensile strain in the channel region 205. For example, according to some embodiments of the present disclosure, the n-doped extension region can be deposited at an arsenic concentration sufficient to produce a targeted tensile strain within the doped extension region 202. Thus, in embodiments where the deposited material 406 includes epitaxially grown Si:As, an additional benefit of forming the doped extension region 202 in the finFET 100 is that the channel region 205 may have improved charge mobility due to the tensile strain introduced in the channel region 205 by forming the n-doped tensile region. In some embodiments, for example, germanium (Ge), antimony (Sb), and/or tin (Sn) are doped into the p-doped extension region to provide compressive stress to the channel.

In some embodiments, an optional carbon-containing layer is formed in the cavity 402. In such embodiments, the carbon-containing layer may be a liner between the doped extension region 202 and the heavily n-doped region 201. One such embodiment is shown in FIG.

FIG. 5 is a schematic cross-sectional view of finFET 100 after forming cavity 402 according to various embodiments of the present disclosure. As shown, a carbon-containing layer 501 is deposited on surface 407 of deposited material 406. The presence of carbon (C) can enhance arsenic diffusion while reducing phosphorus diffusion. Thus, in some embodiments, carbon-containing layer 501 includes between about 0.5% and about 1.0% carbon. In such embodiments, carbon-containing layer 501 can further include phosphorus, for example, between about ^1x1020 atoms/ ^cm3 and about ^5x1020 atoms/ ^cm3 . Such a carbon-containing layer can be grown in an atmospheric or near-atmospheric SEG chamber at a processing temperature of about 650°C ± 50°C. Therefore, in the embodiment where the carbon-containing layer 501 includes Si:C:P, a triple-layer structure including Si:P (heavily n-doped region 201), Si:C:P (carbon-containing layer 501), and Si:As (doped extension region 202) is formed. Such a triple-layer structure can cause arsenic to diffuse away from the channel region 205 and toward the heavily n-doped region 201.

In some embodiments, n-doped semiconductor materials may be formed as part of a nanowire structure in regions of the nanowire structure that are not accessible via conventional ion implantation techniques. One such embodiment is described below in conjunction with FIG. 6 and FIGS. 7A to 7E.

FIG. 6 is a flow chart of a fabrication process 600 for forming a nanowire structure 700 according to various embodiments of the present disclosure. FIG. 7A to FIG. 7E are schematic cross-sectional views of the nanowire structure 700 corresponding to various stages of the process 600 according to embodiments of the present disclosure. Although the process 600 is described as being used to form an n-doped region in a nanowire structure, the process 600 may also be used to form other structures on a substrate.

Process 600 begins at operation 601, as shown in FIG. 7A, where alternating silicon layers 710 and germanium silicon (SiGe) layers are formed on a host semiconductor substrate 701. Host semiconductor substrate 701 may be formed of silicon, germanium silicon, or any other suitable bulk crystalline semiconductor material. Silicon layers 710 and germanium silicon layers 720 may each be formed by a SEG process and typically include crystalline semiconductor materials.

In operation 602, as shown in FIG. 7B, the silicon layer 710 and the germanium silicon layer 720 are patterned and etched to expose the vertical sidewall 711 on the silicon layer 710 and the vertical sidewall 721 on the germanium silicon layer 720. In some embodiments, operation 602 includes a DRIE process.

In operation 603, as shown in FIG. 7C, the germanium silicon layer 720 is selectively etched inward from the vertical sidewalls 721 to form the cavity 706. In some embodiments, a chemical vapor etching (CVE) process is used to selectively remove the germanium silicon layer 720 relative to the silicon layer 710. For example, gaseous hydrochloric acid selective etching of SiGe relative to Si in a reduced pressure chemical vapor deposition reactor has been described. Alternatively, an ex-situ HF immersion followed by a _GeH4 enhanced Si etch performed in-situ in an epitaxy reactor may be used in operation 603.

In operation 604, as shown in FIG. 7D, a low dielectric constant material 704 is then conformally deposited on the main semiconductor substrate 701. The low dielectric constant material 704 fills at least a portion of the cavity 706.

In operation 605, as shown in FIG. 7E, the low-k material 704 is patterned and etched to expose the vertical sidewalls 711 on the silicon layer 710 and the filled cavities 706 on the germanium silicon layer 720. In some embodiments, operation 605 includes a DRIE process. The filled cavities 706 form spacers 702, wherein each spacer 702 is formed at an edge region 705 of the germanium silicon layer 720.

In operation 606, as shown in FIG. 7F, a portion of the silicon layer 710 is selectively removed from the edge region 705 to form a cavity 706. The silicon may be removed from the edge region 705 via a CVE process, such as a CVE process that is selective to silicon relative to the spacer layer 702. In some embodiments, the CVE process may include one or more of a HCl-based CVE process, a HCl and _GeH4 -based CVE process, and/or a _Cl2 -based CVE process.

In operation 607, as shown in FIG. 7G, n-doped silicon material 718 is grown in cavity 706 via a SEG process. In some embodiments, the n-dopant is arsenic, and the n-doped silicon material includes Si:As. In such embodiments, the SEG process of operation 605 may be substantially similar to the SEG process of operation 305 in process 300 described above.

In an alternative embodiment, the spacer layer 702 may be formed by selectively oxidizing portions of the germanium silicon layer 720, while non-selectively etching portions of the germanium silicon layer 720 that are subsequently filled with the low-k material 704.

Implementations of process 600 provide for forming a nanowire structure 700 that includes a doped region, namely, a cavity 706 filled with n-doped silicon material 718. Note that the doped region described above is not accessible by line-of-sight ion implantation techniques because cavity 706 is disposed between the existing structure of nanowire structure 700 and the bulk semiconductor portion of semiconductor substrate 701. Thus, such a doped region cannot be formed by conventional techniques.

FIG. 8 shows another embodiment of the present disclosure. One skilled in the art will recognize that the method 800 shown in FIG. 8 can be combined with process 300 or process 600. Referring to FIG. 8 and FIGS. 4A through 4E, method 800 begins at 801, where a semiconductor substrate is provided for processing. The semiconductor substrate has semiconductor material thereon. As used in this specification and the appended claims, the term "providing" means placing a substrate into a position for processing. For example, the substrate can be placed in a first processing chamber for processing.

At operation 802, an anisotropic etching process is performed on a semiconductor material on a semiconductor substrate. The anisotropic etching process exposes a surface in the semiconductor material. In some embodiments, operation 802 is not performed. The exposed surface of some embodiments is disposed between an existing structure of a semiconductor device and a bulk semiconductor portion of the semiconductor substrate on which the semiconductor material is formed.

At operation 803, an isotropic etching process is performed on the exposed sidewalls to recess the semiconductor material disposed between the existing structure and the bulk semiconductor portion of the substrate. The sidewalls are recessed a distance to form a cavity. The amount of sidewall recessing can vary based on, for example, the isotropic etching conditions.

At operation 804, the distance that the semiconductor material has been recessed by the isotropic etching process is determined. The recess distance can be measured by any suitable technique known to those skilled in the art. In some embodiments, the recess distance is determined by refractometry.

At operation 805, a deposited material layer is formed on the cavity surface via a selective epitaxial growth (SEG) process. In some embodiments, the substrate does not undergo a pre-cleaning process between forming the cavity and the SEG process. In some embodiments, the substrate is not exposed to atmospheric conditions or oxidizing conditions between forming the cavity and the SEG process.

The SEG process of some embodiments is adjusted based on the recess distance from the predetermined method. For example, if the predetermined method is configured for a recess depth of 5 Å and the actual measured recess depth is 6 Å, the SEG conditions can be changed to grow enough film to compensate for the difference. In some embodiments, the SEG process is adjusted to perform more than one type of growth. For example, if the recess depth is greater than a predetermined limit, the SEG process can start by depositing silicon before forming the doped deposited material.

In one or more embodiments, operations 803, 804, and 805 are integrated using advanced process control (APC). As used herein, the term "integrated" means that the lateral push and epitaxial growth are performed in the same platform (under vacuum processing). At operation 804, integrated metrology can be used to determine the amount of recess distance. In some embodiments, the integrated metrology is performed in situ. Once the recess distance has been determined by integrated metrology, the measurement results are fed back to the epitaxial tool so that compensation can be performed (e.g., the thickness/composition of the first epitaxial layer can be adjusted thereby). In some embodiments, the advanced process control includes one or more of scatterometry (i.e., optical critical dimension (OCD) metrology), refraction, elliptical polarization, or electron beam.

Referring to FIG. 9, additional embodiments of the present disclosure relate to a processing tool 900 for performing the methods described herein. FIG. 9 illustrates a system 900 that can be used to process substrates according to one or more embodiments of the present disclosure. The system 900 may be referred to as a cluster tool. The system 900 includes a central delivery station 910 having a robot 912 therein. The robot 912 is shown as a single-leaf robot; however, those skilled in the art will recognize that other robot 912 configurations are within the scope of the present disclosure. The robot 912 is configured to move one or more substrates between chambers connected to the central delivery station 910.

At least one pre-clean/buffer chamber 920 is connected to the central delivery station 910. The pre-clean/buffer chamber 920 may include one or more of a heater, a free radical source, or a plasma source. The pre-clean/buffer chamber 920 may be used as a holding area for an independent semiconductor substrate or a wafer cassette for processing. The pre-clean/buffer chamber 920 may perform a pre-clean process or may preheat a substrate for processing or may simply be a temporary storage area for a process sequence. In some embodiments, there are two pre-clean/buffer chambers 920 connected to the central delivery station 910.

In the embodiment shown in FIG. 9 , a pre-clean chamber 920 may be used as a chamber that passes between a factory interface 905 and a central transfer station 910. The factory interface 905 may include one or more robots 906 for moving substrates from a cassette to the pre-clean/buffer chamber 920. The robot 912 may then move the substrates from the pre-clean/buffer chamber 920 to other chambers within the system 900.

The first processing chamber 930 can be connected to the central delivery station 910. The first processing chamber 930 can be configured as an anisotropic etch chamber and can be in fluid communication with one or more reactive gas sources to provide one or more flows of reactive gas to the first processing chamber 930. The substrate can be moved to and from the deposition chamber 930 by a robot 912 passing through an isolation valve 914.

The processing chamber 940 can also be connected to the central delivery station 910. In some embodiments, the processing chamber 940 includes an isotropic etching chamber and is in fluid communication with one or more reactive gas sources to provide reactive gas flow to the processing chamber 940 to perform an isotropic etching process. The substrate can be moved to and from the deposition chamber 940 by the robot 912 passing through the isolation valve 914.

Processing chamber 945 may also be connected to central delivery station 910. In some embodiments, processing chamber 945 is the same type as processing chamber 940 and is configured to perform the same process as processing chamber 940. This arrangement may be useful in situations where the process occurring in processing chamber 940 takes a significantly longer time than the process in processing chamber 930.

In some embodiments, processing chamber 960 is connected to central transfer station 910 and is configured to be used as a selective epitaxial growth chamber. Processing chamber 960 can be configured to perform one or more different epitaxial growth processes.

In some embodiments, the anisotropic etching process occurs in the same processing chamber as the isotropic etching process. In such embodiments, processing chamber 930 and processing chamber 960 can be configured to perform etching processes on two substrates simultaneously, and processing chamber 940 and processing chamber 945 can be configured to perform a selective epitaxial growth process.

In some embodiments, each of the processing chambers 930, 940, 945, and 960 is configured to perform a different portion of a processing recipe. For example, processing chamber 930 may be configured to perform an anisotropic etch process, processing chamber 940 may be configured to perform an isotropic etch process, processing chamber 945 may be configured as a metrology station or to perform a first selective epitaxial growth process, and processing chamber 960 may be configured to perform a second epitaxial growth process. Those skilled in the art will recognize that the number and arrangement of independent processing chambers on a tool may vary, and that the embodiment shown in FIG. 9 represents only one possible configuration.

In some embodiments, the processing system 900 includes one or more metrology stations. For example, the metrology station can be located in the pre-clean/buffer chamber 920, in the central transfer station 910, or in any independent processing chamber. The metrology station can be any location in the system 900 that allows the measurement of the recess distance without exposing the substrate to an oxidizing environment.

At least one controller 950 is coupled to one or more of the central delivery station 910, pre-clean/buffer chamber 920, processing chambers 930, 940, 945, or 960. In some embodiments, there is more than one controller 950 connected to an individual chamber or station, and a primary control processor is coupled to each of the individual processors to control the system 900. The controller 950 may be one of any form of general purpose computer processor, microcontroller, microprocessor, etc., which may be used in an industrial environment to control various chambers and subprocessors.

At least one controller 950 may have a processor 952, a memory 954 coupled to the processor 952, an input/output element 956 coupled to the processor 952, and a support circuit 958 for communication between different electronic components. The memory 954 may include one or more of a temporary memory (e.g., random access memory) and a non-temporary memory (e.g., storage).

The processor's memory 954 or computer readable medium may be one or more of readily available memories such as random access memory (RAM), read-only memory (ROM), a floppy disk, a hard disk, or any other form of digital storage (local or remote). The memory 954 may store instruction sets that are operable by the processor 952 to control parameters and components of the system 900. Support circuits 958 are coupled to the CPU 952 for supporting the processor in a known manner. For example, the circuits may include cache memory, power supplies, clock circuits, input/output circuits, subsystems, and the like.

The process may be typically stored in memory as a software routine that, when executed by a processor, causes a processing chamber to execute the process disclosed herein. The software routine may also be stored and/or executed by a second processor (not shown) that is remote from the hardware controlled by the processor. Some or all of the methods disclosed herein may also be executed in hardware. Thus, the process may be implemented in software and executed in hardware using a computer system, as, for example, a special application integrated circuit or other type of hardware implementation, or as a combination of software and hardware. When executed by a processor, the software routine converts a general purpose computer into a special purpose computer (controller) that controls the chamber operations so that the process is executed.

In some embodiments, the controller 950 has one or more configurations for executing independent processes or sub-processes to perform the method. The controller 950 can be connected to an intermediate component or configured to operate an intermediate component to perform the functions of the method. For example, the controller 950 can be connected to one or more of a gas valve, an actuator, a motor, a slit valve, a vacuum control, etc. and configured to control one or more of the gas valve, the actuator, the motor, the slit valve, the vacuum control, etc.

The controller 950 of some embodiments has one or more structures selected from the following: a structure for moving a substrate on a robot between a plurality of processing chambers and a metrology station; a structure for performing an anisotropic etching process on a substrate; a structure for performing an isotropic etching process on a substrate in a processing chamber; a structure for performing an analysis to determine recess of a semiconductor material in a metrology station; a structure for performing a selective epitaxial growth process in an epitaxial chamber; a structure for adjusting a selective epitaxial growth process plan to take into account recess of a semiconductor material; a structure for performing a bulk selective epitaxial growth process; a structure for loading and/or unloading a substrate from a system.

In summary, one or more embodiments of the present disclosure provide systems and techniques for forming regions of doped semiconductor material disposed between an existing structure of a semiconductor device and a bulk semiconductor portion of a semiconductor substrate on which a doped silicon-containing material is formed. In embodiments where the semiconductor device comprises a finFET device, the doped semiconductor material forms a doped source and/or drain extension disposed between a gate spacer layer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the doped source or drain extension is disposed.

Reference throughout this specification to "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearance of phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in an embodiment" in various places throughout this specification does not necessarily refer to the same embodiment of the present disclosure. In addition, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

Although the disclosure herein has been described with reference to specific embodiments, it will be understood by those skilled in the art that the described embodiments are merely illustrative of the principles and applications of the disclosure. It will be appreciated by those skilled in the art that various modifications and variations may be made to the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Therefore, the disclosure may include modifications and variations within the scope of the attached patent application and its equivalents.

100: Fin field effect transistor 101: Semiconductor substrate 102: Insulation region 120: Fin structure 121: Semiconductor fin 130: Gate electrode structure 131: Gate electrode layer 132: Gate dielectric layer 133: Gate spacer 133A: Width 134: Nitride portion 135: Oxide portion 136: Mask layer 201: Heavily doped region 202: Doped extension region 202A: Thickness 205: Channel region 300: Process 301: Operation 302: Operation 303: Operation 304: operation 305: operation 306: operation 401: sidewall surface 401A: target length 402: cavity 402A: target width 403: surface 406: deposited material 406A: deposited thickness 407: surface 501: carbon-containing layer 600: process 601: operation 602: operation 603: operation 604: operation 605: operation 606: operation 607: operation 700: nanowire structure 701: main semiconductor substrate 702: spacer layer 704: low dielectric constant material 705: edge region 706: cavity 710: silicon layer 711: vertical sidewall 718: silicon material 720: germanium silicon layer 721: vertical sidewall 800: method 801: operation 802: operation 803: operation 804: operation 805: operation 900: processing tool 905: factory interface 906: robot 910: central transfer station 912: robot 914: isolation valve 920: pre-clean/buffer chamber 930: deposition chamber 940: processing chamber 945: processing chamber 950: controller 952: processor 954: memory 956: input/output element 958: Support circuits 960: Processing chamber

In order to be able to understand in detail the manner in which the above-mentioned features of the present disclosure are used, a more specific description of the present disclosure briefly summarized above may be made with reference to the embodiments, some of which are shown in the accompanying drawings. However, it will be noted that the accompanying drawings only illustrate common embodiments of the present disclosure and are therefore not to be considered as limiting the scope thereof, as the present disclosure may allow for other equally effective embodiments.

FIG. 1 is a perspective view of a fin field effect transistor (finFET) according to one or more embodiments of the present disclosure;

FIG. 2 is a cross-sectional view of the finFET of FIG. 1 according to one or more embodiments of the present disclosure;

FIG. 3 is a flow chart of a fabrication process for forming a finFET according to one or more embodiments of the present disclosure;

FIGS. 4A to 4E illustrate schematic cross-sectional views of a semiconductor device at various stages of a process corresponding to FIG. 3 according to one or more embodiments of the present disclosure;

FIG. 5 is a schematic cross-sectional view of the finFET of FIG. 1 after forming a cavity according to one or more embodiments of the present disclosure;

FIG. 6 is a flow chart of a fabrication process for forming a nanowire structure according to one or more embodiments of the present disclosure;

FIGS. 7A to 7G are schematic cross-sectional views of the nanowire/nanosheet structure of FIG. 7 at various stages of the process of FIG. 6 according to one or more embodiments of the present disclosure;

FIG. 8 is a flow chart of a manufacturing process for forming a semiconductor device according to one or more embodiments of the present disclosure; and

FIG. 9 illustrates a schematic diagram of a processing system for performing any embodiment of the present disclosure.

Domestic storage information (please note the order of storage institution, date, and number) None

Overseas storage information (please note the storage country, institution, date, and number in order) None

100: FinFET

101:Semiconductor substrate

130: Gate electrode structure

131: Gate electrode layer

132: Gate dielectric layer

133: Gate spacer layer

133A: Width

134: Nitride part

135: Oxide part

136: Mask layer

406:Deposition materials

407: Surface

501:Carbon layer

Claims (14)

A method for forming a semiconductor device, the method comprising: performing an anisotropic etching process on a semiconductor material on a semiconductor substrate in a first processing chamber to expose a surface of the semiconductor material, the surface being disposed between an existing structure of the semiconductor device and a main semiconductor portion of the semiconductor substrate on which the semiconductor material is formed; performing an isotropic etching process on an exposed sidewall to recess the semiconductor material disposed between the existing structure and the main semiconductor portion of the semiconductor substrate by a distance to form a cavity; and performing an isotropic etching process on a first processing chamber to expose a surface of the semiconductor material, the surface being disposed between an existing structure of the semiconductor device and a main semiconductor portion of the semiconductor substrate on which the semiconductor material is formed. In one embodiment, the semiconductor substrate is moved from the first processing chamber to a second processing chamber; a distance that the semiconductor material has been recessed after isotropic etching is measured in situ; a layer of deposited material is formed on a surface of the cavity using a selective epitaxial growth (SEG) process in the second processing chamber, and the semiconductor substrate does not undergo a pre-cleaning process between forming the cavity and SEG; and the SEG process is adjusted according to the distance that the semiconductor material has been recessed, wherein the isotropic etching process, the SEG process, and the in situ measurement are performed in a single platform under vacuum processing. The method as described in claim 1 further includes: forming a doped region on the layer of deposited material through a selective epitaxial growth (SEG) process, wherein the doped region includes one or more of the following: phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), lithium (Li), boron (B), aluminum (Al), gallium (Ga) and indium (In), and the doped region has a dopant concentration in a range of about ^1x1020 atoms/ ^cm3 to about ^1x1022 atoms/ ^cm3 . The method of claim 1, wherein the isotropic etching occurs in a first processing chamber, and the method further comprises: moving the substrate from the first processing chamber to a second processing chamber for the SEG process. The method as described in claim 1 further comprises: epitaxially growing a portion of the semiconductor material before forming the layer of deposited material. A method as claimed in claim 1, wherein the distance that the semiconductor material has been recessed is determined by refraction. A method as described in claim 1, wherein the isotropic etching process includes an etching process that is selective to the semiconductor material. The method of claim 6, wherein the isotropic etching process comprises a chemical vapor etching process, the chemical vapor etching process comprising exposing the exposed sidewall to at least one of HCl, GeH ₄ , or Cl ₂ . The method of claim 1, wherein forming the layer of deposited material comprises filling the cavity with the deposited material. The method as described in claim 1 further comprises: depositing a carbon-containing material on the surface of the cavity before forming the layer of deposited material, wherein the carbon-containing material includes a silicon carbon phosphorus (SiCP) material. The method as described in claim 1, wherein the step of performing the isotropic etching process on the exposed sidewall to form the cavity in the semiconductor material comprises: removing the semiconductor material until a portion of the semiconductor material comprising a phosphorus-doped host semiconductor material is exposed. The method of claim 1, wherein the deposited material comprises an n-type dopant, the n-type dopant comprises arsenic (As), and the selective epitaxial growth (SEG) process comprises: exposing the surface of the cavity to at least one of AsCl ₃ , TBA, or AsH ₃ and at least one of dichlorosilane (DCS), HCl, SiH ₄ , Si ₂ H ₆ , or Si ₄ H ₁₀ . The method of claim 11, wherein the step of forming the layer of deposited material comprises: filling the cavity with an arsenic-doped material having an arsenic concentration sufficient to produce a targeted tensile strain in the deposited material. The method of claim 1, wherein the deposited material comprises a p-type dopant, the p-type dopant comprises boron (B), and the selective epitaxial growth (SEG) process comprises: exposing the surface of the cavity to one or more of borane, diborane, or a plasma of borane or diborane. The method of claim 1, wherein the layer of additional deposited material is formed without exposing the layer of deposited material formed on the surface of the cavity to air.