TWI858801B - Gate driving device for display device - Google Patents

Abstract

A gate driving device for a display device is provided. The gate driving device includes gate driving units. The (n)th level gate driving unit among the gate driving units includes a pulling-up circuit, an output circuit, a pulling-down circuit, and an anti-noise circuit. The pulling-up circuit pulls up a biasing value on a bias node in response to a (n-a)th level gate driving signal. The output circuit provides a nth level gate driving signal in response to a corresponding external clock and the biasing value on the bias node. The pulling-down circuit pulls down the biasing value on the bias node in response to a (n+a)th level gate driving signal. The anti-noise circuit includes a noise suppression circuit. The noise suppression circuit suppresses a noise on the bias node. During a display period, the anti-noise circuit disables the noise suppression circuit in response to a high biasing value on the bias node. During a blanking period, the anti-noise circuit disables the noise suppression circuit in response to a reset signal.

Description

Gate driver circuit for display device

The present invention relates to a driving device, and in particular to a gate driving circuit for a display device.

In the existing gate drive circuit, in order to achieve the technical effect of anti-noise, each gate drive unit will include an anti-noise circuit. The anti-noise circuit will perform anti-noise operation on the corresponding gate drive unit. However, in order to achieve full-time anti-noise operation, the execution period of the anti-noise operation will be very long. This causes the noise suppression element in the anti-noise circuit to deteriorate. If the noise suppression circuit includes a thin-film transistor (TFT), the threshold voltage of the thin-film transistor will be significantly offset, thereby reducing the effect of the anti-noise operation. From this, we can see that how to allow the noise suppression circuit to get enough rest to stabilize the effect of anti-noise operation is one of the research focuses of technicians in this field.

The present invention provides a gate drive circuit for a display device. The gate drive circuit includes a plurality of gate drive units. The gate drive unit can allow the noise suppression circuit in the gate drive unit to obtain sufficient rest to stabilize the effect of anti-noise operation.

The gate drive circuit of the present invention is used for a display device. The gate drive circuit includes a plurality of gate drive units. The nth gate drive unit among the plurality of gate drive units includes a lifting circuit, an output circuit, a pull-down circuit and an anti-noise circuit. The lifting circuit is coupled to a bias node. The lifting circuit reacts to the (n-a)th gate drive signal to lift the bias value at the bias node. The output circuit is coupled to the bias node. The output circuit reacts to the corresponding clock signal and the bias value at the bias node to provide the nth gate drive signal. The pull-down circuit is coupled to the bias node. The pull-down circuit is responsive to the (n+a)th gate drive signal to pull down the bias value at the bias node. The anti-noise circuit includes a noise suppression circuit. The noise suppression circuit is coupled to the bias node. The noise suppression circuit suppresses noise at the bias node. During the display period of the display device, the anti-noise circuit is responsive to the high bias value of the bias node to disable the noise suppression circuit. During the blanking period of the display device, the anti-noise circuit is responsive to the high voltage value of the reset signal of the gate drive circuit to disable the noise suppression circuit.

Based on the above, during the display period, the anti-noise circuit responds to the high bias value of the bias node to disable the noise suppression circuit. In addition, during the blanking period, the anti-noise circuit responds to the high voltage value of the reset signal of the gate drive circuit to disable the noise suppression circuit. The noise suppression circuit can rest during the blanking period. In this way, the deterioration of the noise suppression circuit can be alleviated. The noise suppression circuit can provide stable anti-noise operation.

10: Display device

100: Gate drive circuit

110: Lifting circuit

120: Output circuit

130: Pull-down circuit

140: Anti-noise circuit

141: Noise suppression circuit

142: Control circuit

150: Reset circuit

A(n): bias node

B(n): Control node

CC: Capacitor

CLK1~CLK8, CLK(n): clock signal

DA: Display Array

G(1)~G(m), G(n-a), G(n+a): gate drive signal

GU(1)~GU(m): Gate drive unit

M1, M2: transistors

MC1, MC2, MC3: control transistors

MN1, MN2: Noise suppression transistors

MO: output transistor

MR: Reset transistor

RST: Reset signal

RSTb: Inverted reset signal

TB: disappearance period

TD: Display period

TF(n), TF(n+1): frame period

tp1~tp6: time point

VDDF: System high voltage

VDDR: system low voltage

FIG1 is a schematic diagram of a display device according to an embodiment of the present invention.

FIG2 is a schematic diagram of a gate drive unit according to an embodiment of the present invention.

FIG3 is a circuit diagram of a gate drive unit according to an embodiment of the present invention.

FIG4 is a timing diagram of a reset signal and an inverted reset signal according to an embodiment of the present invention.

Figure 5 is a signal timing diagram drawn according to an embodiment of the present invention.

Some embodiments of the present invention will be described in detail with the accompanying drawings. The component symbols cited in the following description will be regarded as the same or similar components when the same component symbols appear in different drawings. These embodiments are only part of the present invention and do not disclose all possible implementation methods of the present invention. More precisely, these embodiments are only examples within the scope of the patent application of the present invention.

Please refer to FIG. 1 and FIG. 2 simultaneously. FIG. 1 is a schematic diagram of a display device according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a gate drive unit according to an embodiment of the present invention. In this embodiment, the display device 10 includes a display array DA and a gate drive circuit 100. The gate drive circuit 100 includes gate drive units GU(1)~GU(m). The gate drive units GU(1)~GU(m) respectively provide gate drive signals G(1)~G(m) with different timings. For example, the gate drive unit GU(1) provides the gate drive signal G(1) (or referred to as the first-level gate drive signal) to the first row of pixels in the display array DA. The gate drive unit GU(2) provides the gate drive signal G(2) (or referred to as the second-level gate drive signal) to the second row of pixels in the display array DA. The gate drive unit GU(n) provides the gate drive signal G(n) (or referred to as the nth-level gate drive signal) to the nth row of pixels in the display array DA, and so on. "n" and "m" are positive integers, respectively. In addition, "n" is less than "m".

In this embodiment, taking the gate drive unit GU(n) as an example, the gate drive unit GU(n) includes a boost circuit 110, an output circuit 120, a pull-down circuit 130, and an anti-noise circuit 140. The boost circuit 110 is coupled to the bias node A(n). The boost circuit 110 responds to the gate drive signal G(n-a) (or referred to as the (n-a)th stage gate drive signal) to boost the bias value at the bias node A(n). The output circuit is coupled to the bias node A(n). The output circuit 120 responds to the corresponding clock signal CLK(n) and the bias value at the bias node A(n) to provide the gate drive signal G(n). The pull-down circuit 130 is coupled to the bias node A(n). The pull-down circuit 130 responds to the gate drive signal G(n+a) (or referred to as the (n+a)th level gate drive signal) to pull down the bias value at the bias node A(n). "a" is a positive integer. In this embodiment, the gate drive signals G(n-a) and G(n+a) are respectively provided by different gate drive units other than the gate drive unit GU(n). For example, "n" is equal to "5" and "a" is equal to "4". Therefore, the gate drive signal G(n-a) (or, the gate drive signal G(1)) is generated by the gate drive unit GU(1). The gate drive signal G(n+a) (or, the gate drive signal G(9)) is generated by the gate drive unit GU(9).

In this embodiment, the anti-noise circuit 140 includes a noise suppression circuit 141. The noise suppression circuit 141 is coupled to the bias node A(n). The noise suppression circuit 141 suppresses noise at the bias node A(n). During the display period of the display device 10, the anti-noise circuit 140 responds to the high bias value of the bias node A(n) to disable the noise suppression circuit 141. In addition, during the blanking period of the display device 10, the anti-noise circuit 140 responds to the high voltage value of the reset signal RST of the gate drive circuit 100 to disable the noise suppression circuit 141.

It is worth mentioning here that the anti-noise circuit 140 not only disables the noise suppression circuit 141 in response to the high bias value of the bias node A(n) during the display period, but also disables the noise suppression circuit 141 during the blanking period. The noise suppression circuit 141 can rest during the blanking period. In this way, the degradation of the noise suppression circuit 141 can be alleviated. The noise suppression circuit 141 can provide stable anti-noise operation. The reliability of the gate drive unit G(n) can be improved.

In addition, during the display period, the anti-noise circuit 140 responds to the low bias value of the bias node A(n) to enable the noise suppression circuit 141. In other words, during the display period, when the bias node A(n) has a low bias value, the noise suppression circuit 141 performs an anti-noise operation.

In this embodiment, the boost circuit 110 is coupled to the system high voltage VDDF. When the gate drive signal G(n-a) has a pulse, the boost circuit 110 uses the system high voltage VDDF to charge the bias node A(n), thereby boosting the bias value at the bias node A(n) to a high bias value.

In this embodiment, the output circuit 120 includes an output transistor MO and a capacitor CC. The first end of the output transistor MO is used to receive the clock signal CLK(n). The second end of the output transistor MO serves as the output end of the gate drive unit GU(n). The control end of the output transistor MO is coupled to the bias node A(n). The capacitor CC is coupled between the second end of the output transistor MO and the control end of the output transistor MO. In this embodiment, when the voltage value at the bias node A(n) is a high bias value, the output transistor MO is turned on. Therefore, the output circuit 120 uses the clock signal CLK(n) as the gate drive signal G(n). In other words, the gate drive unit GU(n) provides the gate drive signal G(n) through the second end of the output transistor MO. At this time, when the clock signal CLK(n) is at a high voltage level, the output circuit 120 further raises the high bias value at the bias node A(n) through the capacitive coupling of the capacitor CC to ensure the conduction of the output transistor MO.

In this embodiment, the output transistor MO can be implemented by an N-type transistor. For example, the output transistor MO can be an N-type thin film transistor (TFT).

In this embodiment, the pull-down circuit 130 is coupled to the system low voltage VDDR. When the gate drive signal G(n+a) has a pulse, the pull-down circuit 130 uses the system low voltage VDDR to discharge the bias node A(n), thereby pulling the bias value at the bias node A(n) down to a low bias value.

Please refer to FIG. 1 and FIG. 3 at the same time. FIG. 3 is a circuit diagram of a gate drive unit according to an embodiment of the present invention. In this embodiment, the gate drive unit GU(n) includes a lift circuit 110, an output circuit 120, a pull-down circuit 130, and an anti-noise circuit 140. The lift circuit 110 includes a transistor M1. The first end of the transistor M1 is coupled to the system high voltage VDDF. The second end of the transistor M1 is coupled to the bias node A(n). The control end of the transistor M1 receives the gate drive signal G(n-a). In this embodiment, when the gate drive signal G(n-a) is at a low voltage level, the transistor M1 is disconnected. Therefore, the boost circuit 110 does not charge the bias node A(n). On the other hand, when the gate drive signal G(n-a) is at a high voltage level, the transistor M1 is turned on. The boost circuit 110 charges the bias node A(n). Therefore, the bias value at the bias node A(n) is boosted to a high bias value. Therefore, the high bias value is close to the voltage value of the system high voltage VDDF (e.g., 15 volts, but the present invention is not limited thereto).

In the present embodiment, the pull-down circuit 130 includes a transistor M2. The first end of the transistor M2 is coupled to the bias node A(n). The second end of the transistor M2 is coupled to the system low voltage VDDR. The control end of the transistor M2 is coupled to the gate drive signal G(n+a). In the present embodiment, when the gate drive signal G(n+a) is at a low voltage level, the transistor M2 is disconnected. Therefore, the pull-down circuit 130 will not discharge the bias node A(n). On the other hand, when the gate drive signal G(n+a) is at a high voltage level, the transistor M2 is turned on. The pull-down circuit 130 will discharge the bias node A(n). Therefore, the voltage value at the bias node A(n) will be pulled down to a low bias value. Therefore, the low bias value will be close to the voltage value of the system low voltage VDDR (for example, -12 volts, but the present invention is not limited thereto).

In this embodiment, transistors M1 and M2 may be implemented by N-type transistors. For example, transistors M1 and M2 may be N-type TFTs.

In this embodiment, the implementation of the output circuit 120 has been clearly described in the embodiments of FIG. 1 and FIG. 2 , so it will not be repeated here.

In this embodiment, the anti-noise circuit 140 includes a noise suppression circuit 141 and a control circuit 142. The control circuit 142 is coupled to the noise suppression circuit 141 and the bias node A(n). The control circuit 142 receives a reset signal RST and an inverted reset signal RSTb. The control circuit 142 controls the noise suppression circuit 141 according to the bias value at the bias node A(n), the reset signal RST, and the inverted reset signal RSTb.

The implementation of the reset signal RST and the inverted reset signal RSTb is specifically described. Please refer to FIG. 4 at the same time, which is a timing diagram of the reset signal and the inverted reset signal according to an embodiment of the present invention. In this embodiment, the inverted reset signal RSTb is a complementary signal of the reset signal RST. The frame period TF(n) includes the display period TD and the blanking period TB. The frame period TF(n+1) also includes the display period TD and the blanking period TB. During the blanking period TB, the reset signal RST has a high voltage value. The inverted reset signal RSTb has a low voltage value. In addition, during the display period TD, the reset signal RST has a low voltage value. The inverted reset signal RSTb has a high voltage value.

The inverted reset signal RSTb may be an inverted signal of the reset signal RST. For example, the display device 10 or the gate driving circuit 100 may invert the reset signal RST to generate the inverted reset signal RSTb. For another example, the control circuit 142 may invert the received reset signal RST to generate the inverted reset signal RSTb. Therefore, the control circuit 142 may reduce the receiving end for receiving the external inverted reset signal RSTb.

Please return to the embodiment of FIG. 1 and FIG. 3. In this embodiment, the control circuit 142 is coupled to the noise suppression circuit 141 via the control node B(n). The control circuit 142 adjusts the bias value at the control node B(n) according to the bias value at the bias node A(n), the reset signal RST, and the inverted reset signal RSTb, thereby controlling the noise suppression circuit 141. The control circuit 142 includes control transistors MC1, MC2, and MC3. The first end of the control transistor MC1 and the control end of the control transistor MC1 are used to receive the inverted reset signal RSTb. The second end of the control transistor MC1 is coupled to the noise suppression circuit 141. Further, the second end of the control transistor MC1 is coupled to the noise suppression circuit 141 via the control node B(n). The first end of the control transistor MC2 is coupled to the second end of the control transistor MC1. The second end of the control transistor MC2 is coupled to the reference low voltage VSS. The voltage value of the reference low voltage VSS is, for example, -12 volts (the present invention is not limited thereto). The control end of the control transistor MC2 is coupled to the bias node A(n). The first end of the control transistor MC3 is coupled to the second end of the control transistor MC1. The second end of the control transistor MC3 is coupled to the reference low voltage VSS. The control end of the control transistor MC3 is used to receive the reset signal RST.

In the present embodiment, the noise suppression circuit 141 includes a noise suppression transistor MN1. A first terminal of the noise suppression transistor MN1 is coupled to the bias node A(n). A second terminal of the noise suppression transistor MN1 is coupled to the reference low voltage VSS. A control terminal of the noise suppression transistor MN1 is coupled to the control circuit 142. When the bias value at the control node B(n) is a high bias value, the noise suppression transistor MN1 is turned on. The noise suppression transistor MN1 pulls down the bias value at the bias node A(n) to a low voltage value, thereby suppressing noise that may occur at the bias node A(n). Therefore, the output transistor MO will not be turned on unexpectedly due to the noise at the bias node A(n).

On the other hand, when the bias value at the control node B(n) is a low bias value, the noise suppression transistor MN1 is disconnected. The noise suppression transistor MN1 is disabled. Therefore, when the bias value at the control node B(n) is a low bias value, the noise suppression transistor MN1 enters a rest state.

In this embodiment, the noise suppression circuit 141 further includes a noise suppression transistor MN2. The first end of the noise suppression transistor MN2 is coupled to the output end of the gate drive unit GU(n). The second end of the noise suppression transistor MN2 is coupled to the reference low voltage VSS. The control end of the noise suppression transistor MN2 is coupled to the control circuit 142. When the bias value at the control node B(n) is a high bias value, the noise suppression transistor MN1 is turned on. The noise suppression transistor MN2 pulls down the voltage value at the output end of the gate drive unit GU(n) to a low voltage value, thereby suppressing noise that may occur at the output end of the gate drive unit GU(n). Therefore, the gate driver unit GU(n) does not provide an abnormal gate driver signal G(n) due to the voltage value at the output terminal of the gate driver unit GU(n).

On the other hand, when the bias value at the control node B(n) is a low bias value, the noise suppression transistor MN2 is disconnected. The noise suppression transistor MN2 is disabled. Therefore, when the bias value at the control node B(n) is a low bias value, the noise suppression transistor MN2 enters a rest state.

In this embodiment, in the anti-noise circuit 140, the control transistors MC1, MC2, MC3 and the noise suppression transistors MN1, MN2 can be implemented by N-type transistors. For example, the control transistors MC1, MC2, MC and the noise suppression transistors MN1, MN2 can be N-type TFTs.

In the present embodiment, the gate drive unit GU(n) further includes a reset circuit 150. The reset circuit 150 uses the high voltage value of the reset signal RST to reset the bias value at the bias node A(n) during the blanking period. The reset circuit 150 includes a reset transistor MR. The first end of the reset transistor MR is coupled to the bias node A(n). The second end of the reset transistor MR is coupled to the reference low voltage VSS. The control end of the reset transistor MR receives the reset signal RST. During the display period, the reset signal RST has a low voltage value. Therefore, the reset transistor MR is disconnected. During the blanking period, the reset signal RST has a high voltage value. The reset transistor MR is turned on to pull down the bias value at the bias node A(n), thereby resetting the bias value at the bias node A(n). In this embodiment, the reset transistor MR can be implemented by an N-type transistor. For example, the reset transistor MR can be an N-type TFT.

It should be noted that the anti-noise circuit 140 includes only five transistors (i.e., transistors MC1, MC2, MC3 and noise suppression transistors MN1, MN2). Therefore, the layout area of the anti-noise circuit 140 can be reduced. The layout area of the gate drive circuit 100 can also be reduced. The gate drive circuit 100 is disposed in the frame area (non-display area) of the display device 10. Therefore, the area of the frame area of the display device 10 can be further reduced.

In some embodiments, the noise suppression transistor MN2 may be omitted.

Please refer to Figures 1, 3 and 5 at the same time. Figure 5 is a signal timing diagram drawn according to an embodiment of the present invention. In this embodiment, the gate drive circuit 100 of this embodiment is applicable to 8 clock signals CLK1~CLK8. "n" is equal to "5" and "a" is equal to "4". Before time point tp1, the display device 10 is in a blanking period. During the blanking period, the reset signal RST has a high voltage value. The inverted reset signal RSTb has a low voltage value. Therefore, the reset transistor MR is turned on to pull down the bias value at the bias node A(n). The bias value at the bias node A(n) is reset to a low bias value. The control transistor MC1 is turned off in response to the low voltage value of the inverted reset signal RSTb. The control transistor MC2 is turned off in response to the low bias value at the bias node A(n). In addition, the control transistor MC3 is turned on in response to the high voltage value of the reset signal RST. Therefore, during the blanking period, the bias value at the control node B(n) is a low bias value. In other words, the control circuit 142 uses the high voltage value of the reset signal RST during the blanking period to pull the bias value at the control node B(n) down to a low bias value. During the blanking period, the noise suppression transistors MN1 and MN2 are both turned off. Therefore, the noise suppression transistors MN1 and MN2 can rest during the blanking period.

At time point tp1, the display device 10 is in the display period, and the reset signal RST has a low voltage value. The inverted reset signal RSTb has a high voltage value. The control transistor MC1 is turned on in response to the high voltage value of the inverted reset signal RSTb. The control transistor MC2 is turned off in response to the low bias value at the bias node A(n). In addition, the control transistor MC3 is turned off in response to the low voltage value of the reset signal RST. Therefore, the control circuit 142 uses the high voltage value of the inverted reset signal RSTb to raise the bias value at the control node B(n) to a high bias value. The noise suppression transistor MN1 is turned on between time point tp1 and time point tp2 to suppress the noise at the bias node A(n). The noise suppression transistor MN2 is also turned on between time point tp1 and time point tp2 to suppress the noise at the output end of the gate driver unit GU(n).

Between time point tp2 and time point tp3, the clock signal CLK1 has a first positive pulse. Between time point tp2 and time point tp3, the gate drive signal G(n-a) (or gate drive signal G(1)) is generated based on the first positive pulse of the clock signal CLK1. Between time point tp2 and time point tp3, the gate drive signal G(n-a) has a positive pulse. Therefore, at time point tp2, the boost circuit 110 responds to the positive pulse of the gate drive signal G(n-a) to boost the bias value at the bias node A(n). At time point tp2, the bias value at the bias node A(n) is a high bias value. The output transistor MO reacts to the high bias value at the bias node A(n) and is turned on. The gate drive signal G(n) (or, gate drive signal G(5)) is generated based on the clock signal CLK5.

Starting at time point tp2, control transistor MC2 is turned on in response to the high bias value at bias node A(n). In this embodiment, control transistor MC1 has a first channel width ratio. Control transistor MC2 has a second channel width ratio. It should be noted that the second channel width ratio is greater than the first channel width ratio. Therefore, when both control transistors MC1 and MC2 are turned on, the control transistor MC2 pulls down the bias value of control node B(n) faster than the control transistor MC1 raises the bias value of control node B(n). In other words, control circuit 142 pulls down the bias value at control node B(n) in response to the high bias value at bias node A(n).

At time point tp3, the gate drive signal G(n-a) has a low voltage value. Therefore, the bias node A(n) is in a floating state. The output transistor MO continues to be turned on.

Between time point tp4 and time point tp5, the clock signal CLK5 (i.e., the clock signal CLKn) has a positive pulse. Based on the capacitive coupling of the capacitor CC, the output circuit 120 uses the positive pulse of the clock signal CLK5 to further raise the high bias value at the bias node A(n) to ensure the conduction of the output transistor MO.

The positive pulse of the gate drive signal G(n+a) (or, the gate drive signal G(9)) is generated based on the second positive pulse of the clock signal CLK1. At time point tp6, the clock signal CLK1 begins to have the second positive pulse. Therefore, at time point tp6, the pull-down circuit 130 reacts to the positive pulse of the gate drive signal G(n+a) to pull down the high bias value at the bias node A(n) to the low bias value. Therefore, the control circuit 142 uses the low bias value at the bias node A(n) to raise the bias value at the control node B(n) to the high bias value. The noise suppression transistor MN1 is turned on at time tp6 to start suppressing the noise at the bias node A(n). The noise suppression transistor MN2 is also turned on at time tp6 to start suppressing the noise at the output end of the gate driver unit GU(n).

In summary, during the display period of the display device, the anti-noise circuit responds to the high bias value of the bias node to disable the noise suppression circuit. In addition, during the blanking period of the display device, the anti-noise circuit also responds to the high voltage value of the reset signal of the gate drive circuit to disable the noise suppression circuit. The noise suppression circuit can rest during the blanking period. In this way, the deterioration of the noise suppression circuit can be reduced. The noise suppression circuit can provide stable anti-noise operation. Therefore, the reliability of the gate drive unit can be improved.

Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of the attached patent application.

110: Lifting circuit

120: Output circuit

130: Pull-down circuit

140: Anti-noise circuit

141: Noise suppression circuit

A(n): bias node

CC: Capacitor

CLK(n): clock signal

GU(n): Gate drive unit

G(n), G(n-a), G(n+a): gate drive signal

MO: output transistor

RST: Reset signal

VDDF: System high voltage

VDDR: system low voltage

Claims (10)

A gate drive circuit for a display device includes: a plurality of gate drive units, wherein the n-th gate drive unit of the plurality of gate drive units includes: a lifting circuit, coupled to a bias node, configured to respond to an (n-a)-th gate drive signal to raise a bias value at the bias node; an output circuit, coupled to the bias node, configured to respond to a corresponding clock signal and the bias value at the bias node to provide an n-th gate drive signal; a pull-down circuit, coupled to the bias node, configured to respond to an (n+a)-th gate drive signal to raise a bias value at the bias node; A gate driving signal is used to pull down the bias value at the bias node; and an anti-noise circuit, comprising: a noise suppression circuit, coupled to the bias node, configured to suppress the noise at the bias node, wherein during the display period of the display device, the anti-noise circuit responds to the high bias value of the bias node to disable the noise suppression circuit, and wherein during the blanking period of the display device, the anti-noise circuit responds to the high voltage value of the reset signal of the gate driving circuit to disable the noise suppression circuit, wherein n and a are positive integers respectively. A gate drive circuit as described in claim 1, wherein during the display period of the display device, the anti-noise circuit responds to the low bias value of the bias node to enable the noise suppression circuit. The gate drive circuit as described in claim 1, wherein the anti-noise circuit further comprises: a control circuit coupled to the noise suppression circuit and the bias node, configured to receive the reset signal and the inverted reset signal, and to control the noise suppression circuit according to the bias value at the bias node, the reset signal and the inverted reset signal, wherein the inverted reset signal is a complementary signal of the reset signal. A gate drive circuit as described in claim 3, wherein: during the blanking period, the reset signal has a high voltage value, the inverted reset signal has a low voltage value, and during the display period, the reset signal has a low voltage value, the inverted reset signal has a high voltage value. The gate drive circuit as described in claim 4, wherein the control circuit comprises: a first control transistor, the first end of the first control transistor and the control end of the first control transistor are used to receive the inverted reset signal, and the second end of the first control transistor is coupled to the noise suppression circuit; a second control transistor, the first end of the second control transistor is coupled to the second end of the first control transistor, the second end of the second control transistor is coupled to the reference low voltage, and the control end of the second control transistor is coupled to the bias node; and a third control transistor, the first end of the third control transistor is coupled to the second end of the first control transistor, the second end of the third control transistor is coupled to the reference low voltage, and the control end of the third control transistor is used to receive the reset signal. A gate drive circuit as described in claim 5, wherein: the first control transistor has a first channel width-to-length ratio, the second control transistor has a second channel width-to-length ratio, and the second channel width-to-length ratio is greater than the first channel width-to-length ratio. The gate drive circuit as described in claim 3, wherein the noise suppression circuit comprises: a first noise suppression transistor, a first end of the first noise suppression transistor is coupled to the bias node, a second end of the first noise suppression transistor is coupled to a reference low voltage, and a control end of the first noise suppression transistor is coupled to the control circuit. The gate drive circuit as described in claim 7, wherein the noise suppression circuit further comprises: a second noise suppression transistor, wherein the first end of the second noise suppression transistor is coupled to the output end of the nth stage gate drive unit, the second end of the second noise suppression transistor is coupled to the reference low voltage, and the control end of the second noise suppression transistor is coupled to the control circuit. The gate drive circuit as described in claim 8, wherein the output circuit comprises: an output transistor, the first end of the output transistor receives the clock signal, the second end of the output transistor serves as the output end of the n-th gate drive unit, the control end of the output transistor is coupled to the bias node; and a capacitor coupled between the second end of the output transistor and the control end of the output transistor. The gate drive circuit as described in claim 1, wherein the n-th gate drive unit further includes: a reset circuit coupled to the bias node, configured to reset the bias value at the bias node using the high voltage value of the reset signal during the blanking period.

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