TWI858768B - Voice activity detection device and voice activity detection method - Google Patents

Abstract

A voice activity detection device includes an audio processing circuit, a first memory, and a processor. The audio processing circuit processes an audio signal from an audio generator circuit to generate first audio data. The first memory stores the first audio data and a first program code. The processor executes the first program code to operate in a first mode, and is switched from operating in the first mode to operating in a second mode in response to an interrupt signal from the audio generator circuit, in order to determine whether the first audio data stored in the first memory includes a human voice signal, in which the power consumption of the processor operating in the first mode is lower than that of the processor operating in the second mode.

Description

Voice activity detection device and voice activity detection method

This case is about a voice activity detection device, and more particularly about a voice activity detection device and a voice activity detection method that can save power consumption.

With the development of technology, more and more electronic devices can be controlled by voice. In the prior art, voice activity detection devices usually use a master processor and a slave processor to detect voice commands. During standby, the master processor is in a dormant state, and the slave processor can operate to wait for receiving a voice command and wake up the master processor accordingly. After waking up the master processor, the slave processor enters a dormant state, and the awakened master processor can perform subsequent operations according to the voice command. In the above technology, the main processor and the slave processor will access the same memory together, so that the memory cannot be actively switched to operate in a low-power mode, and during the same period, one of the main processor and the slave processor is in a sleep state without performing other substantial operations, resulting in increased system cost and power consumption.

In some implementations, one of the purposes of this case is to provide a voice activity detection device and a voice activity detection method that can save power consumption and system cost, so as to improve the shortcomings of the previous technology.

In some embodiments, the voice activity detection device includes an audio processing circuit, a first memory, and a processor. The audio processing circuit processes an audio signal provided by an audio generation circuit to generate a first audio data. The first memory stores the first audio data and a first program code. The processor executes the first program code to operate in a first mode, and switches to operate in a second mode in response to an interrupt signal provided by the audio generation circuit to execute a second program code in a second memory to determine whether the first audio data stored in the first memory includes a human voice signal, wherein the power consumption of the processor operating in the first mode is lower than the power consumption of the processor operating in the second mode.

In some implementations, the voice activity detection method includes the following operations: generating a first audio data according to an audio signal provided by an audio generation circuit, and storing the first audio data in a first memory; executing a first program code in the first memory by a processor to operate in a first mode; and switching to a second mode by the processor in response to an interrupt signal provided by the audio generation circuit to execute a second program code in a second memory to determine whether the first audio data stored in the first memory includes a human voice signal, wherein the power consumption of the processor operating in the first mode is lower than the power consumption of the processor operating in the second mode.

The features, implementation and effects of this case are described in detail below with reference to the diagrams for a preferred embodiment.

100: Voice activity detection device

101: Audio generation circuit

102,150:Memory

110: Interrupt controller

120: Oscillator

130: Processor

140: Audio processing circuit

141:Analog-to-digital converter

142: Audio codec

160:Memory interface unit

170: Clock generator circuit

171,172: Phase-locked loop

300: Annular buffer

600: Voice activity detection method

CK1, CK2: clock signal

CKREF: Reference clock signal

D1,D2,D3: audio data

P1, P2: Program code

RP: Read pointer

S201~S212,S401~S412,S610,S620,S630: Operation

SA: Audio signal

SD: Digital data

ST: interrupt signal

WP: Write Pointer

t0,t1,t2: time

〔Figure 1〕is a schematic diagram of a voice activity detection device drawn according to some embodiments of the present invention;〔Figure 2〕is an operation flow chart of the voice activity detection device of Figure 1 drawn according to some embodiments of the present invention;〔Figure 3〕is an operation schematic diagram of multiple memories in Figure 1 drawn according to some embodiments of the present invention;〔Figure 4〕is an operation flow chart of the voice activity detection device of Figure 1 drawn according to some embodiments of the present invention;〔Figure 5〕is a waveform timing diagram of the audio signal in Figure 1 drawn according to some embodiments of the present invention; and〔Figure 6〕is a flow chart of a voice activity detection method drawn according to some embodiments of the present invention.

All terms used in this article have their usual meanings. The definitions of the above terms in commonly used dictionaries and the use examples of any term discussed herein in the content of this case are only examples and should not limit the scope and meaning of this case. Similarly, this case is not limited to the various embodiments shown in this specification.

As used herein, "coupling" or "connection" may refer to two or more components making physical or electrical contact directly or indirectly, or two or more components operating or acting on each other. As used herein, the term "circuit" may refer to a device that is composed of at least one transistor and/or at least one active and passive component connected in a certain manner to process signals.

FIG1 is a schematic diagram of a voice activity detection (VAD) detection device 100 according to some embodiments of the present invention. The voice activity detection device 100 includes an interrupt controller 110, an oscillator 120, a processor 130, an audio processing circuit 140, a memory 150, a memory interface unit 160, and a clock generator circuit 170. The interrupt controller 110 is coupled to the audio generation circuit 101 to receive an interrupt signal ST generated by the audio generation circuit 101, and requests the processor 130 to perform corresponding hardware/software processing according to the interrupt signal ST. In some embodiments, the audio generation circuit 101 can collect sound signals in the application environment and generate an audio signal SA. The audio generation circuit 101 can provide the audio signal SA to the audio processing circuit 140, and can determine whether the audio signal SA meets a predetermined condition to generate an interrupt signal ST. For example, when the audio generation circuit 101 determines that the volume of the audio signal SA exceeds a predetermined critical value, the audio generation circuit 101 can generate an interrupt signal ST.

The oscillator 120 may generate a reference clock signal CKREF and transmit the reference clock signal CKREF to the clock generator circuit 170. In some embodiments, the oscillator 120 may be, but is not limited to, a quartz oscillator. The clock generator circuit 170 may generate the timing required by the processor 130, the audio processing circuit 140, and other circuits in the system according to the reference clock signal CKREF. For example, the clock generator circuit 170 may include a phase locked loop (PLL) 171 and a phase locked loop 172. The phase locked loop 171 may generate a clock signal CK1 according to the reference clock signal CKREF and provide the clock signal CK1 to the processor 130. Similarly, the phase-locked loop 172 can generate a clock signal CK2 according to the reference clock signal CKREF, and provide the clock signal CK2 to the audio processing circuit 140.

The processor 130 can access the program code P1 stored in the memory 150 to operate in the first mode and wait for the audio generation circuit 101 to generate the interrupt signal ST. When the audio generation circuit 101 generates the interrupt signal ST, the processor 130 can respond to the interrupt signal ST and instead execute the program code P2 in the memory 102 to switch from operating in the first mode to operating in the second mode, thereby determining whether one or more audio data stored in the memory 150 includes a human voice signal. In some embodiments, the power consumption generated by the processor 130 operating in the first mode is lower than the power consumption generated by the processor 130 operating in the second mode. In other words, the first mode can be a low power consumption mode (or can be called a wait for interrupt mode). When the processor 130 operates in the first mode, the processor 130 will operate at a lower operating speed and wait to receive the interrupt signal ST, thereby saving power consumption. Alternatively, when the processor 130 switches to operate in the second mode, the processor 130 switches to receive the clock signal CK1 with a higher frequency, so the processor 130 will operate at a higher operating speed to more quickly detect whether there is a voice control command to be processed.

In some embodiments, the memory 150 may be, but is not limited to, a static random access memory. The processor 130 may be coupled to the memory 102 via the memory interface unit 160. In some embodiments, the memory 102 may be, but is not limited to, a dynamic random access memory. The audio processing circuit 140 may process the audio signal SA to generate audio data (e.g., the audio data D1~D3 in Figure 3). For example, the audio processing circuit 140 may include an analog-to-digital converter 141 and an audio codec (codec) 142. The analog-to-digital converter 141 converts the audio signal SA according to the clock signal CK2 to generate digital data SD. The audio codec 142 processes the digital data SD to generate audio data.

FIG. 2 is a flowchart of the operation of the voice activity detection device 100 of FIG. 1 according to some embodiments of the present invention. In some embodiments, the multiple operations of FIG. 2 correspond to a loop mode. In operation S201, the audio processing circuit 140 and the clock generator circuit 170 are initialized. For example, after the voice activity detection device 100 is started, the processor 130 may execute the relevant software and/or firmware of the system to perform initial settings for various parameters in the audio processing circuit 140 and the clock generator circuit 170 (for example, but not limited to, clock frequency, sampling rate, gain size, codec format, etc.). In operation S202, a part of the circuit (excluding the phase-locked loop 172) is set to operate in a low speed state. For example, after completing the initialization, the aforementioned related software and/or firmware may further close the phase-locked loop 171, and switch the clock signal received by the processor 130 from the clock signal CK1 to another clock signal generated based on the reference clock signal CKREF (not shown in FIG. 1 , whose frequency may be lower than the frequency of the reference clock signal CKREF). At the same time, the aforementioned related software and/or firmware may further switch the clock signal (not shown) received by the memory interface unit 160 to the reference clock signal CKREF, so that the memory interface unit 160 also operates in a low-speed state. On the other hand, since the phase-locked loop 172 is not closed, the phase-locked loop 172 can provide the clock signal CK2 to the audio processing circuit 140 according to the reference clock signal CKREF.

In operation S203, the memory 102 is controlled to operate in the third mode, and the program code P1 in the memory 150 is executed. In operation S204, the processor 130 operates in the first mode. For example, as described above, the processor 130 may execute the program code P1 in the memory 150 to operate in the first mode to wait for the audio generation circuit 101 to generate the interrupt signal ST. On the other hand, the aforementioned related software and/or firmware may control the memory 102 to operate in the third mode. In some embodiments, the third mode may be a low power mode of the memory 102. For example, if the memory 102 is a dynamic random access memory, the third mode may be a self-refresh mode. When the processor 130 executes the program code P1 in the memory 150 to operate in the first mode, the processor 130 does not access the memory 102 or the need to access the memory 102 is relatively small. Under this condition, the operating speed of some circuits (such as including the memory 102, the memory interface unit 160, etc.) can be reduced to save overall power consumption.

In operation S205, the audio generation circuit 101 is enabled to start generating the audio signal SA, and the audio data is written to the memory 150 through the audio processing circuit 140. As mentioned above, when the processor 130 executes the program code P1 in the memory 150, the processor 130 operates in the first mode to wait for the audio generation circuit 101 to send an interrupt signal ST. After the audio generation circuit 101 is activated by the aforementioned related software and/or firmware, the audio generation circuit 101 can start collecting sounds in the environment to generate the audio signal SA, and the audio data corresponding to the audio signal SA is stored in the memory 150 through the audio processing circuit 140.

In operation S206, the audio generation circuit 101 sends an interrupt signal ST, and the processor 130 executes the program code P2 in the memory 102 in response to the interrupt signal ST to switch to the second mode of operation. In operation S207, the clock generator circuit 170 is configured so that the part of the circuit is changed to operate at a higher frequency, and the memory 102 is controlled to operate in the fourth mode. For example, when the audio generation circuit 101 determines that the volume of the audio signal SA exceeds a predetermined threshold value, the audio generation circuit 101 can send an interrupt signal ST to the interrupt controller 110, so that the processor 130 can respond to the interrupt signal ST and change to execute the program code P2 in the memory 102 to operate in the second mode. On the other hand, under this condition, the aforementioned related software and/or firmware can configure the clock generator circuit 170 accordingly, so that the phase-locked loops 171 and 172 can generate clock signals CK1 and CK2 with higher frequencies, and switch the memory interface unit 160 to operate based on the clock signal with higher frequency. At the same time, the aforementioned related software and/or firmware can control the memory 102 to operate in the fourth mode, wherein the fourth mode can be an active mode with faster operation speed. In other words, the power consumption generated by the memory 102 operating in the third mode is lower than the power consumption generated by the memory 102 operating in the fourth mode.

In operation S208, it is determined whether the audio data in the memory 150 includes a human voice signal. If it is determined that the audio data in the memory 150 includes a human voice signal, operation S209 is performed. Alternatively, if it is determined that the audio data in the memory 150 does not include a human voice signal, operation S202 is performed. In operation S209, the memory 150 is controlled to transfer the audio data to the memory 102, and the audio processing circuit 140 is controlled to store the subsequently generated audio data in the memory 102. For example, the program code P2 in the memory 102 includes a signal processing algorithm for identifying a human voice signal. The processor 130 can execute the program code P2 and determine whether the audio data in the memory 150 includes a human voice signal according to the algorithm. If the audio data includes a human voice signal, the processor 130 can control the memory 150 to transfer the audio data to the memory 102 (and no longer store it in the memory 150). In this way, after transferring the audio data to the memory 102, the processor 130 can release the temporary storage space in the memory 150 previously used to store the audio data for use by other circuits in the system. If the audio data does not include a human voice signal, the operation S202 is re-executed to wait for the next voice command again.

In operation S210, it is determined whether the audio data in the memory 102 contains a keyword message. If it is determined that the audio data in the memory 102 contains a keyword message, operation S211 is performed. Alternatively, if it is determined that the audio data in the memory 102 does not contain a keyword message, operation S212 is performed. In operation S211, subsequent processing is performed according to the keyword message. In operation S212, it is continuously detected whether a keyword message appears until the audio generation circuit 101 determines that the volume of the subsequently received audio signal SA does not exceed a predetermined critical value.

For example, the program code P2 in the memory 102 further includes a signal processing algorithm for identifying a keyword message. The processor 130 may execute the program code P2 and determine whether the audio data in the memory 102 includes the keyword message according to the algorithm. In some embodiments, the keyword message may be, but is not limited to, a voice command for controlling a specific device to perform a preset operation. If the processor 130 determines that the audio data in the memory 102 includes a keyword message, the processor 130 may perform subsequent processing according to the keyword message to control the specific device to perform the preset operation. Alternatively, if the processor 130 determines that the audio data in the memory 102 does not contain a keyword message, the processor 130 may continue to determine whether a keyword message appears based on the audio data subsequently stored in the memory 102 until the audio generation circuit 101 determines that the volume of the subsequently received audio signal SA does not exceed a predetermined threshold value (for example, the user stops inputting voice commands).

In the above operation, the processor 130 executes the program code P1 in the memory 150 to operate in the first mode to reduce power consumption and wait for the interrupt signal ST. Therefore, the operation performed by the processor 130 in the first mode is relatively simple. The processor 130 executes the program code P2 in the memory 102 to operate in the second mode to execute multiple algorithms such as human voice recognition and keyword recognition at a higher processing speed. Therefore, the code size and/or complexity of the code P1 are relatively lower than the code size and/or complexity of the code P2. In some embodiments, since the cost of the memory 102 is higher than the cost of the memory 150, the required capacity of the memory 102 can be reduced by the above configuration, thereby reducing the overall cost. In addition, after switching to use the memory 102, the memory 150 can release the temporary storage space originally storing the audio data, so other circuits in the system can also share the memory 150 in a time-sharing manner, thereby avoiding the need for additional memory settings, thereby reducing the additional power consumption and/or system cost of the system.

FIG3 is a schematic diagram of the operation of the memory 150 and the memory 102 in FIG1 according to some embodiments of the present invention. As mentioned above, the memory 150 can be a static random access memory. The processor 130 can configure the memory 150 to plan a temporary storage space, wherein the temporary storage space can be set as a ring buffer 300. The processor 130 can access the ring buffer 300 according to the write pointer WP and the read pointer RP. Before operation S209 is performed, the audio data D1 and the audio data D2 generated by the audio processing circuit 140 according to the audio signal SA of the audio generating circuit 101 may be stored in the ring buffer 300. In operation S209, the processor 130 reads the audio data D1 according to the read pointer RP and determines that the audio data D1 includes a human voice signal, so the audio data D1 and the audio data D2 (the write pointer WP corresponds to the end position of the audio data D2, indicating that the audio data D2 is also valid audio data) are transferred to the memory 102, and the audio processing circuit 140 is controlled to store the subsequently generated audio data D3 in the memory 102. That is, the audio processing circuit 140 generates the audio data D3 according to the audio signal SA after generating the plurality of audio data D1 and D2. After transferring the audio data D1 and the audio data D2 to the memory 102, the corresponding temporary storage space in the circular buffer 300 can be released. Then, the processor 130 can determine whether the multiple continuous audio data D1, D2 and D3 in the memory 102 contain human voice signals and keyword information. In this way, the processor 130 can merge the multiple audio data D1, D2 and D3, and more completely determine whether the user has issued a voice command based on the continuous audio content after the merger of these audio data.

FIG. 4 is an operation flow chart of the voice activity detection device 100 of FIG. 1 according to some embodiments of the present invention. In some embodiments, the multiple operations of FIG. 4 correspond to the interrupt mode, and the power consumption thereof may be lower than the power consumption of the loop mode of FIG. 2. The interrupt mode includes multiple operations S401~S412, wherein multiple operations S403~S404, S406 and S408~S412 are respectively the same as multiple operations S203~S204, S206 and S208~S212 of FIG. 2, so they will not be repeated here. The following mainly describes the parts that are different from the operations of FIG. 2.

In operation S401, the analog-to-digital converter 141 and the clock generator circuit 170 are initialized, and the audio codec 142 is turned off. Different from operation S201, in this example, after the voice activity detection device 100 is just started, the processor 130 can execute the relevant software and/or firmware of the system to only initialize the analog-to-digital converter 141 and the clock generator circuit 170, wherein the audio codec 142 is still in a turned-off state. In operation S402, part of the circuit (including the phase-locked loop 171 and the phase-locked loop 172) is set to operate in a low speed state. Different from operation S202, in this example, the aforementioned related software and/or firmware further closes the phase-locked loop 172. Under this condition, the clock generator circuit 170 does not provide the clock signal CK2 to the audio processing circuit 140.

In operation S405, the audio generation circuit 101 is enabled to start generating the audio signal SA. Different from operation S205, in this example, since the audio processing circuit 140 has not received the clock signal CK2 and the audio codec 142 has not been enabled, the audio processing circuit 140 will not generate corresponding audio data according to the audio signal SA at this stage, nor will it store the corresponding audio data in the memory 150.

In operation S407, the clock generator circuit 170 is configured, and the phase-locked loop 172 and the audio codec 142 are enabled, so that the circuit part is changed to operate at a higher frequency, and the memory 102 is controlled to operate in the fourth mode. Different from FIG. 2, in this example, when the audio generation circuit 101 determines that the volume of the audio signal SA exceeds a predetermined threshold value, the aforementioned related software/firmware can configure the clock generator circuit 170 and enable all phase-locked loops (e.g., including the phase-locked loops 171 and 172) and the audio codec 142 to start generating the clock signal CK1 and the clock signal CK2 with a higher frequency. Thus, the clock generator circuit 170 starts to provide the clock signal CK2 to the analog-to-digital converter 141, so that the audio codec 142 can start to generate corresponding audio data and start to store the audio data in the memory 150. On the other hand, the processor 130 can execute the program code P2 in the memory 102 to determine whether the audio data in the memory 150 contains a human voice signal.

Accordingly, it should be understood that in the loop mode of FIG. 2 , when the processor 130 operates in the first mode, the audio processing circuit 140 stores audio data in the memory 150. Different from FIG. 2 , in the interrupt mode of FIG. 4 , when the processor 130 operates in the first mode, the clock generator circuit 170 does not generate the clock signal CK2, so that at least a portion of the circuits in the audio processing circuit 140 are in a disabled state and do not operate, and no audio data is generated in the memory 150. After receiving the interrupt signal ST, the processor 130 changes to operate in the second mode, and the audio processing circuit 140 starts to generate and store audio data in the memory 150. In this way, the interrupt mode of FIG. 4 can save more power consumption. In contrast, the loop mode in Figure 2 can collect more complete audio data. Please refer to the description of Figure 5 for this.

FIG5 is a waveform timing diagram of the audio signal SA in FIG1 according to some embodiments of the present invention. To make it easier to understand the difference between the loop mode of FIG2 and the interrupt mode of FIG4, as shown in FIG5, in the loop mode, the audio codec 142 and the phase-locked loop 172 are enabled, so that the audio processing circuit 140 can store the corresponding audio data into the memory 150 starting at time t0. When the audio generating circuit 101 determines that the volume of the audio signal SA is greater than a predetermined threshold value, the audio generating circuit 101 sends an interrupt signal ST so that the processor 130 can switch to the second mode at time t1 to start determining whether the audio data contains a human voice signal and a keyword message until the volume of the audio signal SA starts to be continuously lower than the predetermined threshold value at time t2. Different from the loop mode, in the interrupt mode, the audio processing circuit 140 does not start to store the corresponding audio data to the memory 150 at time t0, but starts to store the corresponding audio data to the memory 150 after receiving the interrupt signal ST at time t1. In other words, in the loop mode, the voice activity detection device 100 can store more complete audio data for detection, so a higher voice detection accuracy can be obtained. In the interrupt mode, the power consumption generated by the audio processing circuit 140, the clock generator circuit 170 and the memory 150 before time t1 is lower, so that the voice activity detection device 100 operating in the interrupt mode can have lower power consumption.

FIG6 is a flow chart showing a voice activity detection method 600 according to some embodiments of the present invention. In operation S610, a first audio data is generated according to an audio signal provided by an audio generation circuit, and the first audio data is stored in a first memory. In operation S620, a processor executes a first program code in the first memory to operate in a first mode. In operation S630, the processor switches to the second mode in response to an interrupt signal provided by the audio generation circuit to execute a second program code in a second memory to determine whether the first audio data stored in the first memory includes a human voice signal, wherein the power consumption of the processor operating in the first mode is lower than the power consumption of the processor operating in the second mode.

The multiple operations of the above-mentioned voice activity detection method 600 can refer to the description of the above-mentioned embodiments, so they will not be repeated here. The multiple operations in the above-mentioned Figures 2, 4 and/or 6 are only examples, and are not limited to be executed in the order in this example. Without violating the operation method and scope of each embodiment of this case, the various operations in Figures 2, 4 and/or 6 can be appropriately added, replaced, omitted or executed in a different order (for example, they can be executed simultaneously or partially simultaneously).

In summary, the voice activity detection device and voice activity detection method in some embodiments of the present invention can perform voice activity detection without using an additional slave processor, and can further improve power consumption.

Although the embodiments of this case are described above, these embodiments are not used to limit this case. People with ordinary knowledge in this technical field can make variations to the technical features of this case based on the explicit or implicit content of this case. All these variations may fall within the scope of patent protection sought by this case. In other words, the scope of patent protection of this case shall be subject to the scope of patent application defined in this specification.

100: Voice activity detection device

101: Audio generation circuit

102,150:Memory

110: Interrupt controller

120: Oscillator

130: Processor

140: Audio processing circuit

141:Analog-to-digital converter

142: Audio codec

160:Memory interface unit

170: Clock generator circuit

171,172: Phase-locked loop

CK1, CK2: clock signal

CKREF: Reference clock signal

P1, P2: Program code

SA: Audio signal

SD: Digital data

ST: interrupt signal

Claims (13)

A voice activity detection device comprises: an audio processing circuit, processing an audio signal provided by an audio generating circuit to generate a first audio data; a first memory, storing the first audio data and a first program code; and a processor, executing the first program code to operate in a first mode, and switching to operate in a second mode in response to an interrupt signal provided by the audio generating circuit to execute a second program code in a second memory to determine Whether the first audio data stored in the first memory includes a human voice signal, wherein the power consumption of the processor operating in the first mode is lower than the power consumption of the processor operating in the second mode, the processor further controls the second memory to switch from operating in a third mode to operating in a fourth mode in response to the interrupt signal, and the power consumption of the second memory operating in the third mode is lower than the power consumption of the second memory operating in the fourth mode. As in claim 1, the voice activity detection device, wherein when the processor determines that the audio data includes the human voice signal, the processor further controls the first memory to transfer the first audio data to the second memory, and the audio processing circuit further stores a second audio data in the second memory, wherein the audio processing circuit generates the second audio data according to the audio signal after generating the first audio data. As in the voice activity detection device of claim 2, the processor further determines whether the first audio data and the second audio data in the second memory contain a keyword message. As in claim 2, the voice activity detection device, wherein after the first memory transfers the first audio data to the second memory, the first memory further releases a temporary storage space in the first memory previously used to store the first audio data. 】As claimed in claim 1, the second memory is a dynamic random access memory, the third mode is a self-refresh mode, and the fourth mode is an active mode. A voice activity detection device as claimed in claim 1, wherein when the processor operates in the first mode, the audio processing circuit stores the first audio data in the first memory. A voice activity detection device as claimed in claim 1, wherein when the processor operates in the first mode, the audio processing circuit does not store the first audio data in the first memory. As in claim 1, the voice activity detection device, wherein the audio processing circuit comprises: an analog-to-digital converter, converting the audio signal into digital data; and an audio codec, processing the digital data to generate the first audio data. The voice activity detection device of claim 1 further comprises: a clock generator circuit, which generates a first clock signal according to a reference clock signal, wherein when the processor operates in the first mode, the clock generator circuit generates the first clock signal to the audio processing circuit, and the audio processing circuit processes the audio signal according to the first clock signal to generate the first audio data. The voice activity detection device of claim 1 further comprises: a clock generator circuit that generates a first clock signal according to a reference clock signal, wherein when the processor operates in the first mode, the clock generator circuit does not generate the first clock signal, so that the audio processing circuit does not generate the first audio data. A voice activity detection device comprises: an audio processing circuit, processing an audio signal provided by an audio generating circuit to generate a first audio data; a first memory, storing the first audio data and a first program code; and a processor, executing the first program code to operate in a first mode, and switching to operate in a second mode in response to an interrupt signal provided by the audio generating circuit, to execute a second program code in a second memory to determine whether the first audio data stored in the first memory includes a human voice signal, wherein the power consumption of the processor operating in the first mode is lower than the power consumption of the processor operating in the second mode, and the code size of the first program code is smaller than the code size of the second program code. A voice activity detection method comprises: generating a first audio data according to an audio signal provided by an audio generating circuit, and storing the first audio data in a first memory; executing a first program code in the first memory by a processor to operate in a first mode; switching to a second mode by the processor in response to an interrupt signal provided by the audio generating circuit to execute a second program code in a second memory to determine whether the first audio data stored in the first memory is a first mode; Whether the first audio data in the first memory includes a human voice signal, wherein the power consumption of the processor operating in the first mode is lower than the power consumption of the processor operating in the second mode; and the processor controls the second memory to switch from operating in a third mode to operating in a fourth mode in response to the interrupt signal, wherein the power consumption of the second memory operating in the third mode is lower than the power consumption of the second memory operating in the fourth mode. A voice activity detection method comprises: generating a first audio data according to an audio signal provided by an audio generating circuit, and storing the first audio data in a first memory; executing a first program code in the first memory by a processor to operate in a first mode; and switching to a second mode by the processor in response to an interrupt signal provided by the audio generating circuit to execute a second program code in a second memory to determine whether the first audio data stored in the first memory includes a human voice signal, wherein the power consumption of the processor operating in the first mode is lower than the power consumption of the processor operating in the second mode, and the code size of the first program code is smaller than the code size of the second program code.

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