TWI858629B - Compensation method for wafer bonding - Google Patents

Abstract

A compensation method for wafer bonding includes bonding a first wafer and a second wafer, the first wafer including a first conductive pad and a second conductive pad. A first overlay check is performed. A result of the first overlay check is determined whether the result is within a first predetermined specification. If the result of the first overlay check is determined as beyond the first predetermined specification, performing a first compensation method to form a compensated first wafer and a compensated second wafer, wherein a position of a first conductive pad of the compensated first wafer is different from a position of the first conductive pad of the first wafer, and a position of a second conductive pad of the compensated first wafer is different from a position of the second conductive pad of the first wafer.

Description

Compensation method for wafer bonding

The present disclosure relates to a compensation method for wafer bonding.

With the development of the semiconductor industry, the wafer level packaging (WLP) process has been continuously improved. In order to increase the density of components, three-dimensional integrated circuits (3DICs) have also been developed, in which two chips (or integrated circuits) are bonded together and electrically connected. However, these new bonding technologies will face challenges in the process, such as wafer warpage, and may cause overlay errors in the process. Therefore, a compensation method is needed to solve the above problems.

Some embodiments of the present disclosure provide a compensation method for wafer bonding, comprising bonding a first wafer and a second wafer, wherein the first wafer has a first conductive pad and a second conductive pad, and the second wafer has a third conductive pad and a fourth conductive pad; performing a first covering inspection on the first wafer and the second wafer, the first covering inspection comprising confirming whether the first conductive pad contacts the third conductive pad, and confirming whether the second conductive pad contacts the fourth conductive pad; confirming whether the result of the first covering inspection meets a first predetermined standard; if the result of the first covering inspection does not meet the first predetermined standard, A first compensation method is performed to form a compensated first wafer and a compensated second wafer, the first compensation method comprising defining a position of a first conductive pad and a position of a second conductive pad of the compensated first wafer, and defining a position of a third conductive pad and a position of a fourth conductive pad of the compensated second wafer, wherein the position of the first conductive pad of the compensated first wafer is different from the position of the first conductive pad of the first wafer, and the position of the second conductive pad of the compensated first wafer is different from the position of the second conductive pad of the first wafer; and bonding the compensated first wafer and the compensated second wafer.

In some embodiments, the result of the first coverage inspection failing to meet the first predetermined standard includes a contact area between the first conductive pad of the first wafer and the third conductive pad of the second wafer being smaller than a first predetermined value or a contact area between the second conductive pad of the first wafer and the fourth conductive pad of the second wafer being smaller than a second predetermined value.

In some embodiments, the method further includes executing a second compensation method before executing the first compensation method, the second compensation method including separating the first wafer and the second wafer; adjusting the relative positions of the first wafer and the second wafer; and rejoining the first wafer and the second wafer; performing a second coverage inspection, the second coverage inspection including confirming whether the first conductive pad of the first wafer contacts the third conductive pad of the second wafer, and confirming whether the second conductive pad of the first wafer contacts the fourth conductive pad of the second wafer; and confirming whether the result of the second coverage inspection meets the second predetermined standard, wherein the first compensation method is executed in response to the result of the second coverage inspection not meeting the second predetermined standard.

In some embodiments, the method further includes performing a third coverage inspection before bonding the compensated first wafer and the compensated second wafer, the third coverage inspection including confirming whether the first conductive pad of the compensated first wafer contacts the corresponding first conductive through hole, and confirming whether the second conductive pad of the compensated first wafer contacts the corresponding second conductive through hole.

In some embodiments, the first compensation method is performed by a lithography tool, and the second compensation method is performed by a bonding device.

In some embodiments, the first compensation method is performed so that the position of the compensated third conductive pad of the second wafer is different from the position of the third conductive pad of the second wafer, and the position of the compensated fourth conductive pad of the second wafer is different from the position of the fourth conductive pad of the second wafer.

Some embodiments of the present disclosure provide a compensation method for wafer bonding, comprising bonding a first wafer and a second wafer, wherein the first wafer has a first conductive pad and the second wafer has a second conductive pad; performing a first processing process on the first wafer and the second wafer, wherein before performing the first processing process, the first conductive pad has a first position, and there is a first offset between the first position and an ideal position, and after performing the first processing process, the first conductive pad has a second position, and there is a second offset between the second position and the first position. ; performing a second processing step on the second wafer, wherein after performing the second processing step, the first conductive pad has a third position, and the third position and the second position have a third offset; performing a first compensation method to form a compensated first wafer and a compensated second wafer, the first compensation method comprising defining a position of a first conductive pad of the compensated first wafer, wherein the position of the first conductive pad of the compensated first wafer is determined by a first offset, a second offset, and a third offset; and bonding the compensated first wafer and the compensated second wafer.

In some embodiments, the difference between the position of the first conductive pad of the first wafer to be compensated and the position of the first conductive pad of the first wafer is the sum of the first offset, the second offset and the third offset.

In some embodiments, the method further includes executing a second compensation method before executing the first processing step, the second compensation method including: separating the first wafer and the second wafer; adjusting a relative position of the first wafer and the second wafer; and rejoining the first wafer and the second wafer; performing a coverage inspection, the coverage inspection including confirming whether the first conductive pad of the first wafer contacts the second conductive pad of the second wafer; and confirming whether the result of the coverage inspection meets a predetermined standard.

In some embodiments, the first compensation method is performed by a lithography tool, and the second compensation method is performed by a bonding device.

The following disclosure provides many different embodiments or examples for implementing different features of the subject matter provided. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, in various examples, the disclosure may repeatedly refer to numbers and/or letters. This repetition is for the purpose of simplicity and clarity, and does not itself dictate the relationship between the various embodiments and/or configurations discussed.

Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper," and the like, may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

FIG. 1A to FIG. 6B are schematic diagrams of wafer bonding methods of some embodiments of the present disclosure at different stages, wherein FIG. 1B, 2B, 3B, 4B, 5B and 6B are cross-sectional views of FIG. 1A, 2A, 3A, 4A, 5A and 6A, respectively. In addition, for the sake of convenience, some elements (e.g., bonding layers 120 and 220) in FIG. 1B, 2B, 3B, 4B, 5B and 6B are not shown in FIG. 1A, 2A, 3A, 4A, 5A and 6A.

Please refer to FIG. 1A and FIG. 1B , which illustrate wafers W1 and W2 . In some embodiments, wafers W1 and W2 may be formed by semiconductor processes, wherein the semiconductor processes include deposition, patterning, etching, or other suitable processes to form functional circuits on wafers W1 and W2 .

Wafers W1 and W2 include substrates 100 and 200, respectively. In some embodiments, substrates 100 and 200 may be semiconductor substrates. The semiconductor substrate may be a bulk silicon substrate or a silicon-on-insulator substrate. According to alternative embodiments of the present disclosure, the semiconductor substrate may also use other semiconductor materials containing group III, group IV, and/or group V elements, which may include silicon germanium, silicon carbon, and/or III-V compound semiconductor materials.

A semiconductor element 110 is provided on the substrate 100 of the wafer W1, and a semiconductor element 210 is provided on the substrate 200 of the wafer W2. In some embodiments, the semiconductor elements 110 and 210 may have electronic components, such as transistors, diodes, resistors, capacitors, etc. In some embodiments, the semiconductor element 110 may include a memory array, which may include a non-volatile memory of a NAND structure. In some embodiments, the non-volatile memory of the NAND architecture may be a memory array arranged in three dimensions (3D). In other embodiments, the memory array may also include a memory array of a NOR or AND structure. On the other hand, the semiconductor element 210 may include a complementary metal oxide semiconductor (CMOS) element.

Referring to FIG. 1B , wafers W1 and W2 include bonding layers 120 and 220, respectively, wherein the bonding layer 120 of wafer W1 is bonded to the bonding layer 220 of wafer W2 in a bonding process discussed later. In some embodiments, the bonding layer 120 includes a dielectric layer 122 and a plurality of conductive pads 124 located in the dielectric layer 122. Similarly, the bonding layer 220 includes a dielectric layer 222 and a plurality of conductive pads 224 located in the dielectric layer 222.

In some embodiments, the bonding layer 120 may also be referred to as an internal connection layer, wherein the bonding layer 120 is the topmost layer of the wafer W1, and the conductive pad 124 in the bonding layer 120 is electrically connected to the electronic components in the semiconductor element 110. Similarly, the bonding layer 220 may also be referred to as an internal connection layer, wherein the bonding layer 220 is the topmost layer of the wafer W2, and the conductive pad 224 in the bonding layer 220 is electrically connected to the electronic components in the semiconductor element 210.

In the bonding process discussed later, the conductive pad 124 of the bonding layer 120 and the conductive pad 224 of the bonding layer 220 are connected to each other, so that the semiconductor element 110 of the wafer W1 and the semiconductor element 210 of the wafer W2 can be further electrically connected to each other.

In some embodiments, the material of the dielectric layers 122 and 222 may include silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, and/or other suitable dielectric materials.

In some embodiments, the conductive pads 124 and 224 may include metal materials, such as copper (Cu). In other embodiments, the conductive pads 124 and 224 may also include other suitable metal materials such as aluminum (Al) and tungsten (W).

FIGS. 2A to 4B discuss the bonding process between wafers W1 and W2. The bonding process discussed in FIGS. 2A to 4B may be referred to as hybrid bonding or metal-to-metal bonding. In some embodiments, if the material of the conductive pads 124 and 224 is copper (Cu), the bonding process may also be referred to as Cu-to-Cu bonding.

In some embodiments, before the bonding process discussed in FIGS. 2A to 4B , the bonding layers 120 and 220 of the wafers W1 and W2 may be subjected to a cleaning process and a plasma treatment, respectively, wherein the cleaning process may be used to remove the natural oxide on the conductive pads 124 and 224 , and the plasma treatment may be used to activate the conductive pads 124 and 224 .

Referring to FIG. 2A and FIG. 2B , one of the wafers W1 and W2 is flipped over. For example, in the embodiment of FIG. 2A and FIG. 2B , the wafer W2 is flipped 180 degrees so that the bonding layer 220 of the wafer W2 faces the bonding layer 120 of the wafer W1. Specifically, the conductive pads 224 in the bonding layer 220 of the wafer W2 are aligned with the conductive pads 124 in the bonding layer 120 of the wafer W1.

In some embodiments, wafers W1 and W2 can be docked by a bonding device. For example, the bonding device can include a first wafer support table and a second wafer support table, which are used to fix wafer W1 and wafer W2 respectively. Then, the positions of wafer W1 and wafer W2 are recorded by measuring alignment marks on wafer W1 and wafer W2. Then, wafer W1 is aligned with wafer W2 according to the positions of wafer W1 and wafer W2.

Referring to FIG. 3A and FIG. 3B , wafers W1 and W2 are joined so that the bonding layer 120 of wafer W1 contacts the bonding layer 220 of wafer W2. Wafers W1 and W2 can be squeezed against each other by the above-mentioned bonding device. Specifically, the conductive pads 124 of the bonding layer 120 of wafer W1 contact the conductive pads 224 of the bonding layer 220 of corresponding wafer W2.

In some embodiments, the bonding step of FIG. 3A and FIG. 3B can be referred to as temporary bonding, because in this bonding step, wafer W1 is brought into contact with wafer W2 by only lightly applying pressure to wafer W2 in the direction of wafer W1. In other words, during the temporary bonding, there is no strong bonding force between wafer W1 and wafer W2. Therefore, when the bonding between wafer W1 and wafer W2 is not ideal, a de-bonding process can be performed to separate wafer W1 and wafer W2 without damaging the bonding layers 120 and 220 of wafers W1 and W2. In some embodiments, the bonding step of FIG. 3A and FIG. 3B is performed at room temperature (e.g., about 25° C. to about 27° C.).

Referring to FIGS. 4A and 4B , a first process P1 is performed. In some embodiments, the first process P1 is an annealing process. In embodiments where the first process P1 is an annealing process, the annealing process will cause inter-diffusion of metal materials between the conductive pad 124 of the wafer W1 and the corresponding conductive pad 224 of the wafer W2, thereby tightly bonding the conductive pad 124 and the corresponding conductive pad 224. In some embodiments, the temperature of the annealing process is higher than the temperature of the temporary bonding process discussed in FIGS. 3A and 3B .

5A and 5B , a second processing step P2 is performed on the substrate 200 of the wafer W2 . In some embodiments, the second processing step P2 is a grinding process to reduce the thickness of the substrate 200 .

Referring to FIGS. 6A and 6B , a conductive feature 230 is formed in the substrate 200 of the wafer W2. The conductive feature 230 can pass through the substrate 200 and be electrically connected to the semiconductor element 210 of the wafer W2. In some embodiments, the conductive feature 230 can be formed by patterning the substrate 200 to form an opening in the substrate 200, filling the opening with a conductive material, and performing a planarization process until the substrate 200 is exposed. In some embodiments, the conductive feature 230 includes a metal material, such as copper (Cu). In other embodiments, the conductive feature 230 may also include other suitable metal materials such as aluminum (Al), tungsten (W), etc. In some embodiments, the conductive feature 230 may also be referred to as a through silicon via (TSV).

In some embodiments, other conductive structures (not shown) may also be successively formed on the substrate 200 of the wafer W2 and electrically connected to the conductive features 230 to further establish electrical connections with the semiconductor devices 210 of the wafer W2 and the semiconductor devices 110 of the wafer W1.

FIG. 7A and FIG. 7B are schematic diagrams of the results of wafer bonding of some embodiments of the present disclosure. It should be understood that some of the components in FIG. 7A and FIG. 7B are the same as those discussed in FIG. 1A to FIG. 6B, and these components will use the same symbols, and the relevant details will not be repeated.

FIG. 7A and FIG. 7B are schematic diagrams of bonding wafer W1 and wafer W2. Specifically, conductive pads 124A, 124B, and 124C are provided in dielectric layer 122 of wafer W1. In addition, wafer W1 further includes dielectric layer 132 and conductive vias 134A, 134B, and 134C located in dielectric layer 132, wherein conductive vias 134A, 134B, and 134C contact conductive pads 124A, 124B, and 124C, respectively. Similarly, conductive pads 224A, 224B, and 224C are provided in dielectric layer 222 of wafer W2. In addition, the wafer W2 further includes a dielectric layer 232 and conductive vias 234A, 234B, 234C in the dielectric layer 232, wherein the conductive vias 234A, 234B, 234C contact the conductive pads 224A, 224B, 224C, respectively. In some embodiments, the dielectric layer 132 and the conductive vias 134A, 134B, 134C can be referred to as an internal connection layer. In addition, the dielectric layer 232 and the conductive vias 234A, 234B, 234C can be referred to as an internal connection layer.

FIG. 7A is an ideal situation, and this ideal result is based on the fact that wafer W1 and wafer W2 have not been deformed during the manufacturing process. Therefore, the components on wafer W1 and wafer W2 are substantially located in ideal positions, which will allow wafer W1 and wafer W2 to be bonded as expected. For example, the conductive pad 124A (and conductive through hole 134A) of wafer W1 and the conductive pad 224A (and conductive through hole 234A) of wafer W2 are both located at the ideal position I1, so that the conductive pad 124A of wafer W1 can contact the conductive pad 224A of wafer W2 after bonding. The conductive pad 124B (and conductive through hole 134B) of wafer W1 and the conductive pad 224B (and conductive through hole 234B) of wafer W2 are both located at the ideal position I2, so that the conductive pad 124B of wafer W1 can contact the conductive pad 224B of wafer W2 after bonding. The conductive pad 124C (and conductive through hole 134C) of wafer W1 and the conductive pad 224C (and conductive through hole 234C) of wafer W2 are both located at the ideal position I3, so that the conductive pad 124C of wafer W1 can contact the conductive pad 224C of wafer W2 after bonding.

FIG. 7B is an actual situation according to some embodiments. Unlike FIG. 7A, wafer W1 and wafer W2 may be deformed during the manufacturing process, such as warpage. Taking FIG. 7B as an example, wafer W1 or wafer W2 may bend during the process. Therefore, during the bonding process, the force applied to wafer W1 or wafer W2 may flatten wafer W1 or wafer W2, but also cause the pattern on wafer W1 or wafer W2 to shift.

For example, in FIG. 7B , the conductive pad 124A (and the conductive through hole 134A) of the wafer W1 is offset by S1_A in the -X direction based on the ideal position I1, and the conductive pad 124C (and the conductive through hole 134C) is offset by S1_C in the +X direction based on the ideal position I3.

On the other hand, the conductive pad 224A (and the conductive through hole 234A) of the wafer W2 is offset by S2_A in the +X direction based on the ideal position I1, and the conductive pad 224C (and the conductive through hole 234C) is offset by S2_C in the -X direction based on the ideal position I3.

The above situation will make the conductive pad 124A of wafer W1 unable to contact the conductive pad 224A of wafer W2 (or the contact area is less than a predetermined value). Similarly, the conductive pad 124C of wafer W1 is also unable to contact the conductive pad 224C of wafer W2 (or the contact area is less than a predetermined value). The above situation can be called overlay error, which will cause undesirable electrical connection. In some embodiments, the predetermined value of the contact area is 50% of the junction area of one of the conductive pads 124A or the conductive pad 224A. In some embodiments, the predetermined value of the contact area is 30% of the junction area of one of the conductive pads 124A or the conductive pads 224A. Here, "junction area" may represent the total area of the conductive pad 124A (or the conductive pad 224A) used to connect to the conductive pad 224A (or the conductive pad 124A). The predetermined values of the contact areas of the conductive pads 124C and the conductive pads 224C also have a relationship similar to the above, so they are not repeated.

In some embodiments, the conductive pad 124B (and the conductive via 134B) of the wafer W1 and the conductive pad 224B (and the conductive via 234B) of the wafer W2 are substantially aligned with the ideal position I2. Therefore, the conductive pad 124B of the wafer W1 can contact the conductive pad 224B of the wafer W2 to generate an ideal electrical connection.

Figures 8A to 8D are schematic diagrams of coverage errors of some embodiments of the present disclosure. Figures 8A, 8B, 8C, and 8D illustrate the coverage errors of translation, rotation, scaling, and random, respectively.

In some embodiments, the displacement, rotation, and amplified overlay errors of FIG. 8A, FIG. 8B, and FIG. 8C can be compensated by a method to improve the bonding of wafers W1 and W2. For example, the compensation method can improve the bonding of wafers W1 and W2 by changing the relative positions of wafers W1 and W2. In the case of FIG. 8A, the relative positions of wafers W1 and W2 can be changed by moving wafer W1 (or wafer W2) in a linear manner. In the case of FIG. 8B, the relative positions of wafers W1 and W2 can be changed by moving wafer W1 (or wafer W2) in a rotational manner. In the situation of FIG. 8C , the relative positions of wafers W1 and W2 can be changed by enlarging (or reducing) wafer W1 (or wafer W2). For example, during the bonding process, pressure can be applied to the center of wafer W1 (or wafer W2) so that wafer W1 (or wafer W2) is radially enlarged (or reduced) from the center to the edge. The above compensation method can improve the bonding of wafers W1 and W2 by adjusting the bonding process. For example, referring to FIG. 7B , the above compensation method can be used to allow conductive pads 124A and 124C of wafer W1 to contact conductive pads 224A and 224C of wafer W2. Under certain circumstances (e.g., when the deformation of the wafer due to the process is too large), the bonding device cannot fully compensate for the error of wafer enlargement (or reduction) by adjusting the center pressure, and the bonding coverage of W1 and W2 may still be lower than expected.

In addition, referring to FIG. 8D , in some embodiments, the random error cannot be compensated by the above-mentioned compensation method to improve the bonding of the wafers W1 and W2 . Therefore, another compensation method is needed to improve the bonding of the wafers W1 and W2 .

FIG. 9 is a schematic diagram of a lithography process of some embodiments of the present disclosure. FIG. 10A is a schematic diagram of a bonding result of some embodiments of the present disclosure. FIG. 10B to FIG. 10E are schematic diagrams of compensation methods of some embodiments of the present disclosure. In detail, FIG. 10B to FIG. 10E provide different compensation methods, wherein the compensation method is based on the bonding result of FIG. 10A, and independently adjusts the exposure offset of different areas on the wafer during the subsequent lithography process, thereby achieving better bonding quality.

Please refer to FIG. 9 , which shows a wafer W1 (or wafer W2), wherein the wafer W1 includes a plurality of exposure regions A. During the lithography process, the lithography tool 500 (lithography tool) or scanner includes a light source, and the lithography tool 500 can irradiate the light generated by the light source onto the exposure region A through a photomask (not shown) to transfer the pattern of the photomask to the material layer (e.g., photoresist layer) in the exposure region A on the wafer W1. This pattern can define the position of the components on the wafer W1, such as the positions of the conductive pads 124A, 124B, and 124C. For example, a photoresist layer is formed on the dielectric layer 122 of the wafer W1, and the photoresist layer is exposed to transfer the pattern of the photomask to the top of the photoresist layer. The dielectric layer 122 is etched by the pattern of the photoresist layer to form a plurality of openings, wherein the shape and position of the openings correspond to the pattern of the photoresist layer, and finally conductive pads 124A, 124B, and 124C are formed in the openings. In other words, the positions of the conductive pads 124A, 124B, and 124C are defined by the exposure process of the lithography process. Therefore, by adjusting the exposure position, the positions of the conductive pads 124A, 124B, and 124C on the wafer W1 can be changed. Similarly, by adjusting the exposure position, the positions of the conductive pads 224A, 224B, 224C on the wafer W2 can be changed.

Please refer to FIG. 9 and FIG. 10A, wherein FIG. 10A is the same as the structure discussed in FIG. 7B. In some embodiments, the positions of the conductive pads 124A, 124B, and 124C of the wafer W1 may correspond to different exposure areas on the wafer W1. For example, the conductive pad 124A may correspond to the exposure area A1 of the wafer W1, the conductive pad 124B may correspond to the exposure area A2 of the wafer W1, and the conductive pad 124C may correspond to the exposure area A3 of the wafer W1. That is, during the exposure process of the lithography process, the position of the conductive pad 124A is defined by performing a first exposure step on the exposure area A1, the position of the conductive pad 124B is defined by performing a second exposure step on the exposure area A2, and the position of the conductive pad 124C is defined by performing a third exposure step on the exposure area A3. The first, second, and third exposure steps are performed at different time points, so the positions of the conductive pads 124A, 124B, and 124C can be adjusted independently. In some embodiments, the exposure area A2 is the central area of the wafer W1, and the exposure areas A1 and A3 are the edge areas of the wafer W1, but the present disclosure is not limited to this.

Similarly, the positions of the conductive pads 224A, 224B, 224C of the wafer W2 can also be defined by different exposure steps of the exposure process, so the relevant details will not be repeated.

Please refer to Figures 9 and 10B, and a compensation method is performed based on the bonding result of wafer W1 and wafer W2 in Figure 10A to generate new wafers W1' and W2'. Referring to wafer W1', the conductive pad 124A' of wafer W1' is offset by S1_A relative to the conductive pad 124A of wafer W1, and the conductive pad 124C' of wafer W1' is offset by S1_C relative to the conductive pad 124C of wafer W1. That is, in the first exposure step of forming the conductive pad 124A', the exposure area A1 can be exposed with an offset of S1_A. And in the third exposure step of forming the conductive pad 124C', the exposure area A3 can be offset by S1_C. In some embodiments, since the offset S1_A and the offset S1_C are defined in different exposure steps, the offset S1_A and the offset S1_C may have different directions and sizes, which is beneficial for adjusting the flexibility of the conductive pad position.

Similarly, the conductive pad 224A’ of wafer W2’ is offset by S2_A relative to the conductive pad 224A of wafer W2, and the conductive pad 224C’ of wafer W2’ is offset by S2_C relative to the conductive pad 224C of wafer W2. That is, in the first exposure step of forming the conductive pad 224A’, the exposure area A1 can be exposed with an offset of S2_A. And in the third exposure step of forming the conductive pad 224C’, the exposure area A3 can be offset by S2_C. In some embodiments, since the offset S2_A and the offset S2_C are defined in different exposure steps, the offset S2_A and the offset S2_C can have different directions and sizes, which will be beneficial to adjust the flexibility of the conductive pad position.

In some embodiments, the position of the conductive pad 124B' of the wafer W1' is substantially the same as the position of the conductive pad 124B of the wafer W1. Similarly, the position of the conductive pad 224B' of the wafer W2' is substantially the same as the position of the conductive pad 224B of the wafer W2. That is, in the second exposure step of forming the conductive pad 124B' (or the conductive pad 224B'), no offset is generated in the exposure area A2.

After the compensation method of FIG. 10B is completed, the conductive pads 124A’, 124B’, 124C’ of the wafer W1’ will be able to contact the conductive pads 224A’, 224B’, 224C’ of the wafer W2’ after the bonding process. Therefore, the compensated wafers W1’ and W2’ improve the overlay error of the wafers W1 and W2 as discussed in FIG. 10A.

Please refer to Figure 10C, based on the bonding result of wafer W1 and wafer W2 in Figure 10A, a compensation method is performed to generate new wafers W1' and W2'. Unlike Figure 10B, Figure 10C only performs the compensation method on wafer W2', and does not compensate wafer W1'. In other words, the process conditions of wafer W1' may be substantially the same as the process conditions of wafer W1. In detail, the positions of the conductive pads 124A', 124B', and 124C' of wafer W1' are the same as the positions of the conductive pads 124A, 124B, and 124C of wafer W1. The compensation method for wafer W2' is similar to that discussed in FIG. 10B, and thus the relevant details will not be repeated.

After the compensation method of FIG. 10C is completed, the conductive pads 124A’, 124B’, 124C’ of the wafer W1’ will be able to contact the conductive pads 224A’, 224B’, 224C’ of the wafer W2’ after the bonding process. Therefore, the compensated wafers W1’ and W2’ improve the overlay error of the wafers W1 and W2 as discussed in FIG. 10A.

In some embodiments, since the compensation method is only performed on wafer W2', wafer W1' does not necessarily need to be a new wafer. As mentioned above, during the temporary bonding process discussed in FIG. 3A, wafers W1 and W2 are not tightly bonded, and a stripping process can be performed to separate wafer W1 and wafer W2 without damaging wafer W1 and wafer W2. Therefore, the compensated wafer W2' can be docked with the original wafer W1 to avoid directly discarding the original wafer W1.

Please refer to Figure 10D, a compensation method is performed based on the bonding result of wafer W1 and wafer W2 in Figure 10A, thereby generating new wafers W1' and W2'. Unlike Figure 10B, Figure 10D only performs the compensation method on wafer W1', and does not compensate wafer W2'. In other words, the process conditions of wafer W2' may be substantially the same as the process conditions of wafer W2. In detail, the positions of the conductive pads 224A', 224B', and 224C' of wafer W2' are the same as the positions of the conductive pads 224A, 224B, and 224C of wafer W2. The compensation method for wafer W1' is similar to that discussed in FIG. 10B, and thus the relevant details will not be repeated.

After the compensation method of FIG. 10D is completed, the conductive pads 124A’, 124B’, 124C’ of the wafer W1’ will be able to contact the conductive pads 224A’, 224B’, 224C’ of the wafer W2’ after the bonding process. Therefore, the compensated wafers W1’ and W2’ improve the overlay error of the wafers W1 and W2 as discussed in FIG. 10A.

In some embodiments, since the compensation method is only performed on wafer W1', wafer W2' does not necessarily need to be a new wafer. As mentioned above, during the temporary bonding process discussed in FIG. 3A, wafers W1 and W2 are not tightly bonded, and a stripping process can be performed to separate wafer W1 and wafer W2 without damaging wafer W1 and wafer W2. Therefore, the compensated wafer W1' can be docked with the original wafer W2 to avoid directly discarding the original wafer W2.

Referring to FIG. 10E , a compensation method is performed based on the bonding result of wafer W1 and wafer W2 of FIG. 10A , thereby generating new wafers W1 ′ and W2 ′. The compensation method of FIG. 10E is similar to the compensation method of FIG. 10B , in which compensation is performed on wafer W1 ′ and wafer W2 ′ at the same time. However, in the embodiment of FIG. 10B , offset S1_A, offset S1_C, offset S2_A, and offset S2_C are defined based on the ideal positions of conductive pads 124A, 124C, 224A, and 224C (as discussed in FIG. 7B ). Moving the conductive pads 124A’, 124C’, 224A’, and 224C’ of the compensated wafers W1’ and W2’ to the ideal position can make the conductive pad 124A’ substantially completely aligned with the conductive pad 224A’, and make the conductive pad 124C’ substantially completely aligned with the conductive pad 224C’. However, this may cause the conductive pads 124A’, 124C’, 224A’, 224C’ and their corresponding conductive through holes 134A’, 134C’, 234A’, 234C’ to be offset. If the above offset is too large, additional electrical connection problems may occur.

Therefore, in the compensation method of FIG. 10E, the conductive pad 124A' of wafer W1' is offset by S1_A' relative to the conductive pad 124A of wafer W1, wherein the offset S1_A' is less than the offset S1_A discussed in FIG. 10B. The conductive pad 124C' of wafer W1' is offset by S1_C' relative to the conductive pad 124C of wafer W1, wherein the offset S1_C' is less than the offset S1_C discussed in FIG. 10B. Similarly, the conductive pad 224A' of wafer W2' is offset by S2_A' relative to the conductive pad 224A of wafer W2, wherein the offset S2_A' is less than the offset S2_A discussed in FIG. 10B. The conductive pad 224C' of the wafer W2' is offset by S2_C' relative to the conductive pad 224C of the wafer W2, wherein the offset S2_C' is smaller than the offset S2_C discussed in FIG. 10B. The above method can ensure that the conductive pads 124A' and 224A' are partially in contact, and the conductive pads 124C' and 224C' are partially in contact. On the other hand, it can also ensure that the conductive pads 124A', 124C', 224A', 224C' and their corresponding conductive through holes 134A, 134C, 234A, 234C maintain reliable electrical connection.

Please refer to FIG. 10B and FIG. 10E at the same time. In some embodiments, after the compensated wafers W1' and W2' are formed using the method discussed in FIG. 10B, an overlay check can be performed on the compensated wafers W1' and W2' to confirm whether the components in the wafers W1' and W2' have reliable electrical connections. For example, it can be confirmed whether the conductive pads 124A', 124C', 224A', 224C' and their corresponding conductive through holes 134A, 134C, 234A, 234C are in contact. If the conductive pads 124A', 124C', 224A', 224C' and their corresponding conductive vias 134A, 134C, 234A, 234C are not in contact (or the contact area is less than a predetermined value), the method discussed in FIG. 10B must be adjusted. In some embodiments, the method discussed in FIG. 10E can be used instead of the method discussed in FIG. 10B. In some embodiments, the predetermined value of the contact area is 50% of the junction area of one of the conductive pads 124A' or the conductive vias 134A. In some embodiments, the predetermined value of the contact area is 30% of the junction area of one of the conductive pads 124A' or the conductive vias 134A. Here, "interface area" may represent the total area of the conductive pad 124A (or the conductive via 134A) used to connect to the conductive via 134A (or the conductive pad 124A). The predetermined value of the contact area between the conductive pad 124C' and the conductive via 134C, the predetermined value of the contact area between the conductive pad 224A' and the conductive via 234A, and the predetermined value of the contact area between the conductive pad 224C' and the conductive via 234C also have a relationship similar to the above, so they will not be repeated.

Figure 11 is a flow chart of the compensation method of some embodiments of the present disclosure. Figure 12 is a block diagram of the compensation method of some embodiments of the present disclosure. Although the method of Figure 11 is described by a series of operations or steps, it should be understood that this method does not limit the operations or their order. Therefore, in some embodiments, these operations or steps can be performed in different orders and/or simultaneously. In some embodiments, the described operations or steps can be omitted, or include other operations or steps that are not described. It should be understood that the first compensation method and the second compensation method described in Figure 11 only represent compensation methods at different stages, and there is no restriction on the order. Similarly, the first coverage inspection, the second coverage inspection and the third coverage inspection described in FIG. 11 merely represent coverage inspections at different stages and there is no restriction on the order.

The method M1 of FIG. 11 begins with step S101, where a semiconductor element is formed on a wafer. For example, referring to FIG. 1A and FIG. 1B , a semiconductor element 110 may be formed on a substrate 100 of a wafer W1, and a semiconductor element 210 may be formed on a substrate 200 of a wafer W2. In other embodiments, step S101 may also include forming an internal connection structure (e.g., the dielectric layer 132/232 and the conductive vias 134A-134C and 234A-234C described in FIG. 10A ) on the wafer.

The method proceeds to step S102, where a bonding layer is formed on the wafer. For example, referring to FIG. 1A and FIG. 1B , bonding layers 120 and 220 are formed on wafers W1 and W2, respectively. In some embodiments, the formation of bonding layers 120 and 220 can be performed by a lithography tool 310 (or a scanner) shown in FIG. 12 . For example, the positions of conductive pads 124 and 224 in bonding layers 120 and 220 are defined by lithography tool 310.

The method proceeds to step S103 to perform temporary bonding. For example, referring to FIGS. 2A to 3B, temporary bonding can be performed on wafers W1 and W2. In some embodiments, temporary bonding can be performed by a bonding device (bonder) 320 shown in FIG. 12. For example, the bonding device 320 can include a first wafer support table and a second wafer support table, which are used to fix wafer W1 and wafer W2, respectively. Then, the positions of wafer W1 and wafer W2 are recorded by measuring the alignment marks on wafer W1 and wafer W2. Then, according to the positions of wafer W1 and wafer W2, wafer W1 is aligned with wafer W2. Finally, the wafers W1 and W2 are squeezed against each other so that the wafers W1 and W2 are in contact with each other. During the temporary bonding period, the wafers W1 and W2 are not tightly bonded, so the wafers W1 and W2 can still be peeled off.

The method proceeds to step S104, performing a first covering inspection and confirming whether the result of the first covering inspection meets a predetermined standard. In some embodiments, the first covering inspection includes confirming whether the bonding layers 120 and 220 of the wafers W1 and W2 have achieved the expected electrical connection. For example, referring to FIGS. 7A and 7B, the first covering inspection may include confirming whether the conductive pads 124A, 124B, and 124C of the wafer W1 are in contact with the conductive pads 224A, 224B, and 224C of the wafer W2, respectively. If the conductive pads 124A, 124B, 124C of wafer W1 all contact (or the contact area exceeds a predetermined value) the corresponding conductive pads 224A, 224B, 224C of wafer W2, the first coverage inspection can be considered to meet the predetermined standard (IN SPEC). However, if at least one of the conductive pads 124A, 124B, 124C of wafer W1 does not contact (or the contact area is less than a predetermined value) the corresponding conductive pads 224A, 224B, 224C of wafer W2, the first coverage inspection can be considered to not meet the predetermined standard (OUT SPEC).

In FIG. 12 , the wafers W1 and W2 bonded in the bonding device 320 may be sent to the coverage inspection station 330 for a first coverage inspection. In some embodiments, the coverage inspection station 330 may include using a suitable method to confirm the bonding status of the wafers W1 and W2.

If the result of the first coverage inspection in step S104 meets the predetermined standard (for example, the condition of FIG. 7A), the method proceeds to step S105 to perform the first processing process. In some embodiments, the first processing process may be, for example, the first processing process P1 discussed in FIGS. 4A and 4B (for example, an annealing process). Then, after step S105, the method proceeds to step S106 to perform the second processing process. In some embodiments, the second processing process may include the second processing process P2 discussed in FIGS. 5A and 5B (for example, a grinding process), or the process discussed in FIGS. 6A and 6B, and the relevant details will not be repeated. In FIG. 12 , wafers W1 and W2 meeting predetermined standards may be sent to other process equipment 340 for a second processing step.

Returning to step S104, if the result of the first coverage inspection of step S104 does not meet the predetermined standard (e.g., the situation of FIG. 7B), the method proceeds to step S107 to execute the first compensation method. If the result of the first coverage inspection does not meet the predetermined standard, it means that a coverage error occurs. For example, at least one of the conductive pads 124A, 124B, 124C of wafer W1 does not contact (or the contact area is less than a predetermined value) the corresponding conductive pads 224A, 224B, 224C of wafer W2.

Since wafers W1 and W2 are still in a state of temporary bonding, the first compensation method includes separating wafers W1 and W2 from each other by bonding device 320 of FIG. 12. Next, the first compensation method may include the compensation method discussed in FIGS. 8A to 8C, and the relevant details will not be repeated. In some embodiments, the first compensation method is performed by bonding device 320, which includes separating wafers W1 and W2, adjusting the relative positions of wafers W1 and W2, and rebonding wafers W1 and W2.

The method proceeds to step S108, performs a second coverage inspection, and confirms whether the result of the second coverage inspection meets a predetermined standard. In detail, after the first compensation method, the second coverage inspection is performed. In some embodiments, the second coverage inspection includes confirming whether the bonding layers 120 and 220 of the compensated wafers W1 and W2 have achieved the expected electrical connection. The details of the second coverage inspection are substantially similar to the first coverage inspection, so the relevant details will not be repeated. In some embodiments, the second coverage inspection can be performed by the coverage inspection station 330 of Figure 12.

If the result of the second coverage inspection in step S108 meets the predetermined standard, the method proceeds to step S105 to perform the first processing step. Then, after step S105, the method proceeds to step S106 to perform the second processing step.

If the result of the second coverage inspection in step S108 does not meet the predetermined standard, the method proceeds to step S109 to execute the second compensation method. In some embodiments, the second compensation method may include, for example, the compensation method discussed in FIGS. 10B to 10E, and the relevant details will not be repeated. In some embodiments, the second compensation method includes designing the compensated wafers W1' and W2' so that the compensated wafers W1' and W2' have better bonding results. For example, the second compensation method may include adjusting the positions of the conductive pads 124A to 124C and the conductive pads 224A to 224C discussed in FIG. 10A to the positions of the conductive pads 124A' to 124C' and the conductive pads 224A' to 224C' in FIGS. 10B to 10E.

The method proceeds to step S110, and a wafer is manufactured based on the second compensation method. In some embodiments, the compensated wafers W1' and/or W2' can be re-produced by the compensation method as discussed in Figures 10B to 10E. In some embodiments, the positions of the conductive pads 124A' to 124C' and the conductive pads 224A' to 224C' of Figures 10B to 10E can be defined on the compensated wafers W1' and W2', respectively, by the lithography tool 310 of Figure 12.

The method proceeds to step S111, performs a third coverage inspection, and confirms whether the result of the third coverage inspection meets a predetermined standard. In some embodiments, the third coverage inspection is different from the aforementioned first coverage inspection and second coverage inspection. For example, the first coverage inspection and the second coverage inspection include inspecting the bonding condition between wafers W1 and W2 (or wafers W1' and W2'). The third coverage inspection includes inspecting whether the conductive pads 124A' to 124C' in wafer W1' and the corresponding conductive through holes 134A to 134C are in contact, and inspecting whether the conductive pads 224A' to 224C' in wafer W2' and the corresponding conductive through holes 234A to 234C are in contact. If the conductive pads 124A', 124B', 124C' of the wafer W1' all contact (or the contact area exceeds a predetermined value) the corresponding conductive vias 134A, 134B, 134C, the third coverage inspection can be considered to meet the predetermined standard (IN SPEC). However, if at least one of the conductive pads 124A' , 124B' , 124C' of the wafer W1' does not contact (or the contact area is less than a predetermined value) the corresponding conductive vias 134A, 134B, 134C, the third coverage inspection can be considered to not meet the predetermined standard (OUT SPEC). Performing the third coverage inspection on the wafer W2' is similar to performing the third coverage inspection on the wafer W1', so the relevant details will not be repeated. In some embodiments, the third coverage inspection can be performed by the coverage inspection station 330 of FIG. 12.

If the result of the third coverage inspection in step S111 meets the predetermined standard, the method proceeds to step S103. Here, the compensated wafers W1' and W2' can be temporarily bonded. Then, step S104 (and subsequent steps) can be continued to complete the bonding of wafers W1' and W2'.

If the result of the third coverage inspection of step S111 does not meet the predetermined standard, the method proceeds to step S108. In some embodiments, if the result of the third coverage inspection does not meet the predetermined standard, the second compensation method is re-executed, and the result of the re-executed second compensation method will be different from the result of the second compensation method executed last time. For example, wafers W1’ and W2’ can be formed first by the compensation method of Figure 10B. If the result of the coverage inspection of Figure 10B does not meet the predetermined standard, the compensation method of Figure 10B can be adjusted to the compensation method of Figure 10E to form wafers W1’ and W2’.

Referring to FIG. 12 , the result of the overlay inspection station 330 may be transmitted to an advanced process control (APC) system 350. In addition, FIG. 12 also includes a patterned wafer geometry (PWG) measurement station 360 and a patterned wafer geometry measurement station 370. In some embodiments, the patterned wafer geometry measurement stations 360 and 370 may include a wafer shape monitor for measuring the shape of the wafer, such as the warp of the wafer.

In some embodiments, the patterned wafer geometry measurement station 360 can be used to measure the shapes of wafers W1 and W2 (or wafers W1' and W2') before performing step S102. In detail, the shapes of wafers W1 and W2 (or wafers W1' and W2') are measured before forming the bonding layers 120 and 220. On the other hand, the patterned wafer geometry measurement station 370 can be used to measure the shapes of wafers W1 and W2 (or wafers W1' and W2') after performing step S102. In detail, the shapes of wafers W1 and W2 (or wafers W1' and W2') are measured after forming the bonding layers 120 and 220.

For example, each time method M1 is executed, shape data of multiple wafers W1 and W2 (or wafers W1' and W2') can be collected through the patterned wafer geometry measurement station 360, and shape data of multiple wafers W1 and W2 (or wafers W1' and W2') can be collected through the patterned wafer geometry measurement station 370. Then, the advanced process control system 350 can receive data from the patterned wafer geometry measurement stations 360, 370 and the overlay inspection station 330. The lithography tool 310 and the bonding device 320 can adjust the first compensation method and the second compensation method according to the data collected by the advanced process control system 350, so as to achieve better bonding quality.

FIG. 13 is a flow chart of the compensation method of some embodiments of the present disclosure. FIG. 14 is a schematic diagram of the compensation method of some embodiments of the present disclosure. FIG. 15 is a block diagram of the compensation method of some embodiments of the present disclosure. It should be understood that the first compensation method and the second compensation method described in FIG. 13 merely represent that the two are compensation methods at different stages, and there is no restriction on the order. Similarly, the first coverage inspection and the second coverage inspection described in FIG. 13 merely represent that the two are coverage inspections at different stages, and there is no restriction on the order.

Method M2 of Figure 13 includes step S201, forming a semiconductor element on a wafer. Method M2 includes step S202, forming a bonding layer on a wafer. Method M2 includes step S203, performing temporary bonding. Method M2 includes step S204, performing a first coverage inspection, and confirming whether the result of the first coverage inspection meets a predetermined standard. Method M2 includes step S205, performing a first processing step. Method M2 includes step S206, performing a second processing step. Method M2 includes step S207, performing a first compensation method. Method M2 includes step S208, performing a second coverage inspection, and confirming whether the result of the second coverage inspection meets a predetermined standard. Steps S201 to S208 are similar to steps S101 to S108 discussed in FIG. 11 , and thus the relevant details will not be repeated.

Method M2 of FIG. 13 is different from method M1 of FIG. 11 in that if the result of the first coverage inspection of step S208 does not meet the predetermined standard, the method proceeds to step S209 to calculate the first offset. Please refer to FIG. 14, which includes stages C1, C2 and C3, wherein stage C1 is a schematic diagram of wafer W1 after performing temporary bonding (step S203). In some embodiments, the calculation of the first offset is performed when wafer W1 is in stage C1. For example, in FIG. 14, the position I1' of the conductive pad 124A of wafer W1 and the ideal position I1 have a first offset SA1, and the position I3' of the conductive pad 124C of wafer W1 and the ideal position I3 have a first offset SC1.

In FIG. 15 , the wafers W1 and W2 bonded in the bonding device 320 may be sent to the overlay inspection station 330A for a first overlay inspection. In some embodiments, the overlay inspection station 330A may include using a suitable method to confirm the bonding status of the wafers W1 and W2, wherein the overlay inspection station 330A may be used to calculate the first offsets SA1 and SC1 in FIG. 14 .

Referring back to FIG. 13 , the method proceeds to step S210 to perform a first processing step. In some embodiments, the first processing step may be, for example, the first processing step P1 (eg, an annealing process) discussed in FIG. 4A and FIG. 4B .

Then, after step S210, the method proceeds to step S211 to calculate the second offset. Please refer to Figure 14, in which stage C2 is a schematic diagram of wafer W1 after executing the first processing step (step S210). In some embodiments, the calculation of the second offset is performed when wafer W1 is in stage C2. For example, in Figure 14, the position I1'' of the conductive pad 124A of wafer W1 in stage C2 and the position I1' of the conductive pad 124A of wafer W1 in stage C1 have a second offset SA2. The position I3'' of the conductive pad 124C of wafer W1 in stage C2 and the position I3' of the conductive pad 124C of wafer W1 in stage C1 have a second offset SC2.

In FIG. 15 , wafers W1 and W2 may be sent to an overlay inspection station 330B for overlay inspection. In some embodiments, the overlay inspection station 330B may include using a suitable method to confirm the bonding status of wafers W1 and W2, wherein the overlay inspection station 330B may be used to calculate the second offsets SA2 and SC2 in FIG. 14 .

Then, after step S211, the method proceeds to step S212 to perform a second processing step. In some embodiments, the second processing step may include the second processing step P2 (eg, a grinding process) discussed in FIG. 5A and FIG. 5B.

Then, after step S212, the method proceeds to step S213 to calculate the third offset. Please refer to FIG. 14, in which stage C3 is a schematic diagram of wafer W1 after executing the second processing step (step S212). In some embodiments, the calculation of the third offset is performed when wafer W1 is in stage C3. For example, in FIG. 14, the position I1''' of the conductive pad 124A of wafer W1 in stage C3 and the position I1'' of the conductive pad 124A of wafer W1 in stage C2 have a third offset SA3. The position I3''' of the conductive pad 124C of the wafer W1 in stage C3 and the position I3'' of the conductive pad 124C of the wafer W1 in stage C2 have a third offset SC3.

In FIG. 15 , wafers W1 and W2 may be sent to an overlay inspection station 330C for overlay inspection. In some embodiments, the overlay inspection station 330C may include using a suitable method to confirm the bonding status of wafers W1 and W2, wherein the overlay inspection station 330C may be used to calculate the third offsets SA3 and SC3 in FIG. 14 .

Referring back to FIG. 13 , the method proceeds to step S214 to perform a second compensation method. In some embodiments, the second compensation method includes designing the compensated wafers W1′ and W2′ so that the compensated wafers W1′ and W2′ have better bonding results. For example, the second compensation method may include adjusting the positions of the conductive pads 124A to 124C and the conductive pads 224A to 224C discussed in FIG. 10A .

In more detail, referring to FIG. 14 , the second compensation method is performed based on the first offset, the second offset, and the third offset of steps S209, S211, and S213. For example, the position of the conductive pad 124A′ of the compensated wafer W1′ is determined by the first offset SA1, the second offset SA2, and the third offset SA3. In some embodiments, the conductive pad 124A′ of the wafer W1′ can be formed by offsetting the conductive pad 124A based on the wafer W1 of stage C3, wherein the offset amount can be the sum of the first offset SA1, the second offset SA2, and the third offset SA3 (i.e., SA1+SA2+SA3). In other words, the difference between the position of the conductive pad 124A of the wafer W1 in stage C3 and the position of the conductive pad 124A' of the wafer W1' is substantially equal to SA1+SA2+SA3.

Similarly, the position of the conductive pad 124C' of the compensated wafer W1' is determined by the first offset SC1, the second offset SC2, and the third offset SC3. In some embodiments, the conductive pad 124C' of the wafer W1' can be formed by offsetting the conductive pad 124C based on the wafer W1 of stage C3, wherein the offset amount can be the sum of the first offset SC1, the second offset SC2, and the third offset SC3 (i.e., SC1+SC2+SC3). In other words, the difference between the position of the conductive pad 124C of the wafer W1 of stage C3 and the position of the conductive pad 124C' of the wafer W1' is substantially equal to SC1+SC2+SC3.

In some embodiments of the present disclosure, due to the execution of the first processing process (such as an annealing process) or the second processing process (such as a polishing process), the wafer W1 or W2 may also be warped, resulting in further changes in the position of the conductive pad. Therefore, in the compensation method, taking the offsets at different stages into consideration can make the compensated wafer have better bonding quality. It should be understood that the embodiment in Figure 14 takes wafer W1 as an example. However, in the present disclosure, the second compensation method discussed above can also be executed on wafer W2, and the relevant details will not be repeated. In some embodiments, steps S212 and S213 can be omitted. In other words, the third offset (i.e., the third offset SA3 and SC3) is not used in the second compensation method of step S214.

Referring back to FIG. 13 , the method proceeds to step S215 to manufacture wafers based on the second compensation method. In some embodiments, the compensated wafers W1 'and W2 'can be manufactured by the lithography tool 310 of FIG. 15 . In some embodiments, the compensated wafers W1 'and W2 'can be manufactured based on the first offset, the second offset, and the third offset discussed above.

As discussed in FIG. 9, in the first exposure step of forming the conductive pad 124A', the exposure area A1 may be exposed with an offset of SA1+SA2+SA3 to define the position of the conductive pad 124A'. And in the third exposure step of forming the conductive pad 124C', the exposure area A3 may be exposed with an offset of SC1+SC2+SC3 to define the position of the conductive pad 124C'. In an embodiment where steps S212 and S213 are omitted, in the first exposure step of forming the conductive pad 124A', the exposure area A1 may be exposed with an offset of SA1+SA2 to define the position of the conductive pad 124A'. In the third exposure step of forming the conductive pad 124C', the exposure area A3 may be exposed with an offset of SC1+SC2 to define the position of the conductive pad 124C'.

After step S215, step S203 is performed. Here, the compensated wafers W1' and W2' can be temporarily bonded. Then, step S204 (and subsequent steps) can be continued to complete the bonding of wafers W1' and W2'.

15 , the results of the coverage inspection stations 330A, 330B, and 330C may be transmitted to an advanced process control system 350. In addition, FIG. 15 also includes a patterned wafer geometry measurement station 360 and a patterned wafer geometry measurement station 370.

In some embodiments, the patterned wafer geometry measurement station 360 can be used to measure the measurements of wafers W1 and W2 (or wafers W1' and W2') before performing step S202. In detail, the shapes of wafers W1 and W2 (or wafers W1' and W2') are measured before forming the bonding layers 120 and 220. On the other hand, the patterned wafer geometry measurement station 370 can be used to measure the measurements of wafers W1 and W2 (or wafers W1' and W2') after performing step S202. In detail, the shapes of wafers W1 and W2 (or wafers W1' and W2') are measured after forming the bonding layers 120 and 220.

For example, each time method M2 is executed, shape data of multiple wafers W1 and W2 (or wafers W1’ and W2’) can be collected through the patterned wafer geometry measurement station 360. In some embodiments, the lithography tool 310 can preliminarily adjust the position of the conductive pads on wafers W1 and W2 based on the data collected by the patterned wafer geometry measurement station 360. On the other hand, each time method M2 is executed, shape data of multiple wafers W1 and W2 (or wafers W1’ and W2’) can be collected through the patterned wafer geometry measurement station 370. Then, the advanced process control system 350 can receive data from the patterned wafer geometry measurement station 370 and the overlay inspection stations 330A, 330B, and 330C. The lithography tool 310 and the bonding device 320 can adjust the first compensation method and the second compensation method according to the data collected by the advanced process control system 350, so as to achieve better bonding quality.

The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processing procedures and structures to implement the same purposes and/or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

100, 200                 : Substrate 110, 210                 : Semiconductor device 120, 220                 : Bonding layer 122, 222                 : Dielectric layer 124, 124A, 124B, 124C, 124A’, 124B’, 124C’, 224, 224A, 224B, 224C, 224A’, 224B’, 224C’: Conductive pad 132, 232                 : Dielectric layer 134A, 134B, 134C, 234A, 234B, 234C   : Conductive via 230                        : Conductive features 310                            : Lithography tools 320                        : Bonding equipment 330, 330A, 330B, 330C : Coverage inspection station 340                            : Other process equipment 350                           : Advanced process control system 360, 370                 : Patterned wafer geometry measurement station 500                        : Lithography tools A, A1, A2, A3          : Exposure area C1, C2, C3               : Phase I1, I2, I3                : Ideal position I1’, I1’’, I1’’’, I3’, I3’’, I3’’’: Position M1, M2                  : Method P1                        : First Process P2                        : Second Process S1_A, S1_C, S2_A, S2_C: Offset SA1, SC1                : First Offset SA2, SC2                : Second Offset SA3, SC3                : Third Offset S101~S111                : Step S201~S215                : Step W1, W2, W1’, W2’    : Wafer

The present disclosure is best understood from the following detailed description when read with the accompanying drawings. Note that various features are not drawn to scale, in accordance with standard practice in the industry. In fact, the sizes of various features may be arbitrarily increased or decreased for clarity of discussion. Figures 1A to 6B are schematic diagrams of a method of wafer bonding at different stages of some embodiments of the present disclosure. Figures 7A and 7B are schematic diagrams of bonding of wafer bonding of some embodiments of the present disclosure. Figures 8A to 8D are schematic diagrams of coverage errors of some embodiments of the present disclosure. Figure 9 is a schematic diagram of a lithography process of some embodiments of the present disclosure. Figure 10A is a schematic diagram of the results of bonding of some embodiments of the present disclosure. Figures 10B to 10E are schematic diagrams of compensation methods of some embodiments of the present disclosure. Figure 11 is a flow chart of compensation methods of some embodiments of the present disclosure. Figure 12 is a block diagram of compensation methods of some embodiments of the present disclosure. Figure 13 is a flow chart of compensation methods of some embodiments of the present disclosure. Figure 14 is a schematic diagram of compensation methods of some embodiments of the present disclosure. Figure 15 is a block diagram of compensation methods of some embodiments of the present disclosure.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

M1                        : Method S101~S111               : Steps

Claims (10)

A compensation method for wafer bonding, comprising: bonding a first wafer and a second wafer, wherein the first wafer has a first conductive pad and a second conductive pad, and the second wafer has a third conductive pad and a fourth conductive pad; performing a first covering inspection on the first wafer and the second wafer, the first covering inspection comprising confirming whether the first conductive pad of the first wafer contacts the third conductive pad of the second wafer, and confirming whether the second conductive pad of the first wafer contacts the fourth conductive pad of the second wafer; confirming whether the result of the first covering inspection meets a first predetermined standard; if the result of the first covering inspection does not meet the first predetermined standard, A predetermined standard is provided, and a second compensation method is performed to form a compensated first wafer and a compensated second wafer, the second compensation method comprising defining a position of a first conductive pad and a second conductive pad of the compensated first wafer, and defining a position of a third conductive pad and a fourth conductive pad on the compensated second wafer, wherein the position of the first conductive pad of the compensated first wafer is different from the position of the first conductive pad of the first wafer, and the position of the second conductive pad of the compensated first wafer is different from the position of the second conductive pad of the first wafer; and bonding the compensated first wafer and the compensated second wafer. The method as described in claim 1, wherein the result of the first covering inspection does not meet the first predetermined standard including that a contact area of the first conductive pad of the first wafer and the third conductive pad of the second wafer is less than a first predetermined value or a contact area of the second conductive pad of the first wafer and the fourth conductive pad of the second wafer is less than a second predetermined value. The method as described in claim 1 further comprises: before executing the second compensation method, executing a first compensation method, the first compensation method comprising: separating the first wafer and the second wafer; adjusting a relative position of the first wafer and the second wafer; and rejoining the first wafer and the second wafer; executing a second coverage inspection, the second coverage inspection comprising confirming that the first wafer whether the first conductive pad of the first wafer contacts the third conductive pad of the second wafer, and whether the second conductive pad of the first wafer contacts the fourth conductive pad of the second wafer; and confirming whether the result of the second covering inspection meets a second predetermined standard, wherein the second compensation method is performed in response to the result of the second covering inspection not meeting the second predetermined standard. The method as described in claim 3 further includes performing a third coverage inspection before bonding the compensated first wafer and the compensated second wafer, wherein the third coverage inspection includes confirming whether the first conductive pad of the compensated first wafer contacts a corresponding first conductive through hole, and confirming whether the second conductive pad of the compensated first wafer contacts a corresponding second conductive through hole. The method as described in claim 3, wherein the second compensation method is performed by a lithography tool and the first compensation method is performed by a bonding device. The method as described in claim 1, wherein the second compensation method is performed so that the position of the third conductive pad of the second wafer to be compensated is different from the position of the third conductive pad of the second wafer, and the position of the fourth conductive pad of the second wafer to be compensated is different from the position of the fourth conductive pad of the second wafer. A compensation method for wafer bonding includes: bonding a first wafer and a second wafer, wherein the first wafer has a first conductive pad and the second wafer has a second conductive pad; performing a first processing on the first wafer and the second wafer, wherein before performing the first processing, the first conductive pad has a first position, a first offset is between the first position and an ideal position, and after performing the first processing, the first conductive pad has a second position, a second offset is between the second position and the first position; performing a first processing on the second wafer; A second processing step is performed on the wafer, wherein after the second processing step is performed, the first conductive pad has a third position, and the third position and the second position have a third offset; a second compensation method is performed to form a compensated first wafer and a compensated second wafer, the second compensation method includes defining a position of a first conductive pad of the compensated first wafer, wherein the position of the first conductive pad of the compensated first wafer is determined by the first offset, the second offset, and the third offset; and the compensated first wafer and the compensated second wafer are bonded. The method as described in claim 7, wherein a difference between the position of the first conductive pad of the first wafer to be compensated and the third position of the first conductive pad of the first wafer is a sum of the first offset, the second offset and the third offset. The method as described in claim 7 further includes executing a first compensation method before executing the first processing step, the first compensation method including: separating the first wafer and the second wafer; adjusting a relative position of the first wafer and the second wafer; and rejoining the first wafer and the second wafer; executing a coverage inspection, the coverage inspection including confirming whether the first conductive pad of the first wafer contacts the second conductive pad of the first wafer; and confirming whether the result of the coverage inspection meets a predetermined standard. The method as described in claim 9, wherein the second compensation method is performed by a lithography tool and the first compensation method is performed by a bonding device.