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TWI858373B - Manufacturing method of semiconductor - Google Patents

Manufacturing method of semiconductor Download PDF

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TWI858373B
TWI858373B TW111130137A TW111130137A TWI858373B TW I858373 B TWI858373 B TW I858373B TW 111130137 A TW111130137 A TW 111130137A TW 111130137 A TW111130137 A TW 111130137A TW I858373 B TWI858373 B TW I858373B
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semiconductor substrate
protective film
semiconductor manufacturing
microns
semiconductor
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TW111130137A
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TW202407779A (en
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廖富江
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廖富江
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Abstract

A manufacturing method of a semiconductor includes steps of (a) providing a semiconductor substrate having a front side and a back side, (b) adhering a back protection film on the back side, (c) cutting the semiconductor substrate to a set depth along a plurality of cutting paths from the front side to form a plurality of scribing lines and separate a plurality of dies by the scribing lines, (d) adhering a front protection film on the front side, (e) removing the back protection film, (f) grinding the semiconductor substrate from the back side until a rest thickness of the semiconductor substrate equals to the set depth to expose the plurality of dies and the plurality of scribing lines, and (g) performing an evaporation to the semiconductor substrate to attach a plurality of metal particles to the plurality of dies. As a result, the efficiency of heat-dissipation is effectively enhanced because of the distribution of the metal particles.

Description

半導體製造方法Semiconductor manufacturing method

本發明係關於一種製造方法,特別是關於一種能有效促進散熱效果的半導體製造方法。The present invention relates to a manufacturing method, and in particular to a semiconductor manufacturing method which can effectively promote heat dissipation effect.

在傳統的半導體製程中,對於功率晶片的散熱,通常是以在晶背鍍覆金屬的方式來達成。In traditional semiconductor manufacturing processes, heat dissipation of power chips is usually achieved by coating metal on the back of the chip.

具體而言,其常用的製程主要是先在晶圓的正面貼膜,並對晶背研磨減薄,並在去除應力、清洗、去氧化層及乾燥等製程後,使用蒸鍍機以蒸鍍的方式在晶圓背面鍍上金屬,接著在晶圓背面貼膜並在晶圓正面撕膜,然後進行切割並以金屬支架封裝,最終製成晶片。主要的散熱途徑,是透過晶片底部所鍍覆的金屬促使連接金屬支架散熱。Specifically, the commonly used process is to first apply a film on the front side of the wafer, grind and thin the back side of the wafer, and after processes such as stress removal, cleaning, deoxidation and drying, use an evaporator to plate metal on the back side of the wafer by evaporation, then apply a film on the back side of the wafer and remove the film on the front side of the wafer, then cut and package with a metal bracket to finally make a chip. The main heat dissipation path is to use the metal coated on the bottom of the chip to promote heat dissipation of the connected metal bracket.

然而,此種在對晶圓進行研磨之後才進行切割的製造方法,僅能適用於厚度較厚的產品,例如最終厚度約為250微米的功率晶片。若要應用此傳統製造方法在厚度較薄的產品,常會在生產過程中發生晶圓翹曲甚至破片的情況,使得製造不易且徒增許多額外成本。However, this manufacturing method of grinding the wafer before cutting is only applicable to thicker products, such as power chips with a final thickness of about 250 microns. If this traditional manufacturing method is applied to thinner products, the wafer will often warp or even break during the production process, making manufacturing difficult and adding a lot of extra costs.

故此,有必要提供一種半導體製造方法,以解決先前技術所存在的問題。Therefore, it is necessary to provide a semiconductor manufacturing method to solve the problems existing in the prior art.

本發明之動機在於提供一種半導體製造方法,旨在解決並改善前述先前技術之問題與缺點。The motivation of the present invention is to provide a semiconductor manufacturing method, aiming to solve and improve the problems and shortcomings of the above-mentioned prior art.

本發明之主要目的在於提供一種半導體製造方法,藉由先在半導體基板之背面貼附背面保護膜,並自正面切割至設定深度,後續才在半導體基板之正面貼附正面保護膜,以及自半導體基板之背面研磨半導體基板,可保護半導體基板之背面在切割時不會有斷裂破片的風險,同時也能避免半導體基板發生翹曲。進一步地,透過露出晶粒及切割道並進行蒸鍍,使得金屬粒子深入切割道附著在晶粒四周的分布,可達到有效增加散熱效果之功效。The main purpose of the present invention is to provide a semiconductor manufacturing method, by first attaching a back protective film to the back of a semiconductor substrate, cutting from the front to a set depth, and then attaching a front protective film to the front of the semiconductor substrate, and grinding the semiconductor substrate from the back of the semiconductor substrate, the back of the semiconductor substrate can be protected from the risk of breaking and fragmenting during cutting, and the semiconductor substrate can also be prevented from warping. Furthermore, by exposing the crystal grains and the cutting path and performing evaporation, the metal particles are distributed in the cutting path and attached to the surrounding of the crystal grains, which can effectively increase the heat dissipation effect.

為達上述之目的,本發明提供一種半導體製造方法,包括步驟:(a)提供具有一正面及一背面之一半導體基板;(b)貼附一背面保護膜於該背面;(c)自該正面沿複數個切割路徑切割該半導體基板至一設定深度,以形成複數個切割道,並使複數個晶粒受該複數個切割道相隔開;(d)貼附一正面保護膜於該正面;(e)移除該背面保護膜;(f)自該背面研磨該半導體基板,直到該半導體基板之一剩餘厚度等於該設定深度,以露出該複數個晶粒及該複數個切割道;以及(g)蒸鍍該半導體基板,使複數個金屬粒子附著在該複數個晶粒。To achieve the above-mentioned purpose, the present invention provides a semiconductor manufacturing method, including the steps of: (a) providing a semiconductor substrate having a front side and a back side; (b) attaching a back side protective film to the back side; (c) cutting the semiconductor substrate from the front side along a plurality of cutting paths to a set depth to form a plurality of cutting paths, and separating a plurality of grains by the plurality of cutting paths; (d) attaching a front side protective film to the front side; (e) removing the back side protective film; (f) grinding the semiconductor substrate from the back side until a remaining thickness of the semiconductor substrate is equal to the set depth to expose the plurality of grains and the plurality of cutting paths; and (g) evaporating the semiconductor substrate to attach a plurality of metal particles to the plurality of grains.

在本發明的一實施例中,每一個該晶粒包括相對設置的一第一表面及一第二表面以及與該第一表面及該第二表面垂直的一第三表面、一第四表面、一第五表面及一第六表面,且該複數個金屬粒子附著在該第二表面、該第三表面、該第四表面、該第五表面及該第六表面。In one embodiment of the present invention, each of the crystal grains includes a first surface and a second surface arranged opposite to each other, and a third surface, a fourth surface, a fifth surface and a sixth surface perpendicular to the first surface and the second surface, and the plurality of metal particles are attached to the second surface, the third surface, the fourth surface, the fifth surface and the sixth surface.

在本發明的一實施例中,該複數個金屬粒子為複數個鈦鎳銀粒子。In one embodiment of the present invention, the plurality of metal particles are a plurality of titanium nickel silver particles.

在本發明的一實施例中,該設定深度介於37.5微米至150微米。In one embodiment of the present invention, the set depth is between 37.5 microns and 150 microns.

在本發明的一實施例中,每一個該切割道的寬度為40微米,且每一個該金屬粒子的粒徑為1微米。In one embodiment of the present invention, the width of each of the scribe lines is 40 micrometers, and the particle size of each of the metal particles is 1 micrometer.

在本發明的一實施例中,該背面保護膜的厚度為90微米,且於該步驟(c)中,該半導體基板的厚度為300微米。In one embodiment of the present invention, the thickness of the back protective film is 90 microns, and in the step (c), the thickness of the semiconductor substrate is 300 microns.

在本發明的一實施例中,該設定深度為70微米,該步驟(c)以一晶圓切割機之一刀片實現,且該刀片之一刀片高度參數為320微米。In one embodiment of the present invention, the set depth is 70 microns, the step (c) is implemented with a blade of a wafer saw, and a blade height parameter of the blade is 320 microns.

在本發明的一實施例中,於該步驟(f)及該步驟(g)之間,更包括步驟:(f1)去除該半導體基板之殘留應力;(f2)清洗該半導體基板;(f3)去除該半導體基板之一氧化層;以及(f4)乾燥該半導體基板。In one embodiment of the present invention, between step (f) and step (g), the following steps are further included: (f1) removing residual stress of the semiconductor substrate; (f2) cleaning the semiconductor substrate; (f3) removing an oxide layer of the semiconductor substrate; and (f4) drying the semiconductor substrate.

在本發明的一實施例中,於該步驟(g)之後,更包括步驟:(h)貼附一第二背面保護膜於該背面;(i)移除該正面保護膜;以及(j)封裝該半導體基板。In one embodiment of the present invention, after step (g), the method further includes the steps of: (h) attaching a second back protective film to the back surface; (i) removing the front protective film; and (j) packaging the semiconductor substrate.

在本發明的一實施例中,於該步驟(j)中,該複數個晶粒被封裝形成複數個功率晶片。In one embodiment of the present invention, in the step (j), the plurality of dies are packaged to form a plurality of power chips.

為了讓本發明之上述及其他目的、特徵、優點能更明顯易懂,下文將特舉本發明較佳實施例,並配合所附圖式,作詳細說明如下。再者,本發明所提到的方向用語,例如上、下、頂、底、前、後、左、右、內、外、側面、周圍、中央、水平、橫向、垂直、縱向、軸向、徑向、最上層或最下層等,僅是參考附加圖式的方向。因此,使用的方向用語是用以說明及理解本發明,而非用以限制本發明。In order to make the above and other purposes, features, and advantages of the present invention more clearly understood, the preferred embodiments of the present invention are specifically cited below, and are described in detail with reference to the attached drawings. Furthermore, the directional terms mentioned in the present invention, such as up, down, top, bottom, front, back, left, right, inside, outside, side, periphery, center, horizontal, transverse, vertical, longitudinal, axial, radial, topmost or bottommost, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to explain and understand the present invention, but not to limit the present invention.

請參閱圖1至圖4,其中圖1顯示本案一實施例之一半導體製造方法之流程圖,圖2顯示本案一實施例之一半導體製造方法之半導體基板、背面保護膜以及切割半導體基板之示意圖,圖3顯示本案一實施例之一半導體製造方法中對貼附背面保護膜之半導體基板進行切割以及切割道與晶粒之立體圖,以及圖4顯示本案一實施例之一半導體製造方法之半導體基板、切割道、晶粒以及背面保護膜之示意圖。Please refer to Figures 1 to 4, wherein Figure 1 shows a flow chart of a semiconductor manufacturing method of an embodiment of the present invention, Figure 2 shows a semiconductor substrate, a back side protective film and a schematic diagram of cutting a semiconductor substrate of a semiconductor manufacturing method of an embodiment of the present invention, Figure 3 shows cutting of a semiconductor substrate with a back side protective film attached thereto in a semiconductor manufacturing method of an embodiment of the present invention and a stereoscopic diagram of cutting paths and grains, and Figure 4 shows a schematic diagram of a semiconductor substrate, cutting paths, grains and a back side protective film of a semiconductor manufacturing method of an embodiment of the present invention.

如圖1至圖4所示,根據本案之一實施例,半導體製造方法包括步驟如下:首先,如步驟S10所示,提供具有正面11及背面12之半導體基板1。其次,如步驟S20所示,貼附背面保護膜2於半導體基板1之背面12。然後,如步驟S30所示,自半導體基板1之正面11沿複數個切割路徑切割半導體基板11至設定深度d,以形成複數個切割道13,並使複數個晶粒14受複數個切割道13相隔開。As shown in FIGS. 1 to 4 , according to an embodiment of the present invention, a semiconductor manufacturing method includes the following steps: First, as shown in step S10, a semiconductor substrate 1 having a front surface 11 and a back surface 12 is provided. Next, as shown in step S20, a back surface protective film 2 is attached to the back surface 12 of the semiconductor substrate 1. Then, as shown in step S30, the semiconductor substrate 11 is cut along a plurality of cutting paths from the front surface 11 of the semiconductor substrate 1 to a set depth d to form a plurality of cutting paths 13, and a plurality of die 14 are separated by the plurality of cutting paths 13.

接著,請參閱圖1、圖5及圖6,其中圖5顯示本案一實施例之半導體製造方法之正面保護膜、半導體基板以及自背面研磨半導體基板之示意圖,以及圖6顯示本案一實施例之一半導體製造方法之正面保護膜、半導體基板之剩餘厚度等於設定深度以及自背面對半導體基板進行蒸鍍之示意圖。Next, please refer to Figures 1, 5 and 6, wherein Figure 5 shows a schematic diagram of a front protective film, a semiconductor substrate and grinding a semiconductor substrate from the back side of a semiconductor manufacturing method of an embodiment of the present case, and Figure 6 shows a schematic diagram of a front protective film, a semiconductor substrate having a remaining thickness equal to a set depth and evaporating the semiconductor substrate from the back side of a semiconductor manufacturing method of an embodiment of the present case.

如圖1、圖5及圖6所示,本案之半導體製造方法於步驟S40中,貼附正面保護膜3於半導體基板1之正面11。然後,如步驟S50所示,移除背面保護膜2。接著,於步驟S60中,自半導體基板1之背面12研磨半導體基板1,直到半導體基板1之剩餘厚度t等於設定深度d,以露出複數個晶粒14及複數個切割道13。然後,如步驟S70所示,蒸鍍半導體基板1,使複數個金屬粒子附著在複數個晶粒14。As shown in FIG. 1 , FIG. 5 and FIG. 6 , in the semiconductor manufacturing method of the present case, in step S40, a front protective film 3 is attached to the front surface 11 of the semiconductor substrate 1. Then, as shown in step S50, the back protective film 2 is removed. Then, in step S60, the semiconductor substrate 1 is polished from the back surface 12 of the semiconductor substrate 1 until the remaining thickness t of the semiconductor substrate 1 is equal to the set depth d, so as to expose a plurality of crystal grains 14 and a plurality of sawing streets 13. Then, as shown in step S70, the semiconductor substrate 1 is evaporated so that a plurality of metal particles are attached to the plurality of crystal grains 14.

請再參閱圖1至圖6。相較於先前技術,本案之半導體製造方法藉由先在半導體基板1之背面12貼附背面保護膜2,並自正面11切割至設定深度d,後續才在半導體基板1之正面11貼附正面保護膜3,以及自背面12研磨半導體基板1,可保護半導體基板1之背面12在切割時不會有斷裂破片的風險,同時也能避免半導體基板1發生翹曲。進一步地,透過露出晶粒14及切割道13並進行蒸鍍,使得金屬粒子深入切割道13附著在晶粒14四周的分布,可達到有效增加散熱效果之功效。Please refer to Figures 1 to 6 again. Compared with the prior art, the semiconductor manufacturing method of the present invention can protect the back side 12 of the semiconductor substrate 1 from the risk of breaking and fragmenting during cutting by first attaching a back side protective film 2 to the back side 12 of the semiconductor substrate 1 and cutting from the front side 11 to a set depth d, and then attaching a front side protective film 3 to the front side 11 of the semiconductor substrate 1 and grinding the semiconductor substrate 1 from the back side 12. At the same time, it can also prevent the semiconductor substrate 1 from warping. Furthermore, by exposing the crystal grain 14 and the cutting path 13 and performing evaporation, the metal particles are distributed in the cutting path 13 and attached to the surrounding of the crystal grain 14, which can effectively increase the heat dissipation effect.

更具體地,請參閱圖7及圖8,其中圖7顯示以本案一實施例之一半導體製造方法進行蒸鍍後之一晶粒及其金屬粒子分布之立體圖,以及圖8顯示倒置的圖7所示之晶粒及其金屬粒子分布之立體圖。如圖7及圖8所示,以本案之半導體製造方法進行蒸鍍後之每一晶粒14包括相對設置的第一表面141及第二表面142,以及與第一表面141及第二表面142垂直的第三表面143、第四表面144、第五表面145及第六表面146,且複數個金屬粒子(於圖7及圖8中以斜線網底表示)附著在第二表面142、第三表面143、第四表面144、第五表面145及第六表面146。其中,複數個金屬粒子可為複數個鈦鎳銀粒子,但不以此為限。More specifically, please refer to FIG. 7 and FIG. 8, wherein FIG. 7 shows a three-dimensional diagram of a crystal grain and its metal particle distribution after evaporation by a semiconductor manufacturing method of an embodiment of the present invention, and FIG. 8 shows an inverted three-dimensional diagram of the crystal grain and its metal particle distribution shown in FIG. 7 and FIG. 8 show that each crystal grain 14 after evaporation by the semiconductor manufacturing method of the present invention includes a first surface 141 and a second surface 142 disposed opposite to each other, and a third surface 143, a fourth surface 144, a fifth surface 145 and a sixth surface 146 perpendicular to the first surface 141 and the second surface 142, and a plurality of metal particles (indicated by a diagonal line bottom in FIG. 7 and FIG. 8) are attached to the second surface 142, the third surface 143, the fourth surface 144, the fifth surface 145 and the sixth surface 146. The plurality of metal particles may be a plurality of titanium nickel silver particles, but is not limited thereto.

也就是說,由於本案之半導體製造方法在步驟S30中先切割半導體基板11至設定深度d,再於步驟S60中自背面將半導體基板研磨至剩餘厚度t等於設定深度d,即自背面研磨半導體基板直到已切割部分遭到磨穿,露出所有的切割道13以及晶粒14。在後續蒸鍍時,由於切割道13對於蒸鍍的金屬粒子而言是開放的,因此金屬粒子除了會附著於晶粒14的第二表面142(即靠近半導體基板1的背面12的一側),還會附著於晶粒14的第三表面143、第四表面144、第五表面145及第六表面146。由於晶粒14的第一表面141貼附有正面保護膜3,故金屬粒子不會附著在晶粒14的第一表面141。That is, in the semiconductor manufacturing method of the present case, the semiconductor substrate 11 is first cut to a set depth d in step S30, and then the semiconductor substrate is ground from the back side until the remaining thickness t is equal to the set depth d in step S60, that is, the semiconductor substrate is ground from the back side until the cut portion is worn through, exposing all the cutting paths 13 and the die 14. During the subsequent evaporation, since the cutting paths 13 are open to the evaporated metal particles, the metal particles will not only adhere to the second surface 142 of the die 14 (i.e., the side close to the back side 12 of the semiconductor substrate 1), but also to the third surface 143, the fourth surface 144, the fifth surface 145 and the sixth surface 146 of the die 14. Since the front protection film 3 is attached to the first surface 141 of the die 14, the metal particles will not adhere to the first surface 141 of the die 14.

相對於先前技術僅於半導體基板之背面或晶粒之背面鍍覆金屬粒子,本案之半導體製造方法是以蒸鍍實現金屬粒子附著於晶粒的底面及四個側面,相較於先前技術大大地增加了金屬粒子分布的表面積,因此對於散熱效果有顯著的提升。Compared to the prior art that only coats the back of the semiconductor substrate or the back of the crystal grain with metal particles, the semiconductor manufacturing method of this case uses evaporation to attach metal particles to the bottom and four sides of the crystal grain, which greatly increases the surface area of the metal particle distribution compared to the prior art, thereby significantly improving the heat dissipation effect.

請參閱圖9至圖11,其中圖9顯示本案一實施例之一半導體製造方法之正面保護膜、半導體基板以及第二背面保護膜之示意圖,圖10顯示本案一實施例之一半導體製造方法之半導體基板及第二背面保護膜之示意圖,以及圖11顯示本案一實施例之一半導體製造方法之一細部流程圖。如圖9至圖11所示,根據本案一實施例之一半導體製造方法,在步驟S70後,進一步包括步驟如下:首先,如步驟S80所示,貼附第二背面保護膜4於背面12。接著,如步驟S90所示,移除正面保護膜3。然後,如步驟S100所示,封裝半導體基板1。在一些實施例中,於此步驟S100中,複數個晶粒14可被封裝形成複數個功率晶片,但不以此為限。Please refer to Figures 9 to 11, wherein Figure 9 shows a schematic diagram of a front protective film, a semiconductor substrate, and a second back protective film of a semiconductor manufacturing method of an embodiment of the present invention, Figure 10 shows a schematic diagram of a semiconductor substrate and a second back protective film of a semiconductor manufacturing method of an embodiment of the present invention, and Figure 11 shows a detailed flow chart of a semiconductor manufacturing method of an embodiment of the present invention. As shown in Figures 9 to 11, according to a semiconductor manufacturing method of an embodiment of the present invention, after step S70, the following steps are further included: First, as shown in step S80, the second back protective film 4 is attached to the back surface 12. Then, as shown in step S90, the front protective film 3 is removed. Then, as shown in step S100, the semiconductor substrate 1 is packaged. In some embodiments, in step S100 , a plurality of dies 14 may be packaged to form a plurality of power chips, but the present invention is not limited thereto.

此外,在本案之半導體製造方法的步驟S60及步驟S70之間,可進一步包括步驟S62、步驟S64、步驟S66及步驟S68。在步驟S60完成後,以步驟S62去除半導體基板1之殘留應力,例如採用混酸溶液實現。接著,以步驟S64清洗半導體基板1,例如使用去離子水實現。然後,以步驟S66去除半導體基板1之氧化層,例如以氫氟酸實現。接著,如步驟S68所示,乾燥半導體基板1,以使半導體基板1適於進行後續之蒸鍍製程,即步驟S70。In addition, between step S60 and step S70 of the semiconductor manufacturing method of the present case, step S62, step S64, step S66 and step S68 may be further included. After step S60 is completed, the residual stress of the semiconductor substrate 1 is removed in step S62, for example, by using a mixed acid solution. Then, the semiconductor substrate 1 is cleaned in step S64, for example, by using deionized water. Then, the oxide layer of the semiconductor substrate 1 is removed in step S66, for example, by using hydrofluoric acid. Then, as shown in step S68, the semiconductor substrate 1 is dried to make the semiconductor substrate 1 suitable for the subsequent evaporation process, i.e., step S70.

請再參閱圖1及圖11。在一些實施例中,本案之半導體製造方法的步驟S20、步驟S40及步驟S80較佳是以一貼膜機實現,步驟S30較佳是以一晶圓切割機之一刀片實現,步驟S50及步驟S90較佳是以一撕膜機實現,步驟S60較佳是以一研磨機實現,步驟S70較佳是以一蒸鍍機實現,且步驟S100較佳是以一封裝測試機台實現,但均不以此為限。Please refer to Figure 1 and Figure 11. In some embodiments, the steps S20, S40 and S80 of the semiconductor manufacturing method of the present invention are preferably implemented by a film laminating machine, the step S30 is preferably implemented by a blade of a wafer cutting machine, the step S50 and S90 are preferably implemented by a film peeling machine, the step S60 is preferably implemented by a grinder, the step S70 is preferably implemented by a vapor deposition machine, and the step S100 is preferably implemented by a packaging test machine, but it is not limited thereto.

請再參閱圖2至圖6。根據多個具體實施例,本案之半導體製造方法採用的設定深度d及剩餘厚度t可介於37.5微米(µm)至150微米之間,即1.5mil至6mil之間,較佳為介於50微米至100微米之間,即2mil至4mil之間,且具體可為50微米、60微米、70微米或80微米等。應特別注意的是,設定深度d及剩餘厚度t的實際數值,可依照產品的實際需求進行設定,並不受限於此處所舉之示例。Please refer to Figures 2 to 6 again. According to a number of specific embodiments, the set depth d and the remaining thickness t used in the semiconductor manufacturing method of the present case can be between 37.5 micrometers (µm) and 150 micrometers, that is, between 1.5 mil and 6 mil, preferably between 50 micrometers and 100 micrometers, that is, between 2 mil and 4 mil, and can be specifically 50 micrometers, 60 micrometers, 70 micrometers or 80 micrometers, etc. It should be particularly noted that the actual values of the set depth d and the remaining thickness t can be set according to the actual needs of the product and are not limited to the examples cited here.

在圖2至圖10所示的實施例中,是以設定深度d及剩餘厚度t等於70微米,且每一個切割道13的寬度大約為40微米,以及每一個金屬粒子的粒徑大約為1微米為例。其中,當半導體基板1已完成前段製程且厚度為300微米,且選用的背面保護膜2的厚度為90微米時,即半導體基板1及背面保護膜2的總厚度為390微米,本案之半導體製造方法選用的晶圓切割機之刀片的刀片高度參數設定為320微米,即可實現設定深度d(即欲切割深度)等於70微米。在研磨至半導體基板1之剩餘厚度t等於70微米時,即露出複數個切割道13及複數個晶粒14。由於切割道13的寬度為約40微米,粒徑僅有約1微米的金屬粒子易於深入切割道13並均勻地附著於晶粒14的四個側面,因此每一個晶粒14的底面及四個側面皆分布有均勻的金屬粒子,有助於散熱。In the embodiments shown in FIGS. 2 to 10 , the depth d and the remaining thickness t are set to 70 microns, the width of each cutting path 13 is about 40 microns, and the particle size of each metal particle is about 1 micron. When the semiconductor substrate 1 has completed the front-end process and has a thickness of 300 microns, and the thickness of the selected back protective film 2 is 90 microns, that is, the total thickness of the semiconductor substrate 1 and the back protective film 2 is 390 microns, the blade height parameter of the blade of the wafer cutting machine selected in the semiconductor manufacturing method of this case is set to 320 microns, and the depth d (i.e., the desired cutting depth) can be set to 70 microns. When the remaining thickness t of the semiconductor substrate 1 is polished to 70 microns, a plurality of cutting paths 13 and a plurality of crystal grains 14 are exposed. Since the width of the cutting street 13 is about 40 microns, metal particles with a particle size of only about 1 micron can easily penetrate into the cutting street 13 and evenly adhere to the four sides of the die 14. Therefore, the bottom surface and four sides of each die 14 are evenly distributed with metal particles, which is helpful for heat dissipation.

請參閱圖12至圖14並配合圖1,其中圖12顯示本案另一實施例之一半導體製造方法之半導體基板、背面保護膜以及切割半導體基板之示意圖,圖13顯示本案另一實施例之一半導體製造方法中對貼附背面保護膜之半導體基板進行切割以及切割道與晶粒之立體圖,以及圖14顯示本案另一實施例之一半導體製造方法之半導體基板、切割道、晶粒以及背面保護膜之示意圖。Please refer to Figures 12 to 14 in conjunction with Figure 1, wherein Figure 12 shows a schematic diagram of a semiconductor substrate, a back side protective film and cutting of a semiconductor substrate in a semiconductor manufacturing method in another embodiment of the present invention, Figure 13 shows a semiconductor substrate with a back side protective film attached thereto in a semiconductor manufacturing method in another embodiment of the present invention and a three-dimensional diagram of the cutting paths and grains, and Figure 14 shows a schematic diagram of a semiconductor substrate, a cutting path, a grain and a back side protective film in a semiconductor manufacturing method in another embodiment of the present invention.

如圖1及圖12至圖14所示,根據本案之另一實施例,半導體製造方法包括步驟如下:首先,如步驟S10所示,提供具有正面51及背面52之半導體基板5。其次,如步驟S20所示,貼附背面保護膜6於半導體基板5之背面52。然後,如步驟S30所示,自半導體基板5之正面51沿複數個切割路徑切割半導體基板51至設定深度d2,以形成複數個切割道53,並使複數個晶粒54受複數個切割道53相隔開。As shown in FIG. 1 and FIG. 12 to FIG. 14 , according to another embodiment of the present invention, the semiconductor manufacturing method includes the following steps: First, as shown in step S10, a semiconductor substrate 5 having a front surface 51 and a back surface 52 is provided. Next, as shown in step S20, a back surface protective film 6 is attached to the back surface 52 of the semiconductor substrate 5. Then, as shown in step S30, the semiconductor substrate 51 is cut along a plurality of cutting paths from the front surface 51 of the semiconductor substrate 5 to a set depth d2 to form a plurality of cutting paths 53, and a plurality of crystal grains 54 are separated by the plurality of cutting paths 53.

接著,請參閱圖1、圖15及圖16,其中圖15顯示本案另一實施例之半導體製造方法之正面保護膜、半導體基板以及自背面研磨半導體基板之示意圖,以及圖16顯示本案另一實施例之一半導體製造方法之正面保護膜、半導體基板之剩餘厚度等於設定深度以及自背面對半導體基板進行蒸鍍之示意圖。在步驟S40中,本案之半導體製造方法貼附正面保護膜7於半導體基板5之正面51。然後,如步驟S50所示,移除背面保護膜6。接著,於步驟S60中,自半導體基板5之背面52研磨半導體基板5,直到半導體基板5之剩餘厚度t2等於設定深度d2,以露出複數個晶粒54及複數個切割道53。然後,如步驟S70所示,蒸鍍半導體基板5,使複數個金屬粒子附著在複數個晶粒15。Next, please refer to FIG. 1, FIG. 15 and FIG. 16, wherein FIG. 15 shows a schematic diagram of a front protective film, a semiconductor substrate and grinding a semiconductor substrate from the back of another embodiment of the semiconductor manufacturing method of the present case, and FIG. 16 shows a schematic diagram of a front protective film, a semiconductor substrate with a remaining thickness equal to a set depth and evaporation of a semiconductor substrate from the back of another embodiment of the semiconductor manufacturing method of the present case. In step S40, the semiconductor manufacturing method of the present case attaches the front protective film 7 to the front surface 51 of the semiconductor substrate 5. Then, as shown in step S50, the back protective film 6 is removed. Next, in step S60, the semiconductor substrate 5 is ground from the back side 52 of the semiconductor substrate 5 until the remaining thickness t2 of the semiconductor substrate 5 is equal to the set depth d2, so as to expose the plurality of crystal grains 54 and the plurality of saw streets 53. Then, as shown in step S70, the semiconductor substrate 5 is evaporated so that the plurality of metal particles are attached to the plurality of crystal grains 15.

請參閱圖17及圖18,其中圖17顯示以本案另一實施例之一半導體製造方法進行蒸鍍後之一晶粒及其金屬粒子分布之立體圖,以及圖18顯示倒置的圖17所示之晶粒及其金屬粒子分布之立體圖。如圖17及圖18所示,以本案之半導體製造方法進行蒸鍍後之每一晶粒54包括相對設置的第一表面541及第二表面542,以及與第一表面541及第二表面542垂直的第三表面543、第四表面544、第五表面545及第六表面546,且複數個金屬粒子(於圖17及圖18中以斜線網底表示)附著在第二表面542、第三表面543、第四表面544、第五表面545及第六表面546。其中,複數個金屬粒子可為複數個鈦鎳銀粒子,但不以此為限。Please refer to FIG. 17 and FIG. 18, wherein FIG. 17 shows a three-dimensional diagram of a crystal grain and its metal particle distribution after evaporation by a semiconductor manufacturing method according to another embodiment of the present invention, and FIG. 18 shows an inverted three-dimensional diagram of the crystal grain and its metal particle distribution shown in FIG. 17. As shown in FIG. 17 and FIG. 18, each crystal grain 54 after evaporation by the semiconductor manufacturing method of the present invention includes a first surface 541 and a second surface 542 arranged opposite to each other, and a third surface 543, a fourth surface 544, a fifth surface 545 and a sixth surface 546 perpendicular to the first surface 541 and the second surface 542, and a plurality of metal particles (indicated by a diagonal line bottom in FIG. 17 and FIG. 18) are attached to the second surface 542, the third surface 543, the fourth surface 544, the fifth surface 545 and the sixth surface 546. The plurality of metal particles may be a plurality of titanium nickel silver particles, but is not limited thereto.

也就是說,由於本案之半導體製造方法在步驟S30中先切割半導體基板11至設定深度d,再於步驟S60中自背面將半導體基板研磨至剩餘厚度t等於設定深度d,即自背面研磨半導體基板直到已切割部分遭到磨穿,露出所有的切割道13以及晶粒14。在後續蒸鍍時,由於切割道13對於蒸鍍的金屬粒子而言是開放的,因此金屬粒子除了會附著於晶粒14的第二表面142(即靠近半導體基板1的背面12的一側),還會附著於晶粒14的第三表面143、第四表面144、第五表面145及第六表面146。由於晶粒14的第一表面141貼附有正面保護膜3,故金屬粒子不會附著在晶粒14的第一表面141。That is, in the semiconductor manufacturing method of the present case, the semiconductor substrate 11 is first cut to a set depth d in step S30, and then the semiconductor substrate is ground from the back side until the remaining thickness t is equal to the set depth d in step S60, that is, the semiconductor substrate is ground from the back side until the cut portion is worn through, exposing all the cutting paths 13 and the die 14. During the subsequent evaporation, since the cutting paths 13 are open to the evaporated metal particles, the metal particles will not only adhere to the second surface 142 of the die 14 (i.e., the side close to the back side 12 of the semiconductor substrate 1), but also to the third surface 143, the fourth surface 144, the fifth surface 145 and the sixth surface 146 of the die 14. Since the front protection film 3 is attached to the first surface 141 of the die 14, the metal particles will not adhere to the first surface 141 of the die 14.

請參閱圖11、圖19及圖20,其中圖19顯示本案另一實施例之一半導體製造方法之正面保護膜、半導體基板以及第二背面保護膜之示意圖,以及圖20顯示本案另一實施例之一半導體製造方法之半導體基板及第二背面保護膜之示意圖。如圖11、圖19及圖20所示,本案之半導體製造方法在步驟S70後,進一步包括步驟如下:首先,如步驟S80所示,貼附第二背面保護膜8於背面52。接著,如步驟S90所示,移除正面保護膜7。然後,如步驟S100所示,封裝半導體基板5。在一些實施例中,於此步驟S100中,複數個晶粒54可被封裝形成複數個功率晶片,但不以此為限。Please refer to FIG. 11, FIG. 19 and FIG. 20, wherein FIG. 19 shows a schematic diagram of a front protective film, a semiconductor substrate and a second back protective film of a semiconductor manufacturing method of another embodiment of the present invention, and FIG. 20 shows a schematic diagram of a semiconductor substrate and a second back protective film of a semiconductor manufacturing method of another embodiment of the present invention. As shown in FIG. 11, FIG. 19 and FIG. 20, the semiconductor manufacturing method of the present invention further includes the following steps after step S70: First, as shown in step S80, a second back protective film 8 is attached to the back surface 52. Then, as shown in step S90, the front protective film 7 is removed. Then, as shown in step S100, the semiconductor substrate 5 is packaged. In some embodiments, in this step S100, a plurality of dies 54 can be packaged to form a plurality of power chips, but it is not limited thereto.

在圖12至圖20所示之實施例中,是以設定深度d2及剩餘厚度t2等於50微米,且每一個切割道13的寬度大約為40微米,以及每一個金屬粒子的粒徑大約為1微米為例。其中,當半導體基板5已完成前段製程且厚度為300微米,且選用的背面保護膜2的厚度為90微米時,即半導體基板5及背面保護膜6的總厚度為390微米,本案之半導體製造方法選用的晶圓切割機之刀片的刀片高度參數設定為340微米,即可實現設定深度d2(即欲切割深度)等於50微米。在研磨至半導體基板5之剩餘厚度t2等於50微米時,即露出複數個切割道53及複數個晶粒54。由於切割道53的寬度為約40微米,粒徑僅有約1微米的金屬粒子易於深入切割道53並均勻地附著於晶粒54的四個側面,因此每一個晶粒54的底面及四個側面皆分布有均勻的金屬粒子,有助於散熱。In the embodiments shown in FIG. 12 to FIG. 20, the depth d2 and the remaining thickness t2 are set to 50 microns, and the width of each cutting path 13 is about 40 microns, and the particle size of each metal particle is about 1 micron. Among them, when the semiconductor substrate 5 has completed the front-end process and the thickness is 300 microns, and the thickness of the selected back protective film 2 is 90 microns, that is, the total thickness of the semiconductor substrate 5 and the back protective film 6 is 390 microns, the blade height parameter of the blade of the wafer cutting machine selected in the semiconductor manufacturing method of this case is set to 340 microns, which can achieve the setting depth d2 (that is, the desired cutting depth) equal to 50 microns. When the remaining thickness t2 of the semiconductor substrate 5 is polished to 50 microns, a plurality of cutting paths 53 and a plurality of grains 54 are exposed. Since the width of the cutting street 53 is about 40 microns, metal particles with a particle size of only about 1 micron can easily penetrate into the cutting street 53 and evenly adhere to the four sides of the grain 54. Therefore, the bottom surface and four sides of each grain 54 are evenly distributed with metal particles, which helps to dissipate heat.

綜上所述,本發明提供一種半導體製造方法,藉由先在半導體基板之背面貼附背面保護膜,並自正面切割至設定深度,後續才在半導體基板之正面貼附正面保護膜,以及自半導體基板之背面研磨半導體基板,可保護半導體基板之背面在切割時不會有斷裂破片的風險,同時也能避免半導體基板發生翹曲。進一步地,透過露出晶粒及切割道並進行蒸鍍,使得金屬粒子深入切割道附著在晶粒四周的分布,可達到有效增加散熱效果之功效。In summary, the present invention provides a semiconductor manufacturing method, by first attaching a back protective film to the back of a semiconductor substrate, and cutting from the front to a set depth, and then attaching a front protective film to the front of the semiconductor substrate, and grinding the semiconductor substrate from the back of the semiconductor substrate, the back of the semiconductor substrate can be protected from the risk of breaking and fragmenting during cutting, and the semiconductor substrate can also be prevented from warping. Furthermore, by exposing the crystal grains and the cutting paths and performing evaporation, the metal particles are distributed deep into the cutting paths and attached to the surroundings of the crystal grains, which can effectively increase the heat dissipation effect.

雖然本發明已以較佳實施例揭露,然其並非用以限制本發明,任何熟習此項技藝之人士,在不脫離本發明之精神和範圍內,當可作各種更動與修飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed with preferred embodiments, they are not intended to limit the present invention. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined in the attached patent application.

1:半導體基板 11:正面 12:背面 13:切割道 14:晶粒 141:第一表面 142:第二表面 143:第三表面 144:第四表面 145:第五表面 146:第六表面 2:背面保護膜 3:正面保護膜 4:第二背面保護膜 5:半導體基板 51:正面 52:背面 53:切割道 54:晶粒 541:第一表面 542:第二表面 543:第三表面 544:第四表面 545:第五表面 546:第六表面 6:背面保護膜 7:正面保護膜 8:第二背面保護膜 d:設定深度 d2:設定深度 t:剩餘厚度 t2:剩餘厚度 S10:步驟 S20:步驟 S30:步驟 S40:步驟 S50:步驟 S60:步驟 S62:步驟 S64:步驟 S66:步驟 S68:步驟 S70:步驟 S80:步驟 S90:步驟 S100:步驟 1: semiconductor substrate 11: front 12: back 13: cutting path 14: crystal grain 141: first surface 142: second surface 143: third surface 144: fourth surface 145: fifth surface 146: sixth surface 2: back protective film 3: front protective film 4: second back protective film 5: semiconductor substrate 51: front 52: back 53: cutting path 54: crystal grain 541: first surface 542: second surface 543: third surface 544: fourth surface 545: fifth surface 546: sixth surface 6: back protective film 7: front protective film 8: second back protective film d: set depth d2: set depth t: remaining thickness t2: Remaining thickness S10: Step S20: Step S30: Step S40: Step S50: Step S60: Step S62: Step S64: Step S66: Step S68: Step S70: Step S80: Step S90: Step S100: Step

圖1顯示本案一實施例之一半導體製造方法之流程圖。 圖2顯示本案一實施例之一半導體製造方法之半導體基板、背面保護膜以及切割半導體基板之示意圖。 圖3顯示本案一實施例之一半導體製造方法中對貼附背面保護膜之半導體基板進行切割以及切割道與晶粒之立體圖。 圖4顯示本案一實施例之一半導體製造方法之半導體基板、切割道、晶粒以及背面保護膜之示意圖。 圖5顯示本案一實施例之半導體製造方法之正面保護膜、半導體基板以及自背面研磨半導體基板之示意圖。 圖6顯示本案一實施例之一半導體製造方法之正面保護膜、半導體基板之剩餘厚度等於設定深度以及自背面對半導體基板進行蒸鍍之示意圖。 圖7顯示以本案一實施例之一半導體製造方法進行蒸鍍後之一晶粒及其金屬粒子分布之立體圖。 圖8顯示倒置的圖7所示之晶粒及其金屬粒子分布之立體圖。 圖9顯示本案一實施例之一半導體製造方法之正面保護膜、半導體基板以及第二背面保護膜之示意圖。 圖10顯示本案一實施例之一半導體製造方法之半導體基板及第二背面保護膜之示意圖。 圖11顯示本案一實施例之一半導體製造方法之一細部流程圖。 圖12顯示本案另一實施例之一半導體製造方法之半導體基板、背面保護膜以及切割半導體基板之示意圖。 圖13顯示本案另一實施例之一半導體製造方法中對貼附背面保護膜之半導體基板進行切割以及切割道與晶粒之立體圖。 圖14顯示本案另一實施例之一半導體製造方法之半導體基板、切割道、晶粒以及背面保護膜之示意圖。 圖15顯示本案另一實施例之半導體製造方法之正面保護膜、半導體基板以及自背面研磨半導體基板之示意圖。 圖16顯示本案另一實施例之一半導體製造方法之正面保護膜、半導體基板之剩餘厚度等於設定深度以及自背面對半導體基板進行蒸鍍之示意圖。 圖17顯示以本案另一實施例之一半導體製造方法進行蒸鍍後之一晶粒及其金屬粒子分布之立體圖。 圖18顯示倒置的圖17所示之晶粒及其金屬粒子分布之立體圖。 圖19顯示本案另一實施例之一半導體製造方法之正面保護膜、半導體基板以及第二背面保護膜之示意圖。 圖20顯示本案另一實施例之一半導體製造方法之半導體基板及第二背面保護膜之示意圖。 FIG1 shows a flow chart of a semiconductor manufacturing method according to an embodiment of the present invention. FIG2 shows a schematic diagram of a semiconductor substrate, a back protective film, and a semiconductor substrate cut in a semiconductor manufacturing method according to an embodiment of the present invention. FIG3 shows a semiconductor substrate with a back protective film attached thereto in a semiconductor manufacturing method according to an embodiment of the present invention, and a three-dimensional diagram of the cutting path and the die. FIG4 shows a schematic diagram of a semiconductor substrate, a cutting path, a die, and a back protective film in a semiconductor manufacturing method according to an embodiment of the present invention. FIG5 shows a schematic diagram of a front protective film, a semiconductor substrate, and a semiconductor substrate ground from the back in a semiconductor manufacturing method according to an embodiment of the present invention. FIG6 shows a schematic diagram of a front protective film, a semiconductor substrate, and a semiconductor substrate having a residual thickness equal to a set depth and a semiconductor substrate being evaporated from the back in a semiconductor manufacturing method according to an embodiment of the present invention. FIG7 shows a three-dimensional image of a crystal grain and its metal particle distribution after evaporation by a semiconductor manufacturing method of an embodiment of the present case. FIG8 shows an inverted three-dimensional image of the crystal grain and its metal particle distribution shown in FIG7. FIG9 shows a schematic diagram of a front protective film, a semiconductor substrate, and a second back protective film of a semiconductor manufacturing method of an embodiment of the present case. FIG10 shows a schematic diagram of a semiconductor substrate and a second back protective film of a semiconductor manufacturing method of an embodiment of the present case. FIG11 shows a detailed flow chart of a semiconductor manufacturing method of an embodiment of the present case. FIG12 shows a schematic diagram of a semiconductor substrate, a back protective film, and a cut semiconductor substrate of a semiconductor manufacturing method of another embodiment of the present case. FIG. 13 shows a three-dimensional diagram of cutting a semiconductor substrate with a back protective film attached in a semiconductor manufacturing method according to another embodiment of the present invention, and the cutting path and the grain. FIG. 14 shows a schematic diagram of a semiconductor substrate, a cutting path, a grain and a back protective film according to another embodiment of the present invention. FIG. 15 shows a schematic diagram of a front protective film, a semiconductor substrate and a semiconductor substrate ground from the back according to another embodiment of the present invention. FIG. 16 shows a schematic diagram of a front protective film, a semiconductor substrate having a residual thickness equal to a set depth and evaporating a semiconductor substrate from the back according to another embodiment of the present invention. FIG. 17 shows a three-dimensional diagram of a grain and its metal particle distribution after evaporation according to a semiconductor manufacturing method according to another embodiment of the present invention. FIG. 18 shows a three-dimensional diagram of the inverted crystal grains and their metal particle distribution shown in FIG. 17. FIG. 19 shows a schematic diagram of a front protective film, a semiconductor substrate, and a second back protective film in a semiconductor manufacturing method according to another embodiment of the present invention. FIG. 20 shows a schematic diagram of a semiconductor substrate and a second back protective film in a semiconductor manufacturing method according to another embodiment of the present invention.

S10:步驟 S10: Step

S20:步驟 S20: Step

S30:步驟 S30: Step

S40:步驟 S40: Step

S50:步驟 S50: Step

S60:步驟 S60: Step

S70:步驟 S70: Step

Claims (10)

一種半導體製造方法,包括步驟:(a)提供具有一正面及一背面之一半導體基板;(b)貼附一背面保護膜於該背面;(c)自該正面沿複數個切割路徑切割該半導體基板至一設定深度,以形成複數個切割道,並使複數個晶粒受該複數個切割道相隔開;(d)貼附一正面保護膜於該正面;(e)移除該背面保護膜;(f)自該背面研磨該半導體基板,直到該半導體基板之一剩餘厚度等於該設定深度,以露出該複數個晶粒及該複數個切割道;以及(g)蒸鍍該半導體基板,使複數個金屬粒子附著在該複數個晶粒,其中每一個該金屬粒子的粒徑小於每一個該切割道的寬度。 A semiconductor manufacturing method includes the following steps: (a) providing a semiconductor substrate having a front surface and a back surface; (b) attaching a back surface protective film to the back surface; (c) cutting the semiconductor substrate from the front surface along a plurality of cutting paths to a set depth to form a plurality of cutting paths, and separating a plurality of crystal grains by the plurality of cutting paths; (d) attaching a front surface protective film to the front surface; (e) removing the back surface protective film; (f) grinding the semiconductor substrate from the back surface until a remaining thickness of the semiconductor substrate is equal to the set depth to expose the plurality of crystal grains and the plurality of cutting paths; and (g) evaporating the semiconductor substrate to attach a plurality of metal particles to the plurality of crystal grains, wherein the particle size of each of the metal particles is smaller than the width of each of the cutting paths. 如請求項1所述之半導體製造方法,其中每一個該晶粒包括相對設置的一第一表面及一第二表面以及與該第一表面及該第二表面垂直的一第三表面、一第四表面、一第五表面及一第六表面,且該複數個金屬粒子附著在該第二表面、該第三表面、該第四表面、該第五表面及該第六表面。 A semiconductor manufacturing method as described in claim 1, wherein each of the crystal grains includes a first surface and a second surface disposed opposite to each other, and a third surface, a fourth surface, a fifth surface, and a sixth surface perpendicular to the first surface and the second surface, and the plurality of metal particles are attached to the second surface, the third surface, the fourth surface, the fifth surface, and the sixth surface. 如請求項1所述之半導體製造方法,其中該複數個金屬粒子為複數個鈦鎳銀粒子。 A semiconductor manufacturing method as described in claim 1, wherein the plurality of metal particles are a plurality of titanium nickel silver particles. 如請求項1所述之半導體製造方法,其中該設定深度介於37.5微米至150微米。 A semiconductor manufacturing method as described in claim 1, wherein the setting depth is between 37.5 microns and 150 microns. 如請求項1所述之半導體製造方法,其中每一個該切割道的寬度為40微米,且每一個該金屬粒子的粒徑為1微米。 A semiconductor manufacturing method as described in claim 1, wherein the width of each of the cutting paths is 40 microns and the particle size of each of the metal particles is 1 micron. 如請求項1所述之半導體製造方法,其中該背面保護膜的厚度為90微米,且於該步驟(c)中,該半導體基板的厚度為300微米。 The semiconductor manufacturing method as described in claim 1, wherein the thickness of the back protective film is 90 microns, and in the step (c), the thickness of the semiconductor substrate is 300 microns. 如請求項6所述之半導體製造方法,其中該設定深度為70微米,該步驟(c)以一晶圓切割機之一刀片實現,且該刀片之一刀片高度參數為320微米。 A semiconductor manufacturing method as described in claim 6, wherein the set depth is 70 microns, the step (c) is implemented with a blade of a wafer cutting machine, and a blade height parameter of the blade is 320 microns. 如請求項1所述之半導體製造方法,其中於該步驟(f)及該步驟(g)之間,更包括步驟:(f1)去除該半導體基板之殘留應力;(f2)清洗該半導體基板;(f3)去除該半導體基板之一氧化層;以及(f4)乾燥該半導體基板。 The semiconductor manufacturing method as described in claim 1, wherein between step (f) and step (g), the method further includes the steps of: (f1) removing residual stress of the semiconductor substrate; (f2) cleaning the semiconductor substrate; (f3) removing an oxide layer of the semiconductor substrate; and (f4) drying the semiconductor substrate. 如請求項1所述之半導體製造方法,其中於該步驟(g)之後,更包括步驟:(h)貼附一第二背面保護膜於該背面;(i)移除該正面保護膜;以及(j)封裝該半導體基板。 The semiconductor manufacturing method as described in claim 1, wherein after step (g), further comprising the steps of: (h) attaching a second back protective film to the back surface; (i) removing the front protective film; and (j) packaging the semiconductor substrate. 如請求項9所述之半導體製造方法,其中於該步驟(j)中,該複數個晶粒被封裝形成複數個功率晶片。A semiconductor manufacturing method as described in claim 9, wherein in the step (j), the plurality of dies are packaged to form a plurality of power chips.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6292367B1 (en) * 2000-06-22 2001-09-18 International Business Machines Corporation Thermally efficient semiconductor chip
TW201533783A (en) * 2014-02-25 2015-09-01 Jx日鑛日石金屬股份有限公司 Power element manufacturing method
TW201911530A (en) * 2017-05-19 2019-03-16 學校法人早稻田大學 Power semiconductor module device and power semiconductor module manufacturing method
US20190333782A1 (en) * 2018-04-27 2019-10-31 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
CN111540668A (en) * 2020-01-16 2020-08-14 中国科学院微电子研究所 Process improvement method based on quartz glass epitaxial GaN

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6292367B1 (en) * 2000-06-22 2001-09-18 International Business Machines Corporation Thermally efficient semiconductor chip
TW201533783A (en) * 2014-02-25 2015-09-01 Jx日鑛日石金屬股份有限公司 Power element manufacturing method
TW201911530A (en) * 2017-05-19 2019-03-16 學校法人早稻田大學 Power semiconductor module device and power semiconductor module manufacturing method
US20190333782A1 (en) * 2018-04-27 2019-10-31 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
CN111540668A (en) * 2020-01-16 2020-08-14 中国科学院微电子研究所 Process improvement method based on quartz glass epitaxial GaN

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