TWI858341B - Random number generating circuit - Google Patents

Abstract

A random number generating circuit is provided, which includes a noise-voltage generator, configured to convert an external voltage into a noise voltage; a voltage-controlled oscillator, configured to receive the noise voltage, and generates a first clock signal according to the noise voltage; a ring oscillator, configured to generate a sample clock signal; and a D flip-flop, configured to receive the first clock signal, and sample the first clock signal using the sample clock signal to obtain an output digital signal, wherein the output digital signal represents a random number.

Description

Random Number Generation Circuit

The present invention relates to electronic circuits, and in particular to a random number generation circuit.

Random number generators (RNGs) play an important role in many different applications, such as cryptographic applications, statistical operations, and the row hammer mechanism of dynamic random access memory (DRAM). However, the numbers generated by traditional RNG-related circuits, such as linear feedback shift registers and ring oscillator-based random number generators, are often not truly random numbers, but pseudo-random numbers with determinism/periodicity.

In view of this, the present invention proposes a random number generation circuit to solve the above problem.

The present invention provides a random number generating circuit, comprising: a noise voltage generator for converting an external voltage into a noise voltage; a voltage-controlled oscillator for receiving the noise voltage and generating a first clock signal according to the noise voltage; a ring oscillator for generating a sampling clock signal; and a D-type flip-flop for receiving the first clock signal and sampling the first clock signal with the sampling clock signal to obtain an output digital signal, wherein the output digital signal represents a random number.

100: Random number generation circuit

110: Noise voltage generator

112: Power noise amplifier

114: Temperature reverse reference voltage circuit

116: Operational amplifier

120: Voltage-controlled oscillator

130: Ring oscillator

140: D-type flip-flop

1121: Operational amplifier

1301: Anti-and-gate

1302, 1303: Reverse device

VP, VT, VA, VB: voltage

V1: Noise voltage

VMIX: reference voltage

VEXT: external voltage

VDD: power supply voltage

R1-R7: resistor

N1-N7: Nodes

C1-C4: Capacitor

D1: diode

EN: Enable signal

f1, f2’: clock signal

f2: sampling clock signal

fmix: output digital signal

D: Data terminal

CLK: Clock input terminal

Q: Output terminal

Figure 1 is a block diagram showing a random number generation circuit according to an embodiment of the present invention.

Figure 2 is a circuit diagram of a power noise amplifier and a temperature reverse reference voltage circuit according to an embodiment of the present invention.

Figure 3A is a schematic diagram of the relationship between voltage VT and temperature in an embodiment of the present invention.

Figure 3B is a schematic diagram of voltages VT and VP according to an embodiment of the present invention.

Figure 3C is a schematic diagram of the reference voltage VMIX in an embodiment of the present invention.

Figure 4 is a schematic diagram of a ring oscillator according to an embodiment of the present invention.

Figure 5 is a waveform diagram of the sampling operation of the D-type flip-flop in the embodiment of Figure 1 of the present invention.

The following description is a preferred implementation method for completing the invention. Its purpose is to describe the basic spirit of the invention, but it is not intended to limit the invention. The actual content of the invention must refer to the scope of the subsequent patent application.

Figure 1 is a block diagram of a random number generation circuit according to an embodiment of the present invention.

As shown in FIG. 1 , the random number generating circuit 100 includes a noise voltage generator 110, a voltage-controlled oscillator 120, a ring oscillator 130, and a D-type flip-flop 140. The noise voltage generator 110 is used to convert the external voltage VEXT into a noise voltage V1, and provide the noise voltage V1 to the voltage-controlled oscillator 120.

The voltage-controlled oscillator 120 generates an irregular clock signal f1 according to the noise voltage V1. The ring oscillator 130 is used to generate a sample clock signal f2, wherein the sample clock signal f2 is a regular clock signal.

In addition, the sampling clock signal f2 is provided to the clock input terminal CLK of the D-type flip-flop 140 to sample the clock signal f1 inputted from the data terminal D, and an output digital signal fmix is generated at the output terminal Q, wherein the output digital signal fmix is a random number.

The noise voltage generator 110 includes a power noise amplifier 112, a temperature inversion (complementary to absolute temperature, CTAT) reference voltage circuit 114 and an operational amplifier 116. The power noise amplifier 112 is used to amplify the power noise of the external voltage VEXT to generate a voltage VP, and the temperature inversion reference voltage circuit 114 generates a voltage VT through the ambient temperature, wherein the voltage VT is inversely proportional to the absolute temperature. The voltage VP is mixed with the voltage VT at the node N1 through the capacitor C1 to obtain a reference voltage VMIX.

The operational amplifier 116 can be used as a voltage regulator, for example, wherein the reference voltage VMIX is input to the positive input terminal of the operational amplifier 116, and the noise voltage V1 generated by the output terminal (node N2) of the operational amplifier 116 is input to the negative input terminal of the operational amplifier 116 via a feedback path formed by resistors R2 and R3. For example, the relationship between the noise voltage V1 and the reference voltage VMIX is shown in equation (1):

。 Therefore, the noise voltage can be deduced from equation (1):

.

In detail, the characteristic of ambient temperature is that the relative value changes slowly, so the voltage VT can determine the basic frequency of the clock signal f1. In addition, the characteristic of power supply noise is that the instantaneous change is fast, so the voltage VP will temporarily change the frequency of the clock signal f1.

The voltage-controlled oscillator 120 uses the noise voltage V1 to generate an irregular clock signal f1, and the frequency of the clock signal f1 is affected by the external environment, such as external voltage, ambient temperature, chip process characteristics, etc., but thermal noise is not considered. The ring oscillator 130 can automatically generate a sampling clock signal f2, and the frequency of the sampling clock signal f2 is determined by the internal circuit of the ring oscillator 130. In addition, the voltage-controlled oscillator 120 and the ring oscillator 130 are both controlled by the enable signal EN. When the enable signal EN is in a high logic state, the voltage-controlled oscillator 120 and the ring oscillator 130 are in a working state to generate a clock signal f1 and a sampling clock signal f2 respectively. When the enable signal EN is in a low logic state, the voltage-controlled oscillator 120 and the ring oscillator 130 are turned off.

It should be noted that the present invention can utilize the design of the noise voltage generator 110 to convert the power supply noise and the ambient temperature into the corresponding noise voltage V1, and the voltage-controlled oscillator can generate a clock signal f1 (e.g., a digital signal) based on the noise voltage V1 (e.g., an analog signal). The above design does not require the use of an analog-to-digital converter to convert the thermal noise into a digital signal.

Figure 2 is a circuit diagram of a power noise amplifier and a temperature reverse reference voltage circuit according to an embodiment of the present invention. Please refer to Figures 1 and 2 at the same time.

As shown in FIG. 2 , in one embodiment, the first and second ends of capacitor C2 are connected to external voltage VEXT and node N3, respectively, and the first and second ends of resistor R4 are connected to external voltage VEXT and node N3, respectively. Node N3 has voltage VA, and voltage VA is input to the positive input terminal (+) of operational amplifier 1121. Voltage VA at node N3 passes through an RC circuit formed by resistor R6 and capacitor C3 to generate voltage VB at node N4, and voltage VB is input to the negative input terminal (-) of operational amplifier 1121. Because the RC circuit formed by resistor R6 and capacitor C3 can be regarded as a low-pass filter, the voltage VA with a larger power supply noise variation can be converted into the voltage VB with a smaller power supply noise variation. The difference between the voltage VA and the voltage VB can be amplified by the operational amplifier 1121 to obtain the voltage VP at the output terminal (node N5) of the operational amplifier 1121.

In one embodiment, the temperature reverse reference voltage circuit 114 can be implemented by, for example, a diode D1, a capacitor C4, and a resistor R7, wherein the diode D1 can also be implemented by a bipolar junction transistor (BJT) or a field effect transistor (FET) in a diode connection manner, for example, the collector and base of the NPN bipolar junction transistor can be simultaneously connected to the node N6, and the emitter of the NPN bipolar junction transistor is grounded, which can be equivalent to the diode D1.

If an N-type metal oxide semiconductor field effect transistor (MOSFET) is used, the gate and drain of the transistor can be connected to the node N6 at the same time, and the source of the transistor is grounded, which can be equivalent to a diode D1. Therefore, the temperature reverse reference voltage circuit 114 can obtain a voltage VT with a negative temperature coefficient at the node N6. That is, when the ambient temperature (absolute temperature) is higher, the voltage VT is lower, and when the ambient temperature (absolute temperature) is lower, the voltage VT is higher, wherein the above relationship is shown in Figure 3A.

In detail, the voltage VT can generate the DC level of the reference voltage VMIX at the node N1 after passing through the resistor R1, and the voltage VP can obtain the transient level of the reference voltage VMIX at the node N1 after being disturbed by the capacitor C1. As shown in Figure 3B, the noise variation of the voltage VP is higher, which can be regarded as the transient level of the reference voltage VMIX. Although the voltage VT will change with the ambient temperature, because the ambient temperature changes slowly, the voltage VT can be roughly maintained at a constant value. Therefore, the reference voltage VMIX can be regarded as the above transient level superimposed on the above DC level, as shown in Figure 3C. It should be noted that the random number generation circuit 100 in the present invention uses power supply noise and temperature as noise sources respectively, but does not use thermal noise.

In addition, the noise voltage generator 110 in the random number generation circuit 100 uses a diode, a resistor and a capacitor to generate a noise source, and does not require a complex analog-to-digital converter or a temperature sensor, so the area cost of the integrated circuit is lower.

Figure 4 is a schematic diagram of a ring oscillator according to an embodiment of the present invention.

In one embodiment, the ring oscillator 130 can be implemented by, for example, a NAND gate 1301, a plurality of inverters 1302 and 1303, and a power supply voltage VDD is provided to the NAND gate 1301 and the inverters 1302-1303 for operation, wherein the power supply voltage VDD can be, for example, an external voltage VEXT. The first input terminal of the NAND gate 1301 receives an enable signal EN, and the second input terminal receives a clock signal f2' generated by the output terminal of the last-stage inverter 1302.

For example, when the enable signal EN is in a low logic state, the output terminal of the NAND gate 1301 will continue to be in a high logic state, so the ring oscillator 130 cannot generate oscillation. When the enable signal EN is in a high logic state, the output signal of the NAND gate 1301 is the inverse signal of the input signal of its second input terminal, so the NAND gate 1301 can be regarded as an inverter. Therefore, the NAND gate 1301 and the inverter 1302 of the even number stage can constitute an inverter of the odd number stage for series connection, so it can continue to oscillate and obtain the clock signal f2' at the output terminal of the inverter 1302 of the last stage. For example, the number of inverters 1302 is 2N, and N is a positive integer.

After the clock signal f2' passes through the inverter 1303, the sampling clock signal f2 can be obtained. Those with ordinary knowledge in the field of the present invention should understand that the oscillation frequency of the ring oscillator 130 (i.e., the frequency of the sampling clock signal f2) can be changed by adjusting the order of the inverter 1302 and the size of the transistor, so the details are not described here.

Figure 5 is a waveform diagram of the sampling operation of the D-type flip-flop in the embodiment of Figure 1 of the present invention. Please refer to Figure 1 and Figure 5 at the same time.

As shown in FIG. 5 , when the enable signal EN is in a high logic state, the voltage-controlled oscillator 120 and the ring oscillator 130 start to oscillate to generate a clock signal f1 and a sampling clock signal f2, respectively, wherein the clock signal f1 is an irregular clock signal, and the sampling clock signal f2 is a regular clock signal. The sampling clock signal f2 is provided to the clock input terminal CLK of the D-type flip-flop 140 to sample the clock signal f1 inputted by the data terminal D, and an output digital signal fmix is generated at the output terminal Q.

In detail, the D-type flip-flop 140 samples the clock signal f1 at the rising edge of the sampling clock signal f2. Because the clock signal f1 is an irregular clock signal, whenever the sampling clock signal f2 is at the rising edge, the output digital signal fmix obtained by the D-type flip-flop 140 at its output terminal Q also includes an irregular value of 0 or 1. In other words, the output digital signal fmix is a random number.

In summary, the present invention provides a random number generating circuit that can use power supply noise and temperature as noise sources instead of thermal noise. In addition, the random number generating circuit of the present invention uses diodes, resistors and capacitors to generate noise sources, and does not require complex analog-to-digital converters or temperature sensors, so the area cost of implementing in integrated circuits is lower. In addition, the random numbers generated by the random number generating circuit will be affected by power supply noise, temperature and process, so it is not easy to have regularity, and its effect is close to the real random number.

Although the present invention is disclosed as above with the preferred embodiment, it is not intended to limit the scope of the present invention. Anyone with common knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined in the attached patent application.

100: Random number generator circuit 110: Noise voltage generator 112: Power noise amplifier 114: Temperature reverse reference voltage circuit 116: Operational amplifier 120: Voltage controlled oscillator 130: Ring oscillator 140: D-type flip-flop VP, VT: Voltage V1: Noise voltage VMIX: Reference voltage R1-R3: Resistor N1-N2: Node C1: Capacitor EN: Enable signal f1: Clock signal f2: Sampling clock signal fmix: Output digital signal D: Data terminal CLK: Clock input terminal Q: Output terminal

Claims (10)

A random number generating circuit includes: a noise voltage generator for converting an external voltage into a noise voltage; a voltage-controlled oscillator for receiving the noise voltage and generating a first clock signal according to the noise voltage; a ring oscillator for generating a sampling clock signal, wherein the sampling clock signal is not affected by the external environment; and a D-type flip-flop for receiving the first clock signal and sampling the first clock signal with the sampling clock signal to obtain an output digital signal, wherein the output digital signal represents a random number. The random number generating circuit of claim 1, wherein the noise voltage generator comprises: a power noise amplifier for amplifying the power noise of the external voltage to generate a first voltage; a temperature reverse reference voltage circuit for generating a second voltage through the ambient temperature of the random number generating circuit; and a first operational amplifier; wherein the first voltage is connected to the positive input terminal of the first operational amplifier through a first capacitor, and the second voltage is connected to the positive input terminal of the first operational amplifier through a first resistor, wherein the noise voltage output by the first operational amplifier is input to the negative input terminal of the first operational amplifier through a feedback path. A random number generating circuit as in claim 2, wherein the second voltage has a negative temperature coefficient. A random number generation circuit as claimed in claim 2, wherein the first voltage represents a transient level of a reference voltage, and the second voltage represents a DC level of the reference voltage. The random number generating circuit of claim 2, wherein the feedback path includes a second resistor and a third resistor, and the first end and the second end of the second resistor are respectively connected to the second node and the negative input terminal of the first operational amplifier, and the first end and the second end of the third resistor are respectively connected to the negative input terminal of the first operational amplifier and the ground terminal, wherein the second node is the output terminal of the first operational amplifier. As in claim 2, the random number generating circuit, wherein the power noise amplifier includes a second operational amplifier, and the external voltage is connected to a third node through a second capacitor and a fourth resistor connected in parallel, and the third node is connected to the positive input terminal of the second operational amplifier, wherein the first terminal and the second terminal of the fifth resistor are connected to the third node and the ground terminal respectively, and the third node is connected to the negative input terminal of the second operational amplifier through a low-pass filter composed of a sixth resistor and a third capacitor. The random number generation circuit of claim 2, wherein the temperature reverse reference voltage circuit includes a seventh resistor, a diode and a fourth capacitor, wherein the first end and the second end of the seventh resistor are connected to the external voltage and the sixth node respectively, wherein the anode and the cathode of the diode are connected to the sixth node and the ground terminal respectively, and the first end and the second end of the fourth capacitor are connected to the sixth node and the ground terminal respectively, wherein the sixth node is the output terminal of the temperature reverse reference voltage circuit. As in the random number generating circuit of claim 1, the voltage-controlled oscillator and the ring oscillator are controlled by an enable signal, and when the enable signal is in a high logic state, the voltage-controlled oscillator and the ring oscillator are in a working state to generate the first clock signal and the sampling clock signal respectively, and when the enable signal is in a low logic state, the voltage-controlled oscillator and the ring oscillator are turned off. As in claim 8, the random number generating circuit, wherein the ring oscillator comprises an AND gate, a plurality of first inverters, and a second inverter connected in series in sequence, wherein the enable signal and the second clock signal generated by the last inverter among the first inverters are input to the AND gate, and the first inverters have a number of 2N, and N is a positive integer, wherein the second clock signal is input to the second inverter to obtain the sampling clock signal. As in the random number generation circuit of claim 1, the D-type flip-flop samples the first clock signal at the positive edge of the sampling clock signal to obtain the output digital signal.

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