TWI857808B - Pixel driving circuit - Google Patents

Abstract

A pixel driving circuit includes a first transistor, a second transistor, a third transistor, a plurality of fourth transistors, a plurality of fifth transistors, a storage capacitor, a plurality of light-emitting control lines and a plurality of light-emitting diodes. In the pixel driving circuit, different light-emitting diodes can share the first transistor, the second transistor, the third transistor and the storage capacitor, thereby reducing the area required for wiring.

Description

Pixel driver circuit

The present invention relates to a pixel driving circuit.

Micro-light-emitting diode (µLED) technology is very suitable for manufacturing transparent displays. Compared with traditional transmissive LCDs, transmissive µLED displays do not require polarizers, so there is no loss of transmittance due to polarizers. Generally, the transmittance of transmissive µLED displays is affected by the opaque µLEDs and circuits.

With the continuous advancement of semiconductor technology, the size of µLEDs has gradually shrunk. However, due to the limitations of metal wiring process technology, even if the size of µLEDs is reduced, it is still difficult to improve the transmittance of transmissive µLED display devices. Therefore, a method that can solve the above problems is urgently needed.

The present invention provides a pixel driving circuit, which has the advantage of improving the pixel opening rate.

At least one embodiment of the present invention provides a pixel driving circuit, including a first transistor, a second transistor, a third transistor, a plurality of fourth transistors, a plurality of fifth transistors, a storage capacitor, a plurality of light-emitting control lines, and a plurality of light-emitting diodes. The first source/drain of the first transistor is configured to receive a data line signal. The gate of the second transistor is electrically connected to the second source/drain of the first transistor. The gate of the first transistor and the gate of the third transistor are configured to receive a scan line signal, and the first source/drain of the third transistor is configured to receive an initial voltage signal. The storage capacitor includes a first terminal and a second terminal. The first end, the second source/drain of the first transistor, and the gate of the second transistor are electrically connected to the first node. The first transistor controls the first voltage signal of the first node in response to the scan line signal. The first source/drain of each of the fourth transistors is electrically connected to each other and is configured to receive the first working voltage signal, and the second source/drain of each of the fourth transistors, the first source/drain of the second transistor, the second source/drain of the third transistor, and the second end of the storage capacitor are electrically connected to the second node. The third transistor controls the second voltage signal of the second node in response to the scan line signal. The first source/drain of each of the fifth transistors is electrically connected to each other and electrically connected to the second transistor. Each light-emitting control line is electrically connected to a gate of a corresponding fourth transistor and a gate of a corresponding fifth transistor. The fourth transistor controls the second voltage signal of the second node in response to the control signal of the light-emitting control line. A plurality of light-emitting diodes are electrically connected to the second source/drain of each fifth transistor.

Based on the above, in the pixel driving circuit, different light-emitting diodes can share the first transistor, the second transistor, the third transistor and the storage capacitor, thereby reducing the area occupied by the wiring and increasing the pixel opening rate.

FIG. 1 is a circuit diagram of a pixel driving circuit 10 according to an embodiment of the present invention. FIG. 2 is a schematic top view of a pixel driving circuit 10 according to an embodiment of the present invention. For the convenience of explanation, FIG. 2 omits the light-emitting diodes L1, L2, L3 and some wirings. In FIG. 2, the conductors/semiconductors of the same film layer are drawn with the same filling pattern. In FIG. 2, the conductors/semiconductors of different layers include dielectric layers (not shown), and these dielectric layers may have vias (not shown) connecting the conductors/semiconductors of different layers.

1 , the pixel driving circuit 10 includes a first transistor T1, a second transistor T2, a third transistor T3, a plurality of fourth transistors T4-1, T4-2, T4-3, a plurality of fifth transistors T5-1, T5-2, T5-3, a storage capacitor C, a plurality of light-emitting control lines EM1, EM2, EM3, and a plurality of light-emitting diodes L1, L2, L3. In this embodiment, the pixel driving circuit 10 further includes a data line DL, a scanning line SL, a test signal line ATL, an initial signal line VL, a sixth transistor T6, and a seventh transistor T7.

The first transistor T1, the second transistor T2, the third transistor T3, the plurality of fourth transistors T4-1, T4-2, T4-3, the plurality of fifth transistors T5-1, T5-2, T5-3, the sixth transistor T6, and the seventh transistor T7 each include a gate G, a semiconductor channel CH, a first source SD1, and a second source SD2. The gate G overlaps the semiconductor channel CH, and the first source SD1 and the second source SD2 are electrically connected to the semiconductor channel CH, respectively. In some embodiments, the first source SD1 and/or the second source SD2 are metal electrodes connected to the semiconductor channel CH or semiconductor materials doped to have high conductivity. For example, a doping process is performed on the semiconductor pattern, and a portion of the undoped semiconductor pattern can be used as a semiconductor channel CH, while a portion of the doped semiconductor pattern can be used as a first source SD1 and/or a second source SD2.

The first transistor T1, the second transistor T2, the third transistor T3, the plurality of fourth transistors T4-1, T4-2, T4-3, the plurality of fifth transistors T5-1, T5-2, T5-3, the sixth transistor T6, and the seventh transistor T7 are not limited to the types of transistors shown in Fig. 2. Specifically, the first transistor T1, the second transistor T2, the third transistor T3, the plurality of fourth transistors T4-1, T4-2, T4-3, the plurality of fifth transistors T5-1, T5-2, T5-3, the sixth transistor T6, and the seventh transistor T7 may include any type of transistor, such as a bottom gate thin film transistor, a top gate thin film transistor, a double gate thin film transistor, or other types of thin film transistors.

The first source/drain SD1 of the first transistor T1 is configured to receive the data line signal Data. For example, the first source/drain SD1 of the first transistor T1 is electrically connected to the data line DL, wherein the data line DL is configured to transmit the data line signal Data. The gate G of the second transistor T2 is electrically connected to the second source/drain SD2 of the first transistor T1. The gate G of the first transistor T1 and the gate G of the third transistor T3 are configured to receive the scan line signal SN[n]. For example, the gate G of the first transistor T1 and the gate G of the third transistor T3 are electrically connected to the scan line SL, wherein the scan line SL is configured to transmit the scan line signal SN[n].

It should be noted that the scan line signal SN[n] represents the signal of the scan line SL of the nth level. Specifically, the display device may include a total of x levels of pixel driver circuits, where n is a positive integer between 1 and x. The scan line SL of the nth level is configured to transmit the scan line signal SN[n].

The first source/drain SD1 of the third transistor T3 is configured to receive the initial voltage signal Vini. For example, the first source/drain SD1 of the third transistor T3 is electrically connected to the initial signal line VL, wherein the initial signal line VL is configured to transmit the initial voltage signal Vini.

The storage capacitor C includes a first terminal E1 and a second terminal E2. The first terminal E1, the second source/drain SD2 of the first transistor T1, and the gate G of the second transistor T2 are electrically connected to each other, for example, they are all electrically connected to the first node ND1 shown in FIG. 1. The first transistor T1 controls the first voltage signal of the first node ND1 in response to the scan line signal SN[n].

The first source/drain SD1 of each of the fourth transistors T4-1, T4-2, and T4-3 are electrically connected to each other and configured to receive the first operating voltage signal Vdd. For example, the first source/drain SD1 of each of the fourth transistors T4-1, T4-2, and T4-3 are electrically connected to a first operating signal line (not shown in FIG. 2 ), wherein the first operating signal line is used to transmit the first operating voltage signal Vdd.

The second source/drain SD2 of each of the fourth transistors T4-1, T4-2, and T4-3, the first source/drain SD1 of the second transistor T2, the second source/drain SD2 of the third transistor T3, and the second end E2 of the storage capacitor are electrically connected to each other, for example, they are all electrically connected to the second node ND2 shown in FIG1. The third transistor T3 controls the second voltage signal of the second node ND2 in response to the scan line signal SN[n].

The first sources/drains SD1 of the fifth transistors T5-1, T5-2, and T5-3 are electrically connected to each other and to the second source/drain SD2 of the second transistor T2.

Each luminescence control line EM1, EM2, EM3 is electrically connected to a gate G of a corresponding fourth transistor T4-1, T4-2, T4-3 and a gate G of a corresponding fifth transistor T5-1, T5-2, T5-3. The fourth transistors T4-1, T4-2, T4-3 respectively respond to the control signals EM1[n], EM2[n], EM3[n] of the luminescence control lines EM1, EM2, EM3 to control the second voltage signal of the second node ND2.

It should be noted that the control signals EM1[n], EM2[n], EM3[n] represent the signals of the n-th level of light-emitting control lines EM1, EM2, EM3. Specifically, the display device may include a total of x levels of pixel driver circuits, where n is a positive integer between 1 and x. The n-th level of light-emitting control lines EM1, EM2, EM3 are configured to transmit control signals EM1[n], EM2[n], EM3[n], respectively.

The light-emitting control lines EM1, EM2, and EM3 include light-emitting control lines for controlling light-emitting signals of different colors, such as but not limited to a red light-emitting control line (such as the light-emitting control line EM1), a green light-emitting control line (such as the light-emitting control line EM2), and a blue light-emitting control line (such as the light-emitting control line EM3). The light-emitting control line EM1 is electrically connected to the gate G of the fourth transistor T4-1 and the gate G of the fifth transistor T5-1, the light-emitting control line EM2 is electrically connected to the gate G of the fourth transistor T4-2 and the gate G of the fifth transistor T5-2, and the light-emitting control line EM3 is electrically connected to the gate G of the fourth transistor T4-3 and the gate G of the fifth transistor T5-3.

One end of the plurality of light emitting diodes L1, L2, L3 (not shown in FIG. 2 ) is electrically connected to the second source/drain SD2 of each of the fifth transistors T5-1, T5-2, T5-3. The other end of the plurality of light emitting diodes L1, L2, L3 is configured to receive the second operating voltage signal Vss.

The LEDs L1, L2, L3 include LEDs of different colors, such as but not limited to a red LED (such as LED L1), a green LED (such as LED L2), and a blue LED (such as LED L3). The second source/drain SD2 of the fifth transistor T5-1 is electrically connected to the LED L1; the second source/drain SD2 of the fifth transistor T5-2 is electrically connected to the LED L2; and the second source/drain SD2 of the fifth transistor T5-3 is electrically connected to the LED L3.

In this embodiment, each pixel driving circuit includes three LEDs of different colors and is controlled by three light-emitting control lines, three fourth transistors, and three fifth transistors, but the present invention is not limited thereto. In other embodiments, the pixel driving circuit includes two or more than four LEDs, and the number of light-emitting control lines, the number of fourth transistors, and the number of fifth transistors is the same as the number of LEDs.

The sixth transistor T6 and the seventh transistor T7 are used for detecting the light-emitting diode. The first source/drain SD1 of the sixth transistor T6 is electrically connected to the data line DL and is configured to receive the data line signal Data. The gate G of the sixth transistor T6 is configured to receive the test signal AT. For example, the gate G of the sixth transistor T6 is electrically connected to the test signal line ATL, wherein the test signal line ATL is configured to transmit the test signal AT. The second source/drain SD2 of the sixth transistor T6 is electrically connected to the first source/drain SD1 of the seventh transistor T7. The second source/drain SD2 of the seventh transistor T7 is electrically connected to a corresponding light-emitting diode. In this embodiment, only the light-emitting diode L1 is detected, and the second source/drain SD2 of the seventh transistor T7 is electrically connected to the light-emitting diode L1, but the present invention is not limited thereto. In other embodiments, the pixel driving circuit includes a plurality of sixth transistors and a plurality of seventh transistors, wherein the seventh transistors are respectively connected to light-emitting diodes of different colors, thereby detecting light-emitting diodes of different colors. The gate G of the seventh transistor T7 is electrically connected to a corresponding light-emitting control line. In this embodiment, the gate G of the seventh transistor T7 is electrically connected to the light-emitting control line EM1 as an example, but the present invention is not limited thereto. In other embodiments, the gates G of the plurality of seventh transistors T7 are electrically connected to different light-emitting control lines.

In some embodiments, the first transistor T1, the second transistor T2, the third transistor T3, the plurality of fourth transistors T4-1, T4-2, T4-3, the plurality of fifth transistors T5-1, T5-2, T5-3, the sixth transistor T6, and the seventh transistor T7 are located on the same side of the corresponding scanning line SL. For example, in FIG. 2 , the pixel driving circuit 10 is electrically connected to the scanning line SL, and the first transistor T1, the second transistor T2, the third transistor T3, the plurality of fourth transistors T4-1, T4-2, T4-3, the plurality of fifth transistors T5-1, T5-2, T5-3, the sixth transistor T6, and the seventh transistor T7 are located on the lower side of the scanning line SL.

In some embodiments, the first transistor T1, the second transistor T2, the third transistor T3, the plurality of fourth transistors T4-1, T4-2, T4-3, the plurality of fifth transistors T5-1, T5-2, T5-3, the sixth transistor T6, and the seventh transistor T7 are located on the same side of the corresponding data line DL. For example, in FIG. 2 , the pixel driving circuit 10 is electrically connected to the data line DL, and the first transistor T1, the second transistor T2, the third transistor T3, the plurality of fourth transistors T4-1, T4-2, T4-3, the plurality of fifth transistors T5-1, T5-2, T5-3, the sixth transistor T6, and the seventh transistor T7 are located on the left side of the data line DL.

In some embodiments, the data line DL, the initial voltage signal line VL, and the test signal line ATL extend along the first direction D1. The scanning line SL and the light-emitting control lines EM1, EM2, EM3 extend along the second direction D2 that is not parallel to the first direction D1. In some embodiments, the first direction D1 is perpendicular to the second direction D2. In some embodiments, the fourth transistors T4-1, T4-2, T4-3 are aligned in the second direction D2, and the fifth transistors T5-1, T5-2, T5-3 are also aligned in the second direction D2. In some embodiments, the fourth transistors T4-1, T4-2, T4-3 are aligned with the fifth transistors T5-1, T5-2, T5-3 in the first direction D1, respectively.

FIG. 3A to FIG. 3D are circuit diagrams of a driving method of a pixel driving circuit 10 according to an embodiment of the present invention. In FIG. 3A to FIG. 3D, the direction of the black arrow indicates the direction of the signal/current. In some embodiments, the method of lighting up the light-emitting diode includes a programming step (as shown in FIG. 3A) and a light-emitting step (as shown in FIG. 3B to FIG. 3D). First, as shown in FIG. 3A, in the programming step, the first transistor T1 and the third transistor T3 are switched to the on state (On state) in response to the scan line signal SN[n]. The fourth transistor T4-1, T4-2, T4-3 and the fifth transistor T5-1, T5-2, T5-3 are switched to the off state (Off state).

The data line signal Data is transmitted to the first node ND1 through the first transistor T1, and the initial voltage signal Vini is transmitted to the second node ND2 through the third transistor T3. The voltage difference between the first node ND1 and the second node ND2 charges the storage capacitor C. In some embodiments, the voltage difference between the first node ND1 and the second node ND2 can be referred to as the gate-source voltage (Vgs) of the second transistor T2.

After the programming step, the light-emitting step is performed. In the light-emitting step, the first transistor T1 and the third transistor T3 are switched to the off state. The light-emitting control line is used to turn on one of the fourth transistors and one of the fifth transistors, and the other fourth transistors and the other fifth transistors are turned off at the same time.

In FIG. 3B , the fourth transistor T4-1 and the fifth transistor T5-1 are switched to the on state in response to EM1[n], while the fourth transistor T4-2, T4-3 and the fifth transistor T5-2, T5-3 are kept in the off state. At this time, the signal/current can pass through the fourth transistor T4-1, the second transistor T2 and the fifth transistor T5-1 and light up the LED L1.

In FIG. 3C , the fourth transistor T4-2 and the fifth transistor T5-2 are switched to the on state in response to EM2[n], while the fourth transistor T4-1, T4-3 and the fifth transistor T5-1, T5-3 are kept in the off state. At this time, the signal/current can pass through the fourth transistor T4-2, the second transistor T2 and the fifth transistor T5-2 and light up the LED L2.

In FIG. 3D , the fourth transistor T4-3 and the fifth transistor T5-3 are switched to the on state in response to EM3[n], while the fourth transistor T4-1, T4-2 and the fifth transistor T5-1, T5-2 are kept in the off state. At this time, the signal/current can pass through the fourth transistor T4-3, the second transistor T2 and the fifth transistor T5-3, and light up the LED L3.

In some embodiments, each emitting step is matched with a programming step. For example, the emitting step of FIG. 3B is matched with a programming step of FIG. 3A to light up the LED L1, the emitting step of FIG. 3C is matched with a programming step of FIG. 3A to light up the LED L2, and the emitting step of FIG. 3D is matched with a programming step of FIG. 3A to light up the LED L3. The lighting sequence of the LED L1, the LED L2, and the LED L3 can be adjusted according to the requirements.

In this embodiment, different light-emitting diodes L1, L2, L3 can share the first transistor T1, the second transistor T2, the third transistor T3 and the storage capacitor C, thereby reducing the area occupied by the wiring and increasing the pixel opening rate.

FIG. 4 is a signal diagram of a display device driving method according to an embodiment of the present invention. FIG. 5A to FIG. 5C are top views of a display device driven according to the driving method of FIG. 4 . Please refer to FIG. 4 and FIG. 5A to FIG. 5C . In this embodiment, a field sequential color (FSC) method is used to drive the display device. The display device includes an array of pixel driving circuits 10.

Each pixel driving circuit 10 includes corresponding light emitting control lines EM1, EM2, EM3 (see FIG. 2 ), wherein the light emitting control lines EM1, EM2, EM3 of the n-th pixel driving circuit 10 are configured to transmit control signals EM1[n], EM2[n], EM3[n], respectively. FIG. 4 shows control signals EM1[1], EM2[1], EM3[1] on the light emitting control lines EM1, EM2, EM3 of the first stage to control signals EM1[6], EM2[6], EM3[6] on the light emitting control lines EM1, EM2, EM3 of the sixth stage.

In FIG. 4 , the signal on the data line signal Data can be represented by a letter plus a number, wherein the letter “R” represents the grayscale signal corresponding to the red LED, the letter “G” represents the grayscale signal corresponding to the green LED, and the letter “B” represents the grayscale signal corresponding to the blue LED. The number portion is used to represent the level of the corresponding pixel driver circuit 10. For example, the grayscale signal corresponding to the red LED of the first-level pixel driver circuit 10 is represented by R1, and the grayscale signal corresponding to the blue LED of the second-level pixel driver circuit 10 is represented by B2.

In this embodiment, the time of a frame F is divided into three parts. In the first one-third frame, the grayscale information R1, R2, R3, R4, R5, R6, ... corresponding to the light-emitting diode L1 (for example, a red light-emitting diode) is written into the pixel driver circuit 10 of different levels (or different columns in FIG. 5A ) in sequence using the data line signal Data. The step of writing the grayscale information R1, R2, R3, R4, R5, R6, ... can also be called a programming step (as shown in FIG. 3A ). In addition, the light-emitting steps of the pixel driver circuits 10 of different levels are executed in sequence (as shown in FIG. 3B ) to light up the light-emitting diodes L1 of the pixel driver circuits 10 of different levels in sequence. Specifically, in the first one-third frame, the light-emitting control lines EM2 and EM3 of the pixel driving circuit 10 of each level are maintained at a low potential, and the light-emitting control lines EM1 of the pixel driving circuits 10 of different levels are sequentially adjusted to a high potential and maintained for a period of time (such as the time periods EMR1 to EMR6 shown in FIG. 4 ). In the time period EMR1, the light-emitting diode L1 of the pixel driving circuit 10 of the first level is in a light-on state; in the time period EMR2, the light-emitting diode L1 of the pixel driving circuit 10 of the second level is in a light-on state; and the subsequent time periods EMR3 to EMR6 are similarly applied. As shown in FIG. 5A , in the first one-third frame, the light-emitting diode L1 of the display device is lit.

In this embodiment, in the second third frame, the data line signal Data is used to sequentially write the grayscale information G1, G2, G3, G4, G5, G6, ... corresponding to the light-emitting diode L2 (for example, the green light-emitting diode) to the pixel driver circuits 10 of different levels (or different columns in FIG. 5B ). The step of writing the grayscale information G1, G2, G3, G4, G5, G6, ... can also be called a programming step (as shown in FIG. 3A ). In addition, the light-emitting steps of the pixel driver circuits 10 of different levels are sequentially executed (as shown in FIG. 3C ) to sequentially light up the light-emitting diodes L2 of the pixel driver circuits 10 of different levels. Specifically, in the second one-third frame, the light-emitting control lines EM1 and EM3 of the pixel driving circuit 10 of each level are maintained at a low potential, and the light-emitting control lines EM2 of the pixel driving circuits 10 of different levels are adjusted to a high potential and maintained for a period of time (such as the time periods EMG1 to EMG6 shown in FIG. 4 ). In the time period EMG1, the light-emitting diode L2 of the pixel driving circuit 10 of the first level is in a light-on state; in the time period EMG2, the light-emitting diode L2 of the pixel driving circuit 10 of the second level is in a light-on state; and the subsequent time periods EMG3 to EMG6 are similarly controlled. As shown in FIG. 5B , in the second one-third frame, the light-emitting diode L2 of the display device is turned on.

In this embodiment, in the third one-third frame, the data line signal Data is used to sequentially write grayscale information B1, B2, B3, B4, B5, B6, ... corresponding to the light-emitting diode L3 (for example, a blue light-emitting diode) to the pixel driver circuits 10 of different levels (or different columns in FIG. 5C ). The step of writing the grayscale information B1, B2, B3, B4, B5, B6, ... can also be called a programming step (as shown in FIG. 3A ). In addition, the light-emitting steps of the pixel driver circuits 10 of different levels are sequentially executed (as shown in FIG. 3D ) to sequentially light up the light-emitting diodes L3 of the pixel driver circuits 10 of different levels. Specifically, in the third one-third frame, the light-emitting control lines EM1 and EM2 of the pixel driving circuit 10 of each level are maintained at a low potential, and the light-emitting control lines EM3 of the pixel driving circuits 10 of different levels are adjusted to a high potential and maintained for a period of time (such as the time periods EMB1 to EMB6 shown in FIG. 4 ). In the time period EMB1, the light-emitting diode L3 of the pixel driving circuit 10 of the first level is in a light-on state; in the time period EMB2, the light-emitting diode L3 of the pixel driving circuit 10 of the second level is in a light-on state; and the subsequent time periods EMB3 to EMB6 are similarly controlled. As shown in FIG. 5C , in the third one-third frame, the light-emitting diode L3 of the display device is turned on.

FIG6 is a signal diagram of another driving method of a display device according to an embodiment of the present invention. FIG7A to FIG7C are top views of a display device driven according to the driving method of FIG6. Please refer to FIG6 and FIG7A to FIG7C. In this embodiment, the FSC method is used to drive the display device. The display device includes an array of pixel driving circuits 10.

Each pixel driving circuit 10 includes corresponding light emitting control lines EM1, EM2, EM3 (see FIG. 2 ), wherein the light emitting control lines EM1, EM2, EM3 of the n-th pixel driving circuit 10 are configured to transmit control signals EM1[n], EM2[n], EM3[n], respectively. FIG. 6 shows EM1[1], EM2[1], EM3[1] on the light emitting control lines EM1, EM2, EM3 of the first stage to EM1[6], EM2[6], EM3[6] on the light emitting control lines EM1, EM2, EM3 of the sixth stage.

In FIG6 , the signal on the data line signal Data can be represented by a letter plus a number, wherein the letter “R” represents the grayscale signal corresponding to the red LED, the letter “G” represents the grayscale signal corresponding to the green LED, and the letter “B” represents the grayscale signal corresponding to the blue LED. The number portion is used to represent the level of the corresponding pixel driver circuit 10. For example, the grayscale signal corresponding to the red LED of the first-level pixel driver circuit 10 is represented by R1, and the grayscale signal corresponding to the blue LED of the second-level pixel driver circuit 10 is represented by B2.

In this embodiment, the time of one frame is divided into three parts. In the first one-third frame, the grayscale information R1, G2, B3, R4, G5, B6, ... corresponding to different colors is written into the pixel driver circuits 10 of different levels (or different columns in FIG. 5A ) in sequence using the data line signal Data. The step of writing the grayscale information R1, G2, B3, R4, G5, B6, ... can also be called a programming step (as shown in FIG. 3A ). In addition, the light-emitting steps of the pixel driver circuits 10 of different levels are executed in sequence (as shown in FIGS. 3B to 3D ) to light up the light-emitting diodes L1, L2, L3 of the pixel driver circuits 10 of different levels in sequence. In this embodiment, the light-emitting elements of the pixel driver circuits 10 of adjacent levels (adjacent columns) are illuminated with different colors. As shown in FIG5A , in the first third frame, the light-emitting diode L1 of the pixel driver circuit 10 of the first column is illuminated, the light-emitting diode L2 of the pixel driver circuit 10 of the second column is illuminated, the light-emitting diode L3 of the pixel driver circuit 10 of the third column is illuminated, the light-emitting diode L1 of the pixel driver circuit 10 of the fourth column is illuminated, and the subsequent pixel driver circuits 10 are illuminated in the same manner.

In this embodiment, in the second third frame, the data line signal Data is used to sequentially write grayscale information G1, B2, R3, G4, B5, R6, ... corresponding to different colors to the pixel driver circuits 10 of different levels (or different columns in FIG. 5A). The step of writing the grayscale information G1, B2, R3, G4, B5, R6, ... can also be called a programming step (as shown in FIG. 3A). In addition, the light-emitting steps of the pixel driver circuits 10 of different levels are sequentially executed (as shown in FIGS. 3B to 3D) to sequentially light up the light-emitting diodes L1, L2, L3 of the pixel driver circuits 10 of different levels. In this embodiment, the light-emitting elements of the pixel driver circuits 10 of adjacent levels (adjacent columns) have different colors. As shown in FIG. 5A , in the second one-third frame, the LED L2 of the pixel driver circuit 10 in the first column is turned on, the LED L3 of the pixel driver circuit 10 in the second column is turned on, the LED L1 of the pixel driver circuit 10 in the third column is turned on, the LED L2 of the pixel driver circuit 10 in the fourth column is turned on, and the subsequent pixel driver circuits 10 are turned on in the same manner.

In this embodiment, in the third one-third frame, the data line signal Data is used to sequentially write grayscale information B1, R2, G3, B4, R5, G6, ... corresponding to different colors to the pixel driver circuits 10 of different levels (or different columns in FIG. 5A). The step of writing the grayscale information B1, R2, G3, B4, R5, G6, ... can also be called a programming step (as shown in FIG. 3A). In addition, the light-emitting steps of the pixel driver circuits 10 of different levels are sequentially executed (as shown in FIGS. 3B to 3D) to sequentially light up the light-emitting diodes L1, L2, L3 of the pixel driver circuits 10 of different levels. In this embodiment, the light-emitting elements of the pixel driver circuits 10 of adjacent levels (adjacent columns) have different colors. As shown in FIG. 5A , in the third one-third frame, the LED L3 of the pixel driver circuit 10 in the first column is lit, the LED L1 of the pixel driver circuit 10 in the second column is lit, the LED L2 of the pixel driver circuit 10 in the third column is lit, the LED L3 of the pixel driver circuit 10 in the fourth column is lit, and so on for the subsequent pixel driver circuits 10.

In this embodiment, the light-emitting diodes in the same one-third frame include different colors, thereby eliminating the color separation problem caused by the periodicity of the color arrangement.

FIG8 is a circuit diagram of a pixel driving circuit 20 according to an embodiment of the present invention. It should be noted that the embodiment of FIG8 uses the component numbers and some contents of the embodiments of FIG1 and FIG2, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

The main difference between the pixel driving circuit 20 of FIG. 8 and the pixel driving circuit 10 of FIG. 1 is that the pixel driving circuit 20 omits the sixth transistor and the seventh transistor.

FIG9 is a circuit diagram of a pixel driving circuit 30 according to an embodiment of the present invention. It should be noted that the embodiment of FIG9 uses the component numbers and some contents of the embodiments of FIG1 and FIG2, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

The main difference between the pixel driving circuit 30 of FIG9 and the pixel driving circuit 10 of FIG1 is that the pixel driving circuit 30 includes a plurality of sixth transistors T6-1, T6-2, T6-3 and seventh transistors T7-1, T7-2, T7-3. The first source/drain of the sixth transistors T6-1, T6-2, T6-3 is configured to receive the data line signal Data, and the gate of the sixth transistors T6-1, T6-2, T6-3 is configured to receive the test signal AT. The second source/drain of each of the sixth transistors T6-1, T6-2, and T6-3 is electrically connected to the first source/drain of a corresponding seventh transistor T7-1, T7-2, and T7-3, and the second source/drain of each of the seventh transistors T7-1, T7-2, and T7-3 is electrically connected to a corresponding light-emitting diode L1, L2, and L3, and the gate of each of the seventh transistors T7-1, T7-2, and T7-3 is electrically connected to a corresponding light-emitting control line.

In this embodiment, the sixth transistor T6-1 and the seventh transistor T7-1 are used to detect the light-emitting diode L1, wherein the gate of the seventh transistor T7-1 is configured to receive the control signal EM1[n]. The sixth transistor T6-2 and the seventh transistor T7-2 are used to detect the light-emitting diode L2, wherein the gate of the seventh transistor T7-2 is configured to receive the control signal EM2[n], and the sixth transistor T6-3 and the seventh transistor T7-3 are used to detect the light-emitting diode L3, wherein the gate of the seventh transistor T7-3 is configured to receive the control signal EM3[n]. In this embodiment, the sixth transistor T6-1, T6-2, T6-3 and the seventh transistor T7-1, T7-2, T7-3 can be used to test the light-emitting diodes L1, L2, L3, thereby improving the yield of the display device.

In summary, in the same pixel driving circuit, different light-emitting diodes can share the first transistor, the second transistor, the third transistor and the storage capacitor, thereby reducing the area occupied by the wiring and increasing the pixel opening rate.

10, 20, 30: pixel drive circuit AT: test signal ATL: test signal line B1, B2, B3, B4, B5, B6, G1, G2, G3, G4, G5, G6, R1, R2, R3, R4, R5, R6: grayscale signal C: storage capacitor D1: first direction D2: second direction DL: data line Data: data line signal E1: first end E2: second end F: frame EM1, EM2, EM3: light control line EM1[n], EM2[n], EM3[n], EM1[1], EM2[1], EM3[1], EM1[2], EM2[2], EM3[2], EM1[3], EM2[3], EM3[3], EM1[4], EM2[4], EM3[4], EM1[5], EM2[5], EM3[5], EM1[6], EM2[6], EM3[6]: control signal EMB1, EMB2, EMB3, EMB4, EMB5, EMB6, EMG1, EMG2, EMG3, EMG4, EMG5, EMG6, EMR1, EMR2, EMR3, EMR4, EMR5, EMR6: time period G: gate L1, L2, L3: light-emitting diode ND1: first node ND2: second node ND3: third node SD1: first source/drain SD2: second source/drain SL: scan line SN[n]: Scan line signal T1: First transistor T2: Second transistor T3: Third transistor T4-1, T4-2, T4-3: Fourth transistor T5-1, T5-2, T5-3: Fifth transistor T6, T6-1, T6-2, T6-3: Sixth transistor T7, T7-1, T7-2, T7-3: Seventh transistor Vdd: First operating voltage signal Vini: Initial voltage signal VL: Initial voltage signal line Vss: Second operating voltage signal

FIG. 1 is a circuit diagram of a pixel driving circuit according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a top view of a pixel driving circuit according to an embodiment of the present invention. FIG. 3A to FIG. 3D are circuit diagrams of a driving method of a pixel driving circuit according to an embodiment of the present invention. FIG. 4 is a signal diagram of a driving method of a display device according to an embodiment of the present invention. FIG. 5A to FIG. 5C are top views of a display device driven according to the driving method of FIG. 4. FIG. 6 is a signal diagram of another driving method of a display device according to an embodiment of the present invention. FIG. 7A to FIG. 7C are top views of a display device driven according to the driving method of FIG. 6. FIG8 is a circuit diagram of a pixel driving circuit according to an embodiment of the present invention. FIG9 is a circuit diagram of a pixel driving circuit according to an embodiment of the present invention.

20: Pixel driver circuit

C: Storage capacitor

Data: Data line signal

EM1[n],EM2[n],EM3[n]: control signal

L1, L2, L3: LEDs

ND1: First Node

ND2: Second Node

ND3: Node 3

SN[n]: Scan line signal

T1: First transistor

T2: Second transistor

T3: The third transistor

T4-1, T4-2, T4-3: The fourth transistor

T5-1, T5-2, T5-3: The fifth transistor

Vdd: first working voltage signal

Vini: Initial voltage signal

Vss: Second working voltage signal

Claims (10)

A pixel driving circuit includes: a first transistor, wherein a first source/drain of the first transistor is configured to receive a data line signal; a second transistor, wherein a gate of the second transistor is electrically connected to a second source/drain of the first transistor; a third transistor, wherein the gate of the first transistor and the gate of the third transistor are configured to receive a scan line signal, and a first source/drain of the third transistor is electrically connected to a second source/drain of the first transistor; configured to receive an initial voltage signal; a storage capacitor including a first end and a second end, wherein the first end, the second source/drain of the first transistor and the gate of the second transistor are electrically connected to a first node, wherein the first transistor controls the first voltage signal of the first node in response to the scan line signal; a plurality of fourth transistors, wherein the first source/drain of each of the fourth transistors is electrically connected to each other and configured to When receiving a first working voltage signal, a second source/drain of each of the fourth transistors, a first source/drain of the second transistor, a second source/drain of the third transistor, and the second end of the storage capacitor are electrically connected to a second node, wherein the third transistor controls the second voltage signal of the second node in response to the scan line signal; a plurality of fifth transistors, each of which has a first source/drain electrically connected to each other. and electrically connected to the second transistor; a plurality of light-emitting control lines, wherein each of the light-emitting control lines is electrically connected to a gate of a corresponding one of the fourth transistors and a gate of a corresponding one of the fifth transistors, wherein the fourth transistors control the second voltage signal of the second node in response to control signals of the light-emitting control lines; and a plurality of light-emitting diodes, each electrically connected to a second source/drain of each of the fifth transistors. A pixel driving circuit as described in claim 1, wherein the light-emitting control lines include a red light-emitting control line, a green light-emitting control line, and a blue light-emitting control line, wherein the red light-emitting control line is electrically connected to the gate of one of the fourth transistors and the gate of one of the fifth transistors, the green light-emitting control line is electrically connected to the gate of another of the fourth transistors and the gate of another of the fifth transistors, and the blue light-emitting control line is electrically connected to the gate of another of the fourth transistors and the gate of another of the fifth transistors. A pixel driving circuit as described in claim 2, wherein the light-emitting diodes include a red light-emitting diode, a green light-emitting diode and a blue light-emitting diode, wherein the red light-emitting diode is electrically connected to a second source/drain of one of the fifth transistors, the green light-emitting diode is electrically connected to a second source/drain of another of the fifth transistors, and the blue light-emitting diode is electrically connected to a second source/drain of yet another of the fifth transistors. The pixel driving circuit as described in claim 1 further includes: a sixth transistor, wherein a first source/drain of the sixth transistor is configured to receive the data line signal, and a gate of the sixth transistor is configured to receive a test signal; and a seventh transistor, wherein a second source/drain of the sixth transistor is electrically connected to a first source/drain of the seventh transistor, and a second source/drain of the seventh transistor is electrically connected to a corresponding one of the light-emitting diodes, and a gate of the seventh transistor is electrically connected to a corresponding one of the light-emitting control lines. The pixel driving circuit as described in claim 1 further includes: a plurality of sixth transistors, wherein a first source/drain of the sixth transistors is configured to receive the data line signal, and the gate of the sixth transistors is configured to receive the test signal; and a plurality of seventh transistors, wherein a second source/drain of each of the sixth transistors is electrically connected to a first source/drain of a corresponding one of the seventh transistors, and a second source/drain of each of the seventh transistors is electrically connected to a corresponding one of the light-emitting diodes, and a gate of each of the seventh transistors is electrically connected to a corresponding one of the light-emitting control lines. The pixel driving circuit as described in claim 1 further includes: a data line configured to transmit the data line signal; an initial voltage signal line configured to transmit the initial voltage signal, wherein the data line and the initial voltage signal line extend along a first direction; a scan line configured to transmit the scan line signal, wherein the scan line and the light-emitting control lines extend along a second direction, and the first direction is not parallel to the second direction. A pixel driving circuit as described in claim 6, wherein the first transistor, the second transistor, the third transistor, the fourth transistors and the fifth transistors are located on the same side of the scanning line. A pixel driving circuit as described in claim 6, wherein the first transistor, the second transistor, the third transistor, the fourth transistors and the fifth transistors are located on the same side of the data line. A pixel driving circuit as described in claim 6, wherein the fourth transistors are aligned in the second direction, and the fifth transistors are aligned in the second direction. A pixel driving circuit as described in claim 6, wherein the fourth transistors are respectively aligned with the fifth transistors in the first direction.