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TWI857544B - Simulation method of digital circuit - Google Patents

Simulation method of digital circuit Download PDF

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TWI857544B
TWI857544B TW112112718A TW112112718A TWI857544B TW I857544 B TWI857544 B TW I857544B TW 112112718 A TW112112718 A TW 112112718A TW 112112718 A TW112112718 A TW 112112718A TW I857544 B TWI857544 B TW I857544B
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digital circuit
synthesizable
simulation
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TW202441404A (en
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曾星翰
陳勇仁
羅幼嵐
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瑞昱半導體股份有限公司
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Abstract

A simulation method of digital circuit includes: analyzing an initial digital circuit to find a plurality of unsynthesizable modules in the initial digital circuit; replacing multiple unsynthesizable modules in the initial digital circuit with multiple synthesizable modules to obtain a synthesizable digital circuit; performing loop detection on the synthesizable digital circuit to find out multiple loops inside the synthesizable digital circuit; setting a checking mechanism on the multiple loops to obtain a second synthesizable digital circuit; and simulating the second synthesizable digital circuit.

Description

數位電路的模擬方法Analog methods for digital circuits

本案是一種能找出電路內的所有迴圈，並在模擬時對迴圈做監控的模擬方法。This case is a simulation method that can find all loops in a circuit and monitor the loops during simulation.

在數位電路的模擬中，若有存在於電路內的迴圈，如：零延遲時鐘發生器、組合邏輯電路迴圈或傳輸閘迴圈於模擬時觸發，會導致模擬時間無法前進，進而使模擬失敗。對於這些存在於電路內的迴圈，通常會於模擬前使用商用的程式分析工具對於電路的程式碼進行分析，以找出這些迴圈。In the simulation of digital circuits, if there are loops in the circuit, such as zero-delay clock generators, combinational logic circuit loops, or transmission gate loops, which are triggered during simulation, the simulation time will not be able to advance, thus causing the simulation to fail. For these loops in the circuit, commercial program analysis tools are usually used to analyze the circuit code before simulation to find these loops.

然而，程式分析工具只能在可合成(synthesizable)之語法之電路程式碼找出迴圈，不能在不可合成(unsynthesizable)之語法之電路程式碼找出迴圈。因此，若迴圈出現於不可合成之語法之電路程式碼內部，程式分析工具便無法找出而遺漏掉這些位於不可合成之語法之電路程式碼內部之迴圈。且若迴圈於模擬時觸發，電路設計者並無法即時得知是電路中的哪一個迴圈觸發而花大量時間除錯而影響到驗證效率。However, program analysis tools can only find loops in circuit code with synthesizable syntax, but not in circuit code with unsynthesizable syntax. Therefore, if loops appear in circuit code with unsynthesizable syntax, program analysis tools cannot find them and miss them. Moreover, if loops are triggered during simulation, circuit designers cannot immediately know which loop in the circuit is triggered and spend a lot of time debugging, which affects verification efficiency.

在一實施例中，一種數位電路的模擬方法包含：解析初始數位電路，以找出初始數位電路內部之多個無法合成之模塊；將初始數位電路內部之多個無法合成之模塊取代為多個可合成之模塊，以取得可合成數位電路；對可合成數位電路進行迴圈檢測，以找出可合成數位電路內部之多個迴圈；設置檢查機制於多個迴圈，以取得第二可合成數位電路；及對第二可合成數位電路進行模擬。In one embodiment, a simulation method for a digital circuit includes: analyzing an initial digital circuit to find multiple modules that cannot be synthesized within the initial digital circuit; replacing the multiple modules that cannot be synthesized within the initial digital circuit with multiple synthesizable modules to obtain a synthesizable digital circuit; performing loop detection on the synthesizable digital circuit to find multiple loops within the synthesizable digital circuit; setting a check mechanism on multiple loops to obtain a second synthesizable digital circuit; and simulating the second synthesizable digital circuit.

在一實施例中，一種數位電路的模擬方法包含：解析初始數位電路，以找出初始數位電路內部之多個無法合成之模塊；移除初始數位電路內部之多個無法合成之模塊，以取得可合成數位電路；對可合成數位電路進行迴圈檢測，以找出可合成數位電路內部之多個迴圈；設置檢查機制於多個迴圈，以取得第二可合成數位電路；及對第二可合成數位電路進行模擬。In one embodiment, a simulation method for a digital circuit includes: analyzing an initial digital circuit to find multiple modules that cannot be synthesized within the initial digital circuit; removing multiple modules that cannot be synthesized within the initial digital circuit to obtain a synthesizable digital circuit; performing loop detection on the synthesizable digital circuit to find multiple loops within the synthesizable digital circuit; setting a check mechanism on multiple loops to obtain a second synthesizable digital circuit; and simulating the second synthesizable digital circuit.

在一實施例中，一種數位電路的模擬方法包含：解析初始數位電路，以找出初始數位電路內部之多個無法合成之模塊；將初始數位電路內部之多個無法合成之模塊取代為多個可合成之模塊，以取得可合成數位電路；對可合成數位電路進行迴圈檢測，以找出可合成數位電路內部之多個迴圈；移除多個迴圈，以取得第二可合成數位電路；及對第二可合成數位電路進行模擬。In one embodiment, a simulation method for a digital circuit includes: analyzing an initial digital circuit to find multiple modules that cannot be synthesized within the initial digital circuit; replacing the multiple modules that cannot be synthesized within the initial digital circuit with multiple synthesizable modules to obtain a synthesizable digital circuit; performing loop detection on the synthesizable digital circuit to find multiple loops within the synthesizable digital circuit; removing multiple loops to obtain a second synthesizable digital circuit; and simulating the second synthesizable digital circuit.

在一實施例中，一種數位電路的模擬方法包含：解析初始數位電路，以找出初始數位電路內部之多個無法合成之模塊；移除初始數位電路內部之多個無法合成之模塊，以取得可合成數位電路；對可合成數位電路進行迴圈檢測，以找出可合成數位電路內部之多個迴圈；移除多個迴圈，以取得第二可合成數位電路；及對第二可合成數位電路進行模擬。In one embodiment, a simulation method for a digital circuit includes: analyzing an initial digital circuit to find multiple modules that cannot be synthesized within the initial digital circuit; removing multiple modules that cannot be synthesized within the initial digital circuit to obtain a synthesizable digital circuit; performing loop detection on the synthesizable digital circuit to find multiple loops within the synthesizable digital circuit; removing multiple loops to obtain a second synthesizable digital circuit; and simulating the second synthesizable digital circuit.

在一實施例中，一種數位電路的模擬裝置包含電路解析模組、電路修改模組、迴圈檢測模組、檢查設置模組及模擬模組。電路解析模組用以解析初始數位電路，以找出初始數位電路內部之多個無法合成之模塊。電路修改模組用以將初始數位電路內部之多個無法合成之模塊取代為多個可合成之模塊，以取得可合成數位電路。迴圈檢測模組用以對可合成數位電路進行迴圈檢測，以找出可合成數位電路內部之多個迴圈。檢查設置模組用以設置檢查機制於多個迴圈，以取得第二可合成數位電路。模擬模組用以對第二可合成數位電路進行模擬。In one embodiment, a simulation device for a digital circuit includes a circuit analysis module, a circuit modification module, a loop detection module, a check setting module, and a simulation module. The circuit analysis module is used to analyze the initial digital circuit to find out multiple modules that cannot be synthesized inside the initial digital circuit. The circuit modification module is used to replace multiple modules that cannot be synthesized inside the initial digital circuit with multiple synthesizable modules to obtain a synthesizable digital circuit. The loop detection module is used to perform loop detection on the synthesizable digital circuit to find out multiple loops inside the synthesizable digital circuit. The check setting module is used to set a check mechanism on multiple loops to obtain a second synthesizable digital circuit. The simulation module is used to simulate the second synthesizable digital circuit.

以下在實施方式中詳細敘述本案之詳細特徵以及優點，其內容足以使任何熟習相關技藝者瞭解本案之技術內容並據以實施，且根據本說明書所揭露之內容、申請專利範圍及圖式，任何熟習相關技藝者可輕易地理解本案相關之目的及優點。The detailed features and advantages of the present invention are described in detail in the following implementation method, and the content is sufficient for anyone familiar with the relevant technology to understand the technical content of the present invention and implement it accordingly. Moreover, according to the content disclosed in this specification, the scope of the patent application and the drawings, anyone familiar with the relevant technology can easily understand the relevant purposes and advantages of the present invention.

圖1為數位電路的模擬裝置1之一實施例的方塊示意圖。圖2為數位電路的模擬方法之一實施例之流程圖。請參閱圖1及圖2。數位電路的模擬裝置1包含電路解析模組10、電路修改模組20、迴圈檢測模組30、檢查設置模組40及模擬模組50。FIG1 is a block diagram of an embodiment of a simulation device 1 for a digital circuit. FIG2 is a flow chart of an embodiment of a simulation method for a digital circuit. Please refer to FIG1 and FIG2. The simulation device 1 for a digital circuit includes a circuit analysis module 10, a circuit modification module 20, a loop detection module 30, a check setting module 40 and a simulation module 50.

電路解析模組10用以解析初始數位電路CI，以找出初始數位電路CI內部之多個無法合成之模塊(步驟S11)。在一些實施例中，解析初始數位電路CI，以找出初始數位電路CI內部之多個無法合成之模塊，可為但不限於，在初始數位電路CI之程式碼內搜尋僅會出現於多個無法合成之模塊之多個關鍵字。在一些實施例中，在初始數位電路CI之程式碼內搜尋僅會出現於多個無法合成之模塊之多個關鍵字，可為但不限於，在初始數位電路CI之程式碼內搜尋資料狀態為實數(real)的變數、硬體描述語言內部之原語(primitive)、硬體描述語言內部之單元(cell)、邊緣觸發和非邊緣觸發同時存在之區塊(block)或冪運算運算子(**)。在一些實施例中，初始數位電路CI內部之多個無法合成之模塊可為但不限於類比電路。The circuit analysis module 10 is used to analyze the initial digital circuit CI to find out a plurality of modules that cannot be synthesized in the initial digital circuit CI (step S11). In some embodiments, the initial digital circuit CI is analyzed to find out a plurality of modules that cannot be synthesized in the initial digital circuit CI, which may be, but is not limited to, searching for a plurality of keywords that only appear in a plurality of modules that cannot be synthesized in the program code of the initial digital circuit CI. In some embodiments, searching for multiple keywords that only appear in multiple modules that cannot be synthesized in the program code of the initial digital circuit CI may include, but is not limited to, searching for variables whose data states are real numbers, primitives in the hardware description language, cells in the hardware description language, blocks that are both edge-triggered and non-edge-triggered, or arithmetical operators in the program code of the initial digital circuit CI. In some embodiments, multiple modules that cannot be synthesized in the initial digital circuit CI may be, but are not limited to, analog circuits.

電路修改模組20用以將初始數位電路CI內部之多個無法合成之模塊取代為多個可合成之模塊，以取得可合成數位電路C1(步驟S12)。在一些實施例中，將初始數位電路CI內部之多個無法合成之模塊取代為多個可合成之模塊，以取得可合成數位電路C1，可為但不限於，在電路解析模組10搜尋到初始數位電路CI之程式碼內僅會出現於多個無法合成之模塊之多個關鍵字時，將多個關鍵字所在之程式碼修改為可合成之程式碼。在一些實施例中，在搜尋到初始數位電路CI之程式碼內僅會出現於多個無法合成之模塊之多個關鍵字時，將多個關鍵字所在之程式碼修改為可合成之程式碼，可為但不限於，將資料狀態為實數的變數修改為資料狀態為整數(integer)的變數、將硬體描述語言內部之原語或硬體描述語言內部之單元修改為可合成之程式碼、將邊緣觸發和非邊緣觸發同時存在之區塊修改為僅存在邊緣觸發之區塊或僅存在非邊緣觸發之區塊或將冪運算運算子修改為加法運算子(+)。The circuit modification module 20 is used to replace the multiple modules that cannot be synthesized in the initial digital circuit CI with multiple modules that can be synthesized to obtain the synthesizable digital circuit C1 (step S12). In some embodiments, the multiple modules that cannot be synthesized in the initial digital circuit CI are replaced with multiple modules that can be synthesized to obtain the synthesizable digital circuit C1. It can be, but is not limited to, when the circuit analysis module 10 searches for multiple keywords that only appear in the multiple modules that cannot be synthesized in the program code of the initial digital circuit CI, the program code where the multiple keywords are located is modified to a synthesizable program code. In some embodiments, when multiple keywords that only appear in multiple modules that cannot be synthesized are found in the program code of the initial digital circuit CI, the program code where the multiple keywords are located is modified into a synthesizable code, which may be, but is not limited to, modifying a variable whose data state is a real number to a variable whose data state is an integer, modifying the primitives within the hardware description language or the units within the hardware description language to a synthesizable code, modifying a block where edge triggers and non-edge triggers exist at the same time to a block where only edge triggers exist or a block where only non-edge triggers exist, or modifying an addition operator to an addition operator (+).

迴圈檢測模組30用以對可合成數位電路C1進行迴圈檢測，以找出可合成數位電路C1內部之多個迴圈(步驟S13)。在一些實施例中，對可合成數位電路C1進行迴圈檢測，以找出可合成數位電路C1內部之多個迴圈，可為但不限於，透過程式分析工具分析可合成數位電路C1之程式碼。在一些實施例中，程式分析工具可為但不限於SpyGlass。The loop detection module 30 is used to perform loop detection on the synthesizable digital circuit C1 to find multiple loops inside the synthesizable digital circuit C1 (step S13). In some embodiments, the loop detection is performed on the synthesizable digital circuit C1 to find multiple loops inside the synthesizable digital circuit C1, which can be, but is not limited to, analyzing the program code of the synthesizable digital circuit C1 through a program analysis tool. In some embodiments, the program analysis tool can be, but is not limited to, SpyGlass.

檢查設置模組40用以設置檢查機制於可合成數位電路C1內部之多個迴圈，以取得第二可合成數位電路C2(步驟S14)。在一些實施例中，設置檢查機制於可合成數位電路C1內部之多個迴圈，以取得第二可合成數位電路C2，可為但不限於，在多個迴圈內部加入檢查訊號，並於觸發迴圈時對檢查訊號之切換(toggle)次數進行偵測，且當檢查訊號之切換次數大於閾值時，顯示警告訊息並暫停模擬。在一些實施例中，閾值可為但不限於10000。在一些實施例中，警告訊息會顯示檢查訊號或迴圈之名稱及模擬時間使電路設計者得知因哪個迴圈導致模擬暫停。The check setting module 40 is used to set the check mechanism in multiple loops inside the synthesizable digital circuit C1 to obtain the second synthesizable digital circuit C2 (step S14). In some embodiments, the check mechanism is set in multiple loops inside the synthesizable digital circuit C1 to obtain the second synthesizable digital circuit C2, which can be, but not limited to, adding a check signal inside the multiple loops, and detecting the toggle times of the check signal when the loop is triggered, and when the toggle times of the check signal is greater than a threshold, displaying a warning message and pausing the simulation. In some embodiments, the threshold can be, but not limited to, 10000. In some embodiments, the warning message displays the name of the check signal or loop and the simulation time so that the circuit designer knows which loop caused the simulation to pause.

模擬模組50用以對第二可合成數位電路C2進行模擬(步驟S15)。當對第二可合成數位電路C2進行模擬時觸發多個迴圈之一時，模擬模組50執行檢查設置模組40所設置之檢查機制。換言之，於模擬時若觸發多個迴圈之一時，模擬模組50即開始對檢查訊號之切換次數進行偵測，且當檢查訊號之切換次數大於閾值時顯示警告訊息並暫停模擬。舉例而言，若閾值為10000，當模擬時多個迴圈之一遭觸發，模擬模組50即對遭觸發之迴圈內部之檢查訊號進行切換次數之偵測，當切換次數大於10000時，模擬模組50即顯示警告訊息並暫停模擬。在一些實施例中，於顯示警告訊息並暫停模擬時，電路設計者可依據警告訊息所顯示之資訊對特定訊號賦予固定值並繼續模擬。在一些實施例中，於顯示警告訊息並暫停模擬時，電路設計者可依據警告訊息所顯示之資訊停止模擬。The simulation module 50 is used to simulate the second synthesizable digital circuit C2 (step S15). When one of the multiple loops is triggered during the simulation of the second synthesizable digital circuit C2, the simulation module 50 executes the check mechanism set by the check setting module 40. In other words, when one of the multiple loops is triggered during the simulation, the simulation module 50 starts to detect the switching times of the check signal, and when the switching times of the check signal is greater than the threshold, a warning message is displayed and the simulation is suspended. For example, if the threshold is 10000, when one of the multiple loops is triggered during simulation, the simulation module 50 detects the number of switching times of the check signal inside the triggered loop. When the number of switching times is greater than 10000, the simulation module 50 displays a warning message and suspends the simulation. In some embodiments, when the warning message is displayed and the simulation is suspended, the circuit designer can assign a fixed value to a specific signal according to the information displayed in the warning message and continue the simulation. In some embodiments, when the warning message is displayed and the simulation is suspended, the circuit designer can stop the simulation according to the information displayed in the warning message.

圖3為數位電路的模擬方法之另一實施例之流程圖。請參閱圖1及圖3。在一些實施例中，電路修改模組20移除初始數位電路CI內部之多個無法合成之模塊，以取得可合成數位電路C1(步驟S22)。在一些實施例中，移除初始數位電路CI內部之多個無法合成之模塊，以取得可合成數位電路C1，可為但不限於在搜尋到初始數位電路CI之程式碼內僅會出現於多個無法合成之模塊之多個關鍵字後，將多個關鍵字所在之模塊之程式碼刪除。FIG3 is a flow chart of another embodiment of the simulation method of the digital circuit. Please refer to FIG1 and FIG3. In some embodiments, the circuit modification module 20 removes multiple modules that cannot be synthesized in the initial digital circuit CI to obtain a synthesizable digital circuit C1 (step S22). In some embodiments, removing multiple modules that cannot be synthesized in the initial digital circuit CI to obtain the synthesizable digital circuit C1 may be, but is not limited to, after searching for multiple keywords that only appear in multiple modules that cannot be synthesized in the program code of the initial digital circuit CI, deleting the program code of the module where the multiple keywords are located.

圖4為數位電路的模擬方法之又一實施例之流程圖。請參閱圖1及圖4。在一些實施例中，檢查設置模組40移除可合成數位電路C1內部之多個迴圈，以取得第二可合成數位電路C2(步驟S24)。在一些實施例中，移除可合成數位電路C1內部之多個迴圈，可為但不限於，在透過程式分析工具分析可合成數位電路C1之程式碼，以找出可合成數位電路C1內部之多個迴圈後，將多個迴圈之程式碼刪除。FIG4 is a flow chart of another embodiment of the digital circuit simulation method. Please refer to FIG1 and FIG4. In some embodiments, the check setting module 40 removes multiple loops in the synthesizable digital circuit C1 to obtain the second synthesizable digital circuit C2 (step S24). In some embodiments, removing multiple loops in the synthesizable digital circuit C1 can be, but is not limited to, analyzing the program code of the synthesizable digital circuit C1 through a program analysis tool to find multiple loops in the synthesizable digital circuit C1, and then deleting the program code of the multiple loops.

圖5為數位電路的模擬方法之再一實施例之流程圖。請參閱圖1及圖5。在一些實施例中，電路修改模組20移除初始數位電路CI內部之多個無法合成之模塊，以取得可合成數位電路C1(步驟S22)且檢查設置模組40移除可合成數位電路C1內部之多個迴圈，以取得第二可合成數位電路C2(步驟S24)。FIG5 is a flow chart of another embodiment of the simulation method of the digital circuit. Please refer to FIG1 and FIG5. In some embodiments, the circuit modification module 20 removes multiple unsynthesizable modules in the initial digital circuit CI to obtain a synthesizable digital circuit C1 (step S22) and the check setting module 40 removes multiple loops in the synthesizable digital circuit C1 to obtain a second synthesizable digital circuit C2 (step S24).

在一些實施例中，前述電路解析模組10、電路修改模組20、迴圈檢測模組30、檢查設置模組40及模擬模組50係可由一個或多個處理單元實現。其中，處理單元可以是微處理器、微控制器、數位信號處理器、中央處理器、可編程邏輯控制器、狀態器或任何基於操作指令操作信號的類比和/或數位裝置，在此並不限制處理單元的種類。In some embodiments, the aforementioned circuit analysis module 10, circuit modification module 20, loop detection module 30, check setting module 40 and simulation module 50 can be implemented by one or more processing units. The processing unit can be a microprocessor, a microcontroller, a digital signal processor, a central processing unit, a programmable logic controller, a state machine or any analog and/or digital device based on an operation instruction operation signal, and the type of the processing unit is not limited here.

綜上所述，在一些實施例中，數位電路的模擬裝置1透過電路解析模組10及電路修改模組20將初始數位電路CI內部之多個無法合成之模塊取代為多個可合成之模塊，使程式分析工具能完整找出初始數位電路CI之所有迴圈，而不會遺漏掉設置於初始數位電路CI中不可合成之語法之電路程式碼內部之迴圈。且透過檢查設置模組40設置檢查機制於可合成數位電路C1內部之多個迴圈，可使電路設計者於模擬中迴圈觸發時能即時得知是電路中的哪一個迴圈觸發而不需花大量時間除錯，進而大幅提升驗證效率。In summary, in some embodiments, the simulation device 1 of the digital circuit replaces multiple unsynthesizable modules in the initial digital circuit CI with multiple synthesizable modules through the circuit analysis module 10 and the circuit modification module 20, so that the program analysis tool can completely find all loops of the initial digital circuit CI without missing loops in the circuit code of the unsynthesizable syntax set in the initial digital circuit CI. And by setting the check mechanism in multiple loops in the synthesizable digital circuit C1 through the check setting module 40, the circuit designer can immediately know which loop in the circuit is triggered when the loop is triggered in the simulation without spending a lot of time debugging, thereby greatly improving the verification efficiency.

雖然本案的技術內容已經以較佳實施例揭露如上，然其並非用以限定本案，任何熟習此技藝者，在不脫離本案之精神所作些許之更動與潤飾，皆應涵蓋於本案的範疇內，因此本案之保護範圍當視後附之申請專利範圍所界定者為準。Although the technical content of this case has been disclosed as above with the preferred embodiment, it is not used to limit this case. Any slight changes and embellishments made by anyone familiar with this technology without departing from the spirit of this case should be included in the scope of this case. Therefore, the protection scope of this case shall be defined by the scope of the attached patent application.

1:數位電路的模擬裝置 10:電路解析模組 20:電路修改模組 30:迴圈檢測模組 40:檢查設置模組 50:模擬模組 CI:初始數位電路 C1:可合成數位電路 C2:第二可合成數位電路 S11~S15:步驟 S22:步驟 S24:步驟1: Digital circuit simulation device 10: Circuit analysis module 20: Circuit modification module 30: Loop detection module 40: Inspection setting module 50: Simulation module CI: Initial digital circuit C1: Synthesizable digital circuit C2: Second synthesizable digital circuit S11~S15: Steps S22: Steps S24: Steps

圖1為數位電路的模擬裝置之一實施例的方塊示意圖。 圖2為數位電路的模擬方法之一實施例之流程圖。 圖3為數位電路的模擬方法之另一實施例之流程圖。 圖4為數位電路的模擬方法之又一實施例之流程圖。 圖5為數位電路的模擬方法之再一實施例之流程圖。 FIG1 is a block diagram of an embodiment of a simulation device for a digital circuit. FIG2 is a flow chart of an embodiment of a simulation method for a digital circuit. FIG3 is a flow chart of another embodiment of a simulation method for a digital circuit. FIG4 is a flow chart of another embodiment of a simulation method for a digital circuit. FIG5 is a flow chart of another embodiment of a simulation method for a digital circuit.

1:數位電路的模擬裝置 1: Analog device for digital circuits

10:電路解析模組 10: Circuit analysis module

20:電路修改模組 20: Circuit modification module

30:迴圈檢測模組 30: Loop detection module

40:檢查設置模組 40: Check the settings module

50:模擬模組 50:Simulation module

CI:初始數位電路 CI: Initial digital circuit

C1:可合成數位電路 C1: can synthesize digital circuits

C2:第二可合成數位電路 C2: The second synthesizable digital circuit

Claims (10)

一種數位電路的模擬方法，包含： 解析一初始數位電路，以找出該初始數位電路內部之多個無法合成之模塊； 將該初始數位電路內部之該些無法合成之模塊取代為多個可合成之模塊，以取得一可合成數位電路； 對該可合成數位電路進行迴圈檢測，以找出該可合成數位電路內部之多個迴圈； 設置一檢查機制於該些迴圈，以取得一第二可合成數位電路；及 對該第二可合成數位電路進行模擬。 A method for simulating a digital circuit includes: Analyzing an initial digital circuit to find out multiple modules that cannot be synthesized in the initial digital circuit; Replacing the modules that cannot be synthesized in the initial digital circuit with multiple modules that can be synthesized to obtain a synthesizable digital circuit; Performing loop detection on the synthesizable digital circuit to find out multiple loops in the synthesizable digital circuit; Setting a check mechanism on the loops to obtain a second synthesizable digital circuit; and Simulating the second synthesizable digital circuit. 如請求項1所述之數位電路的模擬方法，在對該第二可合成數位電路進行模擬後，更包含： 當模擬時觸發該些迴圈之一時，執行該檢查機制。 The digital circuit simulation method as described in claim 1, after simulating the second synthesizable digital circuit, further includes: When one of the loops is triggered during simulation, the checking mechanism is executed. 如請求項2所述之數位電路的模擬方法，其中該檢查機制包含： 顯示警告訊息；及 暫停模擬。 A method for simulating a digital circuit as described in claim 2, wherein the checking mechanism comprises: displaying a warning message; and pausing the simulation. 如請求項3所述之數位電路的模擬方法，其中解析該初始數位電路的步驟包含： 於該初始數位電路之程式碼內搜尋僅會出現於該些無法合成之模塊之多個關鍵字。 A method for simulating a digital circuit as described in claim 3, wherein the step of parsing the initial digital circuit includes: Searching the program code of the initial digital circuit for multiple keywords that only appear in those modules that cannot be synthesized. 如請求項4所述之數位電路的模擬方法，其中將該初始數位電路內部之該些無法合成之模塊取代為該些可合成之模塊的步驟包含： 於搜尋到該些關鍵字時，將該些關鍵字所在之程式碼修改為可合成之程式碼。 The digital circuit simulation method as described in claim 4, wherein the step of replacing the modules that cannot be synthesized in the initial digital circuit with the modules that can be synthesized includes: When the keywords are searched, the program code where the keywords are located is modified to a synthesizable program code. 如請求項5所述之數位電路的模擬方法，其中對該可合成數位電路進行迴圈檢測的步驟包含： 透過一程式分析工具分析該可合成數位電路之程式碼。 A method for simulating a digital circuit as described in claim 5, wherein the step of performing loop detection on the synthesizable digital circuit comprises: Analyzing the program code of the synthesizable digital circuit by a program analysis tool. 一種數位電路的模擬方法，包含： 解析一初始數位電路，以找出該初始數位電路內部之多個無法合成之模塊； 移除該初始數位電路內部之該些無法合成之模塊，以取得一可合成數位電路； 對該可合成數位電路進行迴圈檢測，以找出該可合成數位電路內部之多個迴圈； 設置一檢查機制於該些迴圈，以取得一第二可合成數位電路；及 對該第二可合成數位電路進行模擬。 A method for simulating a digital circuit includes: Analyzing an initial digital circuit to find out multiple modules that cannot be synthesized in the initial digital circuit; Removing the modules that cannot be synthesized in the initial digital circuit to obtain a synthesizable digital circuit; Performing loop detection on the synthesizable digital circuit to find out multiple loops in the synthesizable digital circuit; Setting a check mechanism on the loops to obtain a second synthesizable digital circuit; and Simulating the second synthesizable digital circuit. 如請求項7所述之數位電路的模擬方法，在對該第二可合成數位電路進行模擬後，更包含： 當模擬時觸發該些迴圈之一時，執行該檢查機制。 The digital circuit simulation method as described in claim 7, after simulating the second synthesizable digital circuit, further comprises: When one of the loops is triggered during simulation, the checking mechanism is executed. 如請求項8所述之數位電路的模擬方法，其中該檢查機制包含： 顯示警告訊息；及 暫停模擬。 A method for simulating a digital circuit as described in claim 8, wherein the checking mechanism comprises: displaying a warning message; and pausing the simulation. 如請求項9所述之數位電路的模擬方法，其中解析該初始數位電路的步驟包含： 於該初始數位電路之程式碼內搜尋僅會出現於該些無法合成之模塊之多個關鍵字。 A method for simulating a digital circuit as described in claim 9, wherein the step of parsing the initial digital circuit includes: Searching the program code of the initial digital circuit for multiple keywords that only appear in those modules that cannot be synthesized.
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