TWI856865B - Embedded thermal and electrical separation circuit board with ceramic substrate and power transistor - Google Patents

Abstract

The present invention is an embedded thermoelectric separation circuit board with a ceramic substrate and a power transistor, which mainly includes: a dielectric material layer, a heat dissipation ceramic block, a fixing portion, a stepped metal electrode layer, a power transistor and a dielectric material package, wherein the dielectric material layer is formed with through holes, and the heat dissipation ceramic block is embedded in the through holes. The thermal conductivity of the heat dissipation ceramic block is higher than that of the dielectric material layer, and the thickness is thinner than that of the dielectric material layer. Material layer, stepped metal electrode layer, conductive and heat-conducting power transistor, the source pin, collector pin and gate pin of the stepped metal electrode layer are partially exposed after being encapsulated by dielectric material. By changing the thickness of the heat dissipation ceramic block and directly burying the power transistor, not only the overall thermal conductivity is improved, but also the overall thickness is thinner, while maintaining the required thermal and electrical separation function.

Description

Embedded thermal and electrical separation circuit board with ceramic substrate and power transistor

The present invention relates to a printed circuit board, in particular to an embedded thermoelectric separation circuit board with a ceramic substrate and a power transistor.

According to the PCB, the copper foil substrate is used as the main key base material for installing electronic components. The copper foil substrate generally uses dielectric materials as the insulating layer, and the wires formed by the copper foil are used as the conductive material layer, and the conductive material layer is arranged on the dielectric insulating layer. The dielectric material is mainly formed by resin impregnation of paper, bakelite, fiberglass, rubber and other types of polymers. For the convenience of subsequent explanation, this case refers to the insulating layer of the copper foil substrate as the dielectric material layer.

With the increasingly complex and diversified demands for circuit design, the structure of printed circuit boards has gradually evolved from single-layer PCBs to double-layer PCBs to multi-layer PCBs. Currently, multi-layer printed circuit boards use multiple layers of dielectric material layers and conductive material layers to form more complex and diverse circuits, and by forming through holes in the dielectric material layer and forming plugs with conductive materials, the wires of each layer between the multi-layer boards are connected to achieve the purpose of allowing more electronic components to be accommodated in a smaller footprint. Common FR-4, FR-5, FR-6, FR-7, etc. on the market are all commonly used materials for multi-layer PCBs.

As electronic devices continue to miniaturize, electronic components with specific needs are moving towards higher power, which results in higher heat generation in a smaller space. In particular, the wire spacing and wire diameter of the wires are shrinking. For example, on substrate materials based on bakelite and fiberglass, the circuit spacing can be reduced to about 50 microns (μm), which makes the problem of high temperature in the circuit field more serious.

In order to improve the heat dissipation efficiency, the following methods are commonly used: First, the heat energy generated by general electronic components is diffused to the air and environment around the printed circuit board through thermal convection or thermal radiation, but the heat dissipation efficiency of this method is not high; second, it is conducted through metal wires or heat sinks with better thermal conductivity. Although this type of structure has better heat dissipation effect than simple dielectric materials, the wire diameter of the metal wire is not large, so the heat dissipation efficiency of this path is not high; and the heat sink usually needs to be fixed to the printed circuit board through materials such as thermal conductive glue, but the thermal conductivity of the thermal conductive glue itself is much lower than that of metal. Therefore, even if a fan is installed at the far end of the heat sink away from the heat-generating electronic components, the heat conduction effect of the heat sink will be greatly reduced.

The most commonly used solution is to use ceramic materials as the insulating material layer of the circuit substrate. The most common ceramic material is the direct bonded copper (DBC) substrate made of aluminum oxide (Aluminum Oxide, Al2O3). The thermal conductivity of aluminum oxide can reach 35Wm-1K-1 under the single crystal structure, and 20 to 27Wm-1K-1 under the polycrystalline structure. Other common ceramic material substrates include aluminum nitride (AlN), beryllium oxide (BeO) and silicon carbide (SiC). Since the above ceramic materials with good thermal conductivity are often used in circuit substrates with high-power electronic components, this type of substrate is sometimes called a high-power printed circuit substrate (Power Electronic Substrate).

However, in practice, if you want to use a printed circuit board made of a ceramic substrate, although the diameter of the circuit wire can be as thin as 30 microns (μm), it is usually fired at a high temperature. During the process, on the one hand, it will cause a small amount of uneven expansion and warping, so the precision of the substrate is not as good as that of a printed circuit board and is not suitable for manufacturing multi-layer boards; on the other hand, the metal atoms that constitute the circuit are easily dispersed during the high-temperature process, so the wire spacing must be maintained at about 80 microns (μm). Therefore, in addition to increasing costs, using ceramic substrates to make printed circuit boards will also cause the width and spacing of the wires to be unable to be reduced, and the accuracy of the wire line position will be a problem, making it impossible to miniaturize the size of electronic devices that use a whole piece of ceramic substrate.

Therefore, for high-heat electronic components, the applicant's invention patents No. I670998 and I690246 have disclosed that a printed circuit substrate is pre-perforated, and then a ceramic block with a size corresponding to the high-power component is embedded in the perforated hole and the printed circuit board and the heat dissipation ceramic block are aligned. The high-power electronic component is set on the embedded heat dissipation ceramic block, so that the high heat of the high-power component can be transferred from the bottom of the embedded block. On the other hand, the printed circuit board next to it can meet the complex circuit connection requirements. The two have their own functions, providing the technical effects of heat conduction and good electrical signal connection respectively. However, with the increasing power consumption of electric vehicles and computers and the market demand for miniaturization of circuits, how to further improve and optimize the existing invention solutions that have been working well in terms of heat dissipation effect and component area has become the target to be solved by this invention.

In addition, the above invention owned by the applicant uses this type of high-heat electronic components, such as high-power components (IGBT), although they are soldered and fixed to the pads above the heat dissipation ceramic block by surface-mount technology (SMT), but the electrodes of the IGBT must still be connected to the corresponding pads on the external printed circuit board at least partially through metal leads. In particular, once aluminum bars are used to conduct high currents of several amperes or even tens of amperes, it is necessary to rely on pressure welding with ultrasonic probes, which increases the complexity of the processing flow; if the guiding pads can be designed to have a larger conducting area and be completely exposed metal pads, it will be easier to operate during circuit design and manufacturing.

The detailed features and advantages of the present invention are described in detail in the following implementation method. The content is sufficient for anyone familiar with the relevant technology to understand the technical content of the present invention and implement it accordingly. According to the content disclosed in this specification, the scope of the patent application and the drawings, anyone familiar with the relevant technology can easily understand the relevant purposes and advantages of the present invention.

The main purpose of the present invention is to provide an embedded thermoelectric separation circuit board with a ceramic substrate and power transistors, which embeds high-power components and heat dissipation ceramic blocks together in the printed circuit board. As the thickness of the heat dissipation ceramic block becomes thinner, the overall thermal conductivity efficiency is effectively improved.

Another purpose of the present invention is to provide an embedded thermoelectric separation circuit board with a ceramic substrate and power transistors, so that high-power components can be directly embedded in the circuit board, greatly improving the space utilization of the circuit board and facilitating miniaturization.

Another purpose of the present invention is to provide an embedded thermal and electrical separation circuit board with a ceramic substrate and a power transistor, and to expose the corresponding pins of the source, collector and gate of the embedded power transistor to the side of the circuit board opposite to the ceramic block, thereby further improving the effects of heat conduction and circuit separation.

Another object of the present invention is to provide an embedded thermoelectric separation circuit board with a ceramic substrate and a power transistor, which makes the circuit design convenient and reliable through the exposed lead-out portion.

To achieve the above-mentioned purpose, the present invention is an embedded thermoelectric separation circuit board with a ceramic substrate and a power transistor, comprising: a dielectric material layer, including a first upper plate surface and a first lower plate surface opposite to the first upper plate surface, and the dielectric material layer is formed with at least one through hole penetrating the first upper plate surface and the first lower plate surface; at least one heat dissipation ceramic block corresponding to the through hole is embedded in the through hole, including a second upper plate surface and a second lower plate surface, and the heat dissipation ceramic block is The thermal conductivity coefficient of the heat dissipation ceramic block is higher than that of the dielectric material layer, and the thickness of the heat dissipation ceramic block is thinner than that of the dielectric material layer; at least one fixing portion for embedding and fixing the heat dissipation ceramic block in the through hole of the dielectric material layer, so that the second lower plate surface corresponds to the first lower plate surface; a stepped metal electrode layer disposed on the second upper plate surface for heat conduction, including at least one source pin or one collector pin, the source pin or the collector pin is divided into a thin pad portion and a thin pad portion extending from the first lower plate surface; A source or collector lead-out portion of the thin pad portion; a power transistor electrically and thermally mounted on the stepped metal electrode layer, the transistor having at least one source, a gate and a collector, wherein the source or collector is electrically connected to the source or collector pin; at least two collector or source pins electrically connected to the other of the source or the collector, and a gate pin electrically connected to the gate, wherein the collector or source pin and the gate pin are electrically connected to each other. The pins include at least one collector or source lead-out portion and a gate lead-out portion; a dielectric material package filling the aforementioned through hole, encapsulating the aforementioned second upper board surface, the aforementioned thin pad portion, and the aforementioned power transistor, thereby forming a third upper board surface flush with the aforementioned first upper board surface, and the third upper board surface is for the aforementioned source lead-out portion, the aforementioned collector lead-out portion, and the aforementioned collector lead-out portion of the aforementioned source pin, the aforementioned collector pin, and the aforementioned gate pin to be at least partially exposed.

By choosing a thin ceramic block, the heat-generating surface of the power transistor can conduct heat energy through a shorter path, increasing the thermal conductivity and ensuring that the temperature rise of the operating environment can be well controlled; by embedding the power transistor, the installation space on the circuit board is freed up, making the miniaturization of the circuit board more thorough; in particular, the power transistor is conducted with a large-area conductive pin, making the circuit design and connection more convenient and reliable, and the circuit direction is opposite to the heat conduction direction, further reducing the thermal interference of the power transistor heating on the operating environment of other components on the circuit board.

1. 1': Dielectric material layer

10, 10', 10": through-hole

12, 12', 12": the first upper surface

14: First lower panel

2: Heat dissipation ceramic block

22, 22', 22": Second upper board surface

24: Second lower board

3:Fixed part

4, 4': Stepped metal electrode layer

42, 42', 42": Source pins

420, 440, 460, 420', 460': Thin pad part

422, 422', 422": Source lead-out section

462, 462', 462": Gate lead-out section

44, 44', 44": Collector pins

442, 442', 442": Collector lead-out section

46, 46', 46": Gate pins

5, 5', 5": Power transistor

52, 52', 52": Source

54, 54', 54": Jiji

56, 56', 56": Gate

6.6": Dielectric material packaging

62, 62', 62": The third board

7: Interface nanosilver gel layer

8: Copper layer

9, 9': Circuit layer

Figures 1 to 4 are schematic side cross-sectional views of various stages of the manufacturing process of the first preferred embodiment of the present invention for an embedded thermoelectric separation circuit board with a ceramic substrate and power transistors.

Figure 5 is a top view of the state in Figure 1.

Figure 6 is a top view schematic diagram of the state of Figure 4 after packaging of the first embodiment of the present invention.

FIG7 is a schematic bottom view of a power transistor used in the second embodiment of the present invention, illustrating the coplanar configuration of its source, gate, and collector.

Figure 8 is a schematic cross-sectional view of the circuit board after packaging of the second embodiment of the present invention.

Figure 9 is a top view of the embodiment of Figure 8 before the power transistor is installed and packaged.

Figure 10 is a top view of the embodiment of Figure 8 after packaging.

Figure 11 is a schematic cross-sectional view of the circuit board after packaging of the third embodiment of the present invention.

Figure 12 is a top view of the packaging embodiment of Figure 11.

The first preferred embodiment of the embedded thermoelectric separation circuit board with ceramic substrate and power transistor of the present invention, as shown in FIG1 and FIG5, is based on a multi-layer dielectric material layer 1 of FR-4 with a length and width of 10 cm each, and a through hole 10 with a length and width of 2 cm each is pre-cut in the dielectric material layer 1 by, for example, laser, and then a corresponding heat dissipation ceramic block 2 in the shape of a square column made of alumina ( _{Al2O3 )} is embedded in the through hole 10. However, as can be easily understood by those familiar with the art, the size of the FR-4 substrate in this embodiment can be simply replaced within the range of greater than 10 ^cm2 to less than 3600 ^cm2 without affecting the implementation of the present invention.

For ease of explanation, according to the direction of the drawings, the surface of the dielectric material layer 1 located above Figures 1 to 4 is called the first upper board surface 12, and the lower surface opposite is called the first lower board surface 14, and the upper and lower surfaces of the heat dissipation ceramic block 2 are respectively called the second upper board surface 22 and the second lower board surface 24. The thermal conductivity of the heat dissipation ceramic block 2 is higher than that of the dielectric material layer 1, and the thickness of the heat dissipation ceramic block 2 is thinner than that of the dielectric material layer 1. Of course, those skilled in the art can easily understand that the dielectric material layer 1 can be replaced by epoxy resin or glass fiber prepreg substrate such as FR-1 (commonly known as bakelite), FR-3, FR-6, G-10, etc.; the cutting method can also be mechanical cutting or similar methods; the heat dissipation ceramic block 2 can be replaced by silicon nitride (Si ₃ N ₄ ), aluminum nitride (AlN), silicon carbide (SiC), beryllium oxide (BeO), etc., all of which will not hinder the implementation of this case.

The fixing portion 3 is filled with epoxy resin glue, for example, into the gap between the outer periphery of the heat dissipating ceramic block 2 and the inner edge of the through hole 10 of the FR-4 dielectric material layer 1. After the glue is cured, not only the outer periphery of the heat dissipating ceramic block 2 and the inner edge of the through hole 10 can be stably bonded, but the fixing portion 3 itself after the glue is cured also has greater flexibility than the heat dissipating ceramic block 2. Therefore, it is a mechanical buffering mixed material, so that even if the two different materials have different thermal expansion coefficients, they can still provide buffering protection. Of course, people familiar with the art can easily infer that although this example uses epoxy resin adhesive for illustration, it is easy to replace it with silicone or other flexible adhesive materials, which will not hinder the implementation of this case. In this example, this combination will make the second lower plate surface 24 flush with the first lower plate surface 14. In addition, since the second lower plate surface 24 of the heat dissipation ceramic block 2 is the main heat dissipation path, an additional heat dissipation metal layer (not numbered) can be added according to design requirements, and the heat dissipation fin (not shown) can be thermally installed under this heat dissipation metal layer; of course, people familiar with the art can easily understand that the second lower plate surface 24 corresponds to the first lower plate surface 14 here, and it can also be designed to make the heat dissipation metal layer and the first lower plate surface 14 flush, which will not hinder the present invention.

At this time, a stepped metal electrode layer 4 is provided on the second upper plate surface 22 for heat conduction. Since the power transistor in this example has a source and a gate coplanar and a collector on the opposite side, as shown in FIG. 5 , the stepped metal electrode layer 4 includes a source pin 42 and a gate pin 46, and each is divided into a thin pad portion 420, 460 and a source lead portion 422, a gate lead portion 462, and the source lead portion 422 is provided on the second upper plate surface 22. The thin pads 420 and 460, which are coplanar and electrically insulated from each other, are mainly arranged on the second upper surface 22 for heat conduction, while the source lead-out portion 422 and the gate lead-out portion 462 extend upward from the thin pad portion 420 and reach at least the same height as the first upper surface 12 of the dielectric material layer 1 in this example, so that the source lead-out portion 422 and the thin pad portion 420 are bent and extended as a whole. As can be seen from the top view of Figure 5, since the current flow of the gate is low and the pin area is much smaller than that of the source, the area of the source lead-out portion 422 of the source exposed to the first upper surface is also significantly larger, thereby allowing more current to flow.

As shown in FIG2 , the power transistor 5 is directly mounted on the thin pads 420 and 460 of the stepped metal electrode layer for electrical and thermal conduction. Since the source 52 and gate 56 of the power transistor 5 are located below the diagram, they are respectively welded to the thin pads 420 and 460, and the large-area thin pad 420 is used to efficiently conduct a large amount of heat energy of the power transistor 5 downward. The measurement results show that the thickness of the heat dissipation ceramic block is greatly reduced, even to only a few hundred microns (μm), so that the operating environment temperature rise caused by the temperature difference of the ceramic block of the power transistor is significantly reduced from the previous three degrees Celsius to one degree Celsius or lower, which greatly improves the overall heat dissipation effect.

Since the collector 54 of the power transistor 5 is located at the upper side of FIG. 2 in this embodiment, in the subsequent FIG. 3 , the collector pin 44 is connected and mounted on the plane of the collector 54 of the power transistor 5 at the upper side. In this embodiment, the collector pin 44 has only a single copper layer 8, which is referred to as the collector lead 442, so that the collector lead 442 is disposed between the source pin 42 and the gate pin 4 6, the thin pads 420 and 460 are in reverse positions, and in this example, the copper layer of the collector lead 442 and the collector 54 of the power transistor 5 are bonded with the nanosilver glue layer 7, so that the copper layer 8 of several millimeters is reliably conductively bonded to the collector 54, and the thickness of the collector lead 442 can just reach at least the same level as the first upper board surface, thereby being exposed to the upper side of the circuit board.

Then, as shown in FIG. 4 and FIG. 6 , the dielectric material package 6 (which may be epoxy resin glue) filling the through hole 10 is used to encapsulate the second upper board surface 22, the thin pad portions 420, 460, and the power transistor 5, thereby forming a third upper board surface 62 flush with the first upper board surface 12. The source lead portion 422 of the gate pin 46, the gate lead portion 462, and the collector lead portion 442 of the collector pin 44 are exposed through the dielectric material package 6 to form a contact exposed on the upper side of the circuit board. Of course, as those familiar with the technical field can easily understand, once there is a tolerance, it can be By means of polishing, the first upper board surface 12, the third upper board surface 62, and all the source lead-out portions 422, the gate lead-out portions 462, and the collector lead-out portions 442 are made level, so as to facilitate the connection between the circuit components on the dielectric material layer and the source 52, the collector 54, and the gate 56 of the power transistor 5; of course, the first upper board surface 12 may also include the top surface after a circuit layer 9 has been set on the FR-4 board, so that the circuit layer 9 can be located above the first upper board surface 12 and the third upper board surface 62, and coplanar with the exposed source pin 42, the collector pin 44, and the gate pin 46.

As can be seen from the above, the present invention mainly reduces the thickness of the heat dissipation ceramic block 2, making the thickness of the heat dissipation ceramic block 2 much thinner than the dielectric material layer 1, so that the heat dissipation effect of the previous technical structure can be better improved, and the height difference between the heat dissipation ceramic block 2 and the dielectric material layer 1 can accommodate the power transistor 5 to be embedded, which can not only effectively ensure the operating temperature environment of the power transistor, but also make the overall thickness thinner, effectively utilize the layout area of the circuit board, and at the same time ensure the thermoelectric separation function well. In addition, the source 52, collector 54 and gate 56 of the power transistor 5 are designed in an excellent position to maximize the conduction path, thereby allowing a large current to pass through without affecting the overall thermal conductivity and thickness.

In particular, it is emphasized again that the power transistor 5 is soldered and fixed to the pad above the heat dissipation ceramic block 2 by means of, for example, surface-mount technology (SMT). Through the large area contact of the thin pad portion, even if it is applied to electronic equipment with a large amount of work, such as electric vehicles, air conditioners, refrigerators, stereos, motor drivers, and high-power computers, the large amount of heat energy generated by the power transistor 5 will directly pass through the heat dissipation ceramic block 2 of aluminum oxide ( _{Al2O3 )} due to its low thermal resistance, and be conducted downward to the high thermal conductivity layer (unnumbered), and then be conducted away from the position of the heat dissipation ceramic block 2 by the heat dissipation fins or heat pipes at the rear, further ensuring that the performance of the circuit components mounted on the dielectric material layer is not affected by high temperatures.

Different from the first embodiment, in which only the source 52 and the gate 56 of the power transistor 5 are located on the same active surface, and the collector 54 is located on the opposite side of the active surface, the second preferred embodiment of the present invention is mainly in response to the power transistor 5' in which the source 52', the collector 54' and the gate 56' are located on the same plane as shown in FIG. 7. Therefore, the present embodiment is shown in FIG. 8 to FIG. 10, in which the steps The metal electrode layer 4' includes a source pin 42', a collector pin 44' and a gate pin 46', wherein the source pin 42' or the gate pin 46' is divided into a thin pad portion 420', 460' and a source lead portion 422', a gate lead portion 462', wherein the thin pad portion 420', 460' is mainly disposed on the second upper plate surface 22' for heat conduction, and the source lead portion 420', 460' is mainly disposed on the second upper plate surface 22' for heat conduction. The source lead-out portion 422' and the gate lead-out portion 462' extend upward from the thin pad portion 420', 460' and are at the same height as the dielectric material layer 1', so that the source lead-out portion 422', the gate lead-out portion 462' and the thin pad portion 420', 460' are bent and extended as a whole. As for the collector pin 44' in this example, it defines a collector thin pad portion 440' and The collector lead-out portion 442' extends from the collector thin pad portion 440'. The collector thin pad portion 440' is also heat-conductingly disposed on the second upper plate surface 22'. The collector lead-out portion 442' extends upward from the collector thin pad portion 440' and is at the same height as the dielectric material layer 1', so that the collector lead-out portion 442' and the collector thin pad portion 440' are bent and extended as a whole.

Since the collector pin 44' is bent and extended, the copper layer in the first embodiment is not required, and the collector pin 44' is set at a position where the source pin 42' and the gate pin 46' are completely corresponding in height, wherein the source 52', collector 54' and gate 56' of the power transistor 5' are located on the same active surface, therefore, the thin pads 420', 460' of the source pin 42', collector pin 44' and gate pin 46' and the collector thin pad 440' are coplanar and electrically insulated.

Subsequently, a dielectric material package (which may be epoxy resin) is filled in the through hole 10' to encapsulate the second upper panel 22', the thin pad portion 420', the collector thin pad portion 440' and the power transistor 5', thereby forming a third upper panel 62' flush with the first upper panel 12', and the source lead-out portion 422' of the source pin 42', the gate lead-out portion 462' of the gate pin 46' and the collector thin pad portion 440' on the collector pin 44' are at least partially exposed through the dielectric material package to form contacts, so as to facilitate contact with the source 52', the collector 54' and the gate 56 of the power transistor 5'. 'After the above packaging is completed, the third upper surface 62' and the source lead-out portion 422', the gate lead-out portion 462' and the collector lead-out portion 442' that are flush with the first upper surface 12' are polished to have a smoother contact surface. Finally, the circuit layer 9' is set on the first upper surface 12', the third upper surface 62', and the exposed source pin 42', the collector pin 44' and the gate pin 46'. Furthermore, the circuit layer 9' can be located above the first upper surface 12' and the third upper surface 62', and coplanar with the exposed source pin 42', the collector pin 44' and the gate pin 46'.

As can be seen from the above, when the source 52', collector 54' and gate 56' of the power transistor 5' are located in the same plane and exposed to the upper side of the circuit board, the heat generated by the power transistor can be discharged to the bottom of the circuit board by the large-area heat-dissipating ceramic block connected to the bottom. Not only can the temperature rise of the power transistor operating environment be controlled to a lower level by using a thinner ceramic block than the existing technology, but the embedded structure can also clear the upper surface of the circuit board and leave a large area of pins, so that large currents can flow in and out smoothly, which not only makes the overall circuit board structure space more cleverly utilized, but also improves the original thermoelectric separation efficiency.

Different from the first embodiment, the power transistor source and gate correspond to the second upper plate surface of the heat sink ceramic block, and the collector is located on the opposite side. As shown in Figures 11 and 12, the collector 54" is located close to and facing the second upper plate surface 22", while the source and gate are located on the opposite side away from the second upper plate surface. In other words, the positions of the collector, source and gate are opposite to those of the first embodiment.

The collector pin 44" is installed on the plane of the collector 54" of the power transistor 5" below. In this example, in addition to the copper layer provided on the second upper plate surface 22" as a thin pad portion 440", the collector pin 44" also extends upward from the thin pad portion 440" in an L-shape to form a surrounding collector lead portion 442"; in contrast, in this embodiment, the source 52" and the gate 56" are facing upward in the figure, so that the source pin 42" and the gate pin 46" only include the source lead portion 422" and the gate lead portion 462" respectively.

The same as the first embodiment is that the dielectric material package 6" is used to fill the through hole 10", and the second upper board surface 22", the collector lead portion 442", and the power transistor 5" are encapsulated to form a third upper board surface 62" flush with the first upper board surface 12". As for the source lead portion 422", the gate lead portion 462" and the collector lead portion 442", after polishing, they are exposed in the dielectric material package 6" in a coplanar structure to form a contact exposed on the upper side of the circuit board. Therefore, on the one hand, the thickness of the heat dissipation ceramic block is lower than that of the thermoelectric separator. The overall thickness of the circuit board makes the temperature difference between the top and bottom of the heat sink ceramic block lower, which can dissipate heat more efficiently. On the other hand, the power transistor mounted on the heat sink ceramic block is completely embedded in the through hole, effectively saving the volume of the circuit board. The source, collector and gate of the power transistor can be exposed to the circuit board through their respective lead-out parts, and a flat and wide welding surface is maintained to maximize the conductive path. It can fully cope with the parallel pressure welding of multiple conductive wires required for large current to allow large current to pass through, making it easy to implement the operation control of electric vehicles or other large currents.

However, the above is only a preferred embodiment of the present invention, and it cannot be used to limit the scope of implementation of the present invention. In other words, all simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the content of the invention specification should still fall within the scope of the present invention patent.

1: Dielectric material layer

420, 460: thin pad part

422: Source lead-out section

462: Gate lead-out section

44: Collector pin

442: Collector lead-out section

6: Dielectric material packaging

8: Copper layer

9: Circuit layer

Claims (8)

A thermoelectric separation circuit board with an embedded ceramic substrate and a power transistor, comprising: A dielectric material layer, comprising a first upper surface and a first lower surface opposite to the first upper surface, and the dielectric material layer is formed with at least one through hole penetrating the first upper surface and the first lower surface; At least one heat dissipation ceramic block correspondingly embedded in the above-mentioned through hole comprises a second upper plate surface and a second lower plate surface, the thermal conductivity of the above-mentioned heat dissipation ceramic block is higher than the above-mentioned dielectric material layer, and the thickness of the above-mentioned heat dissipation ceramic block is thinner than the above-mentioned dielectric material layer; At least one fixing portion for embedding and fixing the heat dissipation ceramic block in the through hole of the dielectric material layer, so that the second lower plate surface corresponds to the first lower plate surface; A stepped metal electrode layer disposed on the second upper plate surface for heat conduction, including at least one source pin or one collector pin, wherein the source pin or collector pin is divided into a thin pad portion and a source or collector lead portion extending from the thin pad portion; A power transistor electrically and thermally mounted on the stepped metal electrode layer, the transistor having at least a source, a gate and a collector, wherein the source or collector is electrically connected to the source or collector pin; At least two collector or source pins electrically connected to the other of the aforementioned source or the aforementioned collector, and a gate pin electrically connected to the aforementioned gate, wherein the aforementioned collector or source pin and the aforementioned gate pin respectively include at least one collector or source lead portion and a gate lead portion; A dielectric material package filling the through hole encapsulates the second upper surface, the thin pad, and the power transistor, thereby forming a third upper surface flush with the first upper surface, and the third upper surface is for at least partially exposing the source lead-out portion, the collector lead-out portion, and the collector lead-out portion of the source pin, the collector pin, and the gate pin, respectively. As described in claim 1, the embedded thermoelectric separation circuit board with a ceramic substrate and a power transistor, wherein the power transistor is a bare crystal die. As described in claim 2, the embedded thermoelectric separation circuit board with a ceramic substrate and a power transistor, wherein the source, collector and gate of the power transistor are all located in the same plane, wherein the source pin, collector pin and gate pin each have a thin pad portion that is thermally conductively disposed on the second upper plate surface and is coplanar and electrically insulated from each other; and the source lead portion, collector lead portion and gate lead portion are respectively bent and extended from the corresponding thin pad portion. As described in claim 2, the embedded thermoelectric isolation circuit board with a ceramic substrate and a power transistor, wherein the source and gate of the power transistor are located on the same active surface, and the collector is located on the opposite side of the active surface; and the source pin and the gate pin respectively have the thin pad portions that are coplanar and electrically insulated, and the source lead portion and the gate lead portion that are bent and extended from the thin pad portions; and the collector lead portion is arranged on the opposite side. As described in claim 4, the embedded thermoelectric separation circuit board having a ceramic substrate and a power transistor, wherein the collector lead portion is a copper layer disposed on the opposite surface of the power transistor. As described in claim 5, the embedded thermal and electrical isolation circuit board having a ceramic substrate and a power transistor, wherein the collector lead-out portion of the collector pin further includes an interface nanosilver gel layer disposed between the opposite surface of the power transistor and the copper layer. As described in claim 2, the embedded thermoelectric separation circuit board with a ceramic substrate and a power transistor, wherein the collector of the power transistor is located close to and facing the second upper board surface, and the source and gate are located on an opposite side away from the second upper board surface. As described in claim 7, the embedded thermoelectric isolation circuit board with a ceramic substrate and a power transistor, wherein the collector pin has the thin pad portion and the collector lead portion bent and extended from the thin pad portion; and the source lead portion and the gate lead portion are insulated from each other and arranged on the opposite surface in a coplanar manner.

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