TWI856776B - Electrostatic discharge protection device - Google Patents

Abstract

An electrostatic discharge protection device is provided and includes a semiconductor substrate, first to fourth well regions, first to third doping regions, and a metal line. The semiconductor substrate has a first conductive type. The first well region is disposed on the semiconductor substrate and has a second conductive type different from the first conductive type. The second well region is disposed on the semiconductor substrate and adjacent to the first well region and has the first conductive type. The third well region is disposed in the first well region and has the second conductive type. The fourth well region is disposed in the second well region and has the first conductive type. The first and second doping regions are disposed in the third and fourth well regions and have the second conductive type. The third doping region is disposed in the second well region and has the first conductive type. The metal line is electrically connected to the second well region, and a Schottky contact is formed between the metal line and the second well region.

Description

Electrostatic discharge protection device

The present invention relates to an electrostatic discharge (ESD) protection device, and in particular to a bidirectional ESD protection device.

With the development of semiconductor manufacturing process for integrated circuits, the size of semiconductor components has been reduced to the sub-micron stage to improve the performance and computing speed of integrated circuits. However, the reduction in component size has caused some reliability issues, especially the electrostatic discharge (ESD) protection capability of integrated circuits. Therefore, in this technical field, there is a need for a protection device that can provide better ESD performance.

The present invention provides an electrostatic discharge protection device, which includes a semiconductor substrate, an epitaxial layer, a first well region, a second well region, a third well region, a fourth well region, a first doped region, a second doped region, a third doped region, and a first metal wire. The semiconductor substrate has a first conductivity type. The epitaxial layer is located on the semiconductor substrate, and the epitaxial layer has a first conductivity type. The first well region is arranged in the epitaxial layer, and the first well region has a second conductivity type opposite to the first conductivity type. The second well region is arranged in the epitaxial layer, and the second well region has a first conductivity type and is adjacent to the first well region. The third well region is arranged in the first well region, and the third well region has a second conductivity type. The fourth well region is arranged in the second well region, and the fourth well region has the first conductivity type. The first doped region is disposed in the third well region, and the first doped region has a second conductivity type. The second doped region is disposed in the fourth well region, and the second doped region has a second conductivity type. The third doped region is disposed in the second well region, and the first doped region has a second conductivity type. The first metal wire is electrically connected to the second well region. A first Schottky contact is formed between the first metal wire and the second well region.

In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, a preferred embodiment is specifically described below in detail with reference to the accompanying drawings.

FIG. 1A is a schematic cross-sectional view of an electrostatic discharge (ESD) protection device according to an embodiment of the present invention. Referring to FIG. 1A, when an electrostatic discharge event occurs on the bonding pad PVH, the electrostatic discharge protection device 1 provides a discharge path in the direction from the bonding pad PVH to another bonding pad PVL. In this embodiment, the electrostatic discharge protection device 1 is divided into a left side portion S10 and a right side portion S11 by a symmetry line L10. With the symmetry line L10 as a reference, the structure of the left side portion S10 and the structure of the right side portion S11 are symmetrical to each other. In order to clearly and concisely explain the electrostatic discharge protection device 1 of the present case, the structure of the left side portion S10 will be described in detail below. A person skilled in the art can obtain the structure of the right side S11 according to the structure of the left side S10 and based on the above symmetric relationship. The electrostatic discharge protection device 1 includes a semiconductor substrate 100, an epitaxial layer 101, a buried layer 102, well regions 103-112, doped regions 113-117, isolators 119-127, gate structures 128 and 129, and blocking protective oxide layers (PRO) 130 and 131.

According to this embodiment of the present invention, the semiconductor substrate 100 may be a bulk semiconductor, a semiconductor-on-insulation (SOI) substrate. The semiconductor substrate 100 may be a wafer, such as a silicon wafer. Generally speaking, an SOI substrate includes a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or a similar material, which provides an insulating layer on a silicon or glass substrate. Other substrates may be used, for example, a multi-layer or gradient substrate.

In some embodiments, the semiconductor substrate 100 may be a semiconductor material, which may include silicon and germanium. In some embodiments, the semiconductor substrate 100 may also be a compound semiconductor, which includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide. In some embodiments, the semiconductor base 110 may also be an alloy semiconductor, which includes SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP or a combination thereof. In the case where the semiconductor substrate 100 is a silicon substrate, the semiconductor substrate 100 may be implanted with N-type or P-type dopants to change its conductivity type to a first conductivity type of P-type or a second conductivity type of N-type according to design requirements. In the embodiment of FIG. 1A , the conductivity type of the semiconductor substrate 100 is P type (first conductivity type).

1A , an epitaxial layer 101 is formed on a semiconductor substrate 100. The epitaxial layer 100 may include silicon, germanium, silicon and germanium, a III-V compound, or a combination thereof. The epitaxial layer may be formed by an epitaxial growth process, such as metal-organic chemical vapor deposition (MOCVD), metal-organic vapor phase epitaxy (MOVPE), plasma-enhanced chemical vapor deposition (PECVD), remote plasma chemical vapor deposition (RPCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE), or the like. In this embodiment, the conductivity type of the epitaxial layer 101 is P type (first conductivity type), but the present invention is not limited thereto.

The buried layer 102 is disposed on the interface between the epitaxial layer 101 and the semiconductor substrate 100. In this embodiment, the buried layer 102 has, for example, an N-type (second conductivity type), but the present invention is not limited thereto.

As shown in FIG. 1A , well regions 103 to 107 are disposed in the epitaxial layer 101. In this embodiment, the conductivity type of the well regions 103 to 105 is P-type (first conductivity type), and the conductivity type of the well regions 106 and 107 is N-type (second conductivity type). In order to clearly explain the configuration and conductivity type of the well regions 103 to 107, hereinafter, the well regions 103 to 105 are exemplified as high voltage P-type well regions (HVPW), and the well regions 106 and 107 are exemplified as high voltage N-type deep well regions (DHVNW). For example, in an embodiment of the present invention, the doping concentration of the high-voltage P-type well region is about 1E11~1E12 atoms/cm ² , and the doping concentration of the high-voltage N-type deep well region is about 1E11~1E12 atoms/cm ² . Referring to FIG. 1A , the high-voltage N-type deep well region 106 is disposed between the high-voltage P-type well regions 103 and 104 , the high-voltage P-type well region 104 is disposed between the high-voltage N-type deep well regions 106 and 107 , and the high-voltage N-type deep well region 107 is disposed between the high-voltage P-type well regions 104 and 105 . The bottom surfaces of the high-voltage P-type well regions 104 and 105 and the bottom surfaces of the high-voltage N-type deep well regions 106 and 107 are all connected to the buried layer 102 .

Well region 108 is disposed in high voltage P-type well region 103. In this embodiment, the conductivity type of well region 108 is P-type (first conductivity type). In order to clearly explain the configuration and conductivity type of well region 108, well region 108 is exemplified as a P-type well region (PW) hereinafter. For example, in an embodiment of the present invention, the doping concentration of the P-type well region is approximately 1E12~1E13 atoms/cm ² . Well region 111 is disposed in high voltage N-type deep well region 106. In this embodiment, the conductivity type of well region 111 is N-type (second conductivity type). In order to clearly explain the configuration and conductivity type of well region 111, well region 111 is exemplified as an N-type well region (NW) hereinafter. For example, in an embodiment of the present invention, the doping concentration of the N-type well region is about 1E12-1E13 atoms/cm ² .

The well region 109 is disposed in the high voltage P-type well region 104. In this embodiment, the conductivity type of the well region 109 is P-type (first conductivity type). In order to clearly explain the configuration and conductivity type of the well region 109, the well region 109 is exemplified as a P-type well region (PW) in the following. Referring to FIG. 1A , the P-type well region 109 is disposed in the high voltage P-type well region 104 and is close to the high voltage N-type deep well region 107.

The well region 112 is disposed in the high voltage N-type deep well region 107. In this embodiment, the conductivity type of the well region 112 is N-type (second conductivity type). In order to clearly explain the configuration and conductivity type of the well region 112, the well region 112 is exemplified as an N-type well region (NW) hereinafter.

The well region 110 is disposed in the high voltage P-type well region 105. In this embodiment, the conductivity type of the well region 110 is P-type (first conductivity type). In order to clearly explain the configuration and conductivity type of the well region 110, the well region 110 is exemplified as a P-type well region (PW) hereinafter. Referring to FIG. 1A , the P-type well region 110 is disposed in the high voltage P-type well region 105 and is close to the high voltage N-type deep well region 107.

Referring to FIG. 1A , doping region 113 is disposed in P-type well region 108. Doping region 115 is disposed in N-type well region 111. Doping region 114 is disposed in high-voltage P-type well region 104 and is close to high-voltage N-type deep well region 106. Doping region 116 is disposed in P-type well region 109. Doping region 117 is disposed in N-type well region 112. Doping region 118 is disposed in P-type well region 110. In this embodiment, each of the doped regions 113 and 114 has a P-type conductivity type and is, for example, a P-type heavily doped region (P+), and each of the doped regions 115 to 118 has an N-type conductivity type and is, for example, an N-type heavily doped region (N+). For example, in the embodiment of the present invention, the doping concentration of the P-type heavily doped region (P+) is about 1E15 atoms/cm ² , and the doping concentration of the N-type heavily doped region (N+) is about 1E15 atoms/cm ² . In order to clearly explain the configuration and conductivity type of the doped regions 113 to 118 , hereinafter, the doped regions 113 and 114 are referred to as P-type doped regions, and the doped regions 115 to 118 are referred to as N-type doped regions.

As shown in FIG. 1A , isolators 119 to 127 are disposed on the epitaxial layer 101. In this embodiment, the isolators 119 to 127 may be shallow trench isolators (STI). The semiconductor substrate 100 may be patterned by a lithography process and an etching process to form a plurality of openings, and then a dielectric material is filled into the openings by a deposition process to form isolation regions 119 to 127. In other embodiments, the isolation regions 119 to 127 may be field oxide regions formed by silicon oxidation. The above-mentioned lithography process includes photoresist coating (for example, spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, drying (for example, hard baking), other suitable processes or combinations thereof. The lithography process can also be replaced by maskless lithography, electron beam writing, ion beam writing or molecular imprint. The above-mentioned etching process includes dry etching, wet etching or other etching methods (for example, reactive ion etching). The etching process can also be pure chemical etching (plasma etching), pure physical etching (ion milling) or a combination thereof. The above-mentioned deposition process includes chemical vapor deposition, chemical vapor deposition, atomic layer deposition or other deposition methods.

The isolator 119 is disposed on one side of the P-type doped region 113 and covers the high voltage P-type well region 103 and the P-type well region 108. The isolator 120 is disposed on the other side of the P-type doped region 113 and between the P-type doped region 113 and the N-type doped region 115. In addition, the isolator 120 covers the high voltage P-type well region 103, the P-type well region 108, the high voltage N-type deep well region 106, and the N-type well region 111. The isolator 121 is disposed in the N-doped region 115 and the P-doped region 114 and covers the high voltage N-type deep well region 106, the N-type well region 111, and the high voltage P-type well region 104.

The isolator 122 is disposed on one side of the P-type doped region 114 and covers the high voltage P-type well region 104. The isolator 123 is disposed on one side of the N-type doped region 116 and covers the high voltage P-type well region 104 and the P-type well region 109. Referring to FIG. 1A, there is a space between the isolators 122 and 123. The isolator 124 is disposed between the P-type well region 109 and the N-type doped region 117 and covers the high voltage P-type well region 104, the high voltage N-type deep well region 107, and the N-type well region 112.

The isolator 125 is disposed between the N-type doped region 117 and the P-type well region 110 and covers the high voltage N-type deep well region 107, the N-type well region 112, and the high voltage P-type well region 105. The isolator 126 is disposed on one side of the N-type doped region 118 and covers the high voltage P-type well region 105 and the P-type well region 110.

According to the above, based on the symmetry line L10, the structure of the left side portion S10 and the structure of the right side portion S11 of the electrostatic discharge protection device 1 are symmetrical to each other. In order to present the symmetrical structure, FIG. 1A further shows the isolator 127, which belongs to the right side portion S11. Based on the symmetrical structure, the isolator 127 corresponds to the isolator 126.

Referring to FIG. 1A , a gate structure 128 is disposed on the P-type well region 108 and the N-type doped region 116, and a gate structure 129 is disposed on the P-type well region 109 and the N-type doped region 118. In an embodiment of the present invention, each of the gate structures 117 and 118 may be formed by a lower gate insulating layer and an upper gate layer. In one embodiment, the above-mentioned gate insulating layer may include commonly used dielectric materials such as oxide, nitride, oxynitride, oxycarbide, or a combination thereof. In other embodiments, the gate insulating layer may also include aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), hafnium oxynitride (HfON), hafnium silicate (HfSiO ₄ ), zirconium oxide (ZrO ₂ ), zirconium oxynitride (ZrON), zirconium silicate (ZrSiO ₄ ), yttrium oxide (Y ₂ O ₃ ), lanthalum oxide (La ₂ O ₃ ), cerium oxide (CeO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide (Ta ₂ In one embodiment, the gate layer may include silicon _or polysilicon. In other embodiments, the gate layer includes amorphous silicon.

The blocking protection oxide layers 130 and 131 are disposed on the epitaxial layer 101. The blocking protection oxide layer 130 covers the N-type doped region 117, the N-type well region 112, the isolator 124, and a portion of the gate structure 128. The blocking protection oxide layer 131 covers the N-type doped region 117, the N-type well region 112, the isolator 125, and a portion of the gate structure 129.

Referring to FIG. 1A , the metal wire M11 is electrically connected to the high voltage P-type well region 104, so that a Schottky contact 132 is formed between the metal wire M11 and the high voltage P-type well region 104. The metal wire M11 is also electrically connected to the high voltage P-type well region 105, so that a Schottky contact 133 is formed between the metal wire M11 and the high voltage P-type well region 105. The metal wire M11 is electrically connected to the P-type doped region 114, so that an Ohmic contact is formed between the metal wire M11 and the P-type doped region 114. The metal wire M11 further electrically connects the N-type doped regions 116 and 118, and the gate structures 128 and 129. One end of the metal wire M11 is electrically connected to the bonding pad PVL. In other words, the P-type doped region 114, the high voltage P-type well region 104, the N-type doped regions 116 and 118, the high voltage P-type well region 105, and the gate structures 128 and 129 are electrically connected to the bonding pad PVL through the metal wire M11.

The metal wire M10 electrically connects the N-type doped regions 115 and 17. One end of the metal wire M10 is electrically connected to the bonding pad PVH. The metal wire M12 is electrically connected to the P-type doped region 113. One end of the metal wire M12 is electrically connected to the bonding pad Psub. When the electrostatic discharge protection device 1 is in a normal mode, the bonding pads PVL, PVH, and Psub each receive a corresponding voltage. The voltage received by the bonding pad PVL is less than the voltage received by the bonding pad PVH. For example, the voltage received by the bonding pad PVH is the operating voltage VDD, and the bonding pad PVL is coupled to the ground, that is, the voltage received by the bonding pad PVL is equal to or close to 0 volts.

FIG. 1B is a schematic diagram showing an equivalent circuit of an electrostatic discharge protection device 1 according to an embodiment of the present invention. Referring to FIG. 1B , the calibration element of the electrostatic discharge protection device 1 is an N-type metal-oxide-semiconductor (NMOS) transistor 10, which has a gate G, a drain D, a source S, and a base (bulk) B (b). Referring to FIG. 1A and FIG. 1B at the same time, the gate structures 128 and 129 serve as the gate G, the N-type doped region 117 serves as the drain D, and the N-type doped regions 116 and 118 serve as the source S.

The P-type doped region 114 and the Schottky contacts 132 and 133 serve as the base. According to the above, the Schottky contact 132 is formed between the metal wire M11 and the high voltage P-type well region 104, the Schottky contact 133 is formed between the metal wire M11 and the high voltage P-type well region 105, and the ohmic contact is formed between the metal wire M11 and the P-type doped region 114. In this embodiment, the base corresponding to the Schottky contacts 132 and 133 is represented by the symbol "B", and the base corresponding to the ohmic contact is represented by the symbol "b". Although different symbols are used to represent the base, since the high voltage P-type well region 104, the high voltage P-type well region 105, and the P-type doped region 114 are all electrically connected to the metal wire M11, the symbols "B" and "b" represent the same base.

Referring to FIG. 1B , according to the structure of FIG. 1A , the drain D of the NMOS transistor 10 is electrically connected to the bonding pad PVH, and the gate G, the source S, and the base B (b) are electrically connected to the bonding pad PVL. Therefore, the NMOS transistor 10 can become a gate-grounded NMOS (GGNMOS) transistor.

FIG. 2 is a schematic diagram of a parasitic element of an electrostatic discharge protection device according to an embodiment of the present invention. Referring to FIG. 2, the N-type doped region 117, the high voltage P-type well region 104, and the N-type doped region 116 together constitute an N-type-P-type-N-type junction bipolar transistor (NPN bipolar junction transistor, NPN BJT) 20. The N-type doped region 117 serves as the collector of the NPN BJT 20, the high voltage P-type well region 104 serves as the base of the NPN BJT 20, and the N-type doped region 116 serves as the collector of the NPN BJT 20.

Referring to FIG. 2 , the N-type doped region 117 , the high voltage P-type well region 104 , and the metal wire M11 (N-type quasi-region) together constitute the NPN BJT 21 . The N-type doped region 117 serves as the collector of the NPN BJT 21 , the high voltage P-type well region 104 serves as the base of the NPN BJT 21 , and the metal wire M11 serves as the collector of the NPN BJT 21 .

Referring to FIG. 1B and FIG. 2 simultaneously, when an electrostatic discharge event occurs on the bonding pad PVH, the charge caused by the electrostatic discharge event can be conducted to the bonding pad PVL through the NPN BJP 20 and can also be conducted to the bonding pad PVL through the NPN BJP 21, thereby improving the efficiency of electrostatic discharge.

According to the above embodiments, the base of the electrostatic discharge protection device 1 is formed by the Schottky contacts 132 and 133 in addition to the ohmic contact. For example, a parasitic NPN BJP 21 is formed through the Schottky contact 132, which provides an additional discharge path. In this way, when an electrostatic discharge event occurs on the bonding pad PVH, the electrostatic discharge protection device 1 can quickly transfer the charge caused by the electrostatic discharge event to the bonding pad PVL to achieve electrostatic discharge.

FIG. 3 shows a top view of an electrostatic discharge protection device according to an embodiment of the present invention. Referring to FIG. 1A and FIG. 3, the cross-sectional schematic diagram of FIG. 1A is drawn based on the cross-sectional line A-A' of FIG. 3. In order to clearly show the four electrode terminals of the electrostatic discharge protection device 1, the doped region corresponding to the drain is marked with D, the doped region corresponding to the source is marked with S, the Schottky contact corresponding to the base is marked with B, and the ohmic contact corresponding to the base is marked with b. Taking the left side portion S10 of the ESD protection device 1 as an example, the doped region corresponding to the drain D, the doped region corresponding to the source S, and the Schottky contact corresponding to the base B are respectively adjacent strip regions 30-32. The ohmic contact corresponding to the base b is a ring region 33. The ring region 33 surrounds the strip regions 30-32.

The N-type doped region 115 is represented by "N+" in FIG. 3, and the P-type doped region 113 is represented by "P+" in FIG. 3. The N-type doped region 115 (N+) is the annular region 34, and the P-type doped region 113 (P+) is the annular region 35. The annular region 34 surrounds the annular region 33, and the annular region 35 surrounds the annular region 34. In other words, the annular region 34 is disposed between the annular regions 33 and 35.

FIG. 4 shows a top view of an electrostatic discharge protection device according to another embodiment of the present invention. Referring to FIG. 1A and FIG. 4, the cross-sectional schematic diagram of FIG. 1A is drawn based on the cross-sectional line B-B' of FIG. 4. In order to clearly show the four electrode ends of the electrostatic discharge protection device 1, the doping region corresponding to the drain is marked with D, the doping region corresponding to the source is marked with S, the Schottky contact corresponding to the base is marked with B, and the ohmic contact corresponding to the base is marked with b. The doping region corresponding to the drain D is a strip region 40. Another strip region 41 in FIG. 4 includes a plurality of segments 410 and 411. The Schottky contact corresponding to the base B is formed in the section 410, and the doped region corresponding to the source S is formed in the section 411. The ohmic contact corresponding to the base b is the ring region 42. The ring region 42 surrounds the strip regions 40 and 41.

The N-type doped region 115 is represented by "N+" in FIG. 4, and the P-type doped region 113 is represented by "P+" in FIG. 4. The N-type doped region 115 (N+) is the annular region 43, and the P-type doped region 113 (P+) is the annular region 44. The annular region 43 surrounds the annular region 42, and the annular region 44 surrounds the annular region 43. In other words, the annular region 43 is disposed between the annular regions 42 and 44.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined in the attached patent application.

1: ESD protection device 10: NMOS transistor 20, 21: bipolar transistor 30~32: strip region 33~35: ring region 40, 41: strip region 42~44: ring region 100: semiconductor substrate 101: epitaxial layer 102: buried layer 103~105: well region 106, 107: well region 108~110: well region 111, 112: well region 113, 114: doped region 115~118: doped region 119~127: isolator 128, 129: gate structure 130, 131: Blocking protective oxide layer 132, 133: Schottky contact A-A’, B-B’: Section line B, b: Base D: Drain G: Gate L10: Symmetrical line Psub, PVH, PVL: Bonding pad M10~M12: Metal wire S: Source S10: Left side S11: Right side

FIG. 1A is a schematic cross-sectional view of an electrostatic discharge (ESD) protection device according to an embodiment of the present invention. FIG. 1B is a schematic diagram of an equivalent circuit of an electrostatic discharge protection device according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a parasitic element of an electrostatic discharge protection device according to an embodiment of the present invention. FIG. 3 is a top view of an electrostatic discharge protection device according to an embodiment of the present invention. FIG. 4 is a top view of an electrostatic discharge protection device according to another embodiment of the present invention.

1: Electrostatic discharge protection device

100:Semiconductor substrate

101: Epitaxial layer

102: Buried layer

103~105: Well area

106,107: Well area

108~110: Well area

111,112: Well area

113,114: Mixed area

115~118: Mixed area

119~127: Isolation

128,129: Gate structure

130,131: Block and protect the oxide layer

132,133: Xiao Teji contact

B,b: base

D: Drain

G: Gate

L10: Symmetry line

Psub, PVH, PVL: Bonding pad

M10~M12: Metal wire

S: Source

S10: Left side

S11: Right side

Claims (12)

An electrostatic discharge protection device includes: a semiconductor substrate having a first conductivity type; an epitaxial layer located on the semiconductor substrate, wherein the epitaxial layer has the first conductivity type; a first well region arranged in the epitaxial layer, wherein the first well region has a second conductivity type opposite to the first conductivity type; a second well region arranged in the epitaxial layer, wherein the second well region has the first conductivity type and is adjacent to the first well region; a third well region arranged in the first well region, wherein the third well region has the second conductivity type; a fourth well region arranged in the first well region, wherein the third well region has the second conductivity type; and a fourth well region arranged in the first well region. A region is disposed in the second well region, wherein the fourth well region has the first conductivity type; a first doped region is disposed in the third well region, wherein the first doped region has the second conductivity type; a second doped region is disposed in the fourth well region, wherein the second doped region has the second conductivity type; a third doped region is disposed in the second well region, wherein the first doped region has the first conductivity type; and a first metal wire is electrically connected to the second well region; wherein a first Schottky contact is formed between the first metal wire and the second well region. The electrostatic discharge protection device of claim 1 further includes: a fifth well region disposed in the epitaxial layer, wherein the fifth well region has the second conductivity type and the second well region; a sixth well region disposed in the epitaxial layer, wherein the sixth well region has the first conductivity type, and the fifth well region is disposed between the second well region and the sixth well region; a seventh well region disposed in the fifth well region, wherein the fifth well region has the second conductivity type; an eighth well region disposed in the sixth well region, wherein the sixth well region has the first conductivity type; a fourth doped region disposed in the seventh well region, wherein the fourth doped region has the second conductivity type; and a fifth doped region disposed in the eighth well region, wherein the fifth doped region has the first conductivity type. As in claim 2, the electrostatic discharge protection device, wherein the first metal wire is further electrically connected to the third doped region, and an Ohmic contact is formed between the third doped region and the first metal wire. The electrostatic discharge protection device of claim 2 further includes: a second metal wire electrically connecting the first doped region and the fourth doped region; and a third metal wire electrically connecting the fifth doped region. The electrostatic discharge protection device of claim 4, wherein the first metal wire is connected to a first bonding pad to receive a first voltage, the second metal wire is connected to a second bonding pad to receive a second voltage, and the first voltage is less than the second voltage. The electrostatic discharge protection device of claim 1 further includes: a first gate structure disposed on the fourth well region and the second doped region; wherein the first metal wire is further electrically connected to the second doped region, the third doped region, and the first gate structure. As in claim 1, the electrostatic discharge protection device, wherein the first doped region, the second doped region, and the first Schottky contact are respectively a plurality of strip regions adjacent to each other. As in claim 7, the electrostatic discharge protection device, wherein the third doped region is a first annular region, and the first annular region surrounds the strip regions. As in claim 1, the electrostatic discharge protection device, wherein the first doped region is a first strip region; and the second doped region is formed in a plurality of first segments, the first Schottky contact is formed in a plurality of second segments, and the first segments and the second segments are arranged in a second strip region. As in claim 9, the electrostatic discharge protection device, wherein, in the top view of the electrostatic discharge protection device, the third doped region is a first annular region, and the first annular region surrounds the first strip region and the second strip region. As in claim 1, the electrostatic discharge protection device, wherein the first doped region, the second well region, and the second doped region together form a bipolar junction transistor (BJT). As in claim 1, the electrostatic discharge protection device, wherein the first doped region, the second well region, and the first metal wire together form a junction bipolar transistor.

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