TWI856545B - Electronic package and fabricating method thereof - Google Patents

Abstract

An electronic package is provided, in which heat dissipation bumps are embedded in an encapsulation layer to carry an electronic component, and a circuit structure is formed on the encapsulation layer and electrically connected to the heat dissipation bumps. Therefore, heat energy from the electronic component can be transferred to the circuit structure by the heat dissipation bumps and dissipated to the outside, so as to effectively ensure the heat dissipation capability of the electronic package.

Description

Electronic packaging and its manufacturing method

The present invention relates to a semiconductor packaging technology, in particular to an electronic package with embedded components and its manufacturing method.

The technologies currently used in the chip packaging field include chip scale package (CSP), direct chip attached (DCA), double side packaging or multi-chip module (MCM) packaging.

FIG. 1 is a cross-sectional view of a conventional semiconductor package 1. As shown in FIG. 1 , the semiconductor package 1 is a flip-chip package type, which includes a package substrate 10 having a core insulation layer 15, a semiconductor chip 12 disposed on the package substrate 10 by a solder bump 11, and a coating layer 13 for coating the semiconductor chip 12 to reflow the solder bump 11 and fix the semiconductor chip 12, wherein the package substrate 10 has a plurality of dielectric layers 100 and a circuit layer 101 disposed on the dielectric layer 100 on opposite sides of the core insulation layer 15, and the core insulation layer 15 is bis(succinylidene)imide/trinitrogen trap (Bismaleimide triazine, BT for short) layer, and the material forming the coating layer 13 is epoxy molding compound (EMC for short).

However, in the conventional semiconductor package 1, the semiconductor chips 12 are disposed on the surface of the dielectric layer 100 on one side of the package substrate 10, making it difficult to reduce the thickness of the semiconductor package 1, and thus failing to meet the thinning requirement.

Furthermore, if the core insulating layer 15 is removed from the package substrate 10 to reduce the thickness of the semiconductor package 1, the package substrate 10 is prone to warping due to the insufficient strength of the dielectric layer 100.

In addition, the semiconductor chip 12 needs to be fixed on the package substrate 10 by reflowing the solder bumps 11. Therefore, when the reflow process is performed in a high temperature environment or other thermal cycle process, the package substrate 10 is prone to uneven distribution of thermal stress due to heat accumulation, resulting in the problem of warping of the package substrate 10.

Therefore, how to overcome the above-mentioned problems of the knowledge-based manufacturing method has become an issue that needs to be solved urgently.

In view of the above-mentioned deficiencies of the prior art, the present invention provides an electronic package, comprising: a coating layer having a first surface and a second surface opposite to each other; a first circuit layer formed on the first surface of the coating layer; a heat dissipation bump embedded in the second surface of the coating layer; an electronic component embedded in the coating layer and disposed on the heat dissipation bump; and a circuit structure formed on the coating layer. The circuit structure includes at least one insulating layer formed on the cladding layer and a second circuit layer formed on the insulating layer, so that the second circuit layer is electrically connected to the heat dissipation bump, so that the electronic component dissipates heat through the second circuit layer and the heat dissipation bump, and the material forming the insulating layer is Bismaleimide triazine (BT) or Ajinomoto build-up film (ABF).

The present invention also provides a method for manufacturing an electronic package, comprising: disposing a carrier substrate on two opposite sides of a carrier, wherein the carrier substrate has at least one heat dissipation bump; disposing an electronic component on the heat dissipation bump; forming a coating layer on the carrier substrate to cover the heat dissipation bump and the electronic component, wherein the coating layer has a first surface and a second surface opposite to each other, so that the coating layer is bonded to the carrier substrate with its second surface; forming a first circuit layer on the first surface of the coating layer to form a packaging module; removing the carrier and the carrier substrate to obtain a plurality of the packaging modules and exposing the second surface of the coating layer, wherein the packaging module is The heat dissipation bump is left so that the heat dissipation bump is exposed on the second surface of the coating layer; the packaging modules are respectively arranged on two opposite sides of a support member, and each packaging module is pressed onto the support member with its first circuit layer so that the second surface of the coating layer faces outward; a circuit structure is formed on the second surface of the coating layer, wherein the circuit structure is Containing at least one insulating layer formed on the encapsulation layer and a second circuit layer formed on the insulating layer, so that the second circuit layer is electrically connected to the heat dissipation bump, so that the electronic component dissipates heat through the second circuit layer and the heat dissipation bump, and the material forming the insulating layer is Bismaleimide triazine (BT) or Ajinomoto build-up film (ABF); and removing the support.

In the aforementioned electronic package and its manufacturing method, the carrier substrate further has a plurality of conductive bumps, so that the second surface of the coating layer is embedded with the plurality of conductive bumps, so that the first circuit layer is electrically connected to the plurality of conductive bumps through a conductor. For example, the electronic element is electrically connected to the conductive bumps through a wire.

In the aforementioned electronic package and its manufacturing method, the electronic component is bonded to the heat sink bump via an adhesive layer.

The aforementioned electronic package and its manufacturing method further include forming an insulating protective layer on the circuit structure, and the insulating protective layer exposes a portion of the surface of the second circuit layer, wherein the insulating protective layer has a filling material.

As can be seen from the above, the electronic package and its manufacturing method of the present invention mainly save the use space on the first surface of the packaging layer by embedding the electronic component in the packaging layer, thereby facilitating the thinning of the electronic package. Therefore, compared with the conventional technology, the manufacturing method of the present invention can thin the electronic package to meet the needs of miniaturization.

Furthermore, by combining the electronic components with the adhesive layer to replace the conventional flip chip solder bumps and their reflow process, the risk of warping caused by high temperature environment (or thermal cycle) can be effectively reduced when the electronic package meets the requirements of miniaturization. Furthermore, by using the carrier and the support to perform two symmetrical pressing operations, the problem of warping during the manufacturing process of the electronic package can be avoided.

Furthermore, by embedding the heat dissipation bump in the coating layer, the heat energy from the electronic component can be guided to the second circuit layer through the heat dissipation bump and dissipated to the outside, so as to effectively ensure the heat dissipation capacity of the electronic package. Therefore, when the electronic package wants to meet the demand for miniaturization, the electronic package is suitable for the design of thinning the insulation layer, and will not bend due to high temperature environment (or thermal cycle).

In addition, since the insulating protective layer has a filler material to enhance its toughness, if the insulating layer needs to be thinned, the reinforcing design of the insulating protective layer can be used as a supporting structure to prevent the electronic package from warping due to factors such as shrinkage due to stress or asymmetrical construction.

1:Semiconductor packages

10: Packaging substrate

100: Dielectric layer

101: Circuit layer

11: Solder bumps

12: Semiconductor chip

13,23: Coating layer

15: Core insulation layer

2,3: Electronic packaging

2a: Packaging module

20: Carrier substrate

200: Conductive bump

201: Heat dissipation bump

21: Adhesive layer

22,32: Electronic components

22a: Action surface

22b: Non-active surface

220:Electrode pad

23a: First surface

23b: Second surface

230,231: Blind hole

24: First circuit layer

240,241: Conductor

25: Circuit structure

250: Insulation layer

251,252: Second circuit layer

28: Insulation protective layer

280: Opening

29: Conductive element

341: Conductor

80: Tape

9: Carrier

90: Peeling layer

A: Crystal placement area

Figure 1 is a schematic cross-sectional view of a conventional semiconductor package.

Figures 2A to 2H are cross-sectional schematic diagrams of the manufacturing method of the electronic package of the present invention.

Figure 2H-1 is a cross-sectional schematic diagram of another embodiment of Figure 2H.

FIG3 is a cross-sectional schematic diagram of another embodiment of FIG2H.

The following is a specific and concrete example to illustrate the implementation of the present invention. People familiar with this technology can easily understand other advantages and effects of the present invention from the content disclosed in this manual.

It should be noted that the structures, proportions, sizes, etc. depicted in the drawings attached to this specification are only used to match the contents disclosed in the specification for understanding and reading by people familiar with this technology, and are not used to limit the restrictive conditions for the implementation of the present invention. Therefore, they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "above", "first", "second", "one" etc. used in this specification are only for the convenience of description and are not used to limit the scope of implementation of the present invention. Changes or adjustments in their relative relationships shall also be regarded as the scope of implementation of the present invention without substantially changing the technical content.

Figures 2A to 2H are cross-sectional schematic diagrams of the manufacturing method of the electronic package 2 of the present invention.

As shown in FIG. 2A , a carrier 9 is provided to respectively set a carrier substrate 20 on two opposite sides thereof, wherein the carrier substrate 20 has a plurality of adjacent conductive bumps 200 and a die-plating area A, and the die-plating area A has at least one heat dissipation bump 201 arranged to space the conductive bumps 200. Then, an electronic component 22 is set on the heat dissipation bump 201 of the die-plating area A of the carrier substrate 20.

In this embodiment, the carrier 9 is a temporary removable core carrier, which can be a plate having metal layers on opposite sides, such as a copper foil substrate, and a peeling layer 90 is formed on its metal surface, so that the carrier substrate 20 is formed on the peeling layer 90.

Furthermore, the material forming the carrier substrate 20, the heat dissipation bump 201 and the conductive bump 200 is a metal material. For example, a copper plate is etched to integrally form the conductive bump 200 and the heat dissipation bump 201 on the carrier substrate 20. It should be understood that additional bumps can also be added to the carrier substrate 20, such as by electroplating or pasting, without any special restrictions.

Furthermore, the electronic component 22 is an active component, a passive component or a combination of the two, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor or an inductor. For example, if the electronic component 22 is a semiconductor chip, it has an active surface 22a and an inactive surface 22b opposite to each other, the active surface 22a has a plurality of electrode pads 220, and the electronic component 22 is bonded to the heat sink 201 with its inactive surface 22b through an adhesive layer 21.

In addition, the adhesive layer 21 can be a heat dissipation adhesive material, such as silicon oxide (SiO ₂ ) or metal adhesive, so as to facilitate heat transfer from the electronic component 22 to the heat dissipation bump 201 .

As shown in FIG. 2B , a coating layer 23 is formed on the carrier substrate 20 to cover the conductive bump 200 , the heat dissipation bump 201 , the electronic component 22 and the adhesive layer 21 . Then, a plurality of blind holes 230 are formed on the coating layer 23 to expose each of the conductive bumps 200 .

In this embodiment, the cladding layer 23 has a first surface 23a and a second surface 23b opposite to each other, so that the cladding layer 23 is bonded to the carrier substrate 20 with its second surface 23b, and a plurality of blind holes 230 exposing the conductive bumps 200 are formed on the first surface 23a of the cladding layer 23. For example, the blind holes 230 are formed by laser or other methods.

Furthermore, the electrode pad 220 may also be exposed on the first surface 23a of the cladding layer 23. For example, blind holes 231 may be formed at the locations corresponding to the electrode pads 220 by laser or other methods, so that the blind holes 231 expose the electrode pads 220. Alternatively, the electrode pad 220 may be made flush with the first surface 23a of the cladding layer 23 by a leveling process, such as grinding, so that the electrode pad 220 is exposed.

In addition, the material forming the coating layer 23 is an insulating material, such as polyimide (PI), dry film, epoxy molding compound (EMC) or other packaging materials, which can be formed on the carrier substrate 20 by lamination or molding.

As shown in FIG. 2C , conductors 240 , 241 are formed in the blind holes 230 , 231 , and a first circuit layer 24 is formed on the conductors 240 , 241 and on the first surface 23a of the cladding layer 23 to form a package module 2a , so that the first circuit layer 24 is electrically connected to each of the conductive bumps 200 and each of the electrode pads 220 through the conductors 240 , 241 .

In this embodiment, the conductors 240, 241 and the first circuit layer 24 are manufactured together by a patterned electroplating process, so that the first circuit layer 24 and the conductors 240, 241 are formed as one piece.

As shown in FIG. 2D , the carrier 9 and the package module 2a are separated by the peeling layer 90, and then the carrier substrate 20 is removed by etching or other methods to obtain a plurality of package modules 2a and expose the second surface 23b of the encapsulation layer 23.

In this embodiment, the package module 2a retains the conductive bump 200 and the heat dissipation bump 201, so that the conductive bump 200 and the heat dissipation bump 201 are exposed on the second surface 23b of the encapsulation layer 23.

As shown in FIG. 2E , the package modules 2a are symmetrically formed on opposite sides of a support member 8 by pressing, and the package module 2a is pressed onto the support member 8 with its first circuit layer 24.

In this embodiment, the support member 8 has a tape 80, so that the tape 80 covers the first circuit layer 24, so that the first circuit layer 24 is embedded in the tape 80, and the second surface 23b of the covering layer 23 of the packaging module 2a faces outward.

As shown in FIG. 2F , a circuit structure 25 is formed on the second surface 23b of the encapsulation layer 23 of each package module 2a.

In this embodiment, the circuit structure 25 includes at least one insulating layer 250 formed on the cladding layer 23, and second circuit layers 251, 252 formed on the insulating layer 250, so that the second circuit layers 251, 252 are electrically connected to the conductive bump 200 and the heat sink bump 201. For example, the second circuit layers 251, 252 are manufactured by electroplating metal (such as copper) or other methods using a build-up process. It should be understood that, using the build-up process, the circuit structures 25 can add multiple insulating layers as needed to manufacture multiple circuit layers.

Furthermore, the material forming the insulating layer 250 is Bismaleimide triazine (BT) or Ajinomoto build-up film (ABF), which is different from the material forming the coating layer 23. For example, if the insulating layer 250 is BT, its coefficient of thermal expansion (CTE) is 10~15ppm/℃, and if the coating layer 23 is EMC material, its CTE is 6~10ppm/℃, so the strength of the insulating layer 250 is strong enough to avoid the problem of warping caused by uneven distribution of thermal stress.

As shown in FIG. 2G , the support member 8 and the tape 80 are removed to obtain a plurality of electronic packages 2.

In this embodiment, before or after removing the support member 8 and the tape 80, an insulating protection layer 28 such as a solder mask can be formed on the outermost insulating layer 250 of the circuit structure 25 as required, as shown in Figure 2H, and a portion of the surface of the second circuit layer 251, 252 is exposed for bonding a conductive element 29 such as a solder ball. For example, the CTE of the insulating protective layer 28 is less than 20 ppm/°C, and the insulating protective layer 28 has a filler such as alumina (Al ₂ O ₃ ), aluminum hydroxide (Al(OH) ₃ ) or other polymers such as P-compound, so that the insulating protective layer 28 can meet the wiring requirements of the fine line/fine space (L/S) of the circuit structure 25 .

Furthermore, since the solder mask has a filler composition, the insulating protective layer 28 can be strengthened to enhance its toughness. Therefore, when the circuit structure 25 has only a single insulating layer 250, as shown in FIG. 2H-1, the insulating protective layer 28 supports the insulating layer 250, thereby preventing the electronic package 2 from warping due to factors such as shrinkage or asymmetrical construction.

Therefore, if the insulating layer 250 needs to be thinned, the insulating protective layer 28 can prevent the electronic package 2 from warping, so that the insulating layer 250 can be thinned as much as possible, so that the electronic package 2 can simultaneously meet the requirements of thinning and avoiding warping.

Furthermore, the conductive element 29 is electrically connected to the conductive bump 200 via the second circuit layer 251, and the second circuit layer 252 electrically connected to the heat sink bump 201 may not be combined with the conductive element 29, such as at the opening 280 of the insulating protection layer 28.

In addition, in other embodiments, such as the electronic package 3 shown in FIG. 3 , the electronic component 32 can be electrically connected to the electrode pad 220 and the conductive bump 200 by the wire 341 by wire bonding, so that the related process of the conductor 241 can be omitted. It should be understood that in other embodiments (not shown), the electronic component can also be electrically connected to the heat sink bump by a wire.

Therefore, the manufacturing method of the present invention mainly embeds the electronic components 22, 32 in the coating layer 23 to save the use space on the first surface 23a of the coating layer 23, thereby facilitating the thinning of the electronic package 2, 3. Therefore, compared with the prior art, the manufacturing method of the present invention can thin the electronic package 2, 3 to meet the needs of miniaturization.

Furthermore, by combining the electronic components 22, 32 with the adhesive layer 21, the conventional flip chip solder bumps 11 and their reflow process are replaced. Therefore, when the electronic packages 2, 3 meet the requirements of miniaturization, the risk of warping caused by high temperature environment (or thermal cycle) can be effectively reduced. Furthermore, by using the carrier 9 and the support 8 to perform two symmetrical pressing operations, the problem of warping during the manufacturing process of the electronic packages 2, 3 can be avoided.

Furthermore, by embedding the heat dissipation bump 201 in the coating layer 23, the heat dissipation path can be optimized to enhance the heat dissipation effect. Therefore, when the electronic package 2, 3 is to meet the demand for miniaturization, the electronic package 2, 3 is suitable for the design of thinning the insulating layer 250, and will not bend due to high temperature environment (or thermal cycle).

In addition, the heat energy from the electronic component 22 can be guided to the opening 280 corresponding to the second circuit layer 252 through the heat dissipation bump 201 and dissipated to the outside, so as to effectively ensure the heat dissipation capacity of the electronic package 2, 3.

The present invention further provides an electronic package 2,3, comprising: a coating layer 23, a first circuit layer 24, at least one heat dissipation bump 201, at least one electronic component 22,32 and a circuit structure 25.

The coating layer 23 has a first surface 23a and a second surface 23b opposite to each other.

The first circuit layer 24 is formed on the first surface 23a of the cladding layer 23.

The heat dissipation bump 201 is embedded in the second surface 23b of the coating layer 23.

The electronic components 22, 32 are embedded in the coating layer 23 and disposed on the heat dissipation bump 201.

The circuit structure 25 is formed on the second surface 23b of the cladding layer 23, wherein the circuit structure 25 includes at least one insulating layer 250 formed on the cladding layer 23, and second circuit layers 251, 252 formed on the insulating layer 250, so that the second circuit layer 252 is electrically connected to the heat dissipation bump 201, so that the electronic components 22, 32 are heat-dissipated through the second circuit layer 252 and the heat dissipation bump 201, and the material forming the insulating layer 250 is Bismaleimide triazine (BT) or Ajinomoto build-up film (ABF).

In one embodiment, a plurality of conductive bumps 200 are embedded in the second surface 23b of the cladding layer 23, so that the first circuit layer 24 is electrically connected to the plurality of conductive bumps 200 via the conductor 240. For example, the electronic element 32 is electrically connected to the conductive bump 200 via the wire 341.

In one embodiment, the electronic components 22, 32 are bonded to the heat sink 201 via an adhesive layer 21.

In one embodiment, the electronic package 2, 3 further includes an insulating protective layer 28 formed on the circuit structure 25, and partially exposes the surface of the second circuit layer 251, 252, wherein the insulating protective layer 28 has a filling material.

In summary, the electronic package and its manufacturing method of the present invention embeds the electronic component in the coating layer to save the space on the first surface of the coating layer, thereby facilitating the thinning of the electronic package. Therefore, the manufacturing method of the present invention can thin the electronic package to meet the needs of miniaturization.

Furthermore, by combining the electronic components with the adhesive layer, the conventional flip chip solder bumps and their reflow process are replaced. Therefore, when the electronic package meets the requirements of miniaturization, the risk of warping caused by high temperature environment (or thermal cycle) can be effectively reduced. Furthermore, by using the carrier and the support, two symmetrical pressing operations are performed to avoid the problem of warping in the process of manufacturing the electronic package.

Furthermore, by embedding the heat dissipation bump in the coating layer, the heat dissipation path can be optimized to enhance the heat dissipation effect. Therefore, when the electronic package is to meet the demand for miniaturization, the electronic package is suitable for the design of thinning the insulation layer, and will not warp due to high temperature environment (or thermal cycle).

In addition, the heat energy from the electronic component can be guided to the opening corresponding to the second circuit layer through the heat dissipation bump and dissipated to the outside, so as to effectively ensure the heat dissipation capacity of the electronic package.

The above embodiments are used to illustrate the principles and effects of the present invention, but are not used to limit the present invention. Anyone familiar with this technology can modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the scope of the patent application described below.

2: Electronic packaging components

200: Conductive bump

201: Heat dissipation bump

21: Adhesive layer

22: Electronic components

23: Coating layer

23a: First surface

23b: Second surface

24: First circuit layer

240,241: Conductor

25: Circuit structure

250: Insulation layer

251,252: Second circuit layer

28: Insulation protective layer

280: Opening

29: Conductive element

Claims (5)

A method for manufacturing an electronic package comprises: arranging a carrier substrate on two opposite sides of a carrier, wherein the carrier substrate has at least one heat dissipation bump; arranging an electronic component on the heat dissipation bump; forming a coating layer on the carrier substrate to cover the heat dissipation bump and the electronic component, wherein the coating layer has a first surface and a second surface opposite to each other, so that the coating layer is bonded to the carrier substrate with its second surface; forming a first circuit layer on the first surface of the coating layer to form a packaging module; removing the carrier and the carrier substrate to obtain a plurality of the packaging modules and exposing the second surface of the coating layer, wherein the packaging module retains the heat dissipation bump. The heat dissipation protrusion is exposed on the second surface of the coating layer; the packaging modules are respectively arranged on opposite sides of a support member, and each packaging module is pressed onto the support member with its first circuit layer so that the second surface of the coating layer faces outward; a circuit structure is formed on the second surface of the coating layer, wherein the circuit structure includes at least one shaped An insulating layer is formed on the coating layer, and a second circuit layer is formed on the insulating layer, so that the second circuit layer is electrically connected to the heat dissipation bump, so that the electronic component dissipates heat through the second circuit layer and the heat dissipation bump, and the material forming the insulating layer is bis(succinic acid) imide/trinitrogen trap or azobenzene build-up film; and the support is removed. The method for manufacturing an electronic package as described in claim 1, wherein the carrier substrate further has a plurality of conductive bumps, so that the second surface of the encapsulation layer is embedded with the plurality of conductive bumps, so that the first circuit layer is electrically connected to the plurality of conductive bumps through a conductive body. A method for manufacturing an electronic package as described in claim 1, wherein the electronic component is electrically connected to the conductive bump via a wire. A method for manufacturing an electronic package as described in claim 1, wherein the electronic component is bonded to the heat sink bump via an adhesive layer. The method for manufacturing an electronic package as described in claim 1 further includes forming an insulating protective layer on the circuit structure, and the insulating protective layer exposes a portion of the surface of the second circuit layer, wherein the insulating protective layer has a filling material.

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