TWI855809B - Flyback converter power supply and synchronous rectification controller thereof - Google Patents

Abstract

A flyback converter power supply and a synchronous rectification controller thereof are provided. The flyback converter power supply includes a transformer and a synchronous rectification transistor. The synchronous rectification controller is configured to: in a current switching cycle of the synchronous rectification transistor, when the synchronous rectification transistor changes from the on state to the off state, determine whether the synchronous rectification transistor changes from the on state to the off state within a first predetermined time period starting from the moment when the secondary winding of the transformer starts to demagnetize; When the rectifier transistor changes from the on state to the off state within the first predetermined time period, if the duration of the drain voltage of the synchronous rectifier transistor being less than the synchronous rectifier turn-on threshold value from the moment when the synchronous rectifier transistor changes from the on state to the off state to the end moment of the first predetermined time period is greater than the first predetermined threshold value, the synchronous rectifier transistor is controlled to change from the off state to the on state.

Description

Flyback converter power supply and synchronous rectification controller thereof

The present invention relates to the field of circuits, and more specifically to a flyback converter power supply and a synchronous rectification controller thereof.

A switching power supply, also known as an alternating current power supply or a switching converter, is a type of power supply. The function of a switching power supply is to convert a certain range of input voltage into the voltage or current required by the user through different forms of architecture (for example, flyback architecture, buck architecture, or boost architecture, etc.).

According to an embodiment of the present invention, a synchronous rectifier controller for a flyback converter power supply, wherein the flyback converter power supply includes a transformer and a synchronous rectifier transistor, and the synchronous rectifier controller is configured to: in the current switching cycle of the synchronous rectifier transistor: when the synchronous rectifier transistor changes from the on state to the off state, determine whether the synchronous rectifier transistor changes from the on state to the off state within a first predetermined time period starting from the moment when the secondary winding of the transformer starts to demagnetize, wherein the duration of the first predetermined time period is equal to the duration of the synchronous rectifier transistor. The first predetermined ratio of the demagnetization time of the secondary winding of the transformer in the current switching cycle; and when the synchronous rectifier transistor changes from the on state to the off state within the first predetermined time period, if the duration of the drain voltage of the synchronous rectifier transistor being less than the synchronous rectifier turn-on threshold value from the moment when the synchronous rectifier transistor changes from the on state to the off state to the end moment of the first predetermined time period is greater than the first predetermined threshold value, the synchronous rectifier transistor is controlled to change from the off state to the on state, otherwise the synchronous rectifier transistor is kept in the off state.

100: Switch the power on or off

200,600: Synchronous Rectification (SR) Controller

900: Drive self-recovery control module

AND1,AND2: AND gate

autor: drive self-recovery control signal

AVDD: chip internal power supply

C:Integral capacitance

Comp_off: Synchronous Rectification (SR) turns off the comparator

Comp_on: Synchronous rectification (SR) turns on the comparator

Cout: output capacitance

Cr: resonant capacitor

dff1,dff2:D trigger

Gate: Gate control signal

Gate1(n): The gate control signal corresponds to the part of Isec1(n)

Ichar: Charging current

Idis: discharge current

INV1, INV2, INV3: Inverter

iref: reference current

Isec: current

Isec1(n),Isec2(n): switching cycle

K1: The first predetermined ratio

K2: Second predetermined ratio

min_ton: minimum on-time control signal

MNH: High voltage switch

MS: High voltage transistor (synchronous rectification (SR) transistor)

NAND1: NAND gate

NOR1, NOR2: NOR gate

off det: turn off condition detection signal

on ctrl: rectifier on control signal

on det: turn on condition detection signal

Q1, Q2: high voltage transistors

R: Predetermined resistance value

Rcs: Detection resistor

reset: low pulse trigger to emit electrical signal

S502, S504, S506, S508, S510, S512, S514, S516, S518: Steps

samp: sampling signal

sampi: the sampling signal is reflected

sr: synchronous rectification switch signal

srg: transistor control signal

srg_pre: Transistor pre-stage logic control signal

T: Transformer

Tdem(n): Demagnetization time of the secondary winding of transformer T

Th: first predetermined threshold

Ton-min: minimum on-time

tref: second predetermined threshold

ts,Tonp(n),Tsamp(n): time

turn off: synchronous rectification turn off signal

turn on: synchronous rectification turn-on signal

Vd, Vd(n), Vd(n-1): drain voltage

Vd_in: drain voltage characteristic signal

Vdp(n),Vdp(n-1):Vd platform voltage

Vout, Vout(n): system output voltage

vramp: voltage

vref: reference voltage

Vt(off): Synchronous rectification turn-off threshold

Vt(on): Synchronous rectification turn-on threshold

Vt(reg): Vd voltage adjustment value

Vt(slp): Vd slope timing starting voltage

△T: scheduled time increment

The present invention can be better understood from the following description of the specific implementation of the present invention in conjunction with the drawings, wherein:

FIG1 shows a schematic diagram of the system structure of a flyback converter power supply according to an embodiment of the present invention.

FIG2 shows a schematic diagram of the circuit structure of a conventional synchronous rectification controller that can be used in the switching power supply shown in FIG1.

FIG3 shows the timing waveforms of multiple signals when the synchronous rectification is normally turned on and off when the switching power supply shown in FIG1 adopts the synchronous rectification controller shown in FIG2.

FIG4 shows the timing waveforms of multiple signals when the synchronous rectification is abnormally turned on and off when the switching power supply shown in FIG1 adopts the synchronous rectification controller shown in FIG2.

FIG5 shows a flow chart of an example control process executed when the synchronous rectification controller according to an embodiment of the present invention is used in the switching power supply shown in FIG1.

FIG6 shows a schematic diagram of an example circuit structure of a synchronous rectification controller according to an embodiment of the present invention.

Figures 7 and 8 show the timing waveforms of multiple signals when the switching power supply shown in Figure 1 adopts the synchronous rectification controller shown in Figure 6.

FIG9 shows an example implementation circuit diagram of the drive self-recovery control module shown in FIG6.

The features and exemplary embodiments of various aspects of the present invention are described in detail below. In the detailed description below, many specific details are set forth in order to provide a comprehensive understanding of the present invention. However, it is obvious to a person skilled in the art that the present invention can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present invention by illustrating examples of the present invention. The present invention is in no way limited to any specific configuration and algorithm set forth below, but covers any modification, substitution and improvement of elements, components and algorithms without departing from the spirit of the present invention. In the drawings and the following description, well-known structures and techniques are not shown in order to avoid unnecessary ambiguity of the present invention.

FIG1 shows a schematic diagram of the circuit structure of a flyback converter power supply according to an embodiment of the present invention. In the switching power supply 100 shown in FIG1 , T is a transformer, Q1, Q2, and MS are high voltage transistors (e.g., high voltage metal oxide semiconductor field effect transistors), Rcs is a detection resistor, Cr is a resonant capacitor, and Cout is an output capacitor; a synchronous rectification (SR) controller and an SR transistor MS together constitute a synchronous rectifier, which is used to replace a traditional Schottky rectifier diode. Since the SR transistor MS has a relatively low conduction voltage drop, it can effectively reduce the thermal loss of the system (reducing thermal loss can improve system efficiency) and increase the output current capability of the system, so the synchronous rectifier is widely used in large output current systems. Generally, as the input/output voltage and load change, the switching power supply 100 shown in FIG1 can operate in critical conduction mode (CRM), zero voltage-resonant valley switching (ZV-RVS) mode, or burst mode.

FIG2 shows a circuit structure diagram of a conventional SR controller that can be used in the switching power supply shown in FIG1. In the SR controller 200 shown in FIG2, the voltage regulator module generates the chip internal power supply AVDD based on the drain voltage Vd of the SR transistor MS/the system output voltage Vout of the switching power supply 100; the voltage/current reference module generates the reference voltage vref and the reference current iref based on the chip internal power supply AVDD; the high voltage switch MNH generates the drain voltage characteristic signal Vd_in based on the drain voltage Vd of the SR transistor MS; the SR turn-on comparator Comp_on generates the turn-on condition detection signal on based on the drain voltage characteristic signal Vd_in and the synchronous rectification turn-on threshold Vt(on) det; the SR off comparator Comp_off generates an off condition detection signal off det based on the drain voltage characteristic signal Vd_in and the synchronous rectification off threshold Vt(off); the SR on control module generates a rectifier on control signal on ctrl based on the drain voltage Vd of the SR transistor MS and the synchronous rectification switch signal sr; the minimum on time control module generates a minimum on time control signal min_ton for controlling the minimum on time Ton-min of the SR transistor MS based on the synchronous rectification switch signal sr (the SR transistor MS is always in the on state and cannot change from the on state to the off state within the minimum on time Ton-min); the NOR gate NOR1 generates a rectifier on control signal on based on the on condition detection signal on det and the rectification on control signal on ctrl generates a synchronous rectification turn-on signal; the NOR gate NOR2 generates a synchronous rectification turn-off signal based on the off condition detection signal off det and the minimum on-time control signal min_ton; the latch module generates a synchronous rectification switch signal sr based on the synchronous rectification turn-on signal and the synchronous rectification turn-off signal; the driver module generates a gate control signal Gate for controlling the on and off of the SR transistor MS based on the synchronous rectification switch signal sr.

FIG3 shows the timing waveforms of multiple signals when the synchronous rectification is normally turned on and off when the switching power supply shown in FIG1 adopts the SR controller shown in FIG2. In FIG3, Isec represents the current flowing through the SR transistor MS, Vd represents the drain voltage of the SR transistor MS, Gate represents the gate control signal used to control the on and off of the SR transistor MS, Vdp(n) represents the Vd platform voltage of the current switching cycle of the SR transistor MS, and Vt(slp) represents the Vd slope timing starting voltage (for example, 0.75‧Vdp(n-1) , i.e. 0.75 times the Vd platform voltage of the previous switching cycle of the SR transistor MS), Vt(on) represents the synchronous rectification on threshold (e.g., -200mV), Vt(reg) represents the Vd voltage adjustment value (e.g., -30mV), Vt(off) represents the synchronous rectification off threshold (e.g., 0mV), and ts represents the time for Vd to drop from Vt(slp) to Vt(on). The conduction conditions of the SR transistor MS include (1) ts < tref (e.g., 100ns), (2) Vd < Vt(on), and the SR transistor MS changes from the off state to the on state only when conditions (1) and (2) are met at the same time.

In the switching power supply shown in Figure 1, when the switching frequency of the high voltage transistor Q1/Q2 is lower than the resonant frequency of the resonant circuit composed of the resonant capacitor Cr and the primary winding of the transformer T, the current flowing through the secondary winding of the transformer T (i.e., the current flowing through the SR transistor MS) is sometimes divided into two parts. In the case of using the SR controller shown in Figure 2, the SR transistor MS changes from the off state to the on state only when the first part of the current flows and cannot change from the off state to the on state again when the second part of the current flows after changing from the on state to the off state, which will lead to a loss of system efficiency. In addition, when the output voltage is low and the load is light, the duration of the front part of the current is less than the minimum on-time Ton-min of the SR transistor MS. Due to the limitation of the minimum on-time Ton-min, the SR transistor MS cannot change from the on state to the off state in time, which will cause the output current to reverse and be injected into the primary side through the transformer winding, causing a spike voltage on the drain voltage Vd of the SR transistor MS and resulting in system efficiency loss.

FIG4 shows the timing waveforms of multiple signals when the synchronous rectification is abnormally turned on and off when the switching power supply shown in FIG1 adopts the SR controller shown in FIG2. In FIG4, Isec represents the current flowing through the SR transistor MS, which is divided into two parts, Isec1(n) and Isec2(n), in one switching cycle of the SR transistor MS; Vd represents the drain voltage of the SR transistor MS; Gate represents the gate control signal used to control the on and off of the SR transistor MS; min_ton represents the minimum on time control signal used to control the minimum on time Ton-min of the SR transistor MS. As can be seen from FIG4 , there are two problems: First, in each switching cycle of the SR transistor MS, after the SR transistor MS changes from the on state to the off state, the drain voltage Vd of the SR transistor MS no longer satisfies the on condition of the SR transistor MS, and the gate control signal Gate only includes the part Gate1(n) corresponding to Isec1(n) but not the part corresponding to Isec2(n). Isec2(n) flows through the body diode of the SR transistor MS, and the SR transistor MS is turned off. The large voltage drop of the body diode of the crystal MS will lead to system efficiency loss; secondly, due to the limitation of the minimum on-time Ton-min of the SR transistor MS, the gate control signal Gate cannot change in time with it when Isec1(n) becomes zero, so that the SR transistor MS cannot change from the on state to the off state in time, and Isec1(n) flows in the reverse direction and is injected into the primary side, generating a spike voltage on the drain voltage Vd of the SR transistor MS and causing system efficiency loss.

In view of one or more of the above problems, an SR controller according to an embodiment of the present invention that can be used in the switching power supply 100 shown in FIG1 is proposed. The SR controller according to the embodiment of the present invention can be configured to: in the current switching cycle of the SR transistor MS: when the SR transistor MS changes from the on state to the off state, determine whether the SR transistor MS changes from the on state to the off state within a first predetermined time period starting from the moment when the secondary winding of the transformer T starts to demagnetize, wherein the duration of the first predetermined time period is equal to a first predetermined proportion K1 (for example, K1 ) of the demagnetization time Tdem(n) of the secondary winding of the transformer T in the current switching cycle of the SR transistor MS. =0.75); when the SR transistor MS changes from the on state to the off state within the first predetermined time period, if the duration of the drain voltage Vd(n) of the SR transistor MS being less than the synchronous rectification turn-on threshold Vt(on) from the moment when the SR transistor MS changes from the on state to the off state to the end moment of the first predetermined time period is greater than the first predetermined threshold Th (for example, Th=200ns), the SR transistor MS is controlled to change from the off state to the on state, otherwise the SR transistor MS is kept in the off state.

In other words, the SR controller according to the embodiment of the present invention can be configured to perform driving self-recovery control of the SR transistor MS when the SR transistor MS changes from the on state to the off state during the current switching cycle of the SR transistor MS. Specifically, in the current switching cycle of the SR transistor MS, if the SR transistor MS changes from the on state to the off state within the K1‧Tdem(n) time starting from the moment when the secondary winding of the transformer T starts to demagnetize and the duration of the drain voltage Vd(n) of the SR transistor MS being less than the synchronous rectification turn-on threshold Vt(on) (i.e., Vd(n)<Vt(on)) from the moment when the SR transistor MS changes from the on state to the off state is greater than the first predetermined threshold Th, the SR transistor MS is controlled to change from the off state to the on state, otherwise the SR transistor MS is kept in the off state.

In some embodiments, the SR controller according to the embodiment of the present invention is further configured to keep the SR transistor MS in the off state in the current switching cycle of the SR transistor MS when the SR transistor MS changes from the on state to the off state at other times other than the first predetermined time period.

In some embodiments, the SR controller according to the embodiment of the present invention is further configured to obtain the demagnetization time Tdem(n) of the secondary winding of the transformer T based on the drain voltage Vd(n) of the SR transistor MS and the system output voltage Vout(n) of the switching power supply 100 in the current switching cycle of the SR transistor MS by using the inductor volt-second balance principle.

In some embodiments, the SR controller according to the embodiment of the present invention is further configured to allow the SR transistor MS to change from the off state to the on state in the current switching cycle of the SR transistor MS: when the drain voltage Vd(n) of the SR transistor MS is less than the synchronous rectification turn-on threshold Vt(on) and the time ts from the slope timing start voltage Vt(slp) to the synchronous rectification turn-on threshold Vt(on) is less than the second predetermined threshold tref, wherein the slope timing start voltage Vt(slp) is a second predetermined ratio K2 of the drain voltage Vd of the SR transistor MS to the plateau voltage Vdp(n-1) in the previous switching cycle (i.e., Vt(slp)=Vdp(n-1)‧K2).

In some embodiments, the SR controller according to the embodiment of the present invention is further configured to: determine in the current switching cycle of the SR transistor MS: whether the sum of the duration of the SR transistor MS being in the on state and the duration of the drain voltage Vd(n-1) of the SR transistor MS being less than the synchronous rectification turn-on threshold Vt(on) in the second predetermined time period starting from the moment when the secondary winding of the transformer T starts to demagnetize in the previous switching cycle of the SR transistor MS is greater than the minimum on time Ton-min of the SR transistor MS, wherein the duration of the second predetermined time period is equal to the sum of the minimum on time Ton-min of the SR transistor MS and the predetermined time period. The sum of the time increment △T; if the sum of the duration of the SR transistor MS in the on state and the duration of the drain voltage Vd(n-1) of the SR transistor MS being less than the synchronous rectification turn-on threshold Vt(on) in the second predetermined time period is not greater than the minimum on time Ton-min of the SR transistor MS, then from the moment when the drain voltage Vd(n) of the SR transistor MS drops to the synchronous rectification turn-on threshold Vt(on), the SR transistor MS is controlled to change from the off state to the on state after the minimum on time Ton-min of the SR transistor MS is delayed, otherwise the SR transistor MS is controlled to change from the off state to the on state without time delay.

In some embodiments, the SR controller according to the embodiment of the present invention is further configured to control the SR transistor MS from the on state to the off state in the current switching cycle of the SR transistor MS: when the duration of the SR transistor MS in the on state is greater than or equal to the minimum on time Ton-min of the SR transistor MS and the drain voltage Vd(n) of the SR transistor MS is greater than the synchronous rectification off threshold Vt(off).

FIG5 is a flow chart showing an example control process executed when the SR controller according to an embodiment of the present invention is used in the switching power supply shown in FIG1. As shown in FIG5 , an exemplary control process executed when the SR controller according to an embodiment of the present invention is used in the switching power supply shown in FIG1 includes: step S502, detecting the drain voltage Vd(n) of the SR transistor MS, and allowing the SR transistor MS to change from the off state to the on state when the drain voltage Vd(n) of the SR transistor MS satisfies the on conditions (1) and (2) described in conjunction with FIG3 ; step S504, determining whether the duration of the on state of the SR transistor MS during the last switching cycle of the SR transistor MS within the time (Ton-min+△T) from the moment when the secondary winding of the transformer T starts to demagnetize is equal to the duration of the on state of the SR transistor MS during the time (Ton-min+△T) from the moment when the secondary winding of the transformer T starts to demagnetize. Whether the sum of the durations during which the drain voltage Vd(n-1) of the SR transistor MS is less than the synchronous rectification turn-on threshold Vt(on) is greater than the minimum on-time Ton-min of the SR transistor MS; if the judgment result of step S504 is yes, then turn to step S506, and control the SR transistor MS from the off state to the on state without time delay; if the judgment result of step S504 is no, then turn to step S508, and control the minimum on-time Ton-min of the SR transistor MS after delaying from the moment when the drain voltage Vd(n) of the SR transistor MS drops to the synchronous rectification turn-on threshold Vt(on), SR transistor MS changes from the off state to the on state; step S510, when the drain voltage Vd(n) of SR transistor MS is greater than the synchronous rectification off threshold Vt(off) and the duration of SR transistor MS in the on state is greater than or equal to the minimum on time Ton-min, control SR transistor MS to change from the on state to the off state; step S512, determine whether SR transistor MS changes from the on state to the off state within the K1‧Tdem(n) time starting from the moment when the secondary winding of transformer T starts to demagnetize; if the determination result of step S512 is yes, turn to step S514 to determine whether the SR transistor MS changes from the on state to the off state within the K1‧Tdem(n) time starting from the moment when the secondary winding of transformer T starts to demagnetize. Whether the duration of the drain voltage Vd(n) of SR transistor MS being less than the synchronous rectification on threshold Vt(on) from the moment when SR transistor MS changes from on state to off state is greater than Th within the time K1‧Tdem(n) starting from the moment when the secondary winding of device T starts to demagnetize is greater than Th; if the judgment result of step S512 is no, then turn to step S516 to keep SR transistor MS in off state; if the judgment result of step S514 is yes, then turn to step S518 to control SR transistor MS from off state to on state; if the judgment result of step S514 is no, then turn to step S516.

FIG6 is a schematic diagram showing an exemplary circuit structure of an SR controller according to an embodiment of the present invention. In the SR controller 600 shown in FIG6 , a synchronous rectification on signal turn on is generated based on the drain voltage Vd of the SR transistor MS, the synchronous rectification on threshold Vt(on), and the synchronous rectification switch signal sr; a synchronous rectification off signal turn off is generated based on the drain voltage Vd of the SR transistor MS, the synchronous rectification off threshold Vt(off), and the synchronous rectification switch signal sr; a synchronous rectification switch signal sr and a transistor control signal srg are generated based on the drain voltage Vd of the SR transistor MS, the synchronous rectification on signal turn on, and the synchronous rectification off signal turn off; and a gate control signal Gate for controlling the on and off of the SR transistor MS is generated based on the transistor control signal srg.

In some embodiments, as shown in FIG6 , the high voltage switch MNH generates a drain voltage characteristic signal Vd_in based on the drain voltage Vd of the SR transistor MS; the SR turn-on comparator Comp_on generates a turn-on condition detection signal on det based on the drain voltage characteristic signal Vd_in and the synchronous rectification turn-on threshold Vt(on); the SR turn-on control module generates a rectification turn-on control signal on ctrl based on the drain voltage Vd of the SR transistor MS and the synchronous rectification switch signal sr; the negative OR gate NOR1 generates a synchronous rectification turn-on signal turn on based on the turn-on condition detection signal on det and the rectification turn-on control signal on ctrl.

In some embodiments, as shown in FIG6 , the high voltage switch MNH generates a drain voltage characteristic signal Vd_in based on the drain voltage Vd of the SR transistor MS; the SR off comparator Comp_off generates a turn-off condition detection signal off det based on the drain voltage characteristic signal Vd_in and the synchronous rectification turn-off threshold Vt(off); the minimum on-time control module generates a minimum on-time control signal min_ton for controlling the minimum on-time Ton-min of the SR transistor MS based on the synchronous rectification switch signal sr; the NOR gate NOR2 generates a synchronous rectification turn-off signal turn off based on the turn-off condition detection signal off det and the minimum on-time control signal min_ton.

In some embodiments, as shown in FIG6 , the driving self-recovery control module generates a synchronous rectification switch signal sr based on a synchronous rectification turn on signal and a synchronous rectification turn off signal, and generates a transistor control signal srg based on a drain voltage Vd of the SR transistor MS, a synchronous rectification turn on signal, a synchronous rectification turn off signal, and a synchronous rectification switch signal sr.

FIG7 and FIG8 show the timing waveforms of multiple signals when the switching power supply shown in FIG1 adopts the SR controller shown in FIG6. In FIG7 and FIG8, Isec represents the current flowing through the SR transistor MS, which is divided into two parts, Isec1(n) and Isec2(n), in one switching cycle of the SR transistor MS; Vd represents the drain voltage of the SR transistor MS; Gate represents the gate control signal for controlling the on and off of the SR transistor MS; on det represents the rectifier on detection signal; srg represents the transistor control signal; sr represents the synchronous rectifier switch signal; min_ton represents the minimum on time control signal; Ton-min represents the minimum on time of the SR transistor MS. It can be seen that in the nth switching cycle, the forward current duration of Isec1(n) is less than Ton-min, and the sum of the duration of srg at a high level and the duration of on det at a low level during the (Ton-min+△T) time is equal to Ton-min (the overlapping part is not calculated repeatedly), so in the (n+1)th switching cycle, Gate(n+1) will be shielded for a Ton-min time (that is, after a delay of Ton-min from the moment Vd(n) drops to Vt(on), the SR transistor MS is controlled to change from the off state to the on state). In Figure 7, since the forward current duration of Isec1(n+1) is less than Ton-min, Gate1(n+1) is completely shielded and Isec1(n+1) is not reversely injected. In Figure 8, since the forward current duration of Isec1(n+1) is greater than Ton-min, Gate1(n+1) is shielded for the Ton-min time and then released, and Isec1(n+1) is not reversely injected either. In the n/(n+1)th switching cycle, within the time K1‧Tdem(n)/K1‧Tdem(n+1), when Vd>Vt(off), srg changes from high level to low level, while sr remains at a high level. Isec2(n)/Isec2(n+1) current flows through the body diode of SR transistor MS. When the duration of Vd<Vt(on) is greater than Th, Gate2(n)/Gate2(n+1) outputs, causing SR transistor MS to change from off state to on state again.

FIG9 shows an example implementation circuit diagram of the driving self-recovery control module shown in FIG6. In the driving self-recovery control module 900 shown in FIG9, INV1, INV2, and INV3 are inverters, AND1 and AND2 are AND gates, NAND1 is an anti-AND gate, dff1 and dff2 are D triggers, C is an integral capacitor, vramp is the voltage on the integral capacitor C, reset is a low pulse trigger discharge signal, Ichar is a charging current related to the drain voltage Vd of the SR transistor MS and the system output voltage Vout, Idis is a discharge current related to the system output voltage Vout, and R is a predetermined resistance value (not shown in the figure).

In Figure 9, the charging current Ichar is the time for the integral capacitor C to charge, Tonp(n) (i.e., the pulse width of the drain voltage Vd(n) of the SR transistor MS), and the discharging current Idis is the time for the integral capacitor C to discharge, Tsamp(n). When the circuit is balanced, the charging voltage and the discharging voltage on the integral capacitor C are equal, i.e.

I _char . Tonp ( n ) _=Idis ． Tsamp ( n )(3)

Combining equations (1) to (3), we can obtain,

When the switching power supply shown in Figure 1 is working, according to the inductor volt-second balance principle,

( Vdp ( n ) -Vout ₎ ． Tonp ( n ) ₌ Vout ． Tdem ( n )(5)

Where Tdem(n) is the demagnetization time of the secondary winding of the transformer T in the current switching cycle of the SR transistor MS. Combining equations (4) and (5), we can get,

Tsamp ( n )= K1 . Tdem ( n )(6)

In the current switching cycle of the SR transistor MS, the sampling signal samp generated by the RS trigger is at a high level for a time equal to Tsamp(n).

When the synchronous rectification turn-on signal turns on from a low level to a high level, a falling edge is generated through INV1. After being input to AND1, AND1 also generates a falling edge. Therefore, dff1 and dff2 output high levels at the same time, that is, sr, srg_pre, and srg change from a low level to a high level at the same time, and the SR transistor MS changes from an off state to an on state; when the synchronous rectification turn-off signal turns off from a low level to a high level, it changes to a low level through INV2, setting the output of dff2 to a low level, that is, srg_pre changes from a high level to a low level, srg also changes from a high level to a low level, and the SR transistor MS changes from an on state to an off state. At the same time, the synchronous rectification shutdown signal turn off is input to NAND1. If the time when the synchronous rectification shutdown signal turn off changes from low level to high level is within the K1‧Tdem time starting from the moment when the secondary winding of the transformer T starts to demagnetize, sampi is low level, the output of NAND1 remains high level, and the output sr of dff1 does not change from high level to low level, but remains high level. Only when the sampi signal changes from low level to high level, the synchronous rectification shutdown signal turn off will be turned on. off to set the output of dff1 to a low level; therefore, when Isec2 rises again, this current flows through the body diode of the SR transistor MS and continues to flow, and Vd will drop below Vt(on) again. At this time, the self-recovery detection module is driven to compare Vd_in (equal to Vd at this time) with Vt(on) and count. If the duration of Vd<Vt(on) is greater than Th, and the During the K1‧Tdem time starting from the moment when the secondary winding of transformer T begins to demagnetize, the output autor of the self-recovery detection module will flip to a low level, AND1 will output a falling edge, and the output srg_pre of dff2 will flip to a high level. At this time, sr maintains a high level state, srg changes from a low level to a high level, and the SR transistor changes from the off state to the on state again.

The present invention may be implemented in other specific forms without departing from its spirit and essential features. For example, the algorithm described in a specific embodiment may be modified, and the system architecture does not depart from the basic spirit of the present invention. Therefore, the present embodiments are considered to be exemplary rather than restrictive in all aspects. The scope of the present invention is defined by the attached claims rather than the above description, and all changes that fall within the meaning and equivalent scope of the claims are therefore included in the scope of the present invention.

S502, S504, S506, S508, S510, S512, S514, S516, S518: Steps

Claims (10)

A synchronous rectifier controller for a flyback converter power supply, wherein the flyback converter power supply includes a transformer and a synchronous rectifier transistor, and the synchronous rectifier controller is configured to: in a current switching cycle of the synchronous rectifier transistor: when the synchronous rectifier transistor changes from an on state to an off state, determine whether the synchronous rectifier transistor is starting from the secondary winding of the transformer. The synchronous rectifier transistor is changed from the on state to the off state within a first predetermined time period starting from the moment of demagnetization, wherein the duration of the first predetermined time period is equal to a first predetermined proportion of the demagnetization time of the secondary winding of the transformer in the current switching cycle of the synchronous rectifier transistor; when the synchronous rectifier transistor is changed from the on state to the off state within the first predetermined time period, if the synchronous rectifier transistor From the moment when the conduction state changes to the off state to the end moment of the first predetermined time period, if the duration of the drain voltage of the synchronous rectification transistor being less than the synchronous rectification turn-on threshold value is greater than the first predetermined threshold value, the synchronous rectification transistor is controlled to change from the off state to the on state, otherwise the synchronous rectification transistor is kept in the off state; and when the drain voltage of the synchronous rectification transistor is less than the When the synchronous rectification turn-on threshold is reached and the time for the drain voltage of the synchronous rectification transistor to drop from the slope timing start voltage to the synchronous rectification turn-on threshold is less than the second predetermined threshold, the synchronous rectification transistor is allowed to change from the off state to the on state, wherein the slope timing start voltage is a second predetermined proportion of the platform voltage of the drain voltage of the synchronous rectification transistor in the previous switching cycle. The synchronous rectification controller as described in claim 1 is further configured to keep the synchronous rectification transistor in the off state when the synchronous rectification transistor changes from the on state to the off state at a time other than the first predetermined time period. The synchronous rectification controller as described in claim 1 is further configured to obtain the demagnetization time of the secondary winding of the transformer based on the drain voltage of the synchronous rectification transistor and the system output voltage of the flyback converter power supply by using the inductor volt-second balance principle. The synchronous rectification controller as claimed in claim 1 is further configured to: determine whether the sum of the duration of the synchronous rectification transistor being in the on state and the duration of the drain voltage of the synchronous rectification transistor being less than the synchronous rectification turn-on threshold value is greater than the minimum on time of the synchronous rectification transistor within a second predetermined time period starting from the moment when the secondary winding of the transformer starts to demagnetize in the previous switching cycle of the synchronous rectification transistor, wherein the duration of the second predetermined time period is equal to the minimum on time of the synchronous rectification transistor. The sum of the on-time and the predetermined time increment; and in the case where the sum of the duration of the on-state of the synchronous rectifier transistor and the duration of the drain voltage of the synchronous rectifier transistor being less than the synchronous rectifier on-threshold value in the second predetermined time period is not greater than the minimum on-time of the synchronous rectifier transistor, after the minimum on-time of the synchronous rectifier transistor is delayed from the moment when the drain voltage of the synchronous rectifier transistor drops to the synchronous rectifier on-threshold value, the synchronous rectifier transistor is controlled to change from the off-state to the on-state. The synchronous rectification controller as described in claim 4 is further configured to: when the sum of the duration of the synchronous rectification transistor being in the on state and the duration of the drain voltage of the synchronous rectification transistor being less than the synchronous rectification turn-on threshold value in the second predetermined time period is greater than the minimum on time of the synchronous rectification transistor, control the synchronous rectification transistor to change from the off state to the on state without time delay. The synchronous rectification controller as described in claim 1 or 4 is further configured to: when the duration of the synchronous rectification transistor in the on state is greater than or equal to the minimum on time of the synchronous rectification transistor and the drain voltage of the synchronous rectification transistor is greater than the synchronous rectification off threshold, control the synchronous rectification transistor to change from the on state to the off state. The synchronous rectification controller as described in claim 6 is further configured to: generate a synchronous rectification turn-on signal based on the drain voltage of the synchronous rectification transistor, the synchronous rectification turn-off threshold, and the synchronous rectification switch signal; generate a synchronous rectification turn-off signal based on the drain voltage of the synchronous rectification transistor, the synchronous rectification turn-off threshold, and the synchronous rectification switch signal; generate the synchronous rectification switch signal based on the synchronous rectification turn-on signal and the synchronous rectification turn-off signal; and generate a transistor control signal for controlling the conduction and shutdown of the synchronous rectification transistor based on the drain voltage of the synchronous rectification transistor, the synchronous rectification turn-on signal, the synchronous rectification turn-off signal, and the synchronous rectification switch signal. The synchronous rectification controller as described in claim 7 is further configured to: generate a drain voltage characteristic signal based on the drain voltage of the synchronous rectification transistor; generate a turn-on condition detection signal based on the drain voltage characteristic signal and the synchronous rectification turn-on threshold; generate a rectification turn-on control signal based on the drain voltage of the synchronous rectification transistor and the synchronous rectification switch signal; and generate the synchronous rectification turn-on signal based on the turn-on condition detection signal and the rectification turn-on control signal. The synchronous rectification controller as described in claim 7 is further configured to: generate a drain voltage characteristic signal based on the drain voltage of the synchronous rectification transistor; generate a shutdown condition detection signal based on the drain voltage characteristic signal and the synchronous rectification shutdown threshold; generate a minimum on-time control signal for controlling the minimum on-time of the synchronous rectification transistor based on the synchronous rectification switch signal; and generate the synchronous rectification shutdown signal based on the shutdown condition detection signal and the minimum on-time control signal. A flyback converter power supply comprising a synchronous rectification controller as described in any one of claims 1 to 9.

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