TWI855804B - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

The present disclosure provides a method for manufacturing a semiconductor structure including the following steps: forming a shallow trench isolation structure in a substrate. An active area is formed in the substrate, wherein the active area is adjacent to the shallow trench isolation structure. An active gate is formed on the active area of the substrate. A dummy gate is formed on the shallow trench isolation structure of the substrate. A sidewall spacer is formed on the active gate and the dummy gate. A mask layer is formed to cover the active gate on the active region, wherein the dummy gate is exposed to the opening of the mask layer. The sidewall spacer on the dummy gates is removed. The mask layer is removed, and a source/drain region is formed in the active region of the substrate.

Description

Semiconductor structure and method for manufacturing the same

The present disclosure relates to a semiconductor structure and a method for manufacturing the same.

As electronic devices become thinner and lighter, semiconductor devices such as dynamic random access memory (DRAM) have become more highly integrated. The compression of size reduces the space in which each component inside the semiconductor device can be placed. As the size of DRAM gradually decreases, the distance between the dummy gate and the active region shortens, resulting in a smaller implantation area for the source/drain region next to the dummy gate, making it easier for leakage current to occur between the source/drain region and the contact.

In view of this, one object of the present disclosure is to provide a method for manufacturing a semiconductor structure that can solve the above-mentioned problem, and the method can ensure that the bottom surface of the contact next to the dummy gate is completely surrounded by the source/drain region.

The present disclosure provides a method for manufacturing a semiconductor structure including the following steps: forming a shallow trench isolation structure in a substrate; forming an active region in the substrate, the active region being adjacent to the shallow trench isolation structure; forming an active gate on the active region of the substrate; forming a dummy gate on the shallow trench isolation structure of the substrate; forming sidewall spacers on the active gate and the dummy gate, respectively; forming a mask layer to cover the active gate on the active region, wherein the dummy gate is exposed to an opening of the mask layer; and removing the sidewall spacer on the dummy gate. The mask layer is removed and source/drain regions are formed in the active area of the substrate.

In some embodiments, forming the active region includes performing an implantation process on the substrate.

In some embodiments, the method further includes forming contacts connected to the source/drain regions.

In some embodiments, the maximum width from the side surface of the virtual gate to the spacer surface of the sidewall spacer projected onto the substrate along the first direction is a first width, and the width from the side surface of the virtual gate to the active region projected onto the substrate is a second width, wherein the first width is greater than the second width.

In some embodiments, along the first direction, the dummy gate has a third width from the side surface to the side surface opposite to the other side, the spacer surface of the dummy gate to the spacer surface of the sidewall spacer of the active gate has a fourth width, and the opening of the mask layer has a fifth width.

In some embodiments, the fifth width is greater than the third width plus twice the first width, and the fifth width is less than the third width plus twice the first width plus twice the fourth width.

In some embodiments, the method further includes forming a dielectric layer covering the dummy gate and the active gate of the active region.

The present disclosure provides a semiconductor structure, including a substrate, a shallow trench isolation structure, an active region, a dummy gate, an active gate, a source/drain region, and a contact. The shallow trench isolation structure is located in the substrate, the active region is located in the substrate and is adjacent to the shallow trench isolation structure. The dummy gate is located above the shallow trench isolation structure, the active gate is located above the active region, wherein the active gate has a sidewall spacer. The source/drain region is located in the active region of the substrate, wherein the source/drain region contacts the shallow trench isolation structure. The contact element is located on the source/drain region of the substrate, wherein a bottom surface of the contact element is completely surrounded by the source/drain region.

In some embodiments, the active region comprises an N-type dopant.

In some embodiments, a dielectric layer is further included covering the active gate and the dummy gate, wherein the dielectric layer contacts the top surface and the side surface of the dummy gate, and the dielectric layer contacts the top surface of the active gate and the spacer surface of the sidewall spacer.

In order to make the description of the present disclosure more detailed and complete, the aspects and specific implementations of the present disclosure are described below by way of example. Although a series of operations or steps are used below to illustrate the method of the present disclosure, the order in which these operations or steps are shown should not be interpreted as a limitation of the present disclosure. For example, certain operations or steps can be performed in different orders and/or simultaneously with other steps. In addition, it is not necessary to perform all the operations, steps and/or features shown in the figure to implement the implementation of the present disclosure. Each operation or step described herein may include a number of sub-steps or actions.

For ease of description, spatially relative terms (e.g., "under," "below," "lower," "above," "above," etc.) may be used herein to describe the relationship between one element or feature shown in a figure and another element or feature. It should be understood that in addition to the orientation depicted in the accompanying drawings, spatially relative terms also cover the scope of use or operation of the device in different orientations. For example, if the device in the accompanying drawings is turned over, elements described as being "under" or "beneath" other elements or features will be oriented as being "above" or "above" the other elements or features. Thus, for example, the term "under" can include both above and below orientations. The device can be configured in other orientations and spatially relative descriptors can be used corresponding to such orientations.

The present disclosure provides a semiconductor structure 100 and a method for manufacturing the same. Referring to FIG. 1 , the semiconductor structure 100 has a substrate 110. First, a shallow trench isolation structure 112 is formed in the substrate 110. Next, an active region 114 is formed in the substrate 110 such that the active region 114 is adjacent to the shallow trench isolation structure 112.

In some embodiments, the substrate 110 may include silicon, such as crystalline silicon, polycrystalline silicon, or amorphous silicon. The substrate 110 may include an elemental semiconductor, such as germanium. The substrate 110 may include an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium indium phosphide, or other suitable materials. The substrate 110 may include a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium phosphide (InP), indium arsenide (InAs), or other suitable materials.

As shown in FIG. 1 , the shallow trench isolation structure 112 is located between the active region 114 a and the active region 114 b, so that the active region 114 a and the active region 114 b are isolated from each other. In some embodiments, the shallow trench isolation structure 112 includes silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS) or fluoride-doped silicate (FSG).

In some embodiments, an active region 114 may be formed on the substrate 110 by performing an implantation process. In some embodiments, the active region 114 may include an N-type dopant, such as arsenic (As), antimony (Sb), phosphorus (P), or other appropriate N-type materials. In some embodiments, the active region 114 may include a P-type dopant, such as boron (B) or other appropriate P-type materials.

Referring to FIG. 2 , a gate structure is formed on a substrate 110. Specifically, an active gate 120 is formed on an active region 114, and a dummy gate 124 is formed on a shallow trench isolation structure 112. In some embodiments, the active gate 120 and the dummy gate 124 include polysilicon, metals such as aluminum (Al), copper (Cu) or tungsten (W), other conductive materials or combinations thereof. In some embodiments, the active gate 120 and the dummy gate 124 may be formed by a deposition process, such as a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, other suitable deposition processes, or a combination thereof. In some embodiments, the active gate 120 and the dummy gate 124 are made of the same material. In some embodiments, the active gate 120 and the dummy gate 124 have the same width.

Referring to FIG. 3 , a sidewall spacer 122 is formed on the sidewall of the active gate 120, and a sidewall spacer 126 is formed on the sidewall of the dummy gate 124. In some embodiments, the material of the sidewall spacers 122 and 126 may include a suitable dielectric material, such as silicon oxide, silicon nitride, a low-k dielectric material, or a combination thereof. In some embodiments, the sidewall spacers 122 and 126 may be a single-layer structure, a double-layer structure, or a multi-layer structure, and the multi-layer structure may include different materials.

As shown in FIG. 3 and FIG. 4 , along the direction X, the first width W1 is the maximum width from the side surface 124S of the dummy gate 124 to the spacer surface 126P of the sidewall spacer 122 projected onto the substrate 110. The second width W2 is the width from the side surface 124S of the dummy gate 124 to the boundary of the active region 114. In some embodiments, the first width W1 is greater than the second width W2. The third width W3 is the width of the dummy gate 124. In some embodiments, the width of the active gate 120 is also the third width W3.

Referring to FIGS. 4 and 5 , a mask layer 130 is formed on the substrate 110 to cover the active gate 120 and the dummy gate 124. In some embodiments, the mask layer 130 may be made of silicon oxide, titanium nitride, silicon nitride, high-k dielectric material, other suitable dielectric materials, other suitable photoresist materials, and/or combinations thereof. Generally speaking, the mask layer 130 includes a material that can be selectively etched relative to the sidewall spacer 126. The mask layer 130 may be formed by a deposition process, such as a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, other suitable deposition processes, or a combination thereof. In some embodiments, the mask layer 130 is patterned to form an opening 132. The mask layer 130 may be patterned by a suitable method, such as using a photolithography patterning process and an etching process. Thus, the opening 132 is formed in the mask layer 130, and the opening 132 exposes the dummy gate 124.

As shown in FIG. 4 , along the direction X, the fourth width W4 is the width from the spacer surface 126P of the sidewall spacer 126 to the spacer surface 122P of the adjacent sidewall spacer 122 . The fifth width W5 is the width of the opening 132 of the mask layer 130 .

In some embodiments, the fifth width W5 of the opening 132 of the mask layer 130 is the third width W3 plus twice the first width W1 (W5= W3+2W1). In some embodiments, the fifth width W5 of the opening 132 of the mask layer 130 is greater than the third width W3 plus twice the first width W1 and less than the third width W3 plus twice the first width W1 plus twice the fourth width W4 (W3+2W1＜W5＜W3+2W1+2W4). The fifth width W5 of the opening 132 of the mask layer 130 can expose the dummy gate 124 and the sidewall spacers 126 on both sides thereof, and enable the mask layer 130 to completely cover the active gate 120 and the sidewall spacers 122.

As shown in FIG. 5 , the sidewall spacers 126 on both sides of the dummy gate 124 are removed. In some embodiments, the sidewall spacers 126 can be removed by an etching process, such as a plasma etching process, a reactive ion etching (RIE) process, a wet etching process, etc. In the etching process, the dummy gate 124 is retained, and a portion of the shallow trench isolation structure 112 is exposed after the etching process.

Referring to FIG. 6 and FIG. 7, after removing the sidewall spacer 126, the mask layer 130 is removed, and the source/drain region 140 is formed in the active region 114. In some embodiments, the mask layer 130 can be removed by a photoresist stripping process, such as an ashing process, an etching process, or other appropriate processes, and the sidewall spacer 122 of the active gate 120 is retained.

In some embodiments, source/drain regions 140 may be formed on substrate 110 by performing an implantation process. In some embodiments, source/drain regions 140 may include a P-type dopant, such as boron (B) or other appropriate P-type materials. As shown in FIG. 7 , source/drain regions 140 are located on opposite sides of active gate 120, and source/drain regions 140 are in contact with shallow trench isolation structure 112. Referring to FIGS. 3 , 4 , and 6 , the sixth width is the width from side surface 124S of dummy gate 124 to spacer layer surface 126P on active gate 126. In some embodiments, the sixth width W6 is greater than the fourth width W4. Since the sidewall spacer 126 of the dummy gate 124 is removed before the implantation process of the source/drain region 140 is performed, the distance (pitch) between the dummy gate 124 and the active region 114 does not need to be increased, and the implantation area size of the source/drain region 140 can also be increased.

Referring to FIG. 8 , a contact 150 is formed to connect to the source/drain region 140, and a dielectric layer 160 is formed to cover the dummy gate 124 and the active gate 120 of the active region 114. Specifically, the dielectric layer 160 contacts the top surface 124T and the side surface 124S of the dummy gate 124, and the dielectric layer 160 contacts the top surface 120T of the active gate 120 and the spacer surface 122P of the sidewall spacer 122. The opposite side surfaces 150S and the bottom surface 150B of the contact 150 can be completely surrounded by the source/drain region 140. The probability of leakage can be reduced when the source/drain region 140 completely surrounds the contact 150. As the implantation area of the source/drain region 140 becomes larger, the distance from the contact 150 to the boundary of the source/drain region 140 and the active region 114 can also be increased.

In some embodiments, the contact 150 may include, for example, tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), combinations thereof, and/or other suitable conductive materials. The dielectric layer 160 may be formed by a deposition process, such as a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, other suitable deposition processes, or a combination thereof. In some embodiments, the dielectric layer 160 may be made of silicon oxide, titanium nitride, silicon nitride, high-k dielectric materials, other suitable dielectric materials, and/or combinations thereof. In some embodiments, the dielectric layer 160 and the sidewall spacer 122 are made of different materials.

The method disclosed herein can ensure the implantation size of the source/drain region next to the dummy gate. By forming a mask layer on the active gate before forming the source/drain region, and performing an etching process to remove the sidewall spacer layer on the dummy gate, it can be ensured that the source/drain region can completely surround the bottom surface of the contact. With the method disclosed herein, there is no need to increase the distance between the dummy gate and the active region, nor to reduce the width of the dummy gate. While maintaining the critical dimension of the semiconductor structure relatively small, the implantation area size of the source/drain region can also be ensured to reduce the probability of leakage current. This improves the quality of the semiconductor structure and increases the reliability of the semiconductor structure.

Although the present disclosure has been described in considerable detail with reference to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

It is obvious to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, the present disclosure is intended to cover modifications and variations of the present disclosure that fall within the scope of the attached patent applications.

100:Semiconductor structure

110: Substrate

112: Shallow Trench Isolation Structure

114: Active Zone

120: Active Gate

120T, 124T: Top surface

122, 126: Lateral wall septum

122P, 126P: Interlayer surface

124: Virtual gate

124S: Side surface

130: Mask layer

132: Open

140: Source/Drain Region

150: Contact

150S: Side

150B: Bottom

160: Dielectric layer

W1: First Width

W2: Second width

W3: Third Width

W4: Fourth Width

W5: Fifth Width

W6: Sixth Width

X, Y, Z: Direction

When reading the attached drawings, the various aspects of the present disclosure can be fully understood from the following detailed description, and the attached drawings and various embodiments described below can be referred to. The same numbers in the drawings represent the same or similar elements. In addition, in order to simplify the drawings, some commonly used structures and elements will be shown in the drawings in a simple schematic manner. Figures 1, 2, 3, 5, 6, and 8 are cross-sectional schematic diagrams of the process of semiconductor structures at different manufacturing stages according to some embodiments of the present disclosure. Figures 4 and 7 are top-view schematic diagrams of the process of semiconductor structures at different manufacturing stages according to some embodiments of the present disclosure.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

100:Semiconductor structure

112: Shallow trench isolation structure

120: Active gate

122: Lateral wall septum

124: Virtual gate

130: Mask layer

132: Open your mouth

W5: Fifth width

X,Z: direction

Claims (9)

A method for manufacturing a semiconductor structure includes: forming a shallow trench isolation structure in a substrate; forming an active region in the substrate, the active region being adjacent to the shallow trench isolation structure; forming an active gate on the active region of the substrate; forming a dummy gate on the shallow trench isolation structure of the substrate; forming a sidewall spacer layer on a side surface of the active gate and the dummy gate respectively; forming a Forming a mask layer to cover the active gate on the active region, wherein the dummy gate is exposed from an opening of the mask layer; removing the sidewall spacer on the dummy gate; removing the mask layer; forming a source/drain region in the active region of the substrate; and forming a contact connected to the source/drain region, wherein the opposite side surfaces and a bottom surface of the contact are completely surrounded by the source/drain region. The method as described in claim 1, wherein forming the active region includes performing an implantation process on the substrate. The method as described in claim 1, wherein along a first direction, the maximum width from the side surface of the virtual gate to a spacer surface of the sidewall spacer layer projected onto the substrate is a first width, and the width from the side surface of the virtual gate to the active area projected onto the substrate is a second width, wherein the first width is greater than the second width. The method as described in claim 3, wherein along the first direction, the dummy gate has a third width from one side surface to the side surface opposite to the other side, the spacer surface of the dummy gate to a spacer surface of the sidewall spacer of the active gate has a fourth width, and the opening of the mask layer has a fifth width. The method as described in claim 4, wherein the fifth width is greater than the third width plus twice the first width, and the fifth width is less than the third width plus twice the first width plus twice the fourth width. The method as described in claim 1 further includes: forming a dielectric layer to cover the dummy gate and the active gate of the active region. A semiconductor structure includes: a substrate; a shallow trench isolation structure located in the substrate; an active region located in the substrate and adjacent to the shallow trench isolation structure; a dummy gate located above the shallow trench isolation structure; an active gate located above the active region, wherein the active gate has A sidewall spacer layer; a source/drain region located in the active region of the substrate, wherein the source/drain region contacts the shallow trench isolation structure; a contact member located on the source/drain region of the substrate, wherein two opposite side surfaces and a bottom surface of the contact member are completely surrounded by the source/drain region. A semiconductor structure as described in claim 7, wherein the active region comprises an N-type dopant. The semiconductor structure as described in claim 7 further includes: a dielectric layer covering the active gate and the dummy gate, wherein the dielectric layer contacts a top surface and a side surface of the dummy gate, and the dielectric layer contacts a top surface of the active gate and a spacer surface of the sidewall spacer.

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