TWI855279B - Method of forming package, and package - Google Patents

Abstract

The invention provides a method of forming a package, and a package. The method comprises the following steps: providing a carrier and at least one set of chips, wherein each group of chips comprise at least a first chip and a second chip; arranging the first chip and the second chip of each group of chips on the surface of the carrier, with the front surfaces of the first chip and the second chip facing upwards, wherein the upper surfaces of the first chip and the second chip are provided with first salient points; attaching an interconnection device to the upper surfaces of the first chip and the second chip so as to allow the first chip of each group of chips to be electrically connected to the second chip through the interconnection device; for each group of chips, forming a plastic package layer around the first chip and the second chip, wherein the first chip, the second chip and the interconnection device are embedded in the plastic package layer; thinning the surface of one side, far away from the carrier, of the plastic package layer to expose the first salient points of the first chip and the second chip; and forming second salient points on the surface of one side, exposed out of the first salient points, of the plastic package layer, and removing the carrier. By means of the above method, a flexible, efficient and low-cost packaging scheme is provided for multi-chip connection.

Description

Method for forming a package and package

The present invention belongs to the field of semiconductors, and in particular relates to a method for forming a package and a package.

This section is intended to provide a background or context for the implementation of the invention described in the claims. The description herein is not admitted to be prior art by inclusion in this section.

With the advent of the artificial intelligence era, the development trend of semiconductor integrated circuits is more functions and faster computing speed. If the SOC integration of large chips is simply used to meet this development trend, it will undoubtedly make circuit design more and more difficult and the manufacturing cost more and more expensive. A more practical solution is to use heterogeneous integration technology of multiple small chips to achieve the purpose of functional integration. Based on this, the current important task for high-end packaging is to develop high-efficiency, high-density multi-chip interconnection technology, through direct connection between bare chips to form the physical layer functional blocks of the chip, so as to replace the SOC integration of large chips, achieve low cost and high degree of freedom, and have the same functionality.

Among existing multi-chip interconnect technologies, such as embedded multi-chip interconnect bridge (EMIB), silicon bridges are usually embedded in the substrate to achieve chip interconnection, which can increase interconnection density and interconnection efficiency. However, the existing EMIB technology requires a complex packaging process and is costly.

In view of the above problems existing in the prior art, a method for forming a package and a package are proposed, and the above problems can be solved by using this method and package.

The present invention provides the following solutions.

In a first aspect, a method for forming a package is provided, comprising: providing a carrier and at least one group of chips, wherein each group of chips includes at least a first chip and a second chip; mounting the first chip and the second chip contained in each group of chips on the surface of the carrier with the front side facing upward, wherein the upper surfaces of the first chip and the second chip have first bumps; attaching an interconnection device to the upper surfaces of the first chip and the second chip so that the first chip contained in each group of chips can be electrically connected to the second chip through the interconnection device; forming a plastic layer around the first chip and the second chip, wherein the first chip, the second chip and the interconnection device are embedded in the plastic layer; performing a thinning process on a side surface of the plastic layer away from the carrier to expose the first bumps of the first chip and the second chip; forming a second bump on a side surface of the plastic layer where the first bump is exposed; and removing the carrier.

In some embodiments, a first region on a first side of the interconnect device forms a plurality of first pads for respectively bonding to first bumps of a first chip, a second region on the first side of the interconnect device forms a plurality of second pads for respectively bonding to first bumps of a second chip, and a fan-out circuit is formed between the plurality of first pads and the plurality of second pads of the interconnect device.

In some embodiments, the interconnect device is formed as a passive device or an active device.

In some embodiments, the interconnect device is formed as an interconnect device having vertical interconnect vias.

In some embodiments, attaching the interconnect device to the upper surface of the first wafer and the second wafer further includes: thermocompression bonding the interconnect device to the upper surface of the first wafer and the second wafer, wherein the interconnect device is formed as a flexible circuit.

In some embodiments, the method further includes: forming a redistribution wiring layer on a surface of the plastic packaging layer on which the first bumps are exposed, and forming a plurality of second bumps on the redistribution wiring layer.

In some embodiments, forming the second bump on a side surface of the plastic packaging layer where the first bump is exposed includes: forming a solder capping layer on a side surface of the plastic packaging layer where the first bump is exposed.

In some embodiments, the upper surface of the first chip has a plurality of high-density first bumps, and the upper surface of the second chip has a plurality of low-density first bumps, wherein the contact area of the high-density first bumps is smaller than that of the low-density first bumps. The method further includes: aligning and bonding the first pads of the interconnect device to the high-density first bumps of the first chip, so that the second pads of the interconnect device are self-aligned and bonded to the low-density first bumps of the second chip with the high-density first bumps as a reference.

In some embodiments, the first chip is a processor chip and the second chip is a memory chip.

In a second aspect, a package is provided, comprising: a first chip and a second chip, wherein the upper surfaces of the first chip and the second chip have a plurality of first bumps; an interconnection device formed on the upper surfaces of the first chip and the second chip, and the first chip can be electrically connected to the second chip through the interconnection device; a plastic layer formed around the first chip and the second chip, wherein the first chip and the second chip and the interconnection device are embedded in the plastic layer, and the first bumps of the first chip and the second chip are exposed on the upper surface of the plastic layer; and a plurality of second bumps are formed on the upper surface of the plastic layer.

In some embodiments, a first region on a first side of the interconnect device forms a plurality of first pads for respectively bonding to first bumps of a first chip, a second region on the first side of the interconnect device forms a plurality of second pads for respectively bonding to first bumps of a second chip, and a fan-out circuit is formed between the plurality of first pads and the plurality of second pads of the interconnect device.

In some embodiments, the interconnect device is formed as a passive device or an active device.

In some embodiments, the interconnect device is formed as an interconnect device having vertical interconnect vias.

In some embodiments, the interconnect device is formed as a flexible circuit that is thermocompressively bonded to the upper surfaces of the first wafer and the second wafer.

In some embodiments, the package further includes: a redistribution wiring layer formed on a surface of the plastic packaging layer that exposes the first bumps, and a plurality of second bumps are formed on the redistribution wiring layer.

In some embodiments, the plurality of second bumps are formed as a solder capping layer formed on a surface of the plastic layer at a side where the first bumps are exposed.

In some embodiments, the upper surface of the first chip has a plurality of high-density first bumps, and the upper surface of the second chip has a plurality of low-density first bumps, wherein the contact area of the high-density first bumps is smaller than that of the low-density first bumps, and wherein, in the package, the first pads of the interconnect device are aligned and bonded to the high-density first bumps of the first chip, so that the second pads of the interconnect device are self-aligned and bonded to the low-density first bumps of the second chip with the high-density first bumps as a reference.

In some embodiments, the first chip is a logic chip and the second chip is a memory chip.

At least one of the above technical solutions adopted in the embodiment of the present application can achieve the following beneficial effects: According to various aspects of the above embodiments, by adopting a new packaging structure design and a unique process flow, the same or similar effect as the EMIB technology can be achieved at a lower cost and a simpler manufacturing process. On the one hand, it does not require the embedding of interconnect devices in the substrate, reducing the complexity and cycle time of design and manufacturing. On the other hand, the cost associated with the substrate is eliminated, thereby providing a flexible and low-cost solution for multi-chip connection.

It should be understood that the above description is only an overview of the technical solution of the present invention, so that the technical means of the present invention can be more clearly understood and implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following examples are given to illustrate the specific implementation of the present invention.

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, attaching the interconnection device (13, 14, 15) to the upper surface of the first chip 11 and the second chip 12 may include an embodiment in which the first chip 11, the second chip 12 and the interconnection device (13, 14, 15) are directly in contact with each other, and may also include an embodiment in which additional components can be formed between the first chip 11, the second chip 12 and the interconnection device (13, 14, 15), so that the first chip 11, the second chip 12 and the interconnection device (13, 14, 15) may not be in direct contact with each other. In addition, the present invention may repeat reference numerals and/or characters in various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

It should be understood that terms such as “including” or “having” are intended to indicate the existence of features, numbers, steps, behaviors, components, parts or combinations thereof disclosed in this specification, and are not intended to exclude the possibility of the existence of one or more other features, numbers, steps, behaviors, components, parts or combinations thereof.

Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," and "above" may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

It should also be noted that, in the absence of conflict, the embodiments and features of the embodiments of the present invention can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

Fig. 1 is a schematic flow chart of a method 100 for forming a package according to an embodiment of the present application. As shown in Fig. 1 , the method 100 may include steps 101-106.

2A to 2E show cross-sectional views of intermediate stages in the process of forming a package according to some embodiments, wherein the process of packaging a group of chips is shown, and the above steps 101 to 106 are described in detail below with reference to FIG. 2A to FIG. 2E.

First, referring to FIG. 2A , first, step 101 is performed: a carrier 10, a first chip 11, and a second chip 12 are provided, and the first chip 11 and the second chip 12 are mounted on the surface of the carrier 10 with the front side facing upward. The upper surfaces of the first chip 11 and the second chip 12 have first bumps 20, which may also be referred to as chip pins. The side surface of the chip having the chip pins is referred to as the front side, and the side surface opposite to the front side is referred to as the back side. For example, in some embodiments, the first bump 20 may be formed as a solder bump made of a conductive material, and the conductive material may include Cu, Ag, Au, etc. or alloys thereof, and may also include other materials. For example, in some embodiments, two or more chips may be connected to the carrier 10 using an automated machine such as a packaging machine or manually. In some embodiments, an adhesive film (not shown) or a die attach film (not shown) may be used to connect the backsides of the first chip 11 and the second chip 12 to any side of the carrier 10, so that the front sides of the first chip 11 and the second chip 12 are facing outward away from the carrier 10, which may also be referred to as face-up in semiconductor packaging. In some embodiments, multiple chips with the same or different functions may be packaged together.

Next, step 102 is performed: attaching the interconnection device 13 to the upper surfaces of the first chip 11 and the second chip 12, so that the first chip 11 can be electrically connected to the second chip 12 through the interconnection device 13. For example, in some embodiments, one area of the interconnection device can be welded to the edge area of the upper surface of the first chip 11, and another area of the interconnection device can be welded to the edge of the upper surface of the second chip 12. For example, in some embodiments, the interconnection device 13 is formed as a passive device. In other embodiments, the interconnection device 13 can also be formed as an active device.

Referring to FIG. 2B , next, step 103 is performed: a plastic layer 30 is formed around the first chip 11 and the second chip 12, wherein the first chip 11, the second chip 12 and the interconnection device 13 are embedded in the plastic layer 30. For example, in some embodiments, the material of the plastic layer 30 may include epoxy resin, organic polymer or polymer with or without silicon-based or glass fillers. In some embodiments, the material of the plastic layer 30 may include a liquid molding compound of a gel-type liquid. The plastic layer 30 may also include other insulating materials and/or packaging materials or other materials.

Referring to FIG. 2C , next, step 104 is performed: a thinning process is performed on a surface of the plastic layer 30 away from the carrier 10 to expose the first bumps 20 of the first chip 11 and the second chip 12. For example, in some embodiments, a chemical mechanical polishing process, an etching process, or other methods may be used to remove part of the plastic material from above the first chip 11 and the second chip 12. After the thinning process, the first bumps 20 (i.e., chip pins) of the first chip 11 and the second chip 12 and the upper part of the interconnection structure may be removed, exposing the conductive contact surfaces of the first bumps 20 of the first chip 11 and the second chip 12 and the interconnection structure.

2D, next, step 105 is performed: forming a second bump 40 on the surface of the plastic layer 30 that exposes the first bump 20. For example, in some embodiments, the second bump 40 can be directly formed on the metal contact surface of the first bump 20 exposed on the surface of the plastic layer 30, that is, a solder bump of a conductive material is formed on the metal contact surface of the first bump 20 as the second bump 40.

In some other embodiments, a redistribution layer (RDL) 50 may be formed on the surface of the plastic encapsulation layer 30 on the side where the metal contact surface of the first bump 20 is exposed, and a plurality of second bumps 40 may be formed on the redistribution layer 50. For example, the redistribution layer 50 may be formed by photolithography and electroplating on the surface of the plastic encapsulation layer 30 on the side where the first bump 20 is exposed, and the dielectric material of the plastic encapsulation layer 30 may be a photosensitive material, a non-photosensitive material, a liquid material, a dry film material, etc. In some other embodiments, a solder capping layer may be formed on the surface of the plastic layer 30 on the side where the first bump 20 is exposed. The solder capping layer accumulates a plurality of conductive bumps on the surface of the plastic layer 30 on the side where the first bump 20 is exposed, so as to realize electrical connection between the package and an external semiconductor. The solder capping layer is easy to manufacture and can save costs.

Referring to FIG. 2E , next, step 106 is performed: removing the carrier 10. For example, in some embodiments, a cutting process may be performed to remove the carrier 10, and the removal of the carrier 10 may be performed by a laser process or an ultraviolet (UV) irradiation process, but not limited thereto. In other embodiments, a tearable adhesive material may be used to connect the carrier 10 and the chip, and the carrier 10 may be torn off in step 106 to be removed, but not limited thereto. After removing the carrier 10, the backs of the first chip 11 and the second chip 12 are exposed.

3A to 3E show cross-sectional views of intermediate stages in the process of forming a package according to some other embodiments. The above steps 101 to 106 are described in detail below with reference to FIG. 3A to 3E.

Referring to FIG. 3A , first, step 101 is performed: a carrier 10, a first chip 11, and a second chip 12 are provided, and the first chip 11 and the second chip 12 are mounted on the surface of the carrier 10 with the front side facing upward. The upper surfaces of the first chip 11 and the second chip 12 have first bumps 20; next, step 102 is performed: an interconnection device 14 is attached to the upper surfaces of the first chip 11 and the second chip 12, so that the first chip 11 can be electrically connected to the second chip 12 through the interconnection device 14. Compared with the above-mentioned embodiment, the difference of the packaging method shown in FIG. 3A to FIG. 3E is mainly that the interconnection device 14 is formed as an interconnection device having a vertical interconnection through hole 141, and the vertical interconnection through hole 141 is specifically a TSV (Through Silicon Vias, silicon through hole 141), so that I/O pins can also be formed on the upper surface of the interconnection device 14 of the package. At this time, if the interconnection device 14 is formed as a passive device, it forms a 2.5D package, and if the interconnection device 14 is formed as an active device, it can be formed into a 3D package.

3B , next, step 103 is performed: a plastic packaging layer 30 is formed around the first chip 11 and the second chip 12 , wherein the first chip 11 , the second chip 12 and the interconnection device 14 are embedded in the plastic packaging layer 30 .

3C , next, step 104 is performed: a thinning process is performed on a surface of the plastic layer 30 away from the carrier 10 to expose the first bumps 20 of the first chip 11 and the second chip 12 .

Referring to FIG. 3D , next, step 105 is performed: forming the second bump 40 on the surface of the plastic encapsulation layer 30 on the side where the first bump 20 is exposed. A redistribution wiring layer 50 may be formed on the surface of the plastic encapsulation layer 30 on the side where the metal contact surface of the first bump 20 is exposed, and a plurality of second bumps 40 are formed on the redistribution wiring layer 50. For example, the redistribution wiring layer 50 may be formed by photolithography or electroplating on the surface of the plastic encapsulation layer 30 on the side where the first bump 20 is exposed, and the dielectric material of the plastic encapsulation layer 30 may be a photosensitive material, a non-photosensitive material, a liquid material, a dry film material, etc. In some alternative embodiments, the second bump 40 may be formed directly on the metal contact surface of the first bump 20 exposed on one side surface of the plastic layer 30; a solder capping layer may also be formed on the side surface of the plastic layer 30 where the first bump 20 is exposed. This has been explained in detail above and will not be repeated here.

Referring to FIG. 3E , next, step 106 is performed: removing the carrier 10.

The steps of mounting the first chip 11 and the second chip 12 on the carrier 10, attaching the interconnect device 14 to the first chip 11 and the second chip 12, forming the plastic encapsulation layer 30, thinning treatment, and removing the carrier 10 shown in Figures 3A to 3E are the same or similar to the steps described in the above embodiments and will not be repeated here.

4A to 4E show cross-sectional views of intermediate stages in the process of forming a package according to some further embodiments. The above steps 101 to 106 are described in detail below with reference to FIGS. 4A to 4E.

Referring to FIG. 4A , first, step 101 is performed: a carrier 10, a first chip 11, and a second chip 12 are provided, and the first chip 11 and the second chip 12 are mounted on the surface of the carrier 10 with the front side facing upward. The upper surfaces of the first chip 11 and the second chip 12 have first bumps 20, i.e., chip pins; next, step 102 is performed: an interconnection device 15 is attached to the upper surfaces of the first chip 11 and the second chip 12, so that the first chip 11 can be electrically connected to the second chip 12 through the interconnection device 15.

Compared with the above embodiment, the packaging method shown in FIG. 4A to FIG. 4E is mainly different in that the interconnect device 15 is formed as a flexible circuit, and the above step 102 may specifically include: hot-pressing the interconnect device 15 to the upper surfaces of the first chip 11 and the second chip 12.

Referring to FIG. 4B , next, step 103 is performed: a plastic packaging layer 30 is formed around the first chip 11 and the second chip 12 , wherein the first chip 11 and the second chip 12 and the interconnection device 15 are embedded in the plastic packaging layer 30 ;

4C , next, step 104 is performed: a thinning process is performed on a surface of the plastic layer 30 away from the carrier 10 to expose the first bumps 20 of the first chip 11 and the second chip 12 .

Referring to FIG. 4D , next, step 105 is performed: forming a second bump 40 on a surface of the plastic layer 30 where the first bump 20 is exposed.

Referring to FIG. 4E , next, step 106 is performed: removing the carrier 10.

The steps shown in FIGS. 4A to 4E of mounting the first chip 11 and the second chip 12 on the carrier 10, attaching the interconnect device 15 to the first chip 11 and the second chip 12, forming the plastic encapsulation layer 30, thinning treatment, and removing the carrier 10 are the same or similar to the steps described in the above embodiments and will not be described again here.

According to various aspects of the above embodiments, by adopting a new packaging structure design and a unique process flow, the same or similar effect as EMIB technology is achieved with a lower cost and a simpler manufacturing process. On the one hand, it does not need to embed interconnect devices in the substrate, reducing the complexity and cycle time of design and manufacturing. On the other hand, the cost associated with the substrate is eliminated, thereby providing a flexible and low-cost solution for multi-chip connection.

5A to 5C are schematic diagrams showing bonding of an interconnect device 13 to upper surfaces of a first wafer 11 and a second wafer 12 according to some embodiments.

5A , in some embodiments, a first region on a first side of the interconnect device is formed with a plurality of first pads 131 for respectively bonding to the first bumps 20 of the first chip 11, a second region on a first side of the interconnect device 13 is formed with a plurality of second pads 132 for respectively bonding to the first bumps 21 of the second chip 12, and a fan-out circuit 133 is formed between the plurality of first pads 131 and the plurality of second pads 132 of the interconnect device 13. The interconnect device 13 can be predetermined and manufactured according to the package design, wherein a plurality of corresponding first pads 131 are formed in the interconnect device 13 according to the positions of a plurality of first bumps 20 in a set area at the edge of the first chip 11, a plurality of corresponding second pads 132 are formed in the interconnect device 13 according to a set spacing between the first chip 11 and the second chip 12 and the positions of a plurality of first bumps 21 in a set area at the edge of the second chip 12, and a fan-out circuit 133 is formed between the corresponding first pads 131 and the second pads 132.

It is understandable that during the semiconductor chip packaging process, installation errors are unavoidable. For example, when the first chip 11 and the second chip 12 are mounted on one side of the carrier 10, a certain degree of installation spacing error occurs, while the first pad 131 and the second pad 132 in the interconnect device 13 still have the standard spacing determined when the chip is designed. This may cause difficulty in aligning and bonding the corresponding pads and bumps when the interconnect device 13 is subsequently attached to the upper surface of the first chip 11 and the second chip 12.

Referring to FIG. 5A to FIG. 5C , according to some embodiments, the upper surface of the first chip 11 has a plurality of high-density first bumps 21, and the upper surface of the second chip 12 has a plurality of low-density first bumps 22, wherein the contact area of the high-density first bumps 21 is smaller than that of the low-density first bumps 22, and thus the first pads 131 of the interconnect device 13 can be aligned and bonded to the high-density first bumps 21 of the first chip 11 first, and the second pads 132 of the interconnect device 13 can be aligned and bonded to the low-density first bumps 22 of the second chip 12 with the high-density first bumps 21 of the first chip 11 as a reference. Thus, the high-density first bumps 21 and the first pads 131 can be aligned and bonded, and the low-density first bumps 22 have a larger tolerance for error due to their larger contact area, thereby avoiding the problem of difficulty in alignment and bonding due to errors.

According to some embodiments, the first chip 11 may be a logic chip such as a processor chip, and the second chip 12 may be a memory chip.

6A to 6E show cross-sectional views of intermediate stages in the process of forming a package according to some other embodiments, wherein the process of packaging two groups of chips is shown, and the above steps 101 to 106 are described in detail below with reference to FIG. 6A to FIG. 6E.

First, referring to FIG. 6A , first, step 101 is performed: a carrier 10 and two groups of chips are provided, wherein each group of chips includes at least a first chip 11 and a second chip 12 , and the first chip 11 and the second chip 12 are mounted on the surface of the carrier 10 with the front side facing upward.

Next, step 102 is performed: attaching an interconnection device 13 to the upper surfaces of the first chip 11 and the second chip 12 of each chip group, so that the first chip 11 of each chip group can be electrically connected to the second chip 12 through the interconnection device 13.

6B , next, step 103 is performed: a plastic packaging layer 30 is formed around the first chip 11 and the second chip 12 of each chip group, wherein the first chip 11 and the second chip 12 and the interconnection device 13 are embedded in the plastic packaging layer 30 .

6C , next, step 104 is performed: a thinning process is performed on a surface of the plastic layer 30 away from the carrier 10 to expose the first bumps 20 of the first chip 11 and the second chip 12 .

Referring to FIG. 6D , next, step 105 is performed: forming a second bump 40 on a surface of the plastic layer 30 where the first bump 20 is exposed.

Referring to FIG. 6E , next, step 106 is performed: removing the carrier 10. Compared with the above embodiment, the difference between the packaging method shown in FIG. 6A to FIG. 6E is mainly that the number of chip groups used for packaging is greater than 1, and further after the above step 106, it is necessary to perform: cutting the formed package to obtain a plurality of unit packages, wherein each of the unit packages contains a group of chips.

The steps of mounting the first chip 11 and the second chip 12 on the carrier 10, attaching the interconnect device 14 to the first chip 11 and the second chip 12, forming the plastic packaging layer 30, thinning treatment, and removing the carrier 10 shown in Figures 6A to 6E are the same or similar to the steps described in the above embodiments and will not be repeated here.

This embodiment shows an example in which the number of chipsets is 2. It should be understood that the number of chipsets can be any integer greater than or equal to 1, so that large-scale chip packaging can be achieved.

The present application embodiment also provides a package. Referring to FIG. 2E , a cross-sectional view of a package according to some embodiments is shown, including: a first chip 11 and a second chip 12, wherein the upper surfaces of the first chip 11 and the second chip 12 have a plurality of first bumps 20; an interconnection device 13 formed on the upper surfaces of the first chip 11 and the second chip 12, and the first chip 11 can be electrically connected to the second chip 12 through the interconnection device 13; a plastic layer 30 formed around the first chip 11 and the second chip 12, wherein the first chip 11 and the second chip 12 and the interconnection device 13 are embedded in the plastic layer 30, and the first bumps 20 of the first chip 11 and the second chip 12 are exposed on the upper surface of the plastic layer 30; and a plurality of second bumps 40 formed on the upper surface of the plastic layer 30.

5A to 5C , in some embodiments, a first region on a first side of the interconnect device 13 forms a plurality of first pads 131 for respectively bonding to the first bumps 20 of the first chip 11, a second region on a first side of the interconnect device 13 forms a plurality of second pads 132 for respectively bonding to the first bumps 20 of the second chip 12, and a fan-out circuit 133 is formed between the plurality of first pads 131 and the plurality of second pads 132 of the interconnect device 13. In some embodiments, the upper surface of the first chip 11 has a plurality of high-density first bumps 21, and the upper surface of the second chip 12 has a plurality of low-density first bumps 22, wherein the contact area of the high-density first bumps 21 is smaller than that of the low-density first bumps 22, wherein, in the package, the first pads 131 of the interconnect device 13 are aligned and bonded to the high-density first bumps 21 of the first chip 11, and the second pads 132 of the interconnect device 13 are aligned and bonded to the low-density first bumps 22 of the second chip 12 with the high-density first bumps 21 of the first chip 11 as a reference.

3E , in some other embodiments, the interconnection device 14 may be formed as an interconnection device having vertical interconnection vias 141. Referring to FIG. 4E , in some other embodiments, the interconnection device 15 may be formed as a flexible circuit 15 bonded to the upper surfaces of the first chip 11 and the second chip 12 by thermal compression.

3E , in some embodiments, the package may further include: a redistribution wiring layer 50 formed on a side surface of the plastic encapsulation layer 30 exposing the first bumps 20, and a plurality of second bumps 40 formed on the redistribution wiring layer 50. In other embodiments, the plurality of second bumps 40 may also be formed as: a solder capping layer formed on a side surface of the plastic encapsulation layer 30 exposing the first bumps 20.

In some embodiments, the interconnect devices (13, 14, 15) can be formed as passive devices or active devices.

In some embodiments, the first chip 11 is a processor chip, and the second chip 12 is a storage chip.

Although the spirit and principle of the present invention have been described with reference to several specific embodiments, it should be understood that the present invention is not limited to the disclosed specific embodiments, and the division of various aspects does not mean that the features in these aspects cannot be combined to benefit. Such division is only for the convenience of expression. The present invention is intended to cover various modifications and equivalent arrangements included in the spirit and scope of the attached claims.

10: Carrier 11: First chip 12: Second chip 13, 14, 15: Interconnection device 131: First pad 132: Second pad 133: Fan-out circuit 141: Vertical interconnection via 20: First bump 21: High-density first bump 22: Low-density first bump 30: Plastic layer 40: Second bump 50: Redistribution layer

The advantages and benefits described herein and other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the exemplary embodiments below. The accompanying drawings are only used for the purpose of illustrating exemplary embodiments and are not to be considered as limiting the present invention. Also, the same reference numerals are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

In the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[Figure 1] is a schematic diagram of the process of forming a package according to an embodiment of the present invention; [Figures 2A to 2E] are schematic diagrams of cross-sections of an intermediate stage in the process of forming a package according to an embodiment of the present invention; [Figures 3A to 3E] are schematic diagrams of cross-sections of an intermediate stage in the process of forming a package according to another embodiment of the present invention; [Figures 4A to 4E] are schematic diagrams of cross-sections of an intermediate stage in the process of forming a package according to another embodiment of the present invention; [Figures 5A to 5C] are top views of an intermediate stage of bonding an interconnect device and a chip according to an embodiment of the present invention; [Figures 6A to 6E] are schematic diagrams of cross-sections of an intermediate stage in the process of forming a package according to another embodiment of the present invention.

Step 101: Provide a carrier and at least one set of chips, each set of chips including a first chip and a second chip; install the first chip and the second chip included in each set of chips on the surface of the carrier with the front side facing up

Step 102: Attach interconnect devices to the upper surfaces of the first chip and the second chip

Step 103: Form a plastic layer around the first chip and the second chip, wherein the first chip, the second chip and the interconnecting device are embedded in the plastic layer

Step 104: Thinning the surface of the plastic layer away from the carrier to expose the first bumps of the first chip and the second chip.

Step 105: Form a second bump on the surface of the plastic layer that exposes the first bump

Step 106: Remove the carrier

Claims (15)

A method for forming a package, characterized in that it includes: providing a carrier and at least one set of chips, wherein each set of chips includes at least a first chip and a second chip; mounting the first chip and the second chip included in each set of chips on the surface of the carrier with the front side facing upward, wherein the upper surfaces of the first chip and the second chip have first bumps; attaching an interconnection device to the upper surfaces of the first chip and the second chip so that the first chip included in each set of chips can be electrically connected to the second chip through the interconnection device. chip; forming a plastic layer around the first chip and the second chip, wherein the first chip, the second chip and the interconnection device are embedded in the plastic layer; performing a thinning process on a side surface of the plastic layer away from the carrier to expose all the first bumps of the first chip and the second chip; forming second bumps on a side surface of the plastic layer exposing the first bumps; and removing the carrier, wherein the interconnection device is formed to have a vertical interconnection through hole penetrating the interconnection device. The method according to claim 1 is characterized in that the number of the chip groups is greater than 1, and the method further comprises: after removing the carrier, cutting the formed package to obtain a plurality of unit packages, wherein each of the unit packages contains a group of chips. The method according to claim 1 is characterized in that a first area of the first side of the interconnect device forms a plurality of first pads for respectively bonding to the first bumps of the first chip, a second area of the first side of the interconnect device forms a plurality of second pads for respectively bonding to the first bumps of the second chip, and a fan-out circuit is formed between the plurality of first pads and the plurality of second pads of the interconnect device. The method according to claim 3 is characterized in that the interconnect device is formed as a passive device or an active device. The method according to claim 1 is characterized in that the interconnection device is attached to the upper surface of the first chip and the second chip, and further includes: thermocompression bonding the interconnection device to the upper surface of the first chip and the second chip, wherein the interconnection device is formed into a flexible circuit. The method according to claim 1 is characterized in that the method further comprises: forming a redistribution wiring layer on a surface of the plastic encapsulation layer that exposes the first bump, and forming a plurality of the second bumps on the redistribution wiring layer. The method according to claim 1 is characterized in that forming a second bump on the surface of the plastic layer on the side where the first bump is exposed includes: forming a solder covering layer on the surface of the plastic layer on the side where the first bump is exposed. The method according to claim 1 is characterized in that the upper surface of the first chip has a plurality of high-density first bumps, and the upper surface of the second chip has a plurality of low-density first bumps, wherein the contact surface of the high-density first bumps is smaller than that of the low-density first bumps, and the method further comprises: aligning and bonding the first pads of the interconnected device to the high-density first bumps of the first chip, so that the second pads of the interconnected device are aligned and bonded to the low-density first bumps of the second chip with the high-density first bumps as a reference. A package, characterized in that it includes: a first chip and a second chip, wherein the upper surfaces of the first chip and the second chip have a plurality of first bumps; an interconnection device attached to the upper surfaces of the first chip and the second chip, wherein the first chip can be electrically connected to the second chip through the interconnection device; a plastic layer formed around the first chip and the second chip, wherein the first chip and the second chip and the interconnection device are embedded in the plastic layer, and all the first bumps of the first chip and the second chip are exposed to the upper surface of the plastic layer; a plurality of second bumps formed on the upper surface of the plastic layer, wherein the interconnection device is formed to have a vertical interconnection through hole penetrating the interconnection device. The package according to claim 9 is characterized in that a first area of the first side of the interconnect device forms a plurality of first pads for respectively bonding to the first bumps of the first chip, a second area of the first side of the interconnect device forms a plurality of second pads for respectively bonding to the first bumps of the second chip, and a fan-out circuit is formed between the plurality of first pads and the plurality of second pads of the interconnect device. The package according to claim 10 is characterized in that the interconnect device is formed as a passive device or an active device. The package according to claim 9 is characterized in that the interconnect device is formed as a flexible circuit that is thermocompressively bonded to the upper surfaces of the first chip and the second chip. The package according to claim 9 is characterized in that the package further comprises: a redistribution wiring layer formed on a side surface of the plastic layer exposing the first bump, and a plurality of the second bumps are formed on the redistribution wiring layer. The package according to claim 9 is characterized in that the plurality of second bumps are formed as: a solder covering layer formed on the surface of the plastic layer on the side where the first bumps are exposed. The package according to claim 10 is characterized in that the upper surface of the first chip has a plurality of high-density first bumps, and the upper surface of the second chip has a plurality of low-density first bumps, wherein the contact surface of the high-density first bumps is smaller than that of the low-density first bumps; wherein, in the package, the first pads of the interconnect device are aligned and bonded to the high-density first bumps of the first chip, so that the second pads of the interconnect device are aligned and bonded to the low-density first bumps of the second chip with the high-density first bumps as a reference.