TWI854969B - Package substrate and chip package having the same - Google Patents

Abstract

A package substrate includes: a first substrate having a first antenna part on one surface thereof; a second substrate having a second antenna part on one surface thereof facing the first substrate and coupled to the other surface of the first substrate; and a cavity in at least one of the first substrate and the second substrate so as to be positioned between the first antenna part and the second antenna part.

Description

Package substrate and chip package having the same

The present invention relates to a package substrate and a chip package comprising the same.

With the development of wireless communication technology, various multimedia application services (such as video broadcasting, video calling, and file transfer) are growing from simple voice transmission/reception-oriented communication services. At the beginning of such various wireless communication services, band multiplexing of the used frequency band and high frequency bands of GHz or more have been used. As high frequency bands are utilized, the size of antennas has been reduced.

In Korean Patent Publication No. 10-2011-0002112 (January 6, 2011), a metal circuit board and a method for manufacturing the same are disclosed.

This disclosure is provided to briefly introduce selected concepts that are further described in the embodiments below. This disclosure is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

An object of the present invention is to provide a packaging substrate on which an antenna is mounted.

In a general aspect, a packaging substrate includes: a first substrate having a first antenna component on one surface thereof; a second substrate having a second antenna component on one surface thereof, the one surface of the second substrate facing the first substrate and coupled to the other surface of the first substrate; and a cavity located in at least one of the first substrate and the second substrate to be located between the first antenna component and the second antenna component.

In another general aspect, a chip package includes: a first substrate having a first antenna component on one surface thereof; a second substrate having a second antenna component on one surface thereof, the one surface of the second substrate facing the first substrate and coupled to the other surface of the first substrate; a chamber located in at least one of the first substrate and the second substrate to be located between the first antenna component and the second antenna component; and a chip mounted on the other surface of the second substrate.

Other features and aspects will become apparent from the following detailed description, drawings and claims.

The following detailed description is provided to help the reader fully understand the methods, apparatuses and/or systems described herein. However, after understanding the following description, a person skilled in the art will understand various changes, modifications and equivalent forms of the methods, apparatuses and/or systems described herein. The operation sequence described herein is only an example and is not limited to the operation sequence described herein, but a person skilled in the art will understand after understanding the following description that the operation sequence can be changed except for operations that must be performed in a specific order.

The features described herein may be embodied in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein have been provided to make the invention thorough and to convey the invention to those skilled in the art.

It should be understood that although any of the terms "first", "second", "third", "fourth", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish between various elements. For example, a first element may be referred to as a second element, and similarly a second element may be referred to as a first element, without departing from the scope of the present invention. Similarly, when describing a method including a series of operations, the order of the operations is not the order in which the operations should be performed in sequence, any technical operation may be omitted, and/or another arbitrary operation not disclosed herein may be added to the method.

Unless otherwise specified, any statement that a first layer is “on” a second layer or a substrate should be interpreted to cover both the following situations: the first layer directly contacts the second layer or the substrate; and one or more other layers are disposed between the first layer and the second layer or the substrate.

The spatial relationship of one device or element to other devices or elements may be conveniently described using terms that describe relative spatial relationships (e.g., any of "below," "beneath," "under," "lower," "bottom," "above," "over," "upper," "top," "left," and "right.") Such terms should be interpreted to encompass devices in the orientations shown in the figures as well as devices in other orientations during use or operation. For example, an instance in which a device includes a second layer disposed above a first layer based on the orientation of the device shown in the figures also encompasses the device when the device is turned upside down during use or operation.

Hereinafter, some embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 1 is a diagram illustrating a package substrate according to an embodiment. Fig. 2 is a diagram illustrating a portion of a package substrate according to an embodiment. Fig. 3 is a diagram illustrating a first substrate in a package substrate according to an embodiment. Fig. 4 is a diagram illustrating a second substrate in a package substrate according to an embodiment. Fig. 5 is a diagram illustrating a portion [A] of Fig. 2.

The package substrate according to the embodiment includes a first substrate 110 and a second substrate 120, wherein a cavity is formed in at least one of the first substrate 110 and the second substrate 120. Hereinafter, an embodiment in which the cavity C1 is formed in the first substrate 110 will be described with reference to FIGS.

The first substrate 110 may be a multi-layer substrate including two or more insulating layers. The first substrate 110 may include, but is not limited to, three insulating layers.

The insulating layer of the first substrate 110 may be a material containing a resin as a main component. The resin contained in the insulating layer of the first substrate 110 may be made of various materials, such as a thermosetting resin, a thermoplastic resin, etc. For example, the resin of the insulating layer of the first substrate 110 may be an epoxy resin, polyimide, a liquid crystal polymer (LCP), etc. Examples of epoxy resins include naphthalene-based epoxy resins, bisphenol A-based epoxy resins, bisphenol F-based epoxy resins, phenolic-based epoxy resins, cresol-based epoxy resins, rubber-modified epoxy resins, epoxy aliphatic epoxy resins, silicone-based epoxy resins, nitrogen-based epoxy resins, phosphorus-based epoxy resins, etc., but are not limited thereto.

The insulating layer of the first substrate 110 may contain an inorganic filler in the resin. The inorganic filler may be at least one of silicon dioxide (SiO ₂ ), barium sulfate (BaSO ₄ ), and aluminum oxide (Al ₂ O ₃ ). The inorganic filler may be used alone or in combination of two or more. Examples of inorganic fillers may also include: calcium carbonate, magnesium carbonate, fly ash, natural silica, synthetic silica, kaolin, clay, calcium oxide, magnesium oxide, titanium oxide, zinc oxide, calcium hydroxide, aluminum hydroxide, magnesium hydroxide, talc, mica, hydrotalcite, aluminum silicate, magnesium silicate, calcium silicate, calcined talc, wollastonite, potassium titanate, magnesium sulfate, calcium sulfate, magnesium phosphate, etc., but are not limited thereto.

The first substrate 110 may include a circuit layer between the two or more insulating layers. The circuit layer is a layer including a circuit 310, which is patterned to carry an electrical signal. The circuit 310 may be electrically connected to the first antenna component 210, supply power, or be used as a ground. The circuit 310 may be formed of a metal such as copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt) or an alloy thereof. The circuits 310 may be insulated from each other by the insulating layers. The first substrate 110 may include three insulating layers and four circuit layers.

The circuits 310 formed in different insulating layers can be electrically connected through vias 410 that pass through the insulating layers. The vias 410 can be formed of the same metal as the circuits 310 of the circuit layer.

The through hole 410 of the first substrate 110 may include a grounding through hole. The grounding through hole may be connected to a circuit used as a ground. The grounding through hole may be formed in each of the two or more insulating layers of the first substrate 110 to form a stacked structure. The grounding through hole may be formed to be vertically aligned with the two or more insulating layers of the first substrate 110. Two or more grounding through holes in the stacked structure may be formed in the first substrate 110.

FIG. 2 is a diagram illustrating a ground via 410' in a stacked structure.

Fig. 3(a) is a diagram illustrating one surface (upper surface) of the first substrate 110. Two or more via pads may be formed on one surface (upper surface) of the first substrate 110. Some of the vias illustrated in Fig. 3(a) may be ground vias.

The solder resist layer SR may be formed on the outermost insulating layer of the first substrate 110. The solder resist layer SR exposes a portion of the outermost circuit formed on the outer surface of the outermost insulating layer while protecting the outermost circuit.

The first antenna element 210 may be formed on one surface of the first substrate 110. Here, "one side" of the first substrate 110 refers to an outer surface, which is the upper surface in FIG. 1 and is a surface that does not face the second substrate 120, which will be described later.

The first antenna component 210 can be used to transmit or receive radio frequency (RF) signals and process high frequency signals of 10 GHz or greater. The first antenna component 210 can be made of metal, such as copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt) or alloys thereof. The first antenna component 210 can be a block antenna A1 and can have various cross-sectional shapes, such as polygonal and circular. Two or more first antenna components 210 can be formed to be spaced apart from each other. That is, the first antenna component 210 can include an array of block antennas A1.

The first antenna part 210 may be formed on an outer surface of an outermost insulating layer (an uppermost layer in FIG. 1 ) among the two or more insulating layers of the first substrate 110 , the outer surface not facing the second substrate 120 .

The second substrate 120 may be a multi-layer substrate including two or more insulating layers. The second substrate 120 may include, but is not limited to, five insulating layers.

The insulating layer of the second substrate 120 may be a material containing a resin as a main component. The resin contained in the insulating layer of the second substrate 120 may be made of various materials, such as a thermosetting resin, a thermoplastic resin, etc. For example, the resin of the insulating layer of the second substrate 120 may be an epoxy resin, polyimide, LCP, etc. Examples of epoxy resins include naphthalene-type epoxy resins, bisphenol A-type epoxy resins, bisphenol F-type epoxy resins, phenolic-type epoxy resins, cresol-phenolic-type epoxy resins, rubber-modified epoxy resins, epoxy aliphatic epoxy resins, silicone-based epoxy resins, nitrogen-based epoxy resins, phosphorus-based epoxy resins, etc., but are not limited thereto.

The insulating layer of the second substrate 120 may contain an inorganic filler in the resin. The inorganic filler may be at least one of silicon dioxide (SiO ₂ ), barium sulfate (BaSO ₄ ) and aluminum oxide (Al ₂ O ₃ ). The inorganic filler may be used alone or in combination of two or more. Examples of inorganic fillers may also include calcium carbonate, magnesium carbonate, fly ash, natural silica, synthetic silica, kaolin, clay, calcium oxide, magnesium oxide, titanium oxide, zinc oxide, calcium hydroxide, aluminum hydroxide, magnesium hydroxide, talc, mica, hydrotalcite, aluminum silicate, magnesium silicate, calcium silicate, calcined talc, wollastonite, potassium titanate, magnesium sulfate, calcium sulfate, magnesium phosphate, etc., but are not limited thereto.

The second substrate 120 may include a circuit layer between the two or more insulating layers. The circuit layer is a layer including a circuit 310 that is patterned to carry an electrical signal. The circuit 320 may be formed of a metal such as copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), or an alloy thereof. The circuits 320 may be insulated from each other by the insulating layers. The second substrate 120 may include five insulating layers and six circuit layers, or seven insulating layers and eight circuit layers, but is not limited thereto.

As with the first substrate 110, the circuits 320 formed in the different insulating layers may be electrically connected through vias 420 passing through the insulating layers. The vias 420 may be formed of the same metal as the circuits 320 of the circuit layer.

The solder resist layer SR may be formed on the outermost insulating layer of the second substrate 120. The solder resist layer SR exposes a portion of the outermost circuit formed on the outer surface of the outermost insulating layer while protecting the outermost circuit. The solder member S may be bonded to the exposed outermost circuit.

The second antenna element 220 may be formed on one surface of the second substrate 120. Here, "one surface" of the second substrate 120 is a surface facing the first substrate 110, which may be an upper surface in FIG.

The second antenna component 220 may interact with the first antenna component 210 and process high frequency signals of 10 GHz or more. The second antenna component 220 may be made of a metal such as copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), or an alloy thereof. The second antenna component 220 may be a block antenna A2 and may have various cross-sectional shapes such as a polygonal shape, a circular shape, etc. Two or more first antenna components 220 may be formed to be spaced apart from each other. That is, the second antenna component 220 may include an array of block antennas A2.

The second antenna part 220 may be formed on an outer surface of an outermost insulating layer (an uppermost layer of the second substrate 120 in FIG. 1 ) among two or more insulating layers of the second substrate 120 , the outer surface facing the first substrate 110 .

The first antenna component 210 and the second antenna component 220 may be formed at positions corresponding to each other, and the number of the first antenna component 210 and the second antenna component 220 may be the same.

The first substrate 110 may have a cavity C1 formed therein. The cavity C1 may be formed between the first antenna component 210 and the second antenna component 220. The cavity C1 may be opened toward the other surface of the first substrate 110. That is, the cavity C1 may be opened toward the second substrate 120. If necessary, the cavity C1 may also be opened toward the side of the first substrate 110.

The chamber C1 may not completely pass through the first substrate 110, but may pass through at least one of the two or more insulating layers of the first substrate 110. The chamber C1 may pass through at least one of the two or more insulating layers of the first substrate 110, except for the outermost insulating layer where the first antenna part 210 is formed.

2, a portion of the first substrate 110 and a portion of the second substrate 120 are illustrated and the portions are cut away to expose the chamber C1. Referring to FIG2, the chamber C1 may pass through all of the two or more insulating layers of the first substrate 110 except for the outermost insulating layer where the first antenna part 210 is formed.

The chamber C1 may be formed between the first antenna unit 210 and the second antenna unit 220 to correspond to each of the first antenna unit 210 and the second antenna unit 220. When the first antenna unit 210 includes two or more block antennas A1 and the second antenna unit 220 includes two or more block antennas A2 corresponding to the first antenna unit 210, two or more chambers C1 may be formed to also correspond to each of the first antenna unit 210 and the second antenna unit 220. The two or more chambers C1 may be separated from each other by an insulating layer of the first substrate 110.

The cross-sectional area of the chamber C1 may be larger than the cross-sectional area of each of the block antennas A1 and A2 of the first antenna component 210 and the second antenna component 220 .

Since the chamber C1 is filled with air (dielectric constant Dk = 1) having a lower dielectric constant than the insulating layer (for example, FR4 (dielectric constant Dk = 3.55)), signal loss during interaction with high-frequency signals of the first antenna element 210 and the second antenna 220 can be reduced.

The first substrate 110 and the second substrate 120 may be spaced apart from each other. Therefore, air may move through the space formed between the first substrate 110 and the second substrate 120. The volume of air in the chamber C1 may increase or decrease according to the temperature. Therefore, since the air moves through the space between the first substrate 110 and the second substrate 120, loss caused by the temperature change of the first substrate 110 may be reduced.

A low melting point metal member may be formed between the first substrate 110 and the second substrate 120. That is, the first substrate 110 and the second substrate 120 may be bonded to each other through the low melting point metal member. Here, the low melting point metal member is made of a metal having a melting point lower than that of the metal constituting the circuit 310 or the circuit 320. For example, a solder member S may be interposed between the first substrate 110 and the second substrate 120. The solder member S may be a solder ball.

A low melting point metal member or a solder member S may be attached to the outermost circuit exposed through the solder resist layer SR.

External air may flow into the chamber C1 through the space between the solder members S, or the air in the chamber C1 may flow out to the outside through the space between the solder members S. For example, as shown in FIG5 , as the temperature increases, a portion of the air in the chamber C1 may flow out to the outside through the solder members S.

FIG3(b) illustrates another surface (lower surface) of the first substrate 110. Two or more solder members S are formed to correspond to the through holes 410 of FIG3(a). Referring to one surface (upper surface) of the second substrate 120 shown in FIG4, the two or more solder members S may be bonded to the through hole pads 321 formed on one surface (upper surface) of the second substrate 120.

6(a), the chamber C2 may be formed only in the second substrate 120, but not in the first substrate 110. In this case, the first substrate 110 may include one insulating layer and two circuit layers. The chamber C2 may be open toward one surface of the second substrate 120, and the second antenna member 220 may be formed at the bottom surface of the chamber C2. The second substrate 120 may include seven insulating layers and eight circuit layers or nine insulating layers and ten circuit layers, but is not limited thereto. The chamber C2 may not pass through the upper and lower surfaces of the second substrate 120 , but may pass through at least one of the two or more insulating layers of the second substrate 120 , except for the outermost insulating layer located on the opposite side of the first substrate 110 .

6(b), chamber C1 and chamber C2 may be formed on the first substrate 110 and the second substrate 120, respectively. In this case, chamber C1 of the first substrate 110 may be opened toward the second substrate 120, and chamber C2 of the second substrate 120 may be opened toward the first substrate 110. Therefore, chamber C1 and chamber C2 may correspond to each other.

The embodiment illustrated in FIG. 6 differs from the embodiments in FIGS. 1 to 5 only in the location of the chamber, so the above description is also applicable to FIG. 6 .

7 to 9 are diagrams for explaining various bonding members for coupling the first substrate 110 and the second substrate 120. Referring to FIG. 7, the first substrate 110 and the second substrate 120 may be spaced apart from each other, and a metal column P may be formed between the first substrate 110 and the second substrate 120. That is, the first substrate 110 and the second substrate 120 may be bonded to each other using the metal column P. Two or more metal columns may be formed. In this case, the height difference between the metal columns P may be smaller than in the case where a low melting point metal component or a solder component S is used to bond the first substrate 110 and the second substrate 120 to each other. The metal column P may be made of the same metal (e.g., copper) as the circuit 310 or the circuit 320.

In FIG8 , both the low melting point metal member (solder member S) and the metal pillar P are formed to connect the first substrate 110 and the second substrate 120, while in FIG9 , only the metal pillar P is formed to connect the first substrate 110 and the second substrate 120. On the other hand, in FIG3 (b), only the low melting point metal member (solder member S) is formed to connect the first substrate 110 and the second substrate 120. The bonding member used to connect the first substrate 110 and the second substrate 120 can be various.

The chip package according to the embodiment includes: a first substrate 110, a first antenna component 210 is formed on one surface of the first substrate 110; a second substrate 120, a second antenna component 220 is formed on one surface of the second substrate 120, and one surface of the second substrate 120 faces the first substrate 110 and is coupled to the other surface of the first substrate 110; a chamber formed in at least one of the first substrate 110 and the second substrate 120 to be located between the first antenna component 210 and the second antenna component 220; and a chip 500 mounted on the other surface of the second substrate.

10 and 11 are diagrams illustrating a wafer package in which a chamber C1 is formed in a first substrate 110 according to an embodiment. Hereinafter, the case where a chamber C1 is formed in the first substrate 110 will be first described with reference to FIGS.

The first substrate 110 may be a multi-layer substrate including two or more insulating layers. The first substrate 110 may include three insulating layers, but is not limited thereto.

The first substrate 110 may include two or more insulating layers and a circuit layer between the two or more insulating layers. The circuit 310 formed between two different insulating layers may be electrically connected through a through hole 410 passing through the insulating layer.

The solder resist layer SR may be formed on the outermost insulating layer of the first substrate 110. The solder resist layer SR exposes a portion of the outermost circuit formed on the outer surface of the outermost insulating layer while protecting the outermost circuit.

The first antenna component 210 may be formed on one surface of the first substrate 110. The first antenna component 210 may be formed on an outer surface of the outermost insulating layer (the uppermost layer of the two or more insulating layers in FIG. 10 ) among the two or more insulating layers of the first substrate 110, the outer surface not facing the second substrate 120.

The second substrate 120 may be a multi-layer substrate including two or more insulating layers. The second substrate 120 may include but is not limited to five insulating layers.

The first substrate 110 may include two or more insulating layers and a circuit layer between the two or more insulating layers. The circuit 320 formed between two different insulating layers may be electrically connected through a through hole 420 passing through the insulating layer.

The solder resist layer SR may be formed on the outermost insulating layer of the second substrate 120. The solder resist layer SR exposes a portion of the outermost circuit formed on the outer surface of the outermost insulating layer while protecting the outermost circuit.

The second antenna member 220 may be formed on one surface of the second substrate 120. That is, the second antenna member 220 may be formed on a surface of the second substrate 120 facing the first substrate 110.

The first antenna component 210 and the second antenna component 220 may include a block antenna A1 and a block antenna A2, respectively. The first antenna component 210 and the second antenna component 220 may include a block antenna array including two or more block antennas A1 and A2. The first antenna component 210 and the second antenna component 220 may be formed to correspond to each other, and the number thereof may also be the same.

The chamber C1 may be formed in the first substrate 110. The chamber C1 may be located between the first antenna member 210 and the second antenna member 220. The chamber C1 may be opened toward the other surface of the first substrate 110. That is, the chamber C1 may be opened toward the second substrate 120. If necessary, the chamber C1 may also be opened toward the side of the first substrate 110.

The chamber C1 may not completely pass through the first substrate 110, but may pass through at least one of the two or more insulating layers of the first substrate 110. The chamber C1 may pass through at least one of the two or more insulating layers of the first substrate 110, except for the outermost insulating layer formed with the first antenna component 210. The chamber C1 may pass through all of the two or more insulating layers of the first substrate 110, except for the outermost insulating layer formed with the first antenna component 210.

The chamber C1 may be formed between the first antenna unit 210 and the second antenna unit 220 to correspond to each of the first antenna unit 210 and the second antenna unit 220. When the first antenna unit 210 includes two or more block antennas A1 and the second antenna unit 220 includes two or more block antennas A2 corresponding to the first antenna unit 210, two or more chambers C1 may be formed to correspond to each of the first antenna unit 210 and the second antenna unit 220. The two or more chambers C1 may be separated from each other by an insulating layer of the first substrate 110.

The cross-sectional area of the chamber C1 may be larger than the cross-sectional area of each of the block antennas A1 and A2 of the first antenna component 210 and the second antenna component 220 .

The first substrate 110 and the second substrate 120 may be spaced apart from each other. Therefore, air may move through the space formed between the first substrate 110 and the second substrate 120. The volume of air in the chamber C1 may increase or decrease according to the temperature. Therefore, since the air moves through the space between the first substrate 110 and the second substrate 120, loss caused by the temperature change of the first substrate 110 may be reduced.

A low melting point metal component may be formed between the first substrate 110 and the second substrate 120. That is, the first substrate 110 and the second substrate 120 may be bonded to each other through the low melting point metal component. Here, the low melting point metal component is made of a metal having a melting point lower than that of a metal forming a circuit. For example, a solder component S may be interposed between the first substrate 110 and the second substrate 120. The solder component S may be a solder ball.

A low melting point metal member or a solder member S may be attached to the outermost circuit exposed through the solder resist layer SR.

The chip 500 may be mounted on the other surface of the second substrate 120 and may be a radio frequency integrated circuit (RFIC). The chip 500 may be electrically connected to the second antenna component 220 through a through hole.

The chip package according to the embodiment may further include a third substrate 130.

The third substrate 130 may be formed on the other surface of the second substrate 120. The third substrate 130 may include an opening passing through the upper and lower surfaces of the third substrate 130, and the chip 500 may be installed in the opening. The third substrate 130 may be used to connect the package substrate to the main board MB.

The third substrate 130 may be a multi-layer substrate and may include a circuit layer and a through hole. The circuit layer of the third substrate 130 may be bonded to the pad of the main board MB through the solder member S.

FIG. 11 is a diagram illustrating that the first substrate 110 , the second substrate 120 , and the third substrate 130 are bonded to each other.

Unlike FIG. 10 and FIG. 11 , the chamber C2 may be formed on the second substrate 120. The chamber C2 may be formed only on the second substrate 120. In this case, the first substrate 110 may include one insulating layer and two circuit layers. The chamber C2 may be open toward one surface of the second substrate 120, and the second antenna member 220 may be formed at the bottom surface of the chamber C2. The second substrate 120 may include seven insulating layers and eight circuit layers, or nine insulating layers and ten circuit layers, but is not limited thereto. The chamber C2 may not pass through both the upper and lower surfaces of the second substrate 120 , but may pass through at least one of the two or more insulating layers of the second substrate 120 , except for the outermost insulating layer located on the opposite side of the first substrate 110 .

The chamber C1 and the chamber C2 may be formed on both the first substrate 110 and the second substrate 120. In this case, the chamber C1 of the first substrate 110 may be opened toward the second substrate 120, and the chamber C2 of the second substrate 120 may be opened toward the first substrate 110. Therefore, the chamber C1 and the chamber C2 may correspond to each other.

FIG. 12 is a diagram illustrating a chip package according to another embodiment.

The joining member used to connect the first substrate 110 and the second substrate 120 in FIG. 12 is different from the members in FIGS. 10 and 11 .

12 , the first substrate 110 and the second substrate 120 may be spaced apart from each other, and a metal column P may be formed between the first substrate 110 and the second substrate 120. That is, the first substrate 110 and the second substrate 120 may be bonded to each other through the metal column P. Two or more metal columns P may be formed. In this case, the height difference between the metal columns P may be smaller than in the case where a low melting point metal member or a solder member S is used to bond the first substrate 110 and the second substrate 120 to each other. The metal column P may be made of the same metal as the circuit (e.g., copper).

The bonding member for bonding the first substrate 110 and the second substrate 120 may include both a low melting point metal member (solder member S) and a metal pillar P, or may include only the metal pillar P.

Although the present invention includes specific examples, it will be apparent after understanding the disclosure of this application that various changes in form and detail may be made in those examples without departing from the spirit and scope of the scope of the application and its equivalents. The examples described herein should be considered only in an illustrative sense and not for limiting purposes. The description of the features or aspects in each example should be considered to be applicable to similar features or aspects in other examples. Appropriate results may be achieved if the techniques are performed in a different order and/or if the components in the system, architecture, device or circuit are combined in a different manner and/or replaced or supplemented with other components or their equivalent components. Therefore, the scope of the present invention is defined not by the detailed description but by the scope of the patent applications and their equivalents, and all variations within the scope of the patent applications and their equivalents should be deemed to be included in the present invention.

110: First substrate 120: Second substrate 130: Third substrate 210: First antenna component 220: Second antenna component 310, 320: Circuit 311, 321: Through-hole pad 410, 420: Through-hole 410’: Ground through-hole 500: Chip [A]: Part A1, A2: Block antenna C1, C2: Chamber MB: Motherboard P: Metal pillar S: Solder component SR: Solder resist

FIG. 1 is a diagram illustrating a package substrate according to an embodiment. FIG. 2 is a diagram illustrating a portion of a package substrate according to an embodiment. FIG. 3 is a diagram illustrating a first substrate in a package substrate according to an embodiment. FIG. 4 is a diagram illustrating a second substrate in a package substrate according to an embodiment. FIG. 5 is a diagram illustrating portion [A] of FIG. 2. FIG. 6 to FIG. 9 are diagrams illustrating a package substrate according to one or more embodiments. FIG. 10 and FIG. 11 are diagrams illustrating a chip package according to one or more embodiments. FIG. 12 is a diagram illustrating a chip package according to another embodiment. Throughout the drawings and detailed description, the same reference numerals refer to the same elements. The drawings may not be drawn to scale, and the relative size, proportion, and depiction of the elements in the drawings may be exaggerated for clarity, illustration, and convenience.

110: First base

120: Second base

210: First antenna component

220: Second antenna component

310, 320: Circuit

311, 321: Through hole pads

410, 420: through hole

A1, A2: Block antenna

C1: Chamber

S: Solder components

SR: Solder mask

Claims (12)

A packaging substrate, comprising: a first substrate having a plurality of first insulating layers connected to each other, a plurality of first circuits respectively arranged on or in the plurality of first insulating layers, and a solder resist layer arranged on the outermost insulating layer of the plurality of first insulating layers, a first antenna component being provided on one surface of the first substrate; a second substrate having a plurality of second insulating layers connected to each other and a second antenna component being provided on one surface of the second substrate, the one surface of the second substrate facing the first substrate and coupled to the other surface of the first substrate; and a first cavity formed in the first substrate and opened toward the other surface of the first substrate, passing through at least one of the plurality of first insulating layers, but excluding the outermost insulating layer. and having a bottom surface formed by a surface of the outermost insulating layer among the plurality of first insulating layers; and a second chamber formed in the second substrate and opened toward the first substrate, wherein the first antenna component is disposed on the outer surface of the first substrate, wherein one of the plurality of first circuits is disposed in the outermost insulating layer among the plurality of first insulating layers, the one first circuit having a first surface and a second surface opposite to the first surface, the first surface being coplanar with the one surface of the outermost insulating layer among the plurality of first insulating layers, the second surface being at least partially covered by the outermost insulating layer among the plurality of first insulating layers, and wherein the first substrate and the second substrate are spaced apart from each other. As described in item 1 of the patent application scope, a solder component is provided between the first substrate and the second substrate. As described in item 1 of the patent application scope, a packaging substrate is provided between the first substrate and the second substrate. A packaging substrate as described in item 1 of the patent application, wherein each of the first antenna component and the second antenna component includes two or more block antennas, and wherein the first cavity and the second cavity are formed in a position corresponding to each of the block antennas. A packaging substrate as described in item 1 of the patent application, wherein the second antenna component is formed on the bottom surface of the second cavity. A chip package comprises: a first substrate having a plurality of first insulating layers connected to each other, a plurality of first circuits respectively arranged on or in the plurality of first insulating layers, and a solder resist layer arranged on the outermost insulating layer of the plurality of first insulating layers, a first antenna component being provided on one surface of the first substrate; a second substrate having a plurality of second insulating layers connected to each other and a second antenna component being provided on one surface of the second substrate, the one surface of the second substrate facing the first substrate and coupled to the other surface of the first substrate; a first cavity formed in the first substrate and opened toward the other surface of the first substrate, passing through at least one of the plurality of first insulating layers, but excluding the outermost insulating layer, and having a first cavity formed by the plurality of first insulating layers; The outermost insulating layer in the insulating layer is a bottom surface formed by a surface of one of the insulating layers; a second chamber formed in the second substrate and opened toward the first substrate; and a chip mounted on the other surface of the second substrate, wherein the first antenna component is disposed on the outer surface of the first substrate, wherein one of the plurality of first circuits is disposed in the outermost insulating layer among the plurality of first insulating layers, the one first circuit has a first surface and a second surface opposite to the first surface, the first surface is coplanar with the one surface of the outermost insulating layer among the plurality of first insulating layers, the second surface is at least partially covered by the outermost insulating layer among the plurality of first insulating layers, and wherein the first substrate and the second substrate are spaced apart from each other. A chip package as described in item 6 of the patent application, wherein a solder component is provided between the first substrate and the second substrate. A chip package as described in item 6 of the patent application, wherein a metal column is provided between the first substrate and the second substrate. A chip package as described in item 6 of the patent application, wherein each of the first antenna component and the second antenna component includes two or more block antennas, and wherein the first chamber and the second chamber are respectively formed in positions corresponding to each block antenna. A chip package as described in item 6 of the patent application, wherein the second antenna component is formed on the bottom surface of the second chamber. The chip package as described in item 6 of the patent application further includes a third substrate coupled to the other surface of the second substrate, wherein an opening is formed in the third substrate to pass through the upper surface and the lower surface of the third substrate, and wherein the chip is mounted in the opening. A chip package as described in claim 11, wherein the second substrate and the third substrate are coupled via a solder member.