TWI854724B - Polarity inversion driving method, display driver chip and information processing device - Google Patents

Abstract

The present invention mainly discloses a polarity inversion driving method, which is applied in an LCD display and is executed by a control unit to generate a channel output control signal including K*N control signals and transmitted to a source driving unit; the polarity inversion driving method includes: in every N control signals of the channel output control signal, adjusting the low level width and/or pulse width of each control signal, thereby realizing disturbance of the voltage level of the positive polarity output signal and/or the voltage level of the negative polarity output signal output by the source driving unit, thereby improving the bright and dark stripe phenomenon derived from the staggered N-line inversion.

Description

Polarity reversal driving method, display driver chip and information processing device

The present invention relates to the technical field of LCD display devices, and in particular to a polarity inversion driving method that can avoid the bright and dark stripe problem derived from the staggered 4-line inversion method.

Liquid crystal display (LCD) has the advantages of low radiation, small size and low energy consumption. It has been widely used in laptops, tablet computers, smart phones, and other electronic products that need to be equipped with displays. Figure 1 is a block diagram of a known LCD display. As shown in Figure 1, the known LCD display 1a mainly includes: an LCD panel 11a, a color filter, a timing controller (Timing controller, Tcon) 120a, a gate drive circuit 121a, and a source drive circuit 122a, wherein the LCD panel includes a plurality of light valves and a plurality of pixel circuits for respectively controlling the plurality of light valves.

Electronic engineers familiar with the design and manufacture of LCD displays 1a know that the arrangement direction of the liquid crystal molecules of the light valve can be changed by controlling the driving voltage and the pixel circuit to adjust the transmittance of the light valve, and then the filtering effect of the color filter makes the designated sub-pixel display the designated color. However, liquid crystal molecules have a characteristic that they cannot be driven with a fixed voltage all the time, otherwise polarization will occur over time and the liquid crystal molecules will not be able to rotate with the change of the applied electric field. Therefore, the old technology uses the staggered 2-line inversion method to exchange the positive and negative polarity of the driving voltage of two adjacent rows, thereby avoiding the polarization of the liquid crystal molecules. Unfortunately, the interleaved 2-line inversion method will significantly increase the power consumption of the LCD display, so some system manufacturers have proposed an interleaved 4-line inversion method to drive the LCD panel with relatively low power consumption polarity inversion.

FIG2 is a working timing diagram of multiple signals used to implement interleaved 4-line inversion in the prior art. As shown in FIG1 and FIG2, electronic engineers familiar with the design and manufacture of LCD display 1a know that each channel of the timing controller 120a can be switched to provide a positive output signal Output_a or a negative output signal Output_b to the corresponding source line in the LCD panel 11a. Therefore, in the staggered 4-line inversion method, the timing controller 120a uses a channel output control signal TP to control the source driving circuit 122a, so that every four channels are switched to output a positive output signal Output_a or a negative output signal Output_b, and by pulling Output_a/Output_b to a low level/high level, the liquid crystal molecules of the light valves in the i-th row, i+1-th row, i+2-th row, and i+3-th row are successfully driven to achieve polarity inversion in regions (1), (2), (3), and (4), where i is a positive integer greater than 4. It should be noted that #0TP is a charge sharing pulse used to control the i-1-th row channel and the i-th row channel to perform charge sharing. Moreover, #1TP~#4TP are the pulse widths of the control signals respectively used to control the output signals of the channels in the i-th row to the i+3-th row. Under the control of pulses #1TP~#3TP, the channels in the i-th row to the i+2-th row are set in a high impedance state to maintain their positive or negative output. Furthermore, under the control of pulse #4TP, the channels in the i+3-th row and the channels in the i+4-th row share charge.

FIG3 is a diagram showing a display screen of an LCD panel 11a operating in staggered 4-line inversion. As shown in FIG2 and FIG3, practical experience shows that when displaying a white screen, the pixels in the i-th row that undergoes polarity inversion form dark lines due to insufficient charging, while the i+2 and i+3 rows have the same display potential as the i+1 row, so the storage capacitors are more fully charged and bright lines appear. At this time, the brightness of the pixels in the i-th row, i+1 row, i+2 row, and i+3 row are dark, bright, brighter, and brighter, respectively. In order to solve the problem of bright and dark stripes derived from the staggered 4-line inversion method, some industry insiders have developed a polymer stabilized liquid crystal (PSLC), whose discharge voltage response time toff is shortened, and the voltage response time ton can be improved by overdrive voltage. Unfortunately, the actual application results show that the PSLC LCD panel 11a with a fast response time still cannot improve the problem of bright and dark stripes derived from the staggered 4-line inversion method.

From the above description, it can be seen that a new polarity reversal driving method is urgently needed in this field.

The main purpose of the present invention is to provide a polarity inversion driving method, which is applied in an LCD display and is executed by a control unit to generate a channel output control signal including K*N control signals and transmit it to a source driving unit; the polarity inversion driving method includes: in each of the N control signals of the channel output control signal, adjusting the low level width and/or pulse width of each of the control signals, thereby disturbing the voltage level of the positive polarity output signal and/or the voltage level of the negative polarity output signal output by the source driving unit, thereby improving the bright and dark stripe phenomenon derived from the staggered N-line inversion.

For LCD displays using a point-to-point high-speed interface, the control unit is integrated into a source driver chip, which can output the channel output control signal to the source driver unit accordingly after receiving a width adjustment indication signal.

For an LCD display using a mini-LVDS interface, the source driver unit is integrated into a source driver chip, and the control unit is a timing controller, which is used to transmit a width adjustment indication signal including at least one low level width and at least one pulse width of each control signal to the source driver chip, so that the source driver chip generates the channel output control signal correspondingly according to the width adjustment indication signal and provides it to the source driver unit.

To achieve the above-mentioned purpose, the present invention proposes an embodiment of the polarity reversal driving method, which is applied in an LCD display and executed by a control unit to generate a channel output control signal to be transmitted to a source driving unit; wherein the channel output control signal includes a charge sharing control signal and K*N control signals, the charge sharing control signal and each of the control signals have a low level width and a pulse width, N is an even number and at least 4, and K is a positive integer; its characteristic is that the polarity reversal driving method includes: receiving a width adjustment indication signal; and adjusting the low level width and/or pulse width of each of the control signals in each of the N control signals according to the width adjustment indication signal.

In one embodiment, among every N control signals, the pulse width of at least one control signal with an even sequence number is shortened.

According to a feasible embodiment of the present invention, when the pulse width of the control signal with an even sequence number is shortened, the voltage levels of the positive output signal and the negative output signal output by the corresponding channel of the source drive unit are pulled to a first reference voltage and a second reference voltage respectively. The first reference voltage and the second reference voltage are the same or different.

According to another feasible embodiment of the present invention, when the pulse width of the control signal with an even sequence number is shortened, the corresponding channel of the source drive unit and the adjacent channel perform charge sharing.

In one embodiment, in every N control signals, the low level width of the first control signal is extended, and the low level width of the second control signal is correspondingly shortened.

In a feasible embodiment, among every N control signals, the pulse width of at least one control signal with an odd sequence number is also shortened.

According to a feasible embodiment of the present invention, when the pulse width of the control signal with an odd sequence number is shortened, the voltage levels of the positive output signal and the negative output signal output by the corresponding channel of the source drive unit are pulled to a first reference voltage and a second reference voltage respectively. The first reference voltage and the second reference voltage are the same or different.

According to another feasible embodiment of the present invention, when the pulse width of the control signal with an odd sequence number is shortened, the corresponding channel of the source drive unit and the adjacent channel perform charge sharing.

In one application example, the source drive unit and the control unit are integrated into a source drive chip, and the control unit includes at least one register, which records at least one low level width and at least one pulse width of each control signal, so that the control unit can output the channel output control signal to the source drive unit accordingly after receiving the width adjustment indication signal.

In another application example, the source driver unit is integrated into a source driver chip, and the control unit is a timing controller, which is used to transmit the width adjustment indication signal including at least one low-level width and at least one pulse width of each control signal to the source driver chip, so that the source driver chip generates the channel output control signal correspondingly according to the width adjustment indication signal and provides it to the source driver unit.

In addition, the present invention also proposes a display driver chip, which executes the polarity inversion driving method of the present invention as described above to drive an LCD panel, thereby enabling the LCD panel to achieve staggered N-line inversion.

Furthermore, the present invention also proposes an information processing device having an LCD display including a display driver circuit and an LCD panel; the characteristic of the display driver circuit is that the display driver circuit performs the polarity inversion driving method of the present invention as described above to drive an LCD panel, thereby enabling the LCD panel to achieve N-line inversion.

In one embodiment, the information processing device is an electronic device selected from the group consisting of a head-mounted display device, a smart TV, a smart phone, a smart watch, a tablet computer, an all-in-one computer, a laptop computer, an in-vehicle entertainment device, a digital camera, and a video door phone.

1a: LCD display

11a: LCD panel

120a: Timing controller

121a: Gate drive circuit

122a: Source drive circuit

1: LCD display

11: LCD panel

120: Timing controller

121: Gate drive circuit

122: Source drive circuit

S1: Receive a width adjustment indication signal

S2: According to the width adjustment indication signal, in each of the N control signals, adjust the low level width and/or pulse width of each of the control signals.

FIG. 1 is a block diagram of a known LCD display; FIG. 2 is a timing diagram of a plurality of signals used to implement interlaced 4-line inversion in the known art; FIG. 3 is a diagram of a display screen of an LCD panel operating in interlaced 4-line inversion; FIG. 4 is a block diagram of an LCD display to which a polarity inversion driving method of the present invention is applied; FIG. 5 is a flow chart of a polarity inversion driving method of the present invention; FIG. 6 is a flow chart of a polarity inversion driving method of the present invention; FIG. 7 is a first working timing diagram of multiple signals of the first application example of the polarity reversal driving method of the present invention; FIG. 8 is a first working timing diagram of multiple signals of the second application example of the polarity reversal driving method of the present invention; FIG. 9 is a second working timing diagram of multiple signals of the second application example of the polarity reversal driving method of the present invention; FIG. 10 is a second working timing diagram of multiple signals of the second application example of the polarity reversal driving method of the present invention. FIG. 11 is a first working timing diagram of multiple signals of the third application example of the polarity reversal driving method of the present invention; FIG. 12 is a first working timing diagram of multiple signals of the fourth application example of the polarity reversal driving method of the present invention; FIG. 13 is a second working timing diagram of multiple signals of the fourth application example of the polarity reversal driving method of the present invention; FIG. 14 is a second working timing diagram of multiple signals of the fourth application example of the polarity reversal driving method of the present invention; FIG15 is a first working timing diagram of multiple signals of the fifth application example of the polarity reversal driving method of the present invention; FIG16 is a first working timing diagram of multiple signals of the sixth application example of the polarity reversal driving method of the present invention; and FIG17 is a second working timing diagram of multiple signals of the sixth application example of the polarity reversal driving method of the present invention.

In order to enable the review committee to further understand the structure, features, purpose, and advantages of the present invention, the detailed description of the drawings and preferred specific embodiments is attached as follows.

FIG4 is a block diagram of an LCD display using a polarity inversion driving method of the present invention. As shown in FIG4 , the LCD display 1 mainly includes: an LCD panel 11, a color filter, a timing controller (Tcon) 120, a gate driving circuit 121, and a source driving circuit 122. The polarity inversion driving method of the present invention is improved on the basis of the known technology of staggered N-line inversion, so that the timing controller 120 executes the polarity inversion driving method of the present invention, thereby controlling the source driving circuit 122 to drive the LCD panel 11 to realize staggered N-line inversion, and the display screen of the LCD panel 11 will not have bright and dark stripes.

FIG5 is a flow chart of a polarity reversal driving method of the present invention. As shown in FIG5, the polarity reversal driving method of the present invention includes the following steps: Step S1: receiving a width adjustment indication signal; and Step S2: adjusting the low level width and/or pulse width of each of the N control signals according to the width adjustment indication signal, where N is an even number greater than or equal to 4.

According to the design of the present invention, among every N control signals, the pulse width of the control signal with an even sequence number is shortened.

According to a feasible embodiment of the present invention, when the pulse width of the control signal with an even sequence number is shortened, the voltage level of a positive output signal output by a corresponding channel of the source drive unit is pulled to a first reference voltage, and the voltage level of a negative output signal output by the channel is pulled to a second reference voltage. The first reference voltage and the second reference voltage are the same or different.

Furthermore, according to another feasible embodiment of the present invention, when the pulse width of an even-numbered sequence is shortened, a corresponding channel of the source drive unit and the next adjacent channel share charge, so that the voltage level of a positive output signal output by the channel is pulled to a first reference voltage, and the voltage level of a negative output signal output by the channel is pulled to a second reference voltage. The first reference voltage and the second reference voltage are the same or different.

To explain in more detail, according to the design of the present invention, in every N control signals, the low level width of the first control signal is extended, and the low level width of the second control signal is correspondingly shortened. In addition, in conjunction with the shortening of the low level width and pulse width of the second control signal, the low level widths of the other control signals are appropriately adjusted to eliminate the bright and dark fringes phenomenon derived from the interlaced N-line inversion of the prior art.

First application case

FIG6 is a first operation timing diagram of multiple signals of the first application example of the polarity inversion driving method of the present invention. As shown in FIG6, if the source driving circuit 122 adopts multiple signals as shown in FIG6, it can drive the LCD panel 11 to achieve 4-line inversion. In FIG6, a channel output control signal TP for transmitting to a source driving unit of the source driving circuit 122 includes a charge sharing control signal and K*N control signals, where N is 4 and K is 1. To be more specific, the charge sharing control signal has a low level width and a pulse width (#0TP), and each of the control signals has a low level width and a pulse width (#1TP~#4TP).

Please refer again to the channel output control signal TP designed by the prior art shown in FIG. 2, which also includes a charge sharing control signal and K*N control signals, wherein the charge sharing control signal has a low level width and a pulse width (#0TP), and each of the control signals has a low level width and a pulse width (#1TP~#4TP). It is worth noting that the charge sharing control signal and each of the control signals have the same signal cycle (1 clock), the low level width of the charge sharing control signal and the low level width of each of the control signals are the same, and the pulse width of the charge sharing control signal and the pulse width of each of the control signals (#1TP~#4TP) are also the same.

By comparing FIG. 2 with FIG. 6 , it can be found that after receiving the width adjustment indication signal (i.e., step S1), the control unit adjusts the low level width and/or pulse width of each of the control signals in each of the N control signals according to the width adjustment indication signal. Specifically, in the first application example shown in FIG. 6 , when the charge sharing control signal #0TP performs charge sharing when the positive and negative polarity is switched, the display brightness of the i-th row display area (i.e., area (1)) and the i+1-th row display area (i.e., area (2)) shown in FIG. 3 can be adjusted to be similar by extending the low level width of the control signal #1TP and shortening the low level width of the control signal #2TP. At the same time, by shortening the pulse width of the control signal #2TP, the voltage level of a positive output signal output by a corresponding channel of the source drive unit is pulled to a first reference voltage so that the positive output potential is close to HAVDD, and the voltage level of a negative output signal output by the channel is pulled to a second reference voltage so that the negative output potential is close to HAVDD. The first reference voltage and the second reference voltage can be the same or different.

In other words, except for the last control signal (#4TP) as the charge sharing control signal, the present invention shortens the pulse width of the second control signal (#2TP) with an even ranking bit, thereby causing the voltage level of the positive output signal and/or the voltage level of the negative output signal output by the corresponding channel of the source drive unit to be disturbed, thereby improving the bright and dark stripes phenomenon derived from the staggered 4-line inversion. At the same time, as shown in FIG6, the present invention also adaptively adjusts the low-level width of the control signal #3TP in conjunction with the shortening of the pulse width and low-level width of the control signal #2TP, so that the display brightness of the i+1th row display area (i.e., area (2)) and the i+2th row display area (i.e., area (3)) shown in FIG3 are similar. At the same time, in conjunction with the change of the low-level width of the control signal #3TP, the low-level width of the control signal #4TP is also adaptively adjusted, so that the display brightness of the i+2th row display area (i.e., area (3)) and the i+3th row display area (i.e., area (4)) shown in FIG3 are similar.

FIG7 is a second operation timing diagram of multiple signals of the first application example of the polarity inversion driving method of the present invention. Comparing FIG6 and FIG7, it can be seen that if the source driving circuit 122 adopts multiple signals as shown in FIG7, it can drive the LCD panel 11 to achieve 8-line inversion. In FIG7, a channel output control signal TP for transmitting to a source driving unit of the source driving circuit 122 includes a charge sharing control signal and K*N control signals, where N is 4 and K is 2. To explain in more detail, the charge sharing control signal has a low level width and a pulse width (#0TP), and each of the control signals has a low level width and a pulse width (#1TP~#8TP). It should be noted that in FIG6, the last control signal (#4TP) is also a charge sharing control signal. Similarly, in FIG7, the last control signal (#8TP) is also a charge sharing control signal, so it is not specially drawn in the channel output control signal TP shown in FIG7.

As shown in FIG. 7 , after receiving the width adjustment indication signal (ie, step S1 ), the control unit adjusts the low level width and/or pulse width of each of the N control signals according to the width adjustment indication signal. Specifically, among every N control signals, except for the last control signal (#8TP) as the charge sharing control signal, the pulse widths of the control signals with even numbers (i.e., #2TP, #4TP, #6TP) are shortened so that the voltage levels of the positive output signal and the negative output signal output by the corresponding channel of the source drive unit are pulled to the first reference voltage (i.e., toward HAVDD) and the second reference voltage (i.e., toward HAVDD) respectively.

That is, the present invention shortens the pulse width of the control signal (#2TP, #4TP, #6TP) with an even sequence number to disturb the voltage level of the positive output signal and/or the voltage level of the negative output signal output by the corresponding channel of the source drive unit, thereby improving the bright and dark stripe phenomenon derived from the interlaced 8-line inversion.

It is additionally explained that for an LCD display 1 using a point-to-point high-speed interface, the source drive circuit and the control unit may be integrated into a source drive chip at the same time. In this case, the control unit may include at least one register, and at least one low-level width and at least one pulse width of each control signal (#1TP~#4TP or #1TP~#8TP) may be pre-set in the register, so that the control unit can quickly and correspondingly output the channel output control signal TP to the source drive unit after receiving a width adjustment indication signal.

On the other hand, for an LCD display using a mini-LVDS interface, the source driver unit is integrated into a source driver chip, and the control unit is a timing controller. In this case, the timing controller can be configured to transmit a width adjustment indication signal including at least one low level width and at least one pulse width of each of the control signals to the source driver chip, so that the source driver chip generates the channel output control signal correspondingly according to the width adjustment indication signal and provides it to the source driver unit.

Second application case

FIG8 is a first operation timing diagram of multiple signals of the second application example of the polarity inversion driving method of the present invention. As shown in FIG8, if the source driving circuit 122 adopts multiple signals as shown in FIG8, it can drive the LCD panel 11 to achieve staggered 4-line inversion. In FIG8, a channel output control signal TP of a source driving unit for transmitting to the source driving circuit 122 includes a charge sharing control signal and K*N control signals, where N is 4 and K is 1. To explain in more detail, the charge sharing control signal has a low level width and a pulse width (#0TP), and each of the control signals has a low level width and a pulse width (#1TP~#4TP). By comparing FIG. 2 with FIG. 8 , it can be found that after receiving the width adjustment indication signal (i.e., step S1), the control unit adjusts the low level width and/or pulse width of each of the control signals in every N control signals according to the width adjustment indication signal. Specifically, in the second application example shown in FIG. 8 , when the charge sharing control signal #0TP performs charge sharing when the polarity of the charge sharing control signal #0TP is switched between positive and negative, the display brightness of the i-th row display area (i.e., area (1)) and the i+1-th row display area (i.e., area (2)) shown in FIG. 3 can be adjusted to be similar by extending the low level width of the control signal #1TP and shortening the low level width of the control signal #2TP. At the same time, by shortening the pulse width of the control signal (#2TP) with an even sequence number, the corresponding channel of the source drive unit and the next adjacent channel share charge, so that the voltage level of the positive output signal output by the channel is close to HAVDD, and the voltage level of the negative output signal output by the channel is also close to HAVDD. That is, the present invention shortens the pulse width of the control signal (#2TP) with an even sequence number to disturb the voltage level of the positive output signal and/or the voltage level of the negative output signal output by the corresponding channel of the source drive unit, thereby improving the bright and dark stripe phenomenon derived from the staggered 4-line inversion.

Furthermore, in conjunction with the shortening of the pulse width and low-level width of the control signal #2TP, the low-level width of the control signal #3TP is adaptively adjusted, so that the display brightness of the i+1th row display area (i.e., area (2)) and the i+2th row display area (i.e., area (3)) as shown in FIG3 can be similar. At the same time, in conjunction with the change of the low-level width of the control signal #3TP, the low-level width of the control signal #4TP is adaptively adjusted, so that the display brightness of the i+2th row display area (i.e., area (3)) and the i+3th row display area (i.e., area (4)) as shown in FIG3 can be similar.

FIG9 is a second operation timing diagram of multiple signals of the second application example of the polarity inversion driving method of the present invention. Comparing FIG8 and FIG9, it can be seen that if the source driving circuit 122 adopts multiple signals as shown in FIG9, it can drive the LCD panel 11 to achieve 8-line inversion. In FIG9, a channel output control signal TP for transmitting to a source driving unit of the source driving circuit 122 includes a charge sharing control signal and K*N control signals, where N is 4 and K is 2. To explain in more detail, the charge sharing control signal has a low level width and a pulse width (#0TP), and each of the control signals has a low level width and a pulse width (#1TP~#8TP). It should be noted that in FIG9, the last control signal (#8TP) is also a charge sharing control signal, so it is not specially drawn in the channel output control signal TP shown in FIG9.

As shown in FIG9 , after receiving the width adjustment indication signal (i.e., step S1), the control unit uses one or more registers inside thereof to adjust the low level width and/or pulse width of each of the control signals in every N control signals according to the width adjustment indication signal. Specifically, in every N control signals, except for the last control signal (#8TP) as the charge sharing control signal, the pulse width of the control signals with even sequence numbers (i.e., #2TP, #4TP, or #6TP) is shortened. As shown in FIG8 , by shortening the pulse width of the control signal with an even sequence number, the corresponding channel of the source drive unit and its adjacent channel share charge, so that the voltage level of the positive output signal output by the channel approaches HAVDD, and at the same time, the voltage level of the negative output signal output by the channel also approaches HAVDD. That is, the present invention shortens the pulse width of the control signal (#2TP, #4TP, #6TP) with an even sequence number to disturb the voltage level of the positive output signal and/or the voltage level of the negative output signal output by the corresponding channel of the source drive unit, thereby improving the bright and dark stripe phenomenon derived from the interlaced 8-line inversion.

Third application case

FIG10 is a first operation timing diagram of multiple signals of the third application example of the polarity inversion driving method of the present invention. As shown in FIG10, if the source driving circuit 122 adopts multiple signals as shown in FIG10, it can drive the LCD panel 11 to achieve 4-line inversion. In FIG10, a channel output control signal TP for transmitting to a source driving unit of the source driving circuit 122 includes a charge sharing control signal and K*N control signals, where N is 4 and K is 1. To explain in more detail, the charge sharing control signal has a low level width and a pulse width (#0TP), and each of the control signals has a low level width and a pulse width (#1TP~#4TP). Moreover, in FIG. 10 , the last control signal (#4TP) is also a charge sharing control signal.

After receiving the width adjustment indication signal (i.e., step S1), the control unit adjusts the low level width and/or pulse width of each of the control signals in every N control signals according to the width adjustment indication signal. Specifically, in the third application example shown in FIG10, when the charge sharing control signal #0TP performs charge sharing when the polarity changes from positive to negative, the display brightness of the i-th row display area (i.e., area (1)) and the i+1-th row display area (i.e., area (2)) shown in FIG3 can be adjusted to be similar by extending the low level width of the control signal #1TP and shortening the low level width of the control signal #2TP. At the same time, by shortening the pulse width of the control signal #2TP, the voltage level of a positive output signal output by a corresponding channel of the source drive unit is pulled to a first reference voltage so that the positive output potential is close to HAVDD, and the voltage level of a negative output signal output by the channel is pulled to a second reference voltage so that the negative output potential is close to HAVDD. The first reference voltage and the second reference voltage can be the same or different. At the same time, by shortening the pulse width of the control signal #3TP, the voltage level of a positive output signal output by a corresponding channel of the source drive unit is pulled to a first reference voltage so that the positive output potential is close to HAVDD, and the voltage level of a negative output signal output by the channel is pulled to a second reference voltage so that the negative output potential is close to HAVDD.

In other words, in the first application example shown in FIG. 6 , the pulse width of the control signal with an even sequence number is shortened (except for the last control signal as a charge sharing control signal) to disturb the voltage level of the positive output signal and/or the voltage level of the negative output signal output by the corresponding channel of the source drive unit, thereby improving the bright and dark stripes phenomenon derived from the interlaced 4-line inversion. It is worth noting that in the third application example shown in FIG. 10 , in addition to shortening the pulse width of the control signal with an even sequence number (i.e., #2TP), the pulse width of the control signal with an odd sequence number (i.e., #3TP) is further shortened, thereby disturbing the voltage level of the positive output signal and/or the voltage level of the negative output signal output by the corresponding channel of the source driving unit, thereby improving the bright and dark fringes phenomenon derived from the interleaved 4-line inversion. As a supplementary explanation, it can be seen from Figure 10 that when the pulse width of the control signal with an odd sequence number is shortened, the pulse width of the first control signal is not shortened.

Similarly, in the third application example, the low level width of the control signal #3TP is adaptively adjusted in conjunction with the shortening of the pulse width and low level width of the control signal #2TP, so that the display brightness of the i+1th row display area (i.e., area (2)) and the i+2th row display area (i.e., area (3)) as shown in FIG. 3 are similar. At the same time, in conjunction with the change of the pulse width and low level width of the control signal #3TP, the low level width of the control signal #4TP is also adaptively adjusted, so that the display brightness of the i+2th row display area (i.e., area (3)) and the i+3th row display area (i.e., area (4)) as shown in FIG. 3 are similar.

FIG11 is a second operation timing diagram of multiple signals of the third application example of the polarity inversion driving method of the present invention. Comparing FIG10 with FIG11, it can be seen that if the source driving circuit 122 adopts multiple signals as shown in FIG11, it can drive the LCD panel 11 to achieve 8-line inversion. In FIG11, a channel output control signal TP for transmitting to a source driving unit of the source driving circuit 122 includes a charge sharing control signal and K*N control signals, where N is 4 and K is 2. To explain in more detail, the charge sharing control signal has a low level width and a pulse width (#0TP), and each of the control signals has a low level width and a pulse width (#1TP~#8TP). In FIG11, the last control signal (#8TP) is also a charge sharing control signal, so it is not specially drawn in the channel output control signal TP shown in FIG11.

As shown in FIG11 , after receiving the width adjustment indication signal (i.e., step S1), the control unit uses one or more registers inside thereof to adjust the low level width and/or pulse width of each of the control signals in each of the N control signals according to the width adjustment indication signal. Specifically, in each of the N control signals, except for the first control signal (#1TP) and the last control signal (#8TP) as the charge sharing control signal, the pulse widths of the control signals with even sequence numbers (i.e., #2TP, #4TP, #6TP) are all shortened, and the pulse widths of the control signals with odd sequence numbers (i.e., #3TP, #5TP, #7TP) are also shortened. In this case, the positive output signal of the corresponding channel of the source drive unit is pulled to the first reference voltage and thus close to HAVDD, and the voltage level of the negative output signal is pulled to the second reference voltage and thus close to HAVDD, thereby improving the bright and dark stripe phenomenon derived from the interlaced 8-line inversion.

Fourth application case

FIG12 is a first operation timing diagram of multiple signals of the fourth application example of the polarity inversion driving method of the present invention. As shown in FIG12, if the source driving circuit 122 adopts multiple signals as shown in FIG12, it can drive the LCD panel 11 to achieve 4-line inversion. In FIG12, a channel output control signal TP for transmitting to a source driving unit of the source driving circuit 122 includes a charge sharing control signal and K*N control signals, where N is 4 and K is 1. To explain in more detail, the charge sharing control signal has a low level width and a pulse width (#0TP), each of the control signals has a low level width and a pulse width (#1TP~#4TP), and the last control signal serves as a charge sharing control signal.

After receiving the width adjustment indication signal (i.e., step S1), the control unit adjusts the low level width and/or pulse width of each of the control signals in each of the N control signals according to the width adjustment indication signal. Specifically, in the fourth application example shown in FIG12, when the charge sharing control signal #0TP performs charge sharing when the polarity changes from positive to negative, the display brightness of the i-th row display area (i.e., area (1)) and the i+1-th row display area (i.e., area (2)) shown in FIG3 can be adjusted to be similar by extending the low level width of the control signal #1TP and shortening the low level width of the control signal #2TP. At the same time, by shortening the pulse width of the control signal (#2TP) with an even sequence number, a channel corresponding to the source drive unit and the next adjacent channel share charge, so that the voltage level of the positive output signal output by the channel approaches HAVDD, and at the same time, the voltage level of the negative output signal output by the channel also approaches HAVDD. At the same time, the pulse width of the control signal (#3TP) with an odd sequence number is shortened, so that the corresponding channel of the source drive unit and the next adjacent channel share charge, so that the voltage level of the positive output signal output by the channel is close to HAVDD, and the voltage level of the negative output signal output by the channel is also close to HAVDD. It can be supplemented that, as shown in Figure 12, when the pulse width of the control signal with an odd sequence number is shortened, the pulse width of the first control signal is not shortened.

That is, the present invention improves the bright and dark stripe phenomenon derived from the staggered 4-line inversion by shortening the pulse width of the control signal (#2TP, #3TP) with even and odd sequence numbers to disturb the voltage level of the positive output signal and/or the voltage level of the negative output signal output by the corresponding channel of the source driving unit. Furthermore, by shortening the low level width of the control signal #2TP and adaptively adjusting the low level width of the control signal #3TP, the display brightness of the i+1th row display area (i.e., area (2)) and the i+2th row display area (i.e., area (3)) as shown in FIG. 3 can be similar. At the same time, in conjunction with the change in the low-level width of the control signal #3TP, the low-level width of the control signal #4TP is adaptively adjusted so that the display brightness of the i+2th row display area (i.e., area (3)) and the i+3th row display area (i.e., area (4)) as shown in Figure 3 are similar.

FIG9 is a second operation timing diagram of multiple signals of the fourth application example of the polarity inversion driving method of the present invention. If the source driving circuit 122 adopts multiple signals as shown in FIG13, it can drive the LCD panel 11 to achieve 8-line inversion. In FIG13, a channel output control signal TP for transmitting to a source driving unit of the source driving circuit 122 includes a charge sharing control signal and K*N control signals, wherein N is 4 and K is 2. In more detail, the charge sharing control signal has a low level width and a pulse width (#0TP), and each of the control signals has a low level width and a pulse width (#1TP~#8TP). It should be noted that in Figure 13, the last control signal (#8TP) is also a charge sharing control signal, so it is not specially drawn in the channel output control signal TP shown in Figure 13.

As shown in FIG13 , after receiving the width adjustment indication signal (i.e., step S1), the control unit uses one or more registers inside thereof to adjust the low level width and/or pulse width of each of the control signals in every N control signals according to the width adjustment indication signal. Specifically, in every N control signals, except for the first control signal (#1TP) and the last control signal (#8TP) as the charge sharing control signal, the pulse width of the control signal with an even sequence number (i.e., #2TP, #4TP, or #6TP) is shortened, and the pulse width of the control signal with an odd sequence number (i.e., #3TP, #5TP, or #7TP) is also shortened. As shown in Figure 12, by shortening the pulse width of the control signal with an even/odd sequence number, the corresponding channel of the source drive unit and its adjacent channel share charge, so that the voltage level of the positive output signal output by the channel is close to HAVDD, and the voltage level of the negative output signal output by the channel is also close to HAVDD, thereby disturbing the voltage level of the positive output signal/negative output signal, thereby improving the bright and dark stripes phenomenon derived from the interlaced 8-line inversion.

Fifth application case

FIG14 is a first operation timing diagram of multiple signals of the fifth application example of the polarity inversion driving method of the present invention. As shown in FIG14, if the source driving circuit 122 adopts multiple signals as shown in FIG10, it can drive the LCD panel 11 to achieve 4-line inversion. In FIG14, a channel output control signal TP for transmitting to a source driving unit of the source driving circuit 122 includes a charge sharing control signal and K*N control signals, where N is 4 and K is 1. To explain in more detail, the charge sharing control signal has a low level width and a pulse width (#0TP), and each of the control signals has a low level width and a pulse width (#1TP~#4TP). Moreover, in FIG. 14 , the last control signal (#4TP) is also a charge sharing control signal.

After receiving the width adjustment indication signal (ie, step S1), the control unit adjusts the low level width and/or pulse width of each of the N control signals according to the width adjustment indication signal. Specifically, in the fifth application example shown in FIG. 14 , when the charge sharing control signal #0TP performs charge sharing when the positive and negative polarities are switched, the pulse width of the control signal (#1TP, #3TP) with an odd sequence number is shortened, so that the voltage level of the positive output signal output by the corresponding channel of the source drive unit is pulled to the first reference voltage to approach HAVDD, and the voltage level of the negative output signal output by the corresponding channel is pulled to the second reference voltage to approach HAVDD. The first reference voltage and the second reference voltage may be the same or different. At the same time, in addition to the last control signal (#4TP) as the charge sharing control signal, the pulse width of the control signal (#2TP) with an even sequence number is shortened, so that the voltage level of the positive output signal output by the corresponding channel of the source drive unit is pulled to the first reference voltage and close to HAVDD, and the voltage level of the negative output signal output by the corresponding channel is pulled to the second reference voltage and close to HAVDD.

Furthermore, by extending the low level width of the control signal #1TP and shortening the low level width of the control signal #2TP, the display brightness of the i-th row display area (i.e., area (1)) and the i+1-th row display area (i.e., area (2)) as shown in FIG. 3 can be adjusted to be similar. At the same time, the low level width of the control signal #3TP is adaptively adjusted in conjunction with the shortening of the low level width of the control signal #2TP, so that the display brightness of the i+1-th row display area (i.e., area (2)) and the i+2-th row display area (i.e., area (3)) as shown in FIG. 3 is similar. At the same time, in conjunction with the change in the low-level width of the control signal #3TP, the low-level width of the control signal #4TP is also adaptively adjusted so that the display brightness of the i+2th row display area (i.e., area (3)) and the i+3th row display area (i.e., area (4)) as shown in FIG. 3 are similar. In other words, in the fifth application example shown in FIG. 14 , the pulse widths of all control signals (except the last control signal as a charge sharing control signal) are shortened to disturb the voltage level of the positive output signal and/or the voltage level of the negative output signal output by the corresponding channel of the source drive unit, thereby improving the bright and dark fringes phenomenon derived from the interleaved 4-line inversion.

FIG15 is a second operation timing diagram of multiple signals of the fifth application example of the polarity inversion driving method of the present invention. If the source driving circuit 122 adopts multiple signals as shown in FIG15, it can drive the LCD panel 11 to achieve 8-line inversion. In FIG15, a channel output control signal TP of a source driving unit for transmitting to the source driving circuit 122 includes a charge sharing control signal and K*N control signals, where N is 4 and K is 2. To explain in more detail, the charge sharing control signal has a low level width and a pulse width (#0TP), and each of the control signals has a low level width and a pulse width (#1TP~#8TP). In Figure 15, the last control signal (#8TP) is also a charge sharing control signal, so it is not specially drawn in the channel output control signal TP shown in Figure 15.

After receiving the width adjustment indication signal (i.e., step S1), the control unit uses one or more registers inside thereof to adjust the low level width and/or pulse width of each of the control signals in each of the N control signals according to the width adjustment indication signal. Specifically, in each of the N control signals, except for the last control signal (#8TP) as the charge sharing control signal, the pulse widths of the control signals with even sequence numbers (i.e., #2TP, #4TP, #6TP) are all shortened, and the pulse widths of the control signals with odd sequence numbers (i.e., #1TP, #3TP, #5TP, #7TP) are also shortened. In this case, the positive output signal of the corresponding channel of the source drive unit is pulled to the first reference voltage and thus close to HAVDD, and the voltage level of the negative output signal is pulled to the second reference voltage and thus close to HAVDD, thereby improving the bright and dark stripe phenomenon derived from the interlaced 8-line inversion.

Sixth application case

FIG16 is a first operation timing diagram of multiple signals of the sixth application example of the polarity inversion driving method of the present invention. If the source driving circuit 122 adopts multiple signals as shown in FIG16, it can drive the LCD panel 11 to achieve staggered 4-line inversion. After receiving the width adjustment indication signal (i.e., step S1), the control unit adjusts the low level width and/or pulse width of each of the control signals in every N control signals according to the width adjustment indication signal. Specifically, in the sixth application example shown in FIG16 , when the charge sharing control signal #0TP performs charge sharing when switching between positive and negative polarity, the pulse width of the control signal (#1TP, #3TP) with an odd sequence number is shortened so that the corresponding channel of the source drive unit performs charge sharing with the adjacent channel, so that the voltage level of the positive output signal output by the corresponding channel approaches HAVDD, and the voltage level of the negative output signal output by the corresponding channel also approaches HAVDD. At the same time, in addition to the last control signal (#4TP) being a charge sharing control signal, the pulse width of the control signal (#2TP) with an even sequence number is shortened, so that the corresponding channel of the source drive unit shares charge with the adjacent channel, so that the voltage level of the positive output signal output by the corresponding channel is close to HAVDD, and the voltage level of the negative output signal output by the corresponding channel is also close to HAVDD.

Furthermore, by extending the low level width of the control signal #1TP and shortening the low level width of the control signal #2TP, the display brightness of the i-th row display area (i.e., area (1)) and the i+1-th row display area (i.e., area (2)) as shown in FIG3 can be adjusted to be similar. At the same time, the low level width of the control signal #3TP is adaptively adjusted in conjunction with the shortening of the low level width of the control signal #2TP, so that the display brightness of the i+1-th row display area (i.e., area (2)) and the i+2-th row display area (i.e., area (3)) as shown in FIG3 is similar. At the same time, in conjunction with the change in the low-level width of the control signal #3TP, the low-level width of the control signal #4TP is also adaptively adjusted so that the display brightness of the i+2th row display area (i.e., area (3)) and the i+3th row display area (i.e., area (4)) as shown in Figure 3 are similar. In other words, in the fifth application example shown in FIG. 14 , the pulse widths of all control signals (except the last control signal as a charge sharing control signal) are shortened to disturb the voltage level of the positive output signal and/or the voltage level of the negative output signal output by the corresponding channel of the source drive unit, thereby improving the bright and dark fringes phenomenon derived from the interleaved 4-line inversion.

FIG17 is a second operation timing diagram of multiple signals of the sixth application example of the polarity inversion driving method of the present invention. If the source driving circuit 122 adopts multiple signals as shown in FIG17, it can drive the LCD panel 11 to achieve 8-line inversion. In FIG17, a channel output control signal TP for transmitting to a source driving unit of the source driving circuit 122 includes a charge sharing control signal and K*N control signals, where N is 4 and K is 2. To explain in more detail, the charge sharing control signal has a low level width and a pulse width (#0TP), and each of the control signals has a low level width and a pulse width (#1TP~#8TP). In Figure 17, the last control signal (#8TP) is also a charge sharing control signal, so it is not specially drawn in the channel output control signal TP shown in Figure 17.

After receiving the width adjustment indication signal (i.e., step S1), the control unit uses one or more registers inside thereof to adjust the low level width and/or pulse width of each of the control signals in each of the N control signals according to the width adjustment indication signal. Specifically, in each of the N control signals, except for the last control signal (#8TP) as the charge sharing control signal, the pulse widths of the control signals with even sequence numbers (i.e., #2TP, #4TP, #6TP) are shortened, and the pulse widths of the control signals with odd sequence numbers (i.e., #1TP, #3TP, #5TP, #7TP) are also shortened. In this case, the corresponding channel of the source drive unit shares charge with its adjacent channel, so that the voltage level of the positive output signal output by the corresponding channel is close to HAVDD, and the voltage level of the negative output signal output by the corresponding channel is also close to HAVDD.

That is, the present invention achieves disturbance of the voltage level of the positive output signal and/or the voltage level of the negative output signal output by the corresponding channel of the source drive unit by shortening the pulse width of the odd/even control signal, thereby improving the bright and dark stripe phenomenon derived from the interlaced 8-line inversion.

According to the above description, the present invention proposes a display driver chip, which executes the polarity inversion driving method of the present invention as mentioned above to drive an LCD panel, so that the LCD panel realizes staggered N-line inversion (N-line inversion), wherein the display driver chip includes a source driver circuit 122.

In addition, according to the above description, the present invention also proposes an information processing device, which has an LCD display including a display driver circuit and an LCD panel; its characteristic is that the display driver circuit executes the polarity inversion driving method of the present invention as mentioned above to drive the LCD panel, so that the LCD panel realizes interlaced N-line inversion (N-line inversion), wherein the display driver circuit includes a source driver circuit 122.

In addition, the information processing device may be a head-mounted display device, a smart TV, a smart phone, a smart watch, a tablet computer, an all-in-one computer, a notebook computer, an in-vehicle entertainment device, a digital camera, or a video door machine.

Thus, the above has completely and clearly described a polarity reversal driving method of the present invention; and, from the above, it can be known that the present invention has the following advantages:

(1) The present invention discloses a polarity inversion driving method, which is applied in an LCD display and is executed by a control unit to generate a channel output control signal including K*N control signals and transmit it to a source driving unit; the polarity inversion driving method includes: in each of the N control signals of the channel output control signal, adjusting the low level width and/or pulse width of each of the control signals, thereby disturbing the voltage level of the positive polarity output signal and/or the voltage level of the negative polarity output signal output by the source driving unit, thereby improving the bright and dark stripe phenomenon derived from the staggered N-line inversion.

(2) The polarity inversion driving method of the present invention can be applied to LCD displays using a point-to-point high-speed interface or an LCD display using a mini-LVDS interface.

(3) The polarity inversion driving method of the present invention can utilize one or more registers to assist in completing the change setting of the pulse width and/or low-level width of at least one control signal.

(4) The polarity inversion driving method of the present invention can be transmitted by the timing controller Tcon to the source driver chip, which includes at least one low-level width and at least one pulse width of each control signal, so that the source driver chip can complete the change setting of the pulse width and/or low-level width of at least one control signal according to the width adjustment indication signal.

It must be emphasized that the above-mentioned case is a preferred embodiment. Any partial changes or modifications that are derived from the technical ideas of this case and are easily inferred by people familiar with the art do not deviate from the scope of the patent rights of this case.

In summary, this case shows that it is very different from the known technology in terms of purpose, means and effect, and it is the first invention that is practical and indeed meets the patent requirements for invention. We sincerely ask the review committee to examine it carefully and grant a patent as soon as possible to benefit the society. This is our utmost prayer.

S1: Receive a width adjustment indication signal

S2: According to the width adjustment indication signal, in each of the N control signals, adjust the low level width and/or pulse width of each of the control signals.

Claims (13)

A polarity reversal driving method is applied in an LCD display and is executed by a control unit to generate a channel output control signal to be transmitted to a source driving unit; wherein the channel output control signal includes a charge sharing control signal and K*N control signals, the charge sharing control signal and each of the control signals have a low level width and a pulse width, N is an even number and at least 4, and K is a positive integer; the polarity reversal driving method comprises: receiving a width adjustment indication signal; according to the width adjustment indication signal, in each of the N control signals, adjusting the low level width and/or pulse width of each of the control signals. A polarity reversal driving method as described in claim 1, wherein, among each of the N control signals, the pulse width of at least one control signal with an even sequence number is shortened. The polarity reversal driving method as described in claim 2, wherein, when the pulse width of the control signal with an even sequence number is shortened, the voltage levels of the positive output signal and the negative output signal output by the corresponding channel of the source driving unit are pulled to a first reference voltage and a second reference voltage respectively. The polarity inversion driving method as described in claim 2, wherein when the pulse width of the control signal with an even sequence number is shortened, the corresponding channel of the source driving unit and the adjacent channel share charge. A polarity inversion driving method as described in claim 1, wherein, in each of the N control signals, the low level width of the first control signal is extended, and the low level width of the second control signal is correspondingly shortened. The polarity reversal driving method as described in claim 2, wherein, among each of the N control signals, the pulse width of at least one control signal with an odd sequence number is also shortened. The polarity inversion driving method as described in claim 6, wherein, when the pulse width of the control signal with an odd sequence number is shortened, the voltage levels of the positive output signal and the negative output signal output by the corresponding channel of the source driving unit are pulled to a first reference voltage and a second reference voltage respectively. The polarity inversion driving method as described in claim 6, wherein when the pulse width of the control signal with an odd sequence number is shortened, the corresponding channel of the source driving unit and the adjacent channel share charge. The polarity inversion driving method as described in claim 1, wherein the source driving unit and the control unit are integrated into a source driving chip, and the control unit includes at least one register, in which at least one low level width and at least one pulse width of each control signal are recorded, so that the control unit can output the channel output control signal to the source driving unit accordingly after receiving the width adjustment indication signal. The polarity inversion driving method as described in claim 1, wherein the source driving unit is integrated into a source driving chip, and the control unit is a timing controller, which is used to transmit the width adjustment indication signal including at least one low level width and at least one pulse width of each control signal to the source driving chip, so that the source driving chip generates the channel output control signal correspondingly according to the width adjustment indication signal and provides it to the source driving unit. A display driver chip that executes the polarity inversion driving method described in claim 1 to drive an LCD panel, thereby enabling the LCD panel to achieve staggered N-line inversion. An information processing device has an LCD display including a display driver circuit and an LCD panel; the display driver circuit executes a polarity inversion driving method as described in any one of claim 1 to claim 10 to drive the LCD panel, thereby enabling the LCD panel to achieve N-line inversion. The information processing device as described in claim 12 is an electronic device selected from the group consisting of a head-mounted display device, a smart TV, a smart phone, a smart watch, a tablet computer, an all-in-one computer, a laptop computer, an in-vehicle entertainment device, a digital camera, and a video portal.