TWI854619B - Power converter and multi-level power conversion system - Google Patents

Abstract

The present disclosure provides a power converter including first to fourth switches, a flying capacitor and a controller. The first terminal of the second switch is electrically connected to the second terminal of the first switch, the first terminal of the third switch is electrically connected to the second terminal of the second switch, and the first terminal of the fourth switch is electrically connected to the second terminal of the third switch. The positive and negative terminals of the flying capacitor are electrically connected to the first terminal of the second switch and the second terminal of the third switch respectively. The controller operates the first and fourth switches to perform a first complementary switching with a first deadtime, and operates the second and third switches to perform a second complementary switching with a second deadtime. The controller detects a capacitor voltage of the flying capacitor and determines to regulate the first or second deadtime accordingly for keeping the capacitor voltage of the flying capacitor within a balance voltage range.

Description

Power converter and multi-level power conversion system

This case relates to a power converter and a multi-level power conversion system, and more particularly to a power converter and a multi-level power conversion system with a Flying Capacitor.

When the Feichi capacitor converter operates in a non-ideal state, the voltage of the Feichi capacitor will gradually shift, causing the reverse voltage on the switch component to gradually increase. If the reverse voltage is too large, the switch component will be permanently damaged due to voltage breakdown.

To avoid damage to the switching components, controlling the voltage of the Flying Capacitor is a necessary condition for maintaining the normal operation of the converter. In the prior art, the switch state is mostly selected based on the active vector adjustment according to the current flow direction of the converter. However, in some practical applications, it may be difficult to accurately determine the current direction of the converter. For example, when multiple converters are connected in parallel and operate at no load, the power of each converter will be injected into each other, resulting in unstable current direction. In addition, when the current in the converter is extremely small, it will be difficult to accurately sample the actual current and determine its direction. If the judgment of the current direction is wrong, the adjustment direction of the Flying Capacitor voltage will be opposite, causing the converter to work abnormally.

Therefore, how to develop a power converter and a multi-level power conversion system that can improve the above-mentioned prior art is an urgent need.

The purpose of this case is to provide a power converter and a multi-level power conversion system, which controls the failure time of a switch according to the capacitance voltage of a Flying Chi capacitor, thereby maintaining the capacitance voltage of the Flying Chi capacitor within a balanced voltage range.

To achieve the above-mentioned purpose, the present invention provides a power converter, including first to fourth switches, a flying capacitor and a controller. The first end of the second switch is electrically connected to the second end of the first switch, the first end of the third switch is electrically connected to the second end of the second switch, and the first end of the fourth switch is electrically connected to the second end of the third switch. The positive end of the flying capacitor is electrically connected to the first end of the second switch, and the negative end of the flying capacitor is electrically connected to the second end of the third switch. The controller operates the first and fourth switches to perform a first complementary switching with a first failure time, and operates the second and third switches to perform a second complementary switching with a second failure time. The first end of the first switch and the second end of the fourth switch are electrically connected to a DC input source. The controller detects the capacitor voltage of the Feichi capacitor to determine whether to adjust the first failure time or the second failure time so that the capacitor voltage of the Feichi capacitor is maintained within the balanced voltage range.

To achieve the above-mentioned purpose, the present invention provides a multi-level power conversion system, including a plurality of power converters, wherein each power converter includes first to fourth switches, a flying capacitor and a controller. The first end of the second switch is electrically connected to the second end of the first switch, the first end of the third switch is electrically connected to the second end of the second switch, and the first end of the fourth switch is electrically connected to the second end of the third switch. The first end of the first switch and the second end of the fourth switch are electrically connected to a DC input source. The positive end of the flying capacitor is electrically connected to the first end of the second switch, and the negative end of the flying capacitor is electrically connected to the second end of the third switch. The controller executes a balanced voltage control method to operate each power converter, wherein the balanced voltage control method includes: operating the first and fourth switches to perform a first complementary switching with a first failure time; operating the second and third switches to perform a second complementary switching with a second failure time; and determining to adjust the first failure time or the second failure time by detecting the capacitor voltage of the Flying Chi capacitor so that the capacitor voltage of the Flying Chi capacitor is maintained within a balanced voltage range.

Some typical embodiments that embody the features and advantages of the present invention will be described in detail in the following description. It should be understood that the present invention can have various variations in different aspects without departing from the scope of the present invention, and the descriptions and illustrations therein are essentially for illustrative purposes rather than for limiting the present invention.

FIG. 1 is a schematic diagram of a circuit structure of a power converter according to an embodiment of the present invention. As shown in FIG. 1 , the power converter 1 includes a first switch SW1 , a second switch SW2 , a third switch SW3 , a fourth switch SW4 , a flying capacitor Cf and a controller 11 .

The first end of the first switch SW1 is electrically connected to the first end of the DC input source, the first end of the second switch SW2 is electrically connected to the second end of the first switch SW1, the first end of the third switch SW3 is electrically connected to the second end of the second switch SW2, and the first end and the second end of the fourth switch SW4 are electrically connected to the second end of the third switch SW3 and the second end of the DC input source, respectively. In some embodiments, the DC input source includes a series capacitor (such as but not limited to the capacitors C1 and C2 shown in FIG. 1), the positive end of the series capacitor is electrically connected to the first end of the first switch SW1, and the negative end of the series capacitor is electrically connected to the second end of the fourth switch SW4. In some embodiments, the second end of the second switch SW2 and the second end of the fourth switch SW4 are electrically coupled to a load (not shown).

The positive end of the flying capacitor Cf is electrically connected to the first end of the second switch SW2, and the negative end of the flying capacitor Cf is electrically connected to the second end of the third switch SW3. In addition, in the example of FIG. 1, the direction of the current I in the power converter 1 is to flow out from the second end of the second switch SW2 or the first end of the third switch SW3, but in fact it is not limited to this, and the direction of the current I may also flow into the second end of the second switch SW2 or the first end of the third switch SW3.

The controller 11 operates the first switch SW1 and the fourth switch SW4 to perform a first complementary switching with a first dead time, and operates the second switch SW2 and the third switch SW3 to perform a second complementary switching with a second dead time, wherein the first switch SW1 and the fourth switch SW4 are closed at the same time during the first dead time, and the second switch SW2 and the third switch SW3 are closed at the same time during the second dead time, and the first dead time and the second dead time do not overlap with each other.

The controller 11 determines to adjust the first failure time or the second failure time by detecting the capacitance voltage of the flying capacitor Cf, so that the capacitance voltage of the flying capacitor Cf is maintained in a balanced voltage range.

FIG. 2A is a schematic diagram of the operating waveform of the power converter of FIG. 1 when there is no failure time and the duty cycle is greater than 0.5, and FIG. 2B is a schematic diagram of the operating waveform of the power converter of FIG. 1 when there is no failure time and the duty cycle is less than 0.5. In FIG. 2A and FIG. 2B, the operating waveform of a switching cycle is shown, wherein TRW1, TRW2 and CW are the first triangular wave, the second triangular wave and the control carrier wave, respectively, and are represented by solid lines, dashed lines and dotted lines, respectively; SW1, SW2, SW3 and SW4 represent the control signals of the first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4, respectively. The controller 11 generates a first triangular wave TRW1 and a second triangular wave TRW2, and generates a pulse width modulation signal by comparing the first triangular wave TRW1 and the second triangular wave TRW2 with the control carrier CW to control the first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4 to selectively turn on or off, wherein the first triangular wave TRW1 and the second triangular wave TRW2 are 180 degrees out of phase. Specifically, when the first triangular wave TRW1 is less than the control carrier CW, the first switch SW1 is turned on and the fourth switch SW4 is turned off; conversely, when the first triangular wave TRW1 is greater than the control carrier CW, the first switch SW1 is turned off and the fourth switch SW4 is turned on. Similarly, when the second triangular wave TRW2 is less than the control carrier CW, the second switch SW2 is turned on and the third switch SW3 is turned off; conversely, when the second triangular wave TRW2 is greater than the control carrier CW, the second switch SW2 is turned off and the third switch SW3 is turned on.

Please refer to Figure 2A in conjunction with Figure 1. When the control carrier wave CW is greater than a first predetermined voltage, the duty cycle of the power converter 1 is greater than 0.5 (i.e., the ratio of the output voltage of the power converter 1 to the bus voltage is greater than 0.5), and at this time, the first switch SW1 and the second switch SW2 will not be turned off at the same time in the switching sequence. When the direction of the current I in the power converter 1 is flowing out from the second end of the second switch SW2 or the first end of the third switch SW3, in the first half of the switching cycle, in the first section T11, the first and third switches SW1 and SW3 are turned on, and the second and fourth switches SW2 and SW4 are turned off, so that the flying capacitor Cf is charged. In the second section T12, the first and second switches SW1 and SW2 are turned on, and the third and fourth switches SW3 and SW4 are turned off. At this time, since the current does not flow through the flying capacitor Cf, the flying capacitor Cf is not charged or discharged. In the third section T13, the second and fourth switches SW2 and SW4 are turned on, and the first and third switches SW1 and SW3 are turned off, so that the flying capacitor Cf is discharged. Symmetrically, in the second half of the switching cycle, the flying capacitor Cf is discharged in the fourth section T14, the flying capacitor Cf is not charged or discharged in the fifth section T15, and the flying capacitor Cf is charged in the sixth section T16. Similarly, it can be deduced that when the direction of the current I in the power converter 1 is to flow into the second end of the second switch SW2 or the first end of the third switch SW3, the Flying-Chi capacitor Cf is discharged in the first and sixth sections T11 and T16, the Flying-Chi capacitor Cf is not charged or discharged in the second and fifth sections T12 and T15, and the Flying-Chi capacitor Cf is charged in the third and fourth sections T13 and T14.

Please refer to Figure 2B in conjunction with Figure 1. When the control carrier wave CW is less than the first predetermined voltage, the duty cycle of the power converter 1 is less than 0.5 (i.e., the ratio of the output voltage of the power converter 1 to the bus voltage is less than 0.5), and at this time, the first switch SW1 and the second switch SW2 will be turned off at the same time in the switching sequence. When the direction of the current I in the power converter 1 is flowing out from the second end of the second switch SW2 or the first end of the third switch SW3, in the first half of the switching cycle, in the first section T21, the first and third switches SW1 and SW3 are turned on, and the second and fourth switches SW2 and SW4 are turned off, so that the flying capacitor Cf is charged. In the second section T22, the first and second switches SW1 and SW2 are turned off, and the third and fourth switches SW3 and SW4 are turned on. At this time, since the current does not flow through the flying capacitor Cf, the flying capacitor Cf is not charged or discharged. In the third section T23, the second and fourth switches SW2 and SW4 are turned on, and the first and third switches SW1 and SW3 are turned off, so that the flying capacitor Cf is discharged. Symmetrically, in the second half of the switching cycle, the flying capacitor Cf is discharged in the fourth section T24, the flying capacitor Cf is not charged or discharged in the fifth section T25, and the flying capacitor Cf is charged in the sixth section T26. Similarly, it can be deduced that when the direction of the current I in the power converter 1 is to flow into the second end of the second switch SW2 or the first end of the third switch SW3, the Flying-Chi capacitor Cf is discharged in the first and sixth sections T21 and T26, the Flying-Chi capacitor Cf is not charged or discharged in the second and fifth sections T22 and T25, and the Flying-Chi capacitor Cf is charged in the third and fourth sections T23 and T24.

The influence of introducing the failure time on the power converter 1 is described below.

Please refer to Figures 3 and 4. Figure 3 is a schematic diagram of the working waveform of the power converter of Figure 1 in half a switching cycle when there is a failure time and the duty cycle is greater than 0.5, and Figure 4 illustrates the switch state change corresponding to Figure 3. The pulse width modulation signal generated by the controller 11 includes a first pulse width modulation signal PWM1 and a second pulse width modulation signal PWM2. When the first pulse width modulation signal PWM1 is 1, the first and fourth switches SW1 and SW4 are turned on and off respectively, and when the first pulse width modulation signal PWM1 is 0, the first and fourth switches SW1 and SW4 are turned off and on respectively. When the second pulse width modulation signal PWM2 is 1, the second and third switches SW2 and SW3 are turned on and off respectively, and when the second pulse width modulation signal PWM2 is 0, the second and third switches SW2 and SW3 are turned off and on respectively.

In FIG. 3 and FIG. 4, point (1, 0) corresponds to the switch state of the first section T11, point (1, 1) corresponds to the switch state of the second section T12, point (0, 1) corresponds to the switch state of the third section T13, point P1 corresponds to the switch state of the second failure time TD1, and point P2 corresponds to the switch state of the first failure time TD2. Compared to the implementation without failure time, the second section T12 is partially reduced in length to serve as the second failure time TD1, and the third section T13 is partially reduced in length to serve as the first failure time TD2.

If the failure time is not introduced, the switch state of the power converter 1 changes in sequence corresponding to point (1, 0), point (1, 1) and point (0, 1). In the case of introducing the failure time, when in the failure time, the direction of the current I in the power converter 1 will determine the subsequent switch state. Specifically, when in the switch state of the second failure time TD1 corresponding to point P1, the first switch SW1 is turned on, and the second, third and fourth switches SW2, SW3 and SW4 are all turned off. In this case, if the direction of the current I is to flow out from the second end of the second switch SW2 or the first end of the third switch SW3, as shown in FIG. 5A, the current I will flow through the parasitic diode of the third switch SW3, so that the power converter 1 returns to the switching state of the first section T11 corresponding to the point (1, 0), thereby increasing the charging time of the flying capacitor Cf. On the contrary, if the direction of the current I is to flow into the second end of the second switch SW2 or the first end of the third switch SW3, as shown in FIG. 5B, the current I will flow through the parasitic diode of the second switch SW2, so that the power converter 1 becomes the switching state of the second section T12 corresponding to the point (1, 1), so the charging and discharging time of the flying capacitor Cf remains unchanged.

When the switching state is in the first failure time TD2 corresponding to point P2, the second switch SW2 is turned on, and the first, third and fourth switches SW1, SW3 and SW4 are all turned off. In this case, if the direction of the current I is to flow out from the second end of the second switch SW2, as shown in Figure 6A, the current I will flow through the parasitic diode of the fourth switch SW4, so that the power converter 1 becomes the switching state of the third section T13 corresponding to point (0, 1), so the charging and discharging time of the flying capacitor Cf remains unchanged. On the contrary, if the direction of the current I is to flow into the second end of the second switch SW2, as shown in Figure 6B, the current I will flow through the parasitic diode of the first switch SW1, causing the power converter 1 to return to the switching state of the second section T12 corresponding to the point (1, 1), thereby reducing the charging time of the flying capacitor Cf.

Please refer to Figures 7 and 8. Figure 7 is a schematic diagram of the operating waveform of the power converter in Figure 1 in the other half of the switching cycle when there is a failure time and the duty cycle is greater than 0.5, and Figure 8 illustrates the corresponding switching state changes of Figure 7. In Figures 7 and 8, point (0, 1) corresponds to the switching state of the fourth section T14, point (1, 1) corresponds to the switching state of the fifth section T15, point (1, 0) corresponds to the switching state of the sixth section T16, point P3 corresponds to the switching state of the first failure time TD3, and point P4 corresponds to the switching state of the second failure time TD4. Compared to the implementation without expiration time, the fifth section T15 is partially reduced in length to serve as the first expiration time TD3, and the sixth section T16 is partially reduced in length to serve as the second expiration time TD4.

If the failure time is not introduced, the switching state of the power converter 1 changes in sequence to point (0, 1), point (1, 1) and point (1, 0). In the case of introducing the failure time, when in the failure time, the direction of the current I in the power converter 1 will determine the subsequent switching state. Specifically, when in the switching state of the first failure time TD3 corresponding to point P3, the second switch SW2 is turned on, and the first, third and fourth switches SW1, SW3 and SW4 are all turned off. In this case, if the direction of the current I is to flow out from the second end of the second switch SW2, the current I will flow through the parasitic diode of the fourth switch SW4, so that the power converter 1 returns to the switching state of the fourth section T14 corresponding to point (0, 1), thereby increasing the discharge time of the flying capacitor Cf. On the contrary, if the direction of the current I is to flow into the second end of the second switch SW2, the current I will flow through the parasitic diode of the first switch SW1, so that the power converter 1 becomes the switching state of the fifth section T15 corresponding to the point (1, 1), so the charging and discharging time of the flying capacitor Cf remains unchanged.

When in the switching state of the second failure time TD4 corresponding to point P4, the first switch SW1 is turned on, and the second, third and fourth switches SW2, SW3 and SW4 are all turned off. In this case, if the direction of the current I is to flow out from the second end of the second switch SW2 or the first end of the third switch SW3, the current I will flow through the parasitic diode of the third switch SW3, so that the power converter 1 becomes the switching state of the sixth section T16 corresponding to point (1, 0), so the charging and discharging time of the flying capacitor Cf remains unchanged. On the contrary, if the direction of the current I is to flow into the second end of the second switch SW2 or the first end of the third switch SW3, the current I will flow through the parasitic diode of the second switch SW2, so that the power converter 1 returns to the switching state of the fifth section T15 corresponding to the point (1, 1), thereby reducing the discharge time of the flying capacitor Cf.

From the above, it can be seen that when the duty cycle of the power converter 1 is greater than 0.5, if the direction of the current I is to flow out from the second end of the second switch SW2 or the first end of the third switch SW3, the existence of the second failure time TD1 increases the charging time of the flying capacitor Cf, the existence of the first failure time TD2 does not affect the charging and discharging time of the flying capacitor Cf, the existence of the first failure time TD3 increases the discharging time of the flying capacitor Cf, and the existence of the second failure time TD4 does not affect the charging and discharging time of the flying capacitor Cf. If the direction of the current I is to flow into the second end of the second switch SW2 or the first end of the third switch SW3, the existence of the second failure time TD1 does not affect the charge and discharge time of the Feichi capacitor Cf, the existence of the first failure time TD2 reduces the charge time of the Feichi capacitor Cf, the existence of the first failure time TD3 does not affect the charge and discharge time of the Feichi capacitor Cf, and the existence of the second failure time TD4 reduces the discharge time of the Feichi capacitor Cf.

Therefore, in terms of the overall switching cycle, when the duty cycle of the power converter 1 is greater than 0.5, regardless of the direction of the current I, the existence of the first failure times TD2 and TD3 will cause the capacitance voltage of the flying capacitor Cf to decrease, and the existence of the second failure times TD1 and TD4 will cause the capacitance voltage of the flying capacitor Cf to increase.

Please refer to Figures 9 and 10. Figure 9 is a schematic diagram of the operating waveform of the power converter of Figure 1 in a half switching cycle with a failure time and a duty cycle less than 0.5, and Figure 10 illustrates the switch state change corresponding to Figure 9. In Figures 9 and 10, point (1, 0) corresponds to the switch state of the first section T21, point (0, 0) corresponds to the switch state of the second section T22, point (0, 1) corresponds to the switch state of the third section T23, point P5 corresponds to the switch state of the first failure time TD5, and point P6 corresponds to the switch state of the second failure time TD6. Compared to the implementation without expiration time, the second section T22 is partially reduced in length to serve as the first expiration time TD5, and the third section T23 is partially reduced in length to serve as the second expiration time TD6.

If the failure time is not introduced, the switch state of the power converter 1 changes in sequence corresponding to point (1, 0), point (0, 0) and point (0, 1). In the case of introducing the failure time, when in the failure time, the direction of the current I in the power converter 1 will determine the subsequent switch state. Specifically, when in the switch state of the first failure time TD5 corresponding to point P5, the third switch SW3 is turned on, and the first, second and fourth switches SW1, SW2 and SW4 are all turned off. In this case, if the direction of the current I is to flow out from the first end of the third switch SW3, as shown in FIG. 11A, the current I will flow through the parasitic diode of the fourth switch SW4, so that the power converter 1 becomes the switching state of the second section T22 corresponding to the point (0, 0), so the charging and discharging time of the flying capacitor Cf remains unchanged. On the contrary, if the direction of the current I is to flow into the first end of the third switch SW3, as shown in FIG. 11B, the current I will flow through the parasitic diode of the first switch SW1, so that the power converter 1 returns to the switching state of the first section T21 corresponding to the point (1, 0), thereby increasing the discharge time of the flying capacitor Cf.

When the switching state is in the second failure time TD6 corresponding to point P6, the fourth switch SW4 is turned on, and the first, second and third switches SW1, SW2 and SW3 are all turned off. In this case, if the direction of the current I is to flow out from the second end of the second switch SW2 or the first end of the third switch SW3, as shown in FIG. 12A, the current I will flow through the parasitic diode of the third switch SW3, so that the power converter 1 returns to the switching state of the second section T22 corresponding to point (0, 0), thereby reducing the discharge time of the flying capacitor Cf. On the contrary, if the direction of the current I is to flow into the second end of the second switch SW2 or the first end of the third switch SW3, as shown in FIG. 12B , the current I will flow through the parasitic diode of the second switch SW2, causing the power converter 1 to become the switching state of the third section T23 corresponding to the point (0, 1), so the charging and discharging time of the flying capacitor Cf remains unchanged.

Please refer to Figures 13 and 14. Figure 13 is a schematic diagram of the operating waveform of the power converter in Figure 1 in the other half of the switching cycle when there is a failure time and the duty cycle is less than 0.5, and Figure 14 illustrates the switch state change corresponding to Figure 13. In Figures 13 and 14, point (0, 1) corresponds to the switch state of the fourth segment T24, point (0, 0) corresponds to the switch state of the fifth segment T25, point (1, 0) corresponds to the switch state of the sixth segment T26, point P7 corresponds to the switch state of the second failure time TD7, and point P8 corresponds to the switch state of the first failure time TD8. Compared to the implementation without expiration time, the fifth section T25 is partially reduced in length to serve as the second expiration time TD7, and the sixth section T26 is partially reduced in length to serve as the first expiration time TD8.

If the failure time is not introduced, the switch state of the power converter 1 changes in sequence corresponding to point (0, 1), point (1, 1) and point (1, 0). In the case of introducing the failure time, when in the failure time, the direction of the current I in the power converter 1 will determine the subsequent switch state. Specifically, when in the switch state of the second failure time TD7 corresponding to point P7, the fourth switch SW4 is turned on, and the first, second and third switches SW1, SW2 and SW3 are all turned off. In this case, if the direction of the current I is to flow out from the second end of the second switch SW2 or the first end of the third switch SW3, the current I will flow through the parasitic diode of the third switch SW3, so that the power converter 1 becomes the switching state of the fifth section T25 corresponding to the point (0, 0), so the charging and discharging time of the flying capacitor Cf remains unchanged. On the contrary, if the direction of the current I is to flow into the second end of the second switch SW2 or the first end of the third switch SW3, the current I will flow through the parasitic diode of the second switch SW2, so that the power converter 1 returns to the switching state of the fourth section T24 corresponding to the point (0, 1), thereby increasing the charging time of the flying capacitor Cf.

When the switching state is in the first failure time TD8 corresponding to point P8, the third switch SW3 is turned on, and the first, second and fourth switches SW1, SW2 and SW4 are all turned off. In this case, if the direction of the current I is to flow out from the first end of the third switch SW3, the current I will flow through the parasitic diode of the fourth switch SW4, so that the power converter 1 returns to the switching state of the fifth section T25 corresponding to point (0, 0), thereby reducing the charging time of the flying capacitor Cf. On the contrary, if the direction of the current I is to flow into the first end of the third switch SW3, the current I will flow through the parasitic diode of the first switch SW1, so that the power converter 1 becomes the switching state of the sixth section T26 corresponding to point (1, 0), so the charging and discharging time of the flying capacitor Cf remains unchanged.

From the above, it can be seen that when the duty cycle of the power converter 1 is less than 0.5, if the direction of the current I is to flow out from the second end of the second switch SW2 or the first end of the third switch SW3, the existence of the first failure time TD5 does not affect the charging and discharging time of the flying capacitor Cf, the existence of the second failure time TD6 reduces the discharge time of the flying capacitor Cf, the existence of the second failure time TD7 does not affect the charging and discharging time of the flying capacitor Cf, and the existence of the first failure time TD8 reduces the charging time of the flying capacitor Cf. If the direction of current I is to flow into the second end of the second switch SW2 or the first end of the third switch SW3, the existence of the first failure time TD5 increases the discharge time of the Flying Capacitor Cf, the existence of the second failure time TD6 does not affect the charge and discharge time of the Flying Capacitor Cf, the existence of the second failure time TD7 increases the charge time of the Flying Capacitor Cf, and the existence of the first failure time TD8 does not affect the charge and discharge time of the Flying Capacitor Cf.

Therefore, in terms of the overall switching cycle, when the duty cycle of the power converter 1 is less than 0.5, no matter what the direction of the current I is, the existence of the first failure time TD5 and TD8 will cause the capacitance voltage of the flying capacitor Cf to decrease, and the existence of the second failure time TD6 and TD7 will cause the capacitance voltage of the flying capacitor Cf to increase.

It can be seen that in a switching cycle, no matter what the duty cycle of the power converter 1 and the direction of the current I are, the existence of the first failure time will cause the capacitor voltage of the flying capacitor Cf to drop, and the existence of the second failure time will cause the capacitor voltage of the flying capacitor Cf to rise. Based on this, the controller 11 can change the capacitor voltage of the flying capacitor Cf by adjusting the first failure time and/or the second failure time, thereby maintaining the capacitor voltage of the flying capacitor Cf in the balanced voltage range. Furthermore, when in the failure time, the direction of the current I in the current power converter 1 will determine the subsequent switching state, so the present case does not need to actively sense the current direction and control the switching state accordingly.

In some embodiments, the controller 11 compares the capacitor voltage of the Feichi capacitor Cf with the second predetermined voltage. If the capacitor voltage detected by the controller 11 is lower than the second predetermined voltage, the controller 11 determines that the Feichi capacitor Cf is undervoltage, and the controller 11 correspondingly adjusts the second failure time to charge the Feichi capacitor Cf and increase its capacitor voltage. On the contrary, if the capacitor voltage detected by the controller 11 is greater than the second predetermined voltage, the controller 11 determines that the Feichi capacitor Cf is overvoltage, and the controller 11 correspondingly adjusts the first failure time to discharge the Feichi capacitor Cf and reduce its capacitor voltage.

FIG. 15 shows a specific implementation of the controller adjusting the failure time. In this implementation, as shown in FIG. 15, the controller 11 subtracts the capacitor voltage Vf of the flying capacitor Cf from the second predetermined voltage Vref, and generates a corresponding adjustment amount after performing a proportional operation on the difference. If the capacitor voltage Vf is lower than the second predetermined voltage Vref, the difference is greater than zero. At this time, the controller 11 generates an adjustment amount for the second failure time, and adds the adjustment amount to the initial duration TD0 of the failure time to generate the actual second failure time. On the contrary, if the capacitor voltage Vf is greater than or equal to the second predetermined voltage Vref, the difference is less than or equal to zero. At this time, the controller 11 generates an adjustment amount for the first failure time, and adds the adjustment amount to the initial duration TD0 of the failure time to generate the actual first failure time. In addition, the second predetermined voltage Vref may be, for example but is limited to being equal to half of the bus voltage of the power converter 1.

Of course, the specific method of the controller 11 adjusting the first failure time and/or the second failure time is not limited to the aforementioned implementation, and can be adjusted according to actual needs.

FIG. 16 is a schematic diagram of the circuit structure of a multi-level power conversion system of an embodiment of the present invention. As shown in FIG. 16, the multi-level power conversion system 10 is used to switch a DC input source and includes a plurality of power converters (for example, but not limited to the three power converters 1a, 1b and 1c shown in the figure) and a controller 11, wherein the structure and operation of each power converter are the same as those of the aforementioned power converter 1, so they are not described in detail here. The controller 11 executes a balanced voltage control method to operate each power converter, wherein the balanced voltage control method executed is the same as the method by which the controller 11 operates the power converter 1 in the aforementioned embodiment, so they are not described in detail here. In addition, in each power converter (1a, 1b, 1c), a first end of a third switch (SW3a, SW3b, SW3c) is electrically connected to a second end of a second switch (SW2a, SW2b, SW2c) to form an output end, and the output end of each power converter (1a, 1b, 1c) is electrically coupled to a load (La, Lb, Lc).

In summary, the present invention provides a power converter and a multi-level power conversion system, which controls the failure time of the switch according to the capacitance voltage of the Flying Capacitor, thereby maintaining the capacitance voltage of the Flying Capacitor in a balanced voltage range. Furthermore, when in the failure time, the direction of the current in the current power converter will determine the subsequent switch state, so the present invention does not need to actively sense the current direction and control the switch state accordingly.

It should be noted that the above is only a preferred embodiment for illustrating the present invention. The present invention is not limited to the above embodiment. The scope of the present invention is determined by the scope of the attached patent application. Moreover, the present invention can be modified in various ways by a person skilled in the art, but it does not deviate from the scope of the attached patent application.

1: Power Converter

SW1: First switch

SW2: Second switch

SW3: The third switch

SW4: The fourth switch

I: Current

Cf: Feichi capacitor

11: Controller

C1, C2: capacitor

TRW1: First triangle wave

TRW2: Second triangle wave

CW: Controlled Wave

T11, T21: First section

T12, T22: Second section

T13, T23: The third section

T14, T24: The fourth section

T15, T25: Fifth Section

T16, T26: The sixth section

PWM1: first pulse width modulation signal

PWM2: Second pulse width modulation signal

P1, P2, P3, P4: Point

TD2, TD3, TD5, TD8: First failure time

TD1, TD4, TD6, TD7: Second failure time

P5, P6, P7, P8: points

Vf: Capacitance voltage of Feichi capacitor

Vref: second predetermined voltage

TD0: Initial duration of failure time

10: Multi-level power conversion system

1a, 1b, 1c: Power converter

La, Lb, Lc: load

SW1a, SW1b, SW1c: First switch

SW2a, SW2b, SW2c: Second switch

SW3a, SW3b, SW3c: The third switch

SW4a, SW4b, SW4c: The fourth switch

Cfa, Cfb, Cfc: Feichi capacitor

FIG. 1 is a schematic diagram of a circuit structure of a power converter according to an embodiment of the present invention.

FIG. 2A is a schematic diagram of the operating waveform of the power converter of FIG. 1 when the power converter has no failure time and the duty cycle is greater than 0.5.

FIG. 2B is a schematic diagram of the operating waveform of the power converter of FIG. 1 when the power converter has no failure time and the duty cycle is less than 0.5.

FIG. 3 is a schematic diagram of the operating waveform of the power converter in FIG. 1 during half a switching cycle when the power converter has a failure time and a duty cycle greater than 0.5.

FIG. 4 shows the switch state change corresponding to FIG. 3.

5A and 5B illustrate the switch state and current path of the power converter of FIG. 1 at the second failure time TD1 of FIG. 3 .

FIG. 6A and FIG. 6B illustrate the switch state and current path of the power converter of FIG. 1 when it is in the first failure time TD2 of FIG. 3 .

FIG. 7 is a schematic diagram of the operating waveform of the power converter in FIG. 1 during the other half of the switching cycle when the power converter has a failure time and the duty cycle is greater than 0.5.

FIG. 8 illustrates the switch state change corresponding to FIG. 7.

FIG. 9 is a schematic diagram of the operating waveform of the power converter in FIG. 1 during half a switching cycle when the power converter has a failure time and a duty cycle less than 0.5.

FIG. 10 illustrates the switch state change corresponding to FIG. 9.

FIG. 11A and FIG. 11B illustrate the switch state and current path of the power converter of FIG. 1 at the first failure time TD5 of FIG. 9 .

FIG. 12A and FIG. 12B illustrate the switch state and current path of the power converter of FIG. 1 at the second failure time TD6 of FIG. 9 .

FIG. 13 is a schematic diagram of the operating waveform of the power converter in FIG. 1 during the other half of the switching cycle when the power converter has a failure time and the duty cycle is less than 0.5.

FIG. 14 illustrates the switch state change corresponding to FIG. 13 .

FIG. 15 shows a specific implementation of the controller adjusting the failure time.

FIG. 16 is a schematic diagram of the circuit structure of a multi-level power conversion system according to an embodiment of the present invention.

1: Power converter

SW1: First switch

SW2: Second switch

SW3: The third switch

SW4: The fourth switch

I: Current

Cf: Feichi capacitor

11: Controller

C1, C2: capacitors

Claims (15)

A power converter includes: a first to a fourth switch, wherein the first end of the second switch is electrically connected to the second end of the first switch, the first end of the third switch is electrically connected to the second end of the second switch, and the first end of the fourth switch is electrically connected to the second end of the third switch; a flying capacitor, wherein the positive end of the flying capacitor is electrically connected to the first end of the second switch, and the negative end of the flying capacitor is electrically connected to the second end of the third switch; and a controller, which operates the first The first and fourth switches perform a first complementary switching with a first failure time, and the second and third switches are simultaneously operated to perform a second complementary switching with a second failure time; wherein the first end of the first switch and the second end of the fourth switch are electrically connected to a DC input source; wherein the controller determines to adjust the first failure time or the second failure time by detecting the capacitance voltage of the Flying Chi capacitor, so that the capacitance voltage of the Flying Chi capacitor is maintained in a balanced voltage range. A power converter as described in claim 1, wherein the controller is used to: compare the capacitor voltage of the Flying Chi capacitor with a first predetermined voltage; if the capacitor voltage is detected to be lower than the first predetermined voltage, determine that the Flying Chi capacitor is under-voltage; and when it is determined that the Flying Chi capacitor is under-voltage, adjust the second failure time to allow the Flying Chi capacitor to be charged. A power converter as described in claim 2, wherein the controller is further used to: if the capacitor voltage is detected to be greater than the first predetermined voltage, determine that the Flying Chi capacitor has an overvoltage; and when it is determined that the Flying Chi capacitor has an overvoltage, adjust the first failure time to allow the Flying Chi capacitor to be discharged. A power converter as described in claim 1, wherein the controller is used to: generate a first and a second triangular wave, wherein the first and the second triangular wave are 180 degrees out of phase with each other; and compare the first and the second triangular wave with a control carrier to generate a pulse width modulation signal to control the first to the fourth switches to selectively turn on or off; wherein if the control carrier is greater than a second predetermined voltage, the first and the second switches will not be turned off simultaneously in the switching timing. A power converter as described in claim 4, wherein if the control carrier is less than the second predetermined voltage, the first and second switches will be turned off simultaneously in the switching sequence. A power converter as described in claim 1, wherein the first failure time and the second failure time do not overlap with each other. A power converter as described in claim 1, wherein the DC input source includes a series capacitor, and the positive terminal of the series capacitor is electrically connected to the first terminal of the first switch, and the negative terminal of the series capacitor is electrically connected to the second terminal of the fourth switch. A power converter as described in claim 1, wherein the second end of the second switch and the second end of the fourth switch are electrically coupled to a load. A power converter as described in claim 1, wherein the first and fourth switches are closed simultaneously during the first failure time, and the second and third switches are closed simultaneously during the second failure time. A multi-level power conversion system for switching a DC input source comprises: a plurality of power converters, wherein each of the power converters comprises: a first to a fourth switch, wherein a first end of the second switch is electrically connected to a second end of the first switch, a first end of the third switch is electrically connected to a second end of the second switch, and a first end of the fourth switch is electrically connected to a second end of the third switch, wherein the first end of the first switch and the second end of the fourth switch of each power converter are electrically connected to the DC input source; and a flying capacitor, wherein a positive end of the flying capacitor is electrically connected to the first end of the second switch. , and the negative end of the Feichi capacitor is electrically connected to the second end of the third switch; and a controller, executing a balanced voltage control method to operate each of the power converters, wherein the balanced voltage control method includes: operating the first and fourth switches to perform a first complementary switching with a first failure time, and simultaneously operating the second and third switches to perform a second complementary switching with a second failure time; and by detecting the capacitor voltage of the Feichi capacitor, determining to adjust the first failure time or the second failure time, so that the capacitor voltage of the Feichi capacitor is maintained in a balanced voltage range. The multi-level power conversion system as described in claim 10, wherein for any of the power converters, the balanced voltage control method further includes: comparing the capacitor voltage of the Flying Chi capacitor with a first predetermined voltage; if the capacitor voltage is detected to be lower than the first predetermined voltage, determining that the Flying Chi capacitor is under-voltage; and when determining that the Flying Chi capacitor is under-voltage, adjusting the second failure time to allow the Flying Chi capacitor to be charged. The multi-level power conversion system as described in claim 11, wherein for any of the power converters, the balanced voltage control method further comprises: if the capacitor voltage is detected to be greater than the first predetermined voltage, it is determined that the Flying Chi capacitor has an overvoltage; and when it is determined that the Flying Chi capacitor has an overvoltage, the first failure time is adjusted to allow the Flying Chi capacitor to be discharged. A multi-level power conversion system as described in claim 10, wherein for any of the power converters, the controller is further used to: generate a first and a second triangular wave, wherein the first and the second triangular wave differ by 180 degrees; and compare the first and the second triangular wave with a control carrier to generate a pulse width modulation signal to control the first to the fourth switches to selectively turn on or off; wherein if the control carrier is greater than a second predetermined voltage, the first and the second switches will not be turned off simultaneously in the switching timing. A multi-level power conversion system as described in claim 13, wherein for any of the power converters, if the control carrier is less than the second predetermined voltage, the first and second switches will be turned off simultaneously in the switching sequence. A multi-level power conversion system as described in claim 10, wherein in each of the power converters, the first end of the third switch is electrically connected to the second end of the second switch to form an output end, and the output end of each of the power converters is electrically coupled to a load.