TWI854295B - Power converter and control method thereof - Google Patents

Abstract

A power converter includes a rectifier device, a power inductor, a semiconductor device and a control module. The semiconductor device includes a drain electrode, an epitaxial layer, a body region disposed in the epitaxial layer, a source region disposed in the body region, a source electrode at least partially adjacent to the body region, a trench gate disposed in the epitaxial layer and extending along a first direction, and a planar gate disposed on the epitaxial layer and extending along a second direction. When the control module is to turn on the semiconductor device, the control module applies a first turn-on voltage to the planer gate at a first time to form a current path adjacent to the planer gate and between the drain electrode and the source electrode, and applies a second turn-on voltage to the trench gate at a second time subsequent to the first time to form a current path adjacent to the trench gate and between the drain electrode and the source electrode.

Description

Power converter and control method thereof

The present invention relates to power conversion, in particular to a power converter and a control method thereof.

Power transistors are transistors used to handle high-power voltages and currents. Common power transistors such as power metal-oxide semiconductor field-effect transistors (MOSFET) can be used in many different fields, such as power supplies, DC-to-DC converters, power converters, power converters, etc.

In recent years, in response to the development of various electronic products, the application of various power converters has also increased. However, the current power MOSFET technology, such as split gate trench (SGT), laterally diffused metal-oxide semiconductor (LDMOS), U-shaped groove metal-oxide semiconductor (UMOS) and other power transistors, is difficult to fully meet the needs of power converters in all aspects, such as it is difficult to achieve the requirements of reducing device size, increasing power supply current, reducing switching loss, reducing conduction loss and reducing dead-time loss at the same time. Therefore, the industry urgently needs to develop new power converters and control methods to overcome the above problems.

The present invention provides an electric energy converter that receives input electric energy from an input node and outputs the converted input electric energy to a load through an output node. The electric energy converter is coupled between the input node and the output node. The conversion circuit includes a rectifier, a power inductor, a semiconductor device, and a control module. The rectifier, the power inductor, and the semiconductor device are coupled at a midpoint. The semiconductor device includes: a drain electrode; an epitaxial layer; a base region disposed in the epitaxial layer; a source electrode disposed on the epitaxial layer; a source region disposed in the base region and at least partially adjacent to the source electrode; a trench gate disposed in the epitaxial layer and adjacent to a first surface of the base region; and a planar gate disposed on the epitaxial layer and adjacent to a second surface of the base region. The control module is used to apply a first control signal to the planar gate and a second control signal to the trench gate. When the control module wants to turn on the semiconductor device, at a first time, the first control signal is switched to a first conduction voltage, so that a first current path between the drain electrode and the source electrode is formed near the planar gate, and at a second time after the first time, the second control signal is switched to a second conduction voltage, so that a second current path between the drain electrode and the source electrode is formed near the trench gate.

The present invention also provides a control method for a semiconductor device, wherein the semiconductor device includes a drain electrode, a source electrode, a trench gate and a planar gate. The method includes switching a first control signal applied to the planar gate to a first conduction voltage at a first time, switching a second control signal applied to the trench gate to a second conduction voltage at a second time after the first time, and switching the first control signal and the second control signal to a cut-off voltage at a third time after the second time.

The present invention also provides a control method for a power converter. The power converter includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first drain electrode, a first source electrode, a first trench gate, and a first planar gate. The second semiconductor device includes a second drain electrode, a second source electrode, a second trench gate, and a second planar gate. The control method includes switching a first control signal applied to the first planar gate to a first conduction voltage at a first time, and switching a first control signal applied to the first planar gate to a first conduction voltage at a second time after the first time. The second control signal of the trench gate is switched to the second conduction voltage, and at a third time after the second time, the first control signal and the second control signal are switched to the first cut-off voltage, and at a fourth time after the third time, the third control signal applied to the second planar gate is switched to the third conduction voltage, and at a fifth time after the fourth time, the fourth control signal applied to the second trench gate is switched to the fourth conduction voltage, and at a sixth time after the fifth time, the third control signal and the fourth control signal are switched to the second cut-off voltage.

1,9: Power converter

10: Semiconductor devices

12: Control module

14: Rectifier

101: Base

103: Epitaxial layer

105: First conductive part

106: First dielectric layer

107: Second conductive part

108: Second dielectric layer

109: Dielectric capping layer

110,TG: Trench Gate

110-1: First trench gate structure

110-2: Second trench gate structure

112-1: First matrix area

112-1A: First Y-Z direction side surface

112-1B: Second Y-Z direction side surface

112-1C, 112-2C: X-Y direction top surface

120-1,120-2,PG: Planar Gate

124,S: Source region

124-1: The first source region

126: Interlayer dielectric layer

128-1: First source electrode

128-2: Second source electrode

130,D: Drain electrode

301,302: Current path

500: Control method

S502 to S512: Steps

a-a’,b-b’: section tangent line

b1 to b4: driving circuit

Cin, Cout: Capacitance

IL, Vds, Vdrv: signal

L: Power inductor

Ngnd: Grounding node

Nin: Input node

Nint: midpoint

Nout: output node

Sc1 to Sc4: control signal

t0 to t6: time

tdf: Dead time after the falling edge of the signal

tdr: Dead time before the rising edge of the signal

Qgd: Gate to drain charge

Vdc: DC power supply

Vpl: Flat voltage

Von1 to Von4: On-state voltage

Voff1 and Voff2: cut-off voltage

Vss: ground voltage

Vth: critical voltage

Vin: Input voltage

Vout: output voltage

Q1, Q3: Planar transistors

Q2, Q4: Trench transistors

Figure 1 is a schematic circuit diagram of an electric energy converter in an embodiment of the present invention.

Figure 2 is a three-dimensional perspective diagram of the semiconductor device in Figure 1.

Figures 3A and 3B are schematic diagrams of the current path of the semiconductor device in Figure 2.

Figure 4 is a circuit diagram of part of the power converter in Figure 1.

Figure 5 is a flow chart of the control method of the circuit in Figure 4.

Figure 6 is a timing diagram of the circuit in Figure 4.

Figure 7 shows the waveform diagram of the transistor conduction.

Figure 8 shows the waveform diagram of the circuit in Figure 4.

Figure 9 is a circuit diagram of another power converter in an embodiment of the present invention.

Figure 1 is a circuit diagram of a power converter 1 in an embodiment of the present invention. The power converter 1 is coupled between an input node Nin and an output node Nout, receives input power from the input node Nin, and outputs the converted input power to a load through the output node Nout. The power converter 1 is a buck converter, the input power can be an input voltage Vin, and the output power can be an output voltage Vout.

The power converter 1 may include an input capacitor Cin, a semiconductor device 10, a rectifier 14, a power inductor L, a control module 12, and an output capacitor Cout. The input node Nin may be coupled to a DC power source Vdc, the input capacitor Cin may be coupled between the input node Nin and a ground node Ngnd, the semiconductor device 10 may be coupled between the input node Nin and a midpoint Nint, the rectifier 14 may be coupled between the midpoint Nint and a ground node Ngnd, the power inductor L may be coupled between the midpoint Nint and an output node Nout, the control module 12 may be coupled to the semiconductor device 10 and the rectifier 14, and the output capacitor Cout may be coupled between the output node Nout and a ground node Ngnd. The ground node Ngnd may provide a ground voltage Vss, such as 0V.

The DC power source Vdc can provide a DC voltage. The semiconductor device 10 can control the charging and discharging of the power inductor L, the power inductor L can store or provide magnetic energy, the output capacitor Cout can maintain the output voltage Vout unchanged or slow down the ripple voltage change of the output voltage Vout, the rectifier device 14 can control the current path between the midpoint Nint and the ground node Ngnd, and the control module 12 can control the switches of the semiconductor device 10 and the rectifier device 14. When the semiconductor device 10 is turned on, the power inductor L can store magnetic energy, the rectifier device 14 can be in reverse bias and cut off the current path between the midpoint Nint and the ground node Ngnd, and the output capacitor Cout can be charged and the current generated by the input voltage can be output to the load. When the semiconductor device 10 is turned off, the power inductor L can release magnetic energy, the rectifier device 14 can be in forward bias and connect the current path between the midpoint Nint and the ground node Ngnd, and the output capacitor Cout can slow down the ripple voltage change of the output voltage Vout and the current generated by the magnetic energy can flow to the load to provide the required power.

FIG. 2 is a perspective view of the semiconductor device 10 in FIG. 1, which has been disclosed in Taiwan Patent Application No. 111123137 and China Patent Application No. 202210361348.8. The rectifying device 14 can also be implemented using the semiconductor device structure in FIG. 2. The semiconductor device 10 includes a substrate 101, the substrate 101 has a first conductivity type, such as an n-type heavily doped silicon substrate (N+ substrate), and an epitaxial layer 103 is disposed on the substrate 101 and has a first conductivity type, such as an n-type silicon epitaxial layer (N epitaxial layer). The semiconductor device 10 further includes a body region 112, such as a first body region 112-1 and a second body region (shaded and not shown in FIG. 2) disposed in the epitaxial layer 103 and having a second conductivity type opposite to the first conductivity type, such as a p-type body region (P body), wherein the doping concentration of the second conductivity type dopant of the body region 112 is higher than the doping concentration of the first conductivity type dopant of the epitaxial layer 103. Although the second body region is not shown in FIG. 2 because it is shaded, the second body region 112-2 is actually separated from the first body region 112-1 along the Y-axis direction.

In addition, the semiconductor device 10 further includes a trench gate structure disposed in the epitaxial layer 103, for example, a first trench gate structure 110-1 and a second trench gate structure 110-2 disposed in the epitaxial layer 103, wherein the horizontal long axes of the two trench gate structures 110-1 and 110-2 substantially extend along the first direction Y, and the second trench gate structure 110-2 is preferably substantially parallel to the first trench gate structure 110-1. Along the second direction X, the first trench gate structure 110-1 and the second trench gate structure 110-2 are respectively located on both sides of the base region 112 (for example, respectively located on both sides of the first base region 112-1 and also respectively located on both sides of the second base region 112-2), and the first trench gate structure 110-1 and the second trench gate structure 110-2 are both adjacent to the first base region 112-1 and the second base region 112-2, wherein the first base region 112-1 and the second base region 112-2 are both disposed between the first trench gate structure 110-1 and the second trench gate structure 110-2. In some embodiments, the first trench gate structure 110-1 and the second trench gate structure 110-2 each include a first conductive portion 105, a second conductive portion 107, a first dielectric layer 106, a second dielectric layer 108, and a dielectric capping layer 109, wherein the second conductive portion 107 is located below the first conductive portion 105, the first dielectric layer 106 is adjacent to the first conductive portion 105, the second dielectric layer 108 is adjacent to the second conductive portion 107, and the dielectric capping layer 109 is located on the first conductive portion 105. In one embodiment, the first conductive portion 105 and the second conductive portion 107 may be electrically connected to each other to serve as trench gate electrodes together. In the second direction x, the width of the first conductive portion 105 is greater than the width of the second conductive portion 107, and the thickness of the first dielectric layer 106 is less than the thickness of the second dielectric layer 108. In some embodiments, the first conductive portion 105 and the second conductive portion 107 may form a trench gate TG, which is formed of polysilicon, metal, alloy, other conductive materials, or a stacked layer containing the above materials, such as p-type or n-type polysilicon. The first dielectric layer 106, the second dielectric layer 108, and the dielectric cap layer 109 may be formed of silicon oxide, silicon nitride, silicon nitride oxide, or a dielectric material with a high dielectric constant, wherein the first dielectric layer 106, the second dielectric layer 108, and the dielectric cap layer 109 may be formed of the same material.

In addition, the semiconductor device 10 further includes a first planar gate 120-1 and a second planar gate 120-2 disposed on the epitaxial layer 103, wherein the long axes of the two planar gates 120-1 and 120-2 substantially extend along the second direction X, and the second direction X and the first direction Y have a non-zero angle, such as 90 degrees, that is, the second direction X may be perpendicular to the first direction Y. The second planar gate 120-2 may preferably be substantially parallel to the first planar gate 120-1, wherein the first planar gate 120-1 is at least partially located directly above the first base region 112-1, and the second planar gate 120-2 is at least partially located directly above the second base region 112-2. In addition, the dielectric capping layer 109 corresponding to the first trench gate structure 110-1 is at least partially disposed between the first planar gate 120-1 and the second planar gate 120-2 and the first conductive portion 105 of the first trench gate structure 110-1; the dielectric capping layer 109 corresponding to the second trench gate structure 110-2 is at least partially disposed between the first planar gate 120-1 and the second planar gate 120-2 and the first conductive portion 105 of the second trench gate structure 110-2. The first planar gate 120-1 and the second planar gate 120-2 are separated from the corresponding first conductive portion 105 in the vertical direction Z. The first planar gate 120-1 and the second planar gate 120-2 may form a planar gate PG. In some embodiments, the first planar gate 120-1 and the second planar gate 120-2 may be formed of polysilicon, metal, alloy, other conductive materials or stacked layers containing the above materials, such as p-type or n-type polysilicon. In some embodiments, the conductive type of the polysilicon of the first planar gate 120-1 and the second planar gate 120-2 is the same as the conductive type of the polysilicon conductive portion of the first trench gate structure 110-1 and the second trench gate structure 110-2. In other embodiments, the conductive type of the polysilicon of the first planar gate 120-1 and the second planar gate 120-2 is opposite to the conductive type of the polysilicon conductive portion of the first trench gate structure 110-1 and the second trench gate structure 110-2. In some embodiments, the conductive type of the polysilicon of the first planar gate 120-1, the second planar gate 120-2, the first trench gate structure 110-1, and the second trench gate structure 110-2 can be independently determined according to actual needs.

The semiconductor device 10 further includes a first source electrode 128-1 and a second source electrode 128-2 disposed on the epitaxial layer 103 and formed in an interlayer dielectric layer (ILD) 126. The first source electrode 128-1 and the second source electrode 128-2 extend downward into the first body region 112-1 and the second body region 112-2, respectively. As shown in FIG. 2 , the first planar gate 120-1 and the second planar gate 120-2 are disposed between the first source electrode 128-1 and the second source electrode 128-2, and the extension direction of the first planar gate 120-1 and the second planar gate 120-2 may be substantially parallel to the surface of the substrate 101, and the extension direction of the first source electrode 128-1 and the second source electrode 128-2 is perpendicular to the surface of the substrate 101. In addition, the semiconductor device 10 further includes a source region 124, for example, a first source region 124-1 is disposed in the first body region 112-1, and at least partially adjacent to and electrically coupled to the first source electrode 128-1, for example, the first source region 124-1 may surround the bottom of the first source electrode 128-1. In addition, although the second source region is not shown in FIG. 2, the second source region is disposed in the second body region, and at least partially adjacent to or surrounds and electrically coupled to the bottom of the second source electrode 128-2. In some embodiments, the first source region 124-1 and the second source region have a first conductivity type, such as an n-type heavily doped region, and the doping concentration of the source region 124 is higher than the doping concentration of the epitaxial layer 103. In addition, the semiconductor device 10 further includes a drain electrode 130 disposed under the substrate 101. The drain electrode 130 may be composed of metal or other conductive materials and is formed on the bottom surface of the substrate 101.

The first direction Y and the vertical direction Z define a Y-Z plane, the first direction Y and the second direction X define an X-Y plane, the first substrate region 112-1 has a first Y-Z direction side surface 112-1A and a second Y-Z direction side surface 112-1B that are substantially parallel to the Y-Z plane, similarly, the second substrate region 112-2 has a third Y-Z direction side surface and a fourth Y-Z direction side surface that are substantially parallel to the Y-Z plane. The first, second, third and fourth Y-Z direction side surfaces are all flat Y-Z direction side surfaces, and the first trench gate structure 110-1 is adjacent to the first Y-Z direction side surface 112-1A of the first base region 112-1 and the third Y-Z direction side surface of the second base region, and the second trench gate structure 110-2 is adjacent to the second Y-Z direction side surface 112-1B of the first base region 112-1 and the fourth Y-Z direction side surface of the second base region. The first base region 112-1 has an X-Y direction top surface 112-1C along the X-Y plane, and the first planar gate 120-1 is at least partially located directly above the X-Y direction top surface 112-1C of the first base region 112-1. In addition, the second base region also has an X-Y direction top surface 112-2C along the X-Y plane, and the second planar gate 120-2 is at least partially located directly above the X-Y direction top surface 112-2C of the second base region. In addition, the first source region 124-1 surrounds the bottom end of the first source electrode 128-1 along the X-Y plane, and the second source region surrounds the bottom end of the second source electrode 128-2 along the X-Y plane.

FIG. 3A and FIG. 3B are schematic diagrams of current paths of the semiconductor device of FIG. 2, wherein section B illustrates a current path 301 controlled by a planar gate PG along section tangent b-b' in FIG. 1, and section A illustrates a current path 302 controlled by a trench gate TG along section tangent a-a' in FIG. 1. Both current paths 301 and 302 have arrow segments to indicate current directions. As shown in section B of FIG. 3A , when the planar gate PG is turned on (on state), the current path 301 will go upward from the drain electrode D, through the substrate 101, the epitaxial layer 103, and then through the horizontal channel below the planar gate PG (located on the top surface of the substrate region 112) to the source region S, and finally reach the source electrode 128. As shown in the cross section A of FIG. 3B , when the trench gate TG is turned on, the current path 302 goes upward from the drain electrode D, passes through the substrate 101, the epitaxial layer 103, and goes upward along the bottom and side walls of the trench gate structures 110-1 and 110-2, and then passes through the vertical channel adjacent to the first conductive portion 105 and the second conductive portion 107 (located on the side of the base region 112) to the source region S, and finally reaches the source electrode 128.

The semiconductor device 10 can be viewed as two metal-oxide-semiconductor field-effect transistors (MOSFETs), one of which is a planar transistor having a planar gate PG for forming a horizontal channel, and the other is a trench transistor having a trench gate TG for forming a vertical channel. The bottoms of the planar transistor and the trench transistor are coupled to the same drain electrode, and the tops of the planar transistor and the trench transistor are coupled to the same source electrode, so that the two metal-oxide semiconductor transistors are connected in parallel. For example, referring to the cross-section A of FIG. 3B , the planar transistor may include a planar gate PG, a drain electrode D, a source region S, a source electrode 128, a base region 112, an epitaxial layer 103, and a substrate 101. Referring to the cross section B of FIG. 3A , the trench transistor may include a trench gate TG, a drain electrode D, a source region S, a source electrode 128, a body region 112, an epitaxial layer 103, and a substrate 101. The planar transistor and the trench transistor may share the drain electrode D, the source region S, the source electrode 128, the body region 112, the epitaxial layer 103, and the substrate 101. The control module 12 may separately control the planar gate PG of the planar transistor and the trench gate TG of the trench transistor.

Planar transistors have a smaller on-resistance (Ron), a smaller gate charge (Qg), and a lower critical voltage, which reduces the figure of merit (FOM), switches quickly, and improves efficiency, making them suitable for light load conditions. Trench transistors have a larger trench gate area and a higher critical voltage, which reduces the drain-to-source unit area on-resistance (Rds on-resistance per unit area, Rsp), but increases parasitic effects, making them suitable for heavy load conditions. Therefore, the control circuit 12 can turn on the planar gate when the load power is relatively light to speed up the switching speed of the semiconductor device 10, and turn on the trench gate and the planar gate at the same time when the load power is relatively heavy to reduce the on-resistance of the semiconductor device 10 and increase the current of the semiconductor device 10.

Similarly, the rectifying device 14 may be another semiconductor device having a structure similar to that shown in FIG. 2, FIG. 3A, and FIG. 3B. In some embodiments, the rectifying device 14 may also be a diode or other types of switching devices.

FIG. 4 is a circuit diagram of a part of the circuit in the power converter 1, including a control module 12, a first drive circuit b1 to a fourth drive circuit b4, a semiconductor device 10 and a rectifier 14. The semiconductor device 10 may include a planar transistor Q1 and a trench transistor Q2, and the rectifier 14 may include a planar transistor Q3 and a trench transistor Q4. The planar transistor Q1 may include a drain electrode coupled to the input node Nin, a source electrode coupled to the midpoint Nint of the output power, and a planar gate PG1. The trench transistor Q2 may include a drain electrode coupled to the input node Nin, a source electrode coupled to the midpoint Nint, and a trench gate TG2. The planar transistor Q3 may include a drain electrode coupled to the midpoint Nint, a source electrode coupled to the ground node Ngnd, and a planar gate PG3. The trench transistor Q4 may include a drain electrode coupled to the midpoint Nint of the output power, a source electrode coupled to the ground node Ngnd, and a trench gate TG4.

The first driving circuit b1 may include a first end coupled to the control circuit 12, and a second end coupled to the planar gate PG1 of the planar transistor Q1. The second driving circuit b2 may include a first end coupled to the control circuit 12, and a second end coupled to the trench gate TG2 of the trench transistor Q2. The third driving circuit b3 may include a first end coupled to the control circuit 12, and a second end coupled to the planar gate PG3 of the planar transistor Q3. The fourth driving circuit b4 may include a first end coupled to the control circuit 12, and a second end coupled to the trench gate TG4 of the trench transistor Q4. The first driving circuit b1 to the fourth driving circuit b4 may be implemented by buffers, respectively.

The control module 12 can apply the first control signal Sc1 to the planar gate PG1 of the planar transistor Q1 through the first driving circuit b1, and apply the second control signal Sc2 to the trench gate TG2 of the trench transistor Q2 through the second driving circuit b2. In addition, the control module 12 can apply the third control signal Sc3 to the planar gate PG3 of the planar transistor Q3 through the third driving circuit b3, and apply the fourth control signal Sc2 to the trench gate TG4 of the trench transistor Q4 through the fourth driving circuit b4. In some embodiments, the driving circuits b1 to b4 can be omitted, and the control module 12 can directly drive the planar transistors Q1 to Q4.

The control module 12 can control the switches of the semiconductor device 10 and the rectifier device 14 respectively through the first control signal Sc1 to the first control signal Sc4, so as to reduce the switching loss, conduction loss and dead-time loss of the power converter 1, while providing the power required by the load.

FIG. 5 is a flow chart of a control method 500 of the circuit in FIG. 4. The control method 500 includes steps S502 to S512, wherein steps S502 to S506 are used to control the semiconductor device 10, and steps S508 to S512 are used to control the rectifying device 14. Any reasonable technical changes or step adjustments are within the scope of the present invention. Steps S502 to S512 are explained as follows: Step S502: At the first time, switch the first control signal to the first conduction voltage; Step S504: At the second time, switch the second control signal to the second conduction voltage; Step S506: At the third time, switch the first control signal and the second control signal to the first cut-off voltage; Step S508: At the fourth time, switch the third control signal to the third conduction voltage; Step S510: At the fifth time, switch the fourth control signal to the fourth conduction voltage. Step S512: At the sixth time, switch the third control signal and the fourth control signal to the second cut-off voltage.

FIG. 6 is a timing diagram of the circuit in FIG. 2, wherein the vertical axis represents voltage and the horizontal axis represents time. Steps S502 to S512 are described below in conjunction with FIGS. 2-4 and 6. At time t1, the control module 12 switches the first control signal Sc1 to the first conduction voltage Von1 to form a horizontal channel of the planar transistor Q1 adjacent to the planar gate PG1, and forms a first current path in the horizontal channel of the planar transistor Q1 (step S502). At time t2, the control module 12 switches the second control signal Sc2 to the second conduction voltage Von2 to form a vertical channel of the trench transistor Q2 near the trench gate TG2, and forms a second current path in the vertical channel of the trench transistor Q2 (step S504). At time t3, the control module 12 switches the first control signal Sc1 and the second control signal Sc2 to the first off-voltage Voff1 to interrupt the first current path and the second current path (step S506).

To avoid forming a short circuit path between the input voltage Vin and the ground node Ngnd, it is necessary to ensure that the semiconductor device 10 and the rectifier device 14 are not turned on at the same time. Therefore, after time t3, a dead time period is required before the control module 12 can turn on both ends of the rectifier device 14. At time t4, the control module 12 switches the third control signal Sc3 to the third conduction voltage Von3, so that a horizontal channel of the planar transistor Q3 is formed near the planar gate PG3, and a horizontal current path is formed in the horizontal channel of the planar transistor Q3 (step S508). At time t5, the control module 12 switches the fourth control signal Sc4 to the fourth conduction voltage Von4, so that a vertical channel of the trench transistor Q4 is formed near the trench gate TG4, and a vertical current path is formed in the vertical channel of the trench transistor Q4 (step S510). At time t6, the control module 12 switches the third control signal Sc3 and the fourth control signal Sc4 to the second off-voltage Voff2 to interrupt the third current path and the fourth current path (step S512).

The voltage levels of the on-state voltages Von1 to Von4 can be the same or different. For example, the on-state voltages Von1 to Von4 can be between 3.3V and 6V, and have different withstand voltages according to different processes. The voltage levels of the off-state voltages Voff1 and Voff2 can be the same or different. For example, the on-state voltages Voff1 and Voff2 can both be 0V.

Figure 7 shows a waveform diagram of the transistor conduction, where the vertical axis is voltage/current and the horizontal axis is time. Signal Vdrv represents the gate voltage of the transistor, signal Vds represents the drain-to-source voltage of the transistor, and signal IL represents the output current of the transistor. At time t0, signal Vdrv is 0, the transistor is cut off, signal Vds maintains a high voltage, and signal IL is 0. At time t1, signal Vdrv begins to rise. At time t2, signal Vdrv reaches the critical voltage Vth, and signal IL begins to rise. Between time t3 and time t4, signal Vdrv reaches the flat voltage Vpl. Due to the relationship between the gate-to-drain charge Qgd, signal Vdrv will remain at the flat voltage Vpl. At this time, signal IL will rise rapidly to the maximum value, and signal Vds will begin to decrease slowly, thereby generating switching loss. After time t4, signal Vds reaches 0V, and signal Vdrv continues to rise until the target voltage is reached, and the transistor is fully turned on. If the gate-to-drain charge Qgd increases, the time for signal Vds to reach 0V is longer, the flat area (the period between time t3 and time t4) will increase, and the switching loss will also increase accordingly.

Since the control module 12 first switches the first control signal Sc1 to the first conduction voltage Von1, and the critical voltage of the planar transistor Q1 is relatively low, the signal Vds of the planar transistor Q1 can be quickly pulled down, shortening the flat area interval, thereby reducing the switching loss. Similarly, the control module 12 first switches the third control signal Sc3 to the third conduction voltage Von3, and the critical voltage of the planar transistor Q3 is relatively low, so the signal Vds of the planar transistor Q3 can be quickly pulled down, shortening the flat area interval, thereby reducing the switching loss. Therefore, compared with the related technology, the switching loss of the power converter 1 is lower.

In addition, the conduction loss Pc1 of the power converter 1 is related to the unit area resistance Rdson from the drain to the source, and can be calculated by Formula 1: Pcl=Pcl _up +Pcl _low =Rdson_up. Irms_up ² +Rdson_low. Irms_low ² Formula 1 wherein Pcl is the conduction loss; Pcl_up is the conduction loss of the semiconductor device 10; Pcl_low is the conduction loss of the rectifier device 14; Rdson_up is the drain-to-source conduction resistance of the semiconductor device 10; Rdson_low is the drain-to-source conduction resistance of the rectifier device 14; Irms_up ² is the square value of the root mean square output current of the semiconductor device 10; and Irms_low ² is the square value of the root mean square output current of the rectifier device 14.

Referring to Formula 1, the conduction loss Pcl_up of the semiconductor device 10 is proportional to the conduction resistance Rdson_up from the drain to the source, and the conduction loss Pcl_low of the rectifier device 14 is proportional to the conduction resistance Rdson_low from the drain to the source. According to the previous paragraph, the conduction resistance from the drain to the source of the trench transistor is lower than that of the transistor in the related art. Therefore, by using the trench transistor Q2 of the semiconductor device 10, the conduction loss Pcl_up can be reduced, and by using the trench transistor Q4 of the rectifier device 14, the conduction loss Pcl_low can be reduced, thereby reducing the conduction loss Pcl of the power converter 1.

In the related art, the upper and lower bridge transistors of the buck converter are not turned on at the same time. The upper bridge transistor is turned off before the lower bridge transistor is turned on. At this time, both the upper and lower bridge transistors are turned off, and the current flows from the ground node to the power inductor through the parasitic diode of the lower bridge transistor. Similarly, the lower bridge transistor is turned off before the upper bridge transistor is turned on. At this time, both the upper and lower bridge transistors are turned off, and the current flows from the power inductor to the power supply terminal through the parasitic diode of the upper bridge transistor. The current flowing through the parasitic diode of the upper bridge transistor and the current flowing through the parasitic diode of the lower bridge transistor will produce dead zone loss Pdl, which is expressed by Formula 2: Pdl=Vd. (IL_max.tdf+IL_min.tdr) Formula 2

Where Pdl is the dead time loss; Vd is the drain voltage; IL_max is the maximum output current; IL_min is the minimum output current; tdf is the dead time after the falling edge of the signal; and tdr is the dead time before the rising edge of the signal.

Referring to Formula 2, the dead time loss Pdl is positively correlated with the dead time tdr and tdf. FIG8 shows a waveform diagram of the power converter 1, wherein the vertical axis is voltage and the horizontal axis is time. The period between time t1 and t2 can be called the rising dead time tdr, and the period between time t4 and t5 can be called the falling dead time tdf. Applying the first conduction voltage Von1 to the planar gate PG1 first can quickly turn on the planar transistor Q1, thereby shortening the rising dead time tdr, and applying the third conduction voltage Von3 to the planar gate PG3 first can quickly turn on the planar transistor Q3, thereby shortening the falling dead time tdf. Compared with related technologies, since the dead time tdr and tdf are both shortened, the dead time loss Pdl of the power converter 1 is reduced.

Figure 9 is a circuit diagram of another power converter 9 in an embodiment of the present invention. The difference between power converter 9 and power converter 1 lies in the connection relationship between semiconductor device 10, rectifier device 14 and power inductor L. Power converter 9 is a boost converter.

The power inductor L can be coupled between the input node Nin and the midpoint Nint, the semiconductor device 10 can be coupled between the midpoint Nint and the ground node Ngnd, and the rectifier device 14 can be coupled between the midpoint Nint and the output node Nout. The control method of the semiconductor device 10 and the rectifier device 14 in the power converter 9 can refer to the control method of the power converter 1, which will not be repeated here.

The embodiments of Figures 1-6, 8 and 9 separately control the planar gate of the planar transistor and the trench gate of the trench transistor, thereby reducing the switching loss, conduction loss and dead-time loss of the power converter, while providing the power required by the load.

The above is only the preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

10: Semiconductor devices

12: Control module

14: Rectifier

b1 to b4: driving circuit

L: Power inductor

Ngnd: Grounding node

Nin: Input node

Nint: midpoint

Sc1 to Sc4: control signal

Vss: ground voltage

Vin: Input voltage

Vout: output voltage

Q1, Q3: Planar transistors

Q2, Q4: Trench transistors

Claims (14)

A power converter receives an input power from an input node and is coupled to a load through an output node. The power converter is coupled between the input node and the output node. The power converter comprises: a power inductor coupled to a midpoint; a rectifier coupled to the midpoint; a first semiconductor device comprising: a first drain electrode; a first an epitaxial layer; a first base region disposed in the first epitaxial layer; a first source electrode disposed on the first epitaxial layer; a first source region disposed in the first base region and at least partially adjacent to the first source electrode; a first trench gate disposed in the first epitaxial layer and adjacent to a first surface of the first base region; and a first planar gate disposed at A second surface of the first substrate region is provided on the first epitaxial layer; and a control module is used to apply a first control signal to the first planar gate and a second control signal to the first trench gate; wherein the control module is used to switch the first control signal to a first conduction voltage at a first time, so that a voltage between A first current path between the first drain electrode and the first source electrode; wherein the control module is used to switch the second control signal to a second conduction voltage at a second time, so that a second current path between the first drain electrode and the first source electrode is formed near the first trench gate, and the second time is later than the first time. The power converter as described in claim 1, wherein the first trench gate extends along a first direction, the first planar gate extends along a second direction, and the second direction has a non-zero angle with the first direction. The power converter as described in claim 1, wherein: the control module is further used to switch the first control signal and the second control signal to a first cut-off voltage at a third time to interrupt the first current path and the second current path, and the third time is later than the second time. An electric energy converter as described in claim 3, wherein the rectifying device comprises a first end and a second end, and the rectifying device is a second semiconductor device, comprising: a second drain electrode; a second epitaxial layer; a second base region disposed in the second epitaxial layer; a second source electrode disposed on the second epitaxial layer; a second source region disposed in the second base region and at least partially adjacent to the second source electrode; a second trench gate disposed in the second epitaxial layer, adjacent to a first surface of the second base region; and a second planar gate disposed on the second epitaxial layer, adjacent to a second surface of the second base region; and the control module is further used to apply a A third control signal is sent to the second planar gate, and a fourth control signal is sent to the second trench gate; wherein the control module is used to switch the third control signal to a third conduction voltage at a fourth time, so that a third current path is formed between the second drain electrode and the second source electrode adjacent to the second planar gate, and the fourth time is later than the third time; and wherein the control module is used to switch the fourth control signal to a fourth conduction voltage at a fifth time, so that a fourth current path is formed between the second drain electrode and the second source electrode adjacent to the second trench gate, and the fifth time is later than the fourth time. The power converter as described in claim 4, wherein the control module is further used to switch the third control signal and the fourth control signal to a second cut-off voltage at a sixth time to interrupt the third current path and the fourth current path, and the sixth time is later than the fifth time. The power converter as described in claim 4, wherein the second trench gate extends along the third direction, the second planar gate extends along a fourth direction, and there is a non-zero angle between the third direction and the fourth direction. The power converter as described in claim 4, wherein the second semiconductor device further comprises: a second substrate, the second epitaxial layer is disposed on the second substrate, and the second drain electrode is disposed under the second substrate. The power converter as described in claim 4 further comprises: a first driving circuit coupled to the first planar gate; a second driving circuit coupled to the first trench gate; a third driving circuit coupled to the second planar gate; and a fourth driving circuit coupled to the second trench gate. The power converter as described in claim 1, wherein the first semiconductor device is coupled between the input node and the midpoint, the power inductor is coupled between the output node and the midpoint, and the power converter is a buck converter. The power converter as described in claim 1, wherein the power inductor is coupled between the input node and the midpoint, the first semiconductor device is coupled between the midpoint and a ground node, and the power converter is a boost converter. The power converter as described in claim 1, wherein: the first semiconductor device further comprises: a first substrate, the first epitaxial layer is disposed on the first substrate, the first drain electrode is disposed under the first substrate; the rectifying device comprises a first end coupled to the first source electrode, and a second end; and the inductor is coupled to the first source electrode and the first end of the rectifying device. The power converter as described in claim 12, wherein the first drain electrode is coupled to a power supply terminal, and the second terminal of the rectifier is coupled to a ground node. A control method for an electric energy converter, the electric energy converter comprising a first semiconductor device, the first semiconductor device comprising a first drain electrode, a first source electrode, a first trench gate and a first planar gate, the method comprising the steps of: at a first time, switching a first control signal applied to the first planar gate to a first conduction voltage, so that a first current path between the first drain electrode and the first source electrode is formed near the first planar gate; At a second time, a second control signal applied to the first trench gate is switched to a second conduction voltage, so that a second current path between the first drain electrode and the first source electrode is formed near the first trench gate, and the second time is later than the first time; and at a third time, the first control signal and the second control signal are switched to a first cut-off voltage to interrupt the first current path and the second current path, and the third time is later than the second time. The control method of the power converter as described in claim 13, the power converter further includes a second semiconductor device, the second semiconductor device includes a second drain electrode, a second source electrode, a second trench gate and a second planar gate, the method further includes the steps of: at a fourth time, switching a third control signal applied to the second planar gate to a third conduction voltage, so that a third current path is formed between the second drain electrode and the second source electrode adjacent to the second planar gate, the third control signal is switched to a third conduction voltage at a fourth time, At a fourth time later than the third time; at a fifth time, a fourth control signal applied to the second trench gate is switched to a fourth conduction voltage, so that a fourth current path between the second drain electrode and the second source electrode is formed near the second trench gate, and the fifth time is later than the fourth time; and at a sixth time, the third control signal and the fourth control signal are switched to a second cut-off voltage to interrupt the third current path and the fourth current path, and the sixth time is later than the fifth time.

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