TWI853349B - Semiconductor device and method for forming the same - Google Patents

Abstract

The present disclosure provides a semiconductor device, including: a semiconductor layer; a deep trench isolation structure separating the semiconductor device into a plurality of units, wherein the plurality of units includes a first unit and a second unit; a shallow trench isolation structure disposed on the semiconductor layer in the plurality of units; a first resistance layer and a second resistance layer disposed on the shallow trench isolation structure in the first unit and the second unit, respectively; a first heavily doped region and a second heavily doped region embedded in the shallow trench isolation structure and physically in contact with the semiconductor layer in the first unit and the second unit, respectively; and a conductive line electrically connecting the first resistance layer, the second resistance layer, and the second heavily doped region.

Description

Semiconductor device and method of forming the same

The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a deep trench isolation (DTI) structure.

Semiconductor devices include a substrate and circuit components disposed on the substrate, and have been widely used in various electronic products, such as personal computers, mobile phones, digital cameras and other electronic equipment. The evolution of semiconductor devices continues to influence and improve people's lifestyles.

Semiconductor devices typically include an isolation structure to electrically isolate different regions of a semiconductor layer. The isolation structure can be formed by etching trenches in the semiconductor device and forming an insulating material in the trenches. Depending on the depth of the trench, the isolation structure can be divided into a shallow trench isolation (STI) structure and a deep trench isolation structure. Shallow trench isolation structures with shallow depths are often used to reduce parasitic capacitance and provide a lower level of voltage isolation between devices. On the other hand, deep trench isolation structures have a greater depth to provide isolation between different parts of integrated circuits that share the same semiconductor layer.

However, although these isolation structures generally meet the requirements, they are still not satisfactory in every aspect and may limit the performance of semiconductor devices in some cases. For example, in the case where multiple partial semiconductor layers are surrounded by multiple tanks formed by deep trench isolation structures, if a resistor layer for connecting conductive lines is set on a shallow trench isolation structure on the semiconductor layer, its operating voltage will be limited by the thickness of the shallow trench isolation structure. In applications where the thickness of the shallow trench isolation structure must be reduced, the operating voltage may be too high, causing breakdown between the resistor layer and the semiconductor layer and generating leakage current. Therefore, there is a need to further improve the configuration of semiconductor devices so that the semiconductor devices can have wider applications.

A semiconductor device includes: a semiconductor layer; a deep trench isolation structure that separates the semiconductor device into a plurality of units, wherein the units include a first unit and a second unit; a shallow trench isolation structure that is disposed on the semiconductor layer in the unit; a first resistor layer and a second resistor layer that are disposed on the shallow trench isolation structure in the first unit and the second unit, respectively; a first heavily doped region and a second heavily doped region that are embedded in the shallow trench isolation structure in the first unit and the second unit, respectively, and physically contact the semiconductor layer; and a conductive line that electrically connects the first resistor layer, the second resistor layer, and the second heavily doped region.

A method for forming a semiconductor device includes: forming a shallow trench isolation structure on a semiconductor layer; forming a first resistor layer and a second resistor layer on the shallow trench isolation structure; embedding a first heavily doped region and a second heavily doped region into the shallow trench isolation structure, and physically contacting the first heavily doped region and the second heavily doped region with the semiconductor layer; forming a semiconductor device A deep trench isolation structure is provided which is divided into a plurality of units, and the units include a first unit and a second unit, wherein a first resistor layer and a first heavily doped region are located in the first unit, and a second resistor layer and a second heavily doped region are located in the second unit; and a conductive line is formed which electrically connects the first resistor layer, the second resistor layer, and the second heavily doped region.

The following disclosure provides many different embodiments or examples to show different components of the embodiments of the present invention. The following will disclose specific examples of the components of this specification and their arrangement to simplify the disclosure. Of course, these specific examples are not used to limit the disclosure. For example, if the following invention content of this specification describes forming a first component on or above a second component, it means that it includes an embodiment in which the first and second components formed are in direct contact, and also includes an embodiment in which an additional component can be formed between the above-mentioned first and second components, and the first and second components are not in direct contact. In addition, the various examples in the disclosure may use repeated reference symbols and/or words. The purpose of these repeated symbols or words is to simplify and clarify, and is not used to limit the relationship between the various embodiments and/or the configurations.

Furthermore, to facilitate description of the relationship between one element or component and another element or component in the drawings, spatially relative terms may be used, such as "under," "below," "lower," "above," "upper," and the like. In addition to the orientation depicted in the drawings, spatially relative terms also cover different orientations of the device in use or operation. When the device is turned to a different orientation (for example, rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the orientation after the rotation.

Here, the terms "about", "approximately", and "generally" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of specific description of "about", "approximately", and "generally", the meaning of "about", "approximately", and "generally" can still be implied.

Some embodiments of the present invention are described below, and additional steps may be provided before, during, and/or after the various stages described in these embodiments. Some of the stages may be replaced or deleted in different embodiments. Additional components may be added to the semiconductor device structure. Some of the components may be replaced or deleted in different embodiments. Although some of the embodiments discussed are performed in a specific order of steps, these steps may still be performed in another logical order.

As used herein, the term "substantially" means that a given amount of value may vary based on a particular technology node associated with the target semiconductor device. In some embodiments, based on a particular technology node, the term "substantially" may mean that a given amount of value is within a range of, for example, ±5% of a target (or desired) value.

The present disclosure provides a semiconductor device including a deep trench isolation structure and a heavily doped region. Multiple heavily doped regions embedded in the shallow trench isolation structure can prevent current collapse from occurring between the resistor layer and the semiconductor layer. In this way, by utilizing the deep trench isolation structure to separate the semiconductor layers of each trench, and electrically connecting each unit with a lower limiting voltage with a conductive line, the voltage can be reduced multiple times between each unit (trench). Compared to the known structure with a resistor layer for voltage reduction, the semiconductor device of the present disclosure can be applied with a higher operating voltage without increasing the thickness of the shallow trench isolation structure on the semiconductor layer.

FIG. 1 is a cross-sectional view of a semiconductor device 10 according to some embodiments of the present disclosure. The semiconductor device 10 includes a semiconductor layer 100 and a deep trench isolation structure 110 that separates the semiconductor device into a plurality of cells, and the plurality of cells include a first cell 10A and a second cell 10B. The semiconductor device 10 further includes a shallow trench isolation structure 120 disposed on the semiconductor layer 100 in the plurality of cells. As shown in FIG. 1 , the first cell 10A and the second cell 10B have a first resistor layer 130A and a second resistor layer 130B disposed on the shallow trench isolation structure 120, respectively. In addition, the first cell 10A and the second cell 10B respectively have a first heavily doped region 140A and a second heavily doped region 140B embedded in the shallow trench isolation structure 120 and physically contacting the semiconductor layer 100. The semiconductor device 10 further includes a conductive line 150 electrically connecting the first resistor layer 130A, the second resistor layer 130B, and the second heavily doped region 140B.

In some embodiments, as shown in FIG. 1 , the deep trench isolation structure 110 passes through the shallow trench isolation structure 120 between each cell. The deep trench isolation structure 110 may laterally surround multiple portions of the semiconductor layer 100 in each cell, and the semiconductor layer 100 is electrically isolated between each cell. In some embodiments, the shallow trench isolation structure 120 is not continuous between each cell. For example, multiple portions of the shallow trench isolation structure 120 in each cell may be separated by the deep trench isolation structure 110.

It should be understood that the “cell” described in the present disclosure includes a portion of the semiconductor layer 100 surrounded by a tank formed by the deep trench isolation structure 110 and other film layers and regions substantially formed directly above the portion of the semiconductor layer 100. For example, the first resistor layer 130A and the first heavily doped region 140A of the first cell 10A, as well as the portion of the semiconductor layer 100 and the shallow trench isolation structure 120 below surrounded by the deep trench isolation structure 110 are located in the same tank.

The materials of the deep trench isolation structure 110 and the shallow trench isolation structure 120 include oxide, nitride, a low-k dielectric material having a dielectric constant less than about 3.9, or an extreme low-k (ELK) dielectric material having a dielectric constant less than about 2, or a combination thereof. In some embodiments, the deep trench isolation structure 110 and the shallow trench isolation structure 120 include different materials.

Specifically, the material of the deep trench isolation structure 110 and the shallow trench isolation structure 120 may be, for example, silicon oxide, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), other suitable materials, or a combination thereof.

The semiconductor layer 100 may be doped (eg, doped with p-type or n-type dopants) or undoped. The material of the semiconductor layer 100 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and/or gallium indium arsenide phosphide; or combinations thereof.

In some embodiments, the semiconductor device 10 has a semiconductor-on-insulator (SOI) substrate. For example, as shown in FIG. 1 , the semiconductor device 10 may further include an insulating layer 102 covering the bottom surface of the semiconductor layer 100. The insulating layer 102 may include a buried dielectric layer, such as a buried oxide (BOX), a buried nitride, a similar material, or a combination thereof. By providing the insulating layer 102, leakage current can be prevented from being generated on the bottom surface of the semiconductor layer 100. In some embodiments, the deep trench isolation structure 110 extends from the top surface of the shallow trench isolation structure 120 to the top surface of the insulating layer 102 to completely isolate the semiconductor layer 100 between the respective cells.

In some embodiments, the semiconductor device 10 further includes a carrier substrate 104 located below the semiconductor layer 100. For example, the carrier substrate 104 may include a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an aluminum nitride substrate, a gallium nitride substrate, similar materials, or a combination thereof.

In some embodiments, the first resistor layer 130A and the second resistor layer 130B are horizontally spaced from multiple edges of the first unit 10A and the second unit 10B, respectively. The thickness of the first resistor layer 130A and the second resistor layer 130B is not limited in the present disclosure, as long as the first resistor layer 130A and the second resistor layer 130B can be used as resistors. The first resistor layer 130A and the second resistor layer 130B may include materials suitable for use as resistors.

The first heavily doped region 140A and the second heavily doped region 140B may be doped with a p-type or n-type dopant. For example, the p-type dopant may be boron, aluminum, gallium, _BF2 , a similar material, or a combination thereof, and the n-type dopant may be nitrogen, phosphorus, arsenic, antimony, a similar material, or a combination thereof. In some embodiments, the first heavily doped region 140A, the second heavily doped region 140B, and the semiconductor layer 100 have the same conductivity type. In some embodiments, the thickness of the first heavily doped region 140A and the second heavily doped region 140B is less than the thickness of the shallow trench isolation structure 120. For example, the thickness of the first heavily doped region 140A and the second heavily doped region 140B may be about 0.5 μm. In some embodiments, as shown in FIG. 1 , the top surface area of the first heavily doped region 140A and the second heavily doped region 140B is smaller than the bottom surface area. By forming the first heavily doped region 140A and the second heavily doped region 140B, an ohmic contact with the subsequently formed conductive line 150 can be established, which is beneficial to provide a voltage in the groove.

When an operating voltage is applied to the semiconductor device 10 through the plurality of conductive lines 150, the first heavily doped region 140A and the second heavily doped region 140B may form an ohmic contact at the interface with the semiconductor layer 100. In this way, current collapse between the first resistor layer 130A and the second resistor layer 130B and the semiconductor layer 100 may be avoided.

In some embodiments, as shown in FIG. 1 , the plurality of cells further include a third cell 10C. The third cell 10C may include a third resistor layer 130C disposed on the shallow trench isolation structure 120 and a third heavily doped region 140C embedded in the shallow trench isolation structure 120 and physically contacting the semiconductor layer 100. The semiconductor device 10 further includes another conductive line 150 electrically connecting the second resistor layer 130B, the third resistor layer 130C, and the third heavily doped region 140C. Each component in the third cell 10C can be formed with the same or similar material as each corresponding component in the first cell 10A and the second cell 10B, and its description is omitted here for simplicity.

Although only three cells in the semiconductor device 10 are shown in FIG. 1 , the present disclosure is not limited thereto. Depending on the operating voltage of the semiconductor device 10 , a number of cells separated by the deep trench isolation structure 110 may be connected in series with a plurality of conductive lines 150 in the semiconductor device 10 , thereby achieving the effect of sequentially reducing the voltage.

For example, the semiconductor device 10 may further include another conductive line 150 electrically connecting the first resistor layer 130A and the first heavily doped region 140A, and this conductive line 150 may be electrically connected to the resistor layer in another cell (trench). On the other side, the semiconductor device 10 may further include another conductive line 150 electrically connecting the third resistor layer 130C and the resistor layer and heavily doped region in another cell (trench).

By forming the above structure disclosed in the present invention, a higher operating voltage can be applied to the entire semiconductor device 10, and there is no need to increase the thickness of the shallow trench isolation structure 120 on the semiconductor layer 100 to achieve the purpose of increasing the operating voltage.

2A to 2F are cross-sectional views of various stages of forming a semiconductor device 10 according to some embodiments of the present disclosure. Although only two cells (grooves) of the formed semiconductor device 10 are shown in FIGS. 2A to 2F, the method of forming the semiconductor device 10 discussed below can be used to form a semiconductor device 10 having any number of cells (grooves).

Referring to FIG. 2A , a semiconductor layer 100 is first provided. In some embodiments, the provided semiconductor layer 100 further includes an insulating layer 102 covering the bottom surface of the semiconductor layer 100. A carrier substrate 104 for transferring the semiconductor layer 100 may be further included below the semiconductor layer 100. In some embodiments, the formation of the semiconductor layer 100, the insulating layer 102, and the carrier substrate 104 may be performed by a wafer bonding process, an epitaxial layer transfer (ELTRAN) process, a similar process, or a combination thereof.

In some embodiments using a wafer bonding process, the insulating layer 102 is directly bonded to the semiconductor layer 100, and both are then bonded to the carrier substrate 104, and the semiconductor layer 100 may be thinned before being bonded to the carrier substrate 104.

In some embodiments using an epitaxial layer transfer process, the semiconductor layer 100 is epitaxially grown on a seed layer (not shown), and then the semiconductor layer 100 is oxidized to form an insulating layer 102. After the insulating layer 102 is bonded to the carrier substrate 104, the seed layer is removed.

In some embodiments, the semiconductor layer 100 may be doped with p-type or n-type dopants. For example, the p-type dopant may be boron, aluminum, gallium, _BF2 , the like, or a combination thereof, and the n-type dopant may be nitrogen, phosphorus, arsenic, antimony, the like, or a combination thereof. In some embodiments, the semiconductor layer 100 may be doped by in-situ doping during epitaxial growth and/or by implanting the p-type or n-type dopant after epitaxial growth.

Next, referring to FIG. 2B , a shallow trench isolation structure 120 is formed on the semiconductor layer 100. In some embodiments, the semiconductor layer 100 has a first protrusion 106A and a second protrusion 106B in the shallow trench isolation structure 120. These protrusions may correspond to the positions of each heavily doped region to be formed subsequently, such as the first heavily doped region 140A and the second heavily doped region 140B. In some embodiments, the first protrusion 106A and the second protrusion 106B have a tapered shape.

In some embodiments, the formation of the shallow trench isolation structure 120 may include etching the semiconductor layer 100 to leave the protrusion, and then depositing an isolation material on the etched semiconductor layer 100 to form the shallow trench isolation structure 120 around the protrusion. The etching process may include, for example, a reactive ion etching (RIE) process, other suitable processes, or a combination thereof.

The isolation material used to form the shallow trench isolation structure 120 may be, for example, silicon oxide, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), other suitable materials, or a combination thereof. In addition, the isolation material may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), other suitable deposition processes, or a combination thereof.

In some embodiments, a planarization process such as chemical mechanical polish (CMP), an etch back process, or a combination thereof may be used to remove excess isolation material. In this way, the top surface of the shallow trench isolation structure 120 may be formed to be level with the top surfaces of the first protrusion 106A and the second protrusion 106B.

2C , a first resistor layer 130A and a second resistor layer 130B are formed on the shallow trench isolation structure 120. The formation of the first resistor layer 130A and the second resistor layer 130B includes depositing materials (such as polysilicon) for the first resistor layer 130A and the second resistor layer 130B on the shallow trench isolation structure 120 and patterning the materials by processes such as lithography and etching.

Next, referring to FIG. 2D , the first heavily doped region 140A and the second heavily doped region 140B are embedded in the shallow trench isolation structure 120 , and the first heavily doped region 140A and the second heavily doped region 140B physically contact the semiconductor layer 100 .

In some embodiments, the formation of the first heavily doped region 140A and the second heavily doped region 140B includes implanting a dopant into the first protrusion 106A and the second protrusion 106B. In some embodiments, the dopant has the same conductivity type as the semiconductor layer 100. The first heavily doped region 140A and the second heavily doped region 140B may include the same dopant as the semiconductor layer 100, and the dopant has a higher concentration in the first heavily doped region 140A and the second heavily doped region 140B.

In some other embodiments, the formation of the first heavily doped region 140A and the second heavily doped region 140B includes removing a portion of the first protrusion 106A and the second protrusion 106B to form a first through hole and a second through hole (not shown) exposing the semiconductor layer 100 in the shallow trench isolation structure 120. Then, a semiconductor material may be filled in the first through hole and the second through hole to form the first heavily doped region 140A and the second heavily doped region 140B. In some embodiments, the semiconductor material includes the same material as the semiconductor layer 100. In some embodiments, p-type or n-type dopants may be further doped in the semiconductor material. For example, the p-type dopant may be boron, aluminum, gallium, _BF2 , a similar material, or a combination thereof, and the n-type dopant may be nitrogen, phosphorus, arsenic, antimony, a similar material, or a combination thereof. It should be understood that, although in the embodiments shown in FIGS. 2A to 2F, the resistor layer is formed first and then the heavily doped region is formed, the present disclosure does not actually limit the order of forming the resistor layer and the heavily doped region. In some other embodiments, the heavily doped region may be formed first and then the resistor layer.

Next, referring to FIG. 2E , a deep trench isolation structure is formed to separate the semiconductor device into a plurality of cells, and the plurality of cells include a first cell 10A and a second cell 10B. As shown in FIG. 2E , a first resistor layer 130A and a first heavily doped region 140A are located in the first cell 10A, and a second resistor layer 130B and a second heavily doped region 140B are located in the second cell 10B.

In some embodiments, the formation of the deep trench isolation structure 110 may include forming a deep trench (not shown) penetrating the shallow trench isolation structure 120 and the semiconductor layer 100 and filling the deep trench with an insulating material.

In some embodiments, the deep trenches described above may be formed using a masking layer (not shown separately) and a suitable etching process. For example, the masking layer may include a hard mask of silicon nitride and may be formed by a process such as chemical vapor deposition (CVD). The masking layer may also be formed using other materials, such as oxides, oxynitrides, silicon carbide, combinations thereof, and may be formed using other processes such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or even forming silicon oxide followed by nitridation. Once formed, the masking layer may be patterned by a suitable lithography process to expose portions of the semiconductor layer 100 that will be removed to form the deep trenches. In some embodiments, the patterned shielding layer substantially corresponds to directly above the semiconductor layer 100 in FIG. 1 .

As will be understood by those skilled in the art, however, the above-described process and materials for forming the shielding layer are not the only methods that may be used to protect portions of the semiconductor layer 100 while exposing other portions of the semiconductor layer 100 for forming deep trenches. Any suitable process, such as patterning and developing a photoresist, may be used to expose portions of the semiconductor layer 100 that will be removed to form shallow trenches. The scope of the present disclosure is intended to include all such methods.

After forming the patterned shielding layer, a deep trench is formed in the semiconductor layer 100. The exposed semiconductor layer 100 can be removed by a suitable process such as reactive ion etching (RIE) to form a deep trench in the semiconductor layer 100, although any suitable process can be used. The depth of the deep trench can depend on the material used for the semiconductor layer 100 and its thickness. As long as the effect of sequentially reducing the voltage between each trench can be achieved, the present disclosure does not limit the depth of the deep trench. In some embodiments, the deep trench is formed so that the bottom surface of the deep trench is the same height as the bottom surface of the semiconductor layer 100. In some other embodiments, the deep trench is formed such that the bottom surface of the deep trench is level with the bottom surface of the insulating layer 102.

The insulating material used to fill the deep trench may be, for example, silicon oxide, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), other suitable materials, or a combination thereof. In addition, the insulating material may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), other suitable deposition processes, or a combination thereof.

Next, referring to FIG. 2F, the formation of the semiconductor device 10 further includes forming a conductive line 150 electrically connecting the first resistor layer 130A, the second resistor layer 130B, and the second heavily doped region 140B.

Although only two units in the semiconductor device 10 are shown in FIGS. 2A to 2F, the present disclosure is not limited thereto. Depending on the operating voltage of the semiconductor device 10, a plurality of conductive lines 150 may be formed in the semiconductor device 10 to connect in series a number of units separated by the deep trench isolation structure 110, thereby achieving the effect of sequentially reducing the voltage.

For example, the semiconductor device 10 may further include another conductive line 150 electrically connecting the first resistor layer 130A and the first heavily doped region 140A, and this conductive line 150 may be electrically connected to the resistor layer in another cell (trench). On the other side, the semiconductor device 10 may further include another conductive line 150 electrically connecting the third resistor layer 130C and the resistor layer and heavily doped region in another cell (trench).

In summary, the present disclosure provides a semiconductor device including a deep trench isolation structure and a heavily doped region. Multiple heavily doped regions embedded in the shallow trench isolation structure can prevent current collapse from occurring between the resistor layer and the semiconductor layer. In this way, by using the deep trench isolation structure to separate the semiconductor layers of each trench and electrically connecting each unit with a lower limiting voltage with a conductive line, the voltage can be reduced multiple times between each unit (trench). Compared to the known structure having a resistor layer for voltage reduction, the semiconductor device disclosed in the present invention can be applied with a higher operating voltage without increasing the thickness of the shallow trench isolation structure on the semiconductor layer.

The features of several embodiments are summarized above so that those with ordinary knowledge in the art to which the present invention belongs can more easily understand the viewpoints of the embodiments of the present invention. Those with ordinary knowledge in the art to which the present invention belongs should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and/or advantages as the embodiments introduced herein. Those with ordinary knowledge in the art to which the present invention belongs should also understand that such equivalent processes and structures do not violate the spirit and scope of the present invention, and various changes, substitutions and replacements can be made without violating the spirit and scope of the present invention.

10: semiconductor device 10A: first unit 10B: second unit 10C: third unit 100: semiconductor layer 102: insulating layer 104: carrier substrate 106A: first protrusion 106B: second protrusion 110: deep trench isolation structure 120: shallow trench isolation structure 130A: first resistor layer 130B: second resistor layer 130C: third resistor layer 140A: first heavily doped region 140B: second heavily doped region 140C: third heavily doped region 150: conductive line

The following will be described in detail with the accompanying drawings. It should be noted that, according to standard practice in the industry, various features are not drawn to scale and are only used for illustration. In fact, the size of the components can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention. Figure 1 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. Figures 2A to 2F are cross-sectional views of various stages of forming a semiconductor device according to some embodiments of the present disclosure.

10: Semiconductor devices

10A: Unit 1

10B: Unit 2

10C: Unit 3

100:Semiconductor layer

102: Insulation layer

104: Supporting base

110: Deep trench isolation structure

120: Shallow trench isolation structure

130A: First resistor layer

130B: Second resistor layer

130C: The third resistor layer

140A: First heavily doped area

140B: Second heavy doping area

140C: The third heavily doped zone

150: Conductive lines

Claims (19)

A semiconductor device comprises: a semiconductor layer; a deep trench isolation structure, which separates the semiconductor device into a plurality of units, wherein the units include a first unit and a second unit; a shallow trench isolation structure, which is disposed on the semiconductor layer in the units; a first resistor layer and a second resistor layer, which are disposed on the shallow trench isolation structure in the first unit and the second unit, respectively; a first heavily doped region and a second heavily doped region, which are disposed on the first unit and the second unit, respectively; The shallow trench isolation structure is embedded in the first unit and the second unit and physically contacts the semiconductor layer; and a conductive line electrically connects the first resistor layer, the second resistor layer, and the second heavily doped region, wherein, in a cross-sectional view, the doped region of the first unit has only the first heavily doped region and the doped region of the second unit has only the second heavily doped region, and the first heavily doped region and the second heavily doped region have the same conductive type. A semiconductor device as claimed in claim 1, wherein the deep trench isolation structure passes through the shallow trench isolation structure between each of the cells. A semiconductor device as claimed in claim 1, wherein the deep trench isolation structure laterally surrounds the semiconductor layer of multiple portions in each of the cells, and the semiconductor layer is electrically isolated between each of the cells. A semiconductor device as claimed in claim 1, wherein the shallow trench isolation structure is not continuous between each of the units. The semiconductor device of claim 1 further includes another conductive line electrically connecting the first resistor layer and the first heavily doped region. A semiconductor device as claimed in claim 1, wherein the first resistor layer and the second resistor layer are horizontally spaced from multiple edges of the first unit and the second unit, respectively. The semiconductor device of claim 1 further includes an insulating layer covering the bottom surface of the semiconductor layer. A semiconductor device as claimed in claim 7, wherein the deep trench isolation structure extends from the top surface of the shallow trench isolation structure to the top surface of the insulating layer. A semiconductor device as claimed in claim 1, wherein the first heavily doped region, the second heavily doped region, and the semiconductor layer have the same conductivity type. A semiconductor device as claimed in claim 1, wherein the thickness of the first heavily doped region and the second heavily doped region is less than the thickness of the shallow trench isolation structure. A semiconductor device as claimed in claim 1, wherein the shallow trench isolation structure and the deep trench isolation structure comprise different materials. A semiconductor device as claimed in claim 1, wherein the units further include a third unit, and the third unit includes: a third resistor layer disposed on the shallow trench isolation structure; and a third heavily doped region embedded in the shallow trench isolation structure and physically contacting the semiconductor layer; wherein the semiconductor device further includes another conductive line electrically connecting the second resistor layer, the third resistor layer, and the third heavily doped region. A method for forming a semiconductor device includes: forming a shallow trench isolation structure on a semiconductor layer; forming a first resistor layer and a second resistor layer on the shallow trench isolation structure; embedding a first heavily doped region and a second heavily doped region into the shallow trench isolation structure, and the first heavily doped region and the second heavily doped region physically contact the semiconductor layer; forming a semiconductor device A deep trench isolation structure is provided which is divided into a plurality of units, and the units include a first unit and a second unit, wherein the first resistor layer and the first heavily doped region are located in the first unit, and the second resistor layer and the second heavily doped region are located in the second unit; and a conductive line is formed which electrically connects the first resistor layer, the second resistor layer, and the second heavily doped region. A method for forming a semiconductor device as claimed in claim 13, wherein before the first heavily doped region and the second heavily doped region are embedded in the shallow trench isolation structure, the semiconductor layer has a first protrusion and a second protrusion in the shallow trench isolation structure. A method for forming a semiconductor device as claimed in claim 14, wherein the formation of the first heavily doped region and the second heavily doped region includes implanting a dopant into the first protrusion and the second protrusion. A method for forming a semiconductor device as claimed in claim 15, wherein the dopant has the same conductivity type as the semiconductor layer. A method for forming a semiconductor device as claimed in claim 13, wherein the formation of the first heavily doped region and the second heavily doped region comprises: forming a first through hole and a second through hole in the shallow trench isolation structure to expose the semiconductor layer; and filling the first through hole and the second through hole with a semiconductor material. A method for forming a semiconductor device as claimed in claim 13, wherein the formation of the deep trench isolation structure includes: forming a deep trench penetrating the shallow trench isolation structure and the semiconductor layer; and filling the deep trench with an insulating material. The method for forming a semiconductor device as claimed in claim 13 further includes forming another conductive line electrically connecting the first resistor layer and the first heavily doped region.

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