TWI852012B - Semiconductor device including a superlattice with different non-semiconductor material monolayers and associated methods - Google Patents

Abstract

A semiconductor device may include a semiconductor substrate, and a superlattice on the semiconductor substrate and including a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A first at least one non-semiconductor monolayer may be constrained within the crystal lattice of a first pair of adjacent base semiconductor portions and comprise a first non-semiconductor material, and a second at least one non-semiconductor monolayer may be constrained within the crystal lattice of a second pair of adjacent base semiconductor portions and comprise a second non-semiconductor material different than the first non-semiconductor material.

Description

Semiconductor device comprising a superlattice having different single layers of non-semiconductor materials and related methods

The present invention generally relates to semiconductor devices, and more particularly, to semiconductor devices using enhanced semiconductor materials and related methods.

Many structures and techniques have been proposed to improve the performance of semiconductor devices by, for example, enhancing the mobility of charge carriers. For example, U.S. Patent Application No. 2003/0057416 by Currie et al. discloses strained material layers of silicon, silicon-germanium, and relaxed silicon that also include impurity-free zones that would otherwise result in performance degradation. The biaxial strain caused by these strained material layers in the upper silicon layer changes the mobility of carriers, thereby enabling the fabrication of higher speed and/or lower power devices. Fitzgerald et al.'s U.S. Patent Application Publication No. 2003/0034529 discloses a CMOS inverter based on similar strained silicon technology.

U.S. Patent No. 6,472,685 B2 issued to Takagi discloses a semiconductor device including a layer of silicon and a carbon layer sandwiched between silicon layers, so that the conduction band and the valence band of the second silicon layer are subjected to tensile strain. In this way, electrons having a small effective mass and induced by an electric field applied to a gate are confined in the second silicon layer, and therefore, it can be determined that the N-channel MOSFET has a higher mobility.

U.S. Patent No. 4,937,204 issued to Ishibashi et al. discloses a superlattice comprising a plurality of layers, the plurality of layers being less than eight monolayers and containing fractional or binary semiconductor layers or a binary compound semiconductor layer, the plurality of layers being alternately grown by epitaxial growth, wherein the main current direction is perpendicular to the layers of the superlattice.

U.S. Patent No. 5,357,119 issued to Wang et al. discloses a silicon-germanium short-period superlattice that achieves higher mobility by reducing alloy scattering in the superlattice. Based on similar principles, U.S. Patent No. 5,683,934 issued to Candelaria discloses a MOSFET with improved mobility, which includes a channel layer comprising an alloy of silicon and a second material that is alternately present in the silicon lattice at a percentage that places the channel layer under tensile stress.

U.S. Patent No. 5,216,262 issued to Tsu discloses a quantum well structure comprising two barrier regions and an epitaxially grown semiconductor layer sandwiched therebetween. Each barrier region is composed of alternating SiO2/Si monolayers with a thickness ranging from approximately two to six. The barrier regions are sandwiched by a much thicker silicon segment.

In the September 6, 2000 online issue of Applied Physics and Materials Science & Processing, pp. 391 – 402, Tsu disclosed a semiconductor-atomic superlattice (SAS) of silicon and oxygen. This silicon/oxygen superlattice structure is disclosed as being useful for silicon quantum and light-emitting devices. In particular, it is disclosed how to make and test a green electroluminescence diode structure. The direction of current flow in the diode structure is vertical, that is, perpendicular to the layers of the SAS. The SAS disclosed in the article may include semiconductor layers separated by adsorbed species such as oxygen atoms and CO molecules. The silicon grown outside the adsorbed oxygen monolayer is described as an epitaxial layer with a relatively low defect density. One SAS structure includes a silicon portion 1.1 nm thick, which is about eight atomic layers of silicon, while another structure has a silicon portion twice as thick. Tsu's light-emitting SAS structure is further discussed in an article published by Luo et al. in Physics Review Letters, Vol. 89, No. 7 (August 12, 2002) entitled "Chemical Design of Direct-Gap Light-Emitting Silicon."

U.S. Patent No. 7,105,895 to Wang et al. discloses a barrier building block of thin silicon and oxygen, carbon, nitrogen, phosphorus, antimony, arsenic or hydrogen that can reduce the vertical current flowing through the lattice by more than four orders of magnitude. The insulating layer/barrier layer allows low-defect epitaxial silicon to be deposited next to the insulating layer.

Published UK Patent Application No. 2,347,520 by Mears et al. discloses that aperiodic photonic band-gap (APBG) structures can be used in electronic bandgap engineering. Specifically, the application discloses that material parameters, such as the position of the band minima, effective mass, etc., can be tuned to obtain new aperiodic materials with desired band structure properties. Other parameters, such as electrical conductivity, thermal conductivity, and dielectric permittivity or magnetic permeability, are disclosed as being potentially engineered into the material.

In addition, U.S. Patent No. 6,376,337 issued to Wang et al. discloses a method for making an insulating or barrier layer for a semiconductor device, which includes depositing a layer of silicon and at least one other element on a silicon substrate, so that the deposited layer is substantially defect-free, so that substantially defect-free epitaxial silicon can be deposited on the deposited layer. As an alternative, a single layer composed of one or more elements, preferably including oxygen, is absorbed on the silicon substrate. Multiple insulating layers sandwiched between the epitaxial silicon form a barrier composite.

Although the above methods exist, it is desirable to further enhance the use of advanced semiconductor materials and processing technologies in order to achieve improved performance of semiconductor devices.

A semiconductor device may include a semiconductor substrate and a superlattice on the semiconductor substrate, the superlattice including a plurality of stacked layer groups. Each layer group of the superlattice may include a plurality of stacked base semiconductor monolayers, which define a base semiconductor portion, and at least one non-semiconductor monolayer constrained in a lattice of an adjacent base semiconductor portion. The first at least one non-semiconductor monolayer constrained in the lattice of a first pair of adjacent base semiconductor portions may include a first non-semiconductor material, and the second at least one non-semiconductor monolayer constrained in the lattice of a second pair of adjacent base semiconductor portions may include a second non-semiconductor material different from the first non-semiconductor material.

For example, the first non-semiconductor material may include oxygen and nitrogen, and the second non-semiconductor material may include at least one of carbon and oxygen. In an exemplary embodiment, the third at least one non-semiconductor monolayer constrained within the lattice of the third pair of adjacent base semiconductor portions may include a third non-semiconductor material different from the first non-semiconductor material and the second non-semiconductor material.

In one exemplary embodiment, the first non-semiconductor material may include nitrogen, and the first at least one non-semiconductor monolayer may be above the second at least one non-semiconductor monolayer in the superlattice. According to another example, a base semiconductor portion between the first at least one non-semiconductor monolayer and the second at least one non-semiconductor monolayer may include carbon doping. The base semiconductor monolayer may include, for example, silicon. The semiconductor device may further include separate source and drain regions defining a channel within the superlattice, and a gate overlying the channel.

A method for making a semiconductor device may include forming a superlattice on a semiconductor substrate, the superlattice comprising a plurality of stacked layer groups. Each layer group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a lattice of an adjacent base semiconductor portion. The first at least one non-semiconductor monolayer constrained within the lattice of a first pair of adjacent base semiconductor portions may include a first non-semiconductor material, and the second at least one non-semiconductor monolayer constrained within the lattice of a second pair of adjacent base semiconductor portions may include a second non-semiconductor material different from the first non-semiconductor material.

For example, the first non-semiconductor material may include oxygen and nitrogen, and the second non-semiconductor material may include at least one of carbon and oxygen. In an exemplary embodiment, the third at least one non-semiconductor monolayer constrained within the lattice of the third pair of adjacent base semiconductor portions may include a third non-semiconductor material different from the first non-semiconductor material and the second non-semiconductor material.

In an exemplary embodiment, the first non-semiconductor material may include nitrogen, and the first at least one non-semiconductor monolayer may be above the second at least one non-semiconductor monolayer in the superlattice. According to another example, a base semiconductor portion between the first at least one non-semiconductor monolayer and the second at least one non-semiconductor monolayer may include carbon doping. The base semiconductor monolayer may include, for example, silicon. In an exemplary embodiment, the method may further include forming a channel within the superlattice with separated source and drain regions, and a gate overlying the channel.

Reference is made to the drawings attached to the specification for detailed description of exemplary embodiments, which are shown in the drawings as exemplary embodiments. However, the embodiments may be implemented in many different forms and should not be construed as being limited to the specific examples provided in this specification. On the contrary, these embodiments are provided only to make the invention disclosed by the present invention more complete and detailed. Throughout this specification and the drawings, the same figure symbols refer to the same elements, and primes (') and double primes ('') are used to indicate similar elements in different embodiments.

Generally speaking, the present invention relates to the use of enhanced superlattice materials within source and drain regions to reduce the Schottky barrier height, thereby reducing the source and drain contact resistance. In this specification and the accompanying drawings, the enhanced semiconductor superlattice is also referred to as an "MST" layer or "MST technology".

In detail, MST technology involves advanced semiconductor materials, such as superlattices 25 which will be further described below. The applicant's theory (but the applicant does not wish to be bound by this theory) is that the superlattice structure described in this specification can reduce the effective mass of charge carriers and thus bring about a higher charge carrier mobility. Various definitions of effective mass have been explained in the literature in the technical field to which the invention belongs. To measure the degree of improvement in effective mass, the applicant uses the "conductivity reciprocal effective mass tensor" for electrons and holes respectively. and : is the definition of an electron, and: is the definition of a hole, where f is the Fermi-Dirac distribution, EF is the Fermi energy, T is the temperature, E(k,n) is the energy of the electron in the n-th band state corresponding to wave vector k, the subscripts i and j refer to the orthogonal coordinates x, y and z, the integration is performed in the Brillouin zone (BZ), and the summation is performed in the energy bands of the electron and hole above and below the Fermi energy, respectively.

The applicant defines the conductivity anti-effective mass tensor as follows: a material has a larger value of the corresponding component of the conductivity anti-effective mass tensor, and its conductivity tensorial component is also larger. The applicant again theorizes (but does not wish to be bound by this theory) that the superlattice described in this specification can set the value of the conductivity anti-effective mass tensor to enhance the conductivity of the material, such as the typical preferred direction of charge carrier transport. The reciprocal of the appropriate tensor term is referred to herein as the conductivity effective mass. In other words, if one wants to describe the characteristics of a semiconductor material structure, as described above, calculating the conductivity effective mass of electrons/holes in the intended carrier transport direction can be used to distinguish better materials.

Applicants have identified improved materials or structures that can be used in semiconductor devices. More specifically, the materials or structures identified by applicants have band structures with values of effective mass for suitable conductivity of electrons and/or holes that are substantially less than the values corresponding to silicon. In addition to being characterized by improved mobility, these structures can be formed or used in a manner that allows them to provide piezoelectric, pyroelectric and/or ferroelectric properties that are beneficial for use in a variety of different device types, as further discussed below.

1 and 2, the material or structure is in the form of a superlattice 25, whose structure is controlled at the atomic or molecular level and can be formed using known techniques of atomic or molecular layer deposition. The superlattice 25 includes a plurality of stacked layer groups 45a-45n, as shown in the schematic cross-sectional view of FIG.

As shown, each layer group 45a-45n of the superlattice 25 includes a plurality of stacked base semiconductor single layers 46, which define respective base semiconductor portions 46a-46n and a band modification layer 50 thereon. For the sake of clarity, the band modification layer 50 is represented by dots in FIG. 1 .

As shown in the figure, the energy band modification layer 50 includes a non-semiconductor monolayer, which is confined in a lattice of the adjacent base semiconductor portion. The phrase "confined in a lattice of the adjacent base semiconductor portion" means that at least some semiconductor atoms from the opposing base semiconductor portions 46a-46n are chemically bonded together through the non-semiconductor monolayer 50 between the opposing base semiconductor portions, as shown in FIG. 2. Generally, such a configuration can be made possible by controlling the amount of non-semiconductor material deposited on the semiconductor portions 46a-46n by atomic layer deposition techniques, so that the available semiconductor bonding sites are not completely (i.e., not completely or less than 100% coverage) occupied by bonding to non-semiconductor atoms, as will be discussed further below. Thus, as more semiconductor material monolayers 46 are deposited on or above a non-semiconductor monolayer 50, the newly deposited semiconductor atoms can fill in the remaining unoccupied semiconductor atom bonding sites below the non-semiconductor monolayer.

In other embodiments, it is possible to use more than one such non-semiconductor monolayer. It should be noted that when this specification refers to a non-semiconductor monolayer or a semiconductor monolayer, it means that the material used for the monolayer would be non-semiconductor or semiconductor if formed in the main body. That is, the properties exhibited by a single monolayer of a material (such as silicon) are not necessarily the same as the properties exhibited when formed in the main body or a relatively thick layer, which should be understood by those skilled in the art to which the present invention belongs.

The applicant's theory suggests (but the applicant does not wish to be bound by this theory) that the band modification layer 50 and the adjacent base semiconductor portions 46a-46n can make the superlattice 25 have a lower effective mass for proper conductivity of electric carriers in the direction parallel to the layers than it would otherwise have. Thinking in another direction, this parallel direction is orthogonal to the stacking direction. The band modification layer 50 can also make the superlattice 25 have a general band structure, while advantageously playing the role of an insulator between multiple layers or regions vertically above and below the superlattice.

Furthermore, the superlattice structure can also advantageously serve as a barrier to diffusion of dopants and/or materials between multiple layers vertically above and below the superlattice 25. Therefore, these characteristics can advantageously allow the superlattice 25 to provide an interface for high-K dielectrics, which can not only reduce the diffusion of high-K materials into the channel region, but can also advantageously reduce unwanted scattering effects and improve device mobility, as will be understood by those skilled in the art to which the present invention belongs.

The theory of the present invention also states that semiconductor devices including superlattice 25 can enjoy higher charge carrier mobility due to the inherently lower conductive effective mass. In certain embodiments, due to the band engineering achieved by the present invention, superlattice 25 can further have a substantially direct band gap, which is particularly advantageous for, for example, optoelectronic devices.

The superlattice 25 may also include a top cap layer 52 above an upper layer group 45n. The top cap layer 52 may include a plurality of base semiconductor monolayers 46. The top cap layer 52 may include between 2 and 100 monolayers of the base semiconductor, and preferably between 10 and 50 monolayers.

Each of the base semiconductor portions 46a-46n may include a base semiconductor selected from the group consisting of a group IV semiconductor, a group III-V semiconductor, and a group II-VI semiconductor. Of course, a group IV semiconductor also includes a group IV-IV semiconductor, which can be understood by those skilled in the art to which the present invention belongs. More specifically, the base semiconductor may include, for example, at least one of silicon and germanium.

Each energy band modification layer 50 may include a non-semiconductor selected from the group consisting of, for example, oxygen, nitrogen, fluorine, carbon, and carbon-oxygen. The non-semiconductor also preferably has the property of being thermally stable during the deposition of the next layer, thereby facilitating manufacturing. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound compatible with a given semiconductor process, as will be understood by those skilled in the art to which the present invention belongs. In more detail, the base semiconductor may include, for example, at least one of silicon and germanium.

It should be noted that the term "monolayer" herein refers to a single atomic layer and also refers to a single molecular layer. It should also be noted that the energy band modification layer 50 provided by a single monolayer should also include a monolayer in which all possible positions in the layer are not completely occupied (i.e., the coverage is not complete or less than 100%). For example, referring to the atomic diagram of FIG. 2 , it presents a 4/1 repeating structure with silicon as the base semiconductor material and oxygen as the energy band modification material. Only half of the possible positions of the oxygen atoms are occupied.

In other embodiments and/or when different materials are used, this is not necessarily a one-half occupancy situation, as will be appreciated by those skilled in the art to which the present invention pertains. In fact, as will be appreciated by those skilled in the art of atomic deposition technology, even in this schematic diagram, the individual oxygen atoms in a given monolayer are not arranged exactly along a flat plane. For example, a preferred occupancy range is one-eighth to one-half of the possible oxygen positions being filled, but other occupancy ranges may also be used in certain embodiments.

Since silicon and oxygen are currently widely used in general semiconductor manufacturing processes, manufacturers will be able to immediately apply the materials described in this specification. Atomic deposition or single layer deposition is also a widely used technology. Therefore, semiconductor devices incorporating superlattice 25 according to the present invention can be immediately adopted and implemented, and those familiar with the technical field to which the present invention belongs should be able to understand.

Applicants' theory suggests (but applicants do not wish to be bound by such theory) that for a superlattice, such as the silicon/oxygen superlattice described, the number of silicon monolayers should ideally be seven or fewer so that the energy bands of the superlattice are common or relatively uniform everywhere to achieve the desired advantages. The silicon/oxygen 4/1 repeating structure shown in Figures 1 and 2 has been modeled to show the preferred mobility of electrons and holes in the x-direction. For example, the calculated conductive effective mass of an electron (isotropic with respect to the bulk silicon) is 0.26, while the calculated conductive effective mass of the 4/1 silicon/oxygen superlattice in the x-direction is 0.12, for a ratio of 0.46. Similarly, in terms of the calculated results for holes, the value for the bulk silicon is 0.36, and the value for the 4/1 silicon/oxygen superlattice is 0.16, with a ratio of 0.44.

While this directionally preferential characteristic may be advantageous for some semiconductor devices, other semiconductor devices may benefit from a more uniform increase in mobility in any direction parallel to the layer grouping. It will be appreciated by those skilled in the art that an increase in the mobility of both electrons and holes, or an increase in the mobility of only one of the charge carriers, may also be beneficial.

The lower conductive effective mass of the 4/1 silicon/oxygen embodiment of the superlattice 25 may be less than two-thirds of the conductive effective mass of the non-superlattice 25, and this is true for both electrons and holes. Of course, the superlattice 25 may further include at least one type of conductive dopant therein, as will be understood by those skilled in the art to which the present invention pertains.

Reference is made to FIG. 3 for another embodiment of a superlattice 25' having different properties according to the present invention. In this embodiment, the repeating pattern is 3/1/5/1. In more detail, the bottom substrate semiconductor portion 46a' has three monolayers, and the second bottom substrate semiconductor portion 46b' has five monolayers. This pattern is repeated throughout the superlattice 25'. Each band modification layer 50' may include a single monolayer. For such a superlattice 25' comprising silicon/oxygen, the enhancement of the charge carrier mobility is independent of the orientation of the planes of the layers. Other elements in FIG. 3 not mentioned here are similar to those discussed above with reference to FIG. 1, and therefore will not be discussed again.

In some device embodiments, each base semiconductor portion of the superlattice may be the same number of monolayers thick. In other embodiments, at least some base semiconductor portions of the superlattice may be different numbers of monolayers thick. In yet other embodiments, each base semiconductor portion of the superlattice may be different numbers of monolayers thick.

Figures 4A-4C present the band structures calculated using Density Functional Theory (DFT). It is well known in the art to which the present invention pertains that DFT generally underestimates the absolute value of the band gap. Therefore, all bands above the gap can be offset using an appropriate "scissors correction". However, the shape of the bands is recognized to be far more reliable. The energy of the longitudinal axis should be interpreted from this perspective.

FIG4A shows the band structures calculated from the Gamma point (G) for bulk silicon (shown as solid lines) and the 4/1 silicon/oxygen superlattice 25 of FIG1 (shown as dashed lines). The directions in the figure refer to the unit cell of the 4/1 silicon/oxygen structure and not to the normal unit cell of silicon, although the direction (001) in the figure does correspond to the direction (001) of the normal silicon unit cell and thus shows the expected location of the silicon conduction band minimum. The directions (100) and (010) in the figure correspond to the directions (110) and (-110) of the normal silicon unit cell. Those skilled in the art will appreciate that the silicon energy bands in the figure are folded and gathered so as to be represented in the appropriate reciprocal lattice directions of the 4/1 silicon/oxygen structure.

As can be seen from the figure, compared with the bulk silicon, the conduction band minimum of the 4/1 silicon/oxygen structure is located at point G, while its valence band minimum appears at the edge of the Brillo zone in the direction (001), which we call point Z. We can also notice that the curvature of the conduction band minimum of the 4/1 silicon/oxygen structure is larger than that of silicon, which is due to the perturbation introduced by the additional oxygen layer, which causes band splitting.

Figure 4B presents the band structures calculated from point Z for both bulk silicon (solid line) and the 4/1 silicon/oxygen superlattice 25 (dashed line). This figure depicts the increasing curvature of the band in the direction (100).

FIG4C presents a graph of the band structures calculated from the Gamma point and the Z point for both bulk silicon (solid line) and the 5/1/3/1 silicon/oxygen superlattice 25' of FIG3 (dashed line). Due to the symmetry of the 5/1/3/1 silicon/oxygen structure, the band structures calculated in the (100) and (010) directions are equivalent. Therefore, in the plane parallel to the layers, i.e., perpendicular to the stacking direction (001), the conductive effective mass and mobility are expected to be isotropic. Note that in the 5/1/3/1 silicon/oxygen embodiment, both the conduction band minimum and the valence band maximum are located at or near the Z point.

Although the increase in curvature is an indicator of the decrease in effective mass, the appropriate comparison and judgment can be made by calculating the conductivity inverse effective mass tensor. This allows the applicant to further infer that the 5/1/3/1 superlattice 25' is actually a direct band gap. Those familiar with the art to which the present invention belongs should understand that the appropriate matrix element of the optical transition is another indicator to distinguish between direct and indirect band gap behavior.

Referring to FIGS. 5-9 , other exemplary superlattice structures incorporating different types of non-semiconductor materials in different non-semiconductor monolayers 50 are described. As background, Weeks et al. in U.S. Patent Application No. 16/176,005 (assigned to the applicants of the present application and incorporated herein in its entirety) teach a method of using the aforementioned MST material as a nitrogen gettering layer. For example, by diffusing nitrogen into the MST thin film monolayer after epitaxial deposition, the final nitrogen dosage can be increased to significantly promote dopant blocking and mobility enhancement.

While this approach is advantageous in many applications, a characteristic of this approach is that the nitrogen implanted into the MST gettering layer can penetrate all of the non-semiconductor monolayers 50, so in the case of a silicon/oxygen superlattice, each non-semiconductor monolayer will contain both oxygen and nitrogen. In some instances, in addition to gettering nitrogen within the superlattice 25, it may be desirable to confine the nitrogen to certain portions or regions of the superlattice. This can be accomplished, for example, by introducing another non-semiconductor material, such as carbon, into one or more of the non-semiconductor monolayers 50, or into the base silicon portions 46a-46n beneath the regions where the nitrogen is to be confined.

5, a superlattice 125 may be formed on a semiconductor (e.g., silicon) substrate 121 (which may or may not have a pattern), the superlattice including, in stacking order, an oxygen monolayer 150a, a carbon-doped base silicon portion 146a, an oxygen monolayer 150b, a non-carbon-doped base silicon portion 146b, an oxygen monolayer 150c, and a carbon-doped base silicon portion 146c. The carbon in the base silicon portion 146c may advantageously help block or prevent nitrogen 153 from diffusing downward into the monolayers 150a to 150c.

In detail, during the nitrogen anneal, nitrogen 153 is blocked from entering the underlying oxygen monolayers 150a-150c by the carbon in the base silicon portion 146c. This allows most or all of the nitrogen to be trapped in the upper MST spacers and intercalated MST oxygen layers. The total amount of nitrogen absorbed will be equal to the total amount of nitrogen that would be evenly distributed throughout the superlattice 125 stack in the absence of the carbon barrier.

Thus, the next three non-semiconductor monolayers 150d to 150f in the stack (with base silicon portions 146d and 146e therebetween) contain oxygen and nitrogen. A silicon cap layer 152 may be formed on the upper non-semiconductor layer 150f and terminate in a nitride (SiN) layer 154. The illustrated embodiment includes six non-semiconductor monolayers 150a to 150f (three of which are above the last carbon-implanted base silicon portion 146c), where the carbon also helps stabilize or prevent oxygen from escaping, but in other embodiments, different numbers of base semiconductor portions and non-semiconductor monolayers may be used.

For greater nitrogen enhancement, more oxygen monolayers can be added below the carbon in some embodiments. This will cause the total amount of nitrogen 153' extracted from the surface to accumulate in the topmost oxygen monolayer above the carbon. Depending on the extent of nitrogen 153' accumulation in the upper carbon-free base silicon portion, this method can be used to form silicon oxynitride layers or greater quantum mechanical manipulation, as will be understood by those skilled in the art to which the present invention belongs.

Referring also to the superlattice 125' shown in FIG6, a similar structure is shown wherein all three lower base silicon portions 146a' to 146c' contain carbon. The upper base silicon portions 146d' to 146e' contain no carbon, and the oxygen monolayers 150d' to 150f' will receive all of the absorbed nitrogen 153' dose. The surface nitrogen 153', although attracted by all of the oxygen in the entire superlattice 125' stack, is blocked from entering the lower oxygen monolayers 150a' to 150c' because it is blocked by the carbon in the base silicon portions 146a' to 146c'. In another exemplary embodiment, if desired, only the base silicon portion 146c' may include carbon (i.e., the base silicon portions 146a' to 146b' do not contain carbon).

Referring to FIG. 7 , yet another exemplary embodiment is illustrated, wherein the superlattice 225 comprises a substrate 221, non-semiconductor (e.g., oxygen) monolayers 250 a to 250 f, base semiconductor (e.g., silicon) portions 246 a to 246 e, a semiconductor (e.g., silicon) cap layer 252, and a nitride (e.g., SiN) layer 254, similar to the previous embodiments. However, in the configuration shown in FIG. 7 , the base silicon portions 246 a to 246 e do not contain carbon dopants. Instead, a carbon source gas is injected during the insertion step of the oxygen monolayer 250 c so that the monolayer contains both carbon atoms and oxygen atoms.

It should be noted that in different embodiments, carbon can be co-added, added after oxygen, or added before oxygen. Thus, in this example, the carbon used to block nitrogen 253 from diffusing into the lower oxygen monolayers 250a, 250b is present in monolayer 250c with oxygen, rather than in any of the base silicon portions 246a-246e. As shown in the figure, only the middle oxygen monolayer 250c contains carbon in this example, but in different embodiments, other oxygen monolayers may also contain carbon to further confine nitrogen 253 to the upper two oxygen monolayers 250e, 250f and the base silicon portions 246d, 246e. In other words, all or nearly all of the nitrogen 253 that would otherwise be distributed among the six oxygen monolayers 250a to 250f is confined to the top two oxygen monolayers 250e and 250f. An example is the superlattice 225' shown in FIG8, in which the bottom three oxygen monolayers 250a' to 250c' have carbon atoms inserted therein.

In yet another exemplary embodiment of the superlattice 325 illustrated in FIG9 , carbon may be inserted into the base silicon portion and the oxygen monolayer. In the illustrated embodiment, the superlattice 325 includes a substrate 321, non-semiconductor (e.g., oxygen) monolayers 350a to 350f, base semiconductor (e.g., silicon) portions 346a to 346e, a semiconductor (e.g., silicon) capping layer 352, and a nitride (e.g., SiN) layer 354, similar to the previous embodiments. However, all of the underlying oxygen monolayers 350a to 350d and base silicon portions 346a to 346c contain carbon to further confine nitrogen 353 in the upper oxygen monolayers 350e, 350f and base silicon layers 346d, 346e.

Referring to the flowchart 400 of FIG. 10 and FIG. 11 , an exemplary method for fabricating a semiconductor device 420 including a superlattice 425 as described above is described. Beginning at block 401, an MST superlattice process (block 402) may be performed to form a base MST structure on a semiconductor substrate 421, the structure having a blocking material (e.g., carbon) in one or more base semiconductor (e.g., silicon) portions and/or non-semiconductor (e.g., oxygen) monolayers by implantation or deposition. If carbon is implanted during oxygen monolayer insertion, the dosage may be about 1E15 atoms/cm ² (or less) per implant, specifically about 2.5E14 atoms/cm ² per implant, for example.

If carbon is added during formation of the base semiconductor portion, the concentration may be between 0.01 and 10 atomic percent, more specifically between 0.1 and 2 atomic percent carbon in each base silicon portion, for example. The carbon source gas may be added with the silicon precursor gas during chemical vapor deposition of the base silicon layer. Examples of gaseous carbon sources may include, for example, propylene (propylene C ₃ H ₆ ), cyclopropane (C ₃ H ₆ ), and methylsilane (SiH ₃ CH ₃ ). Another approach is to implant carbon only in the lower base silicon portion, leaving the upper base silicon portion free of carbon.

As previously described, after the superlattice structure of the MST process 402 is formed, additional processing steps can be performed during the device process 403 to produce a semiconductor device 420, in this example, a planar MOSFET. However, those skilled in the art to which the present invention belongs should understand that the materials and techniques mentioned in this specification can be used for many different types of semiconductor devices, such as discrete devices and/or integrated circuits. As shown in the figure, MOSFET 420 includes a substrate 421, source/drain regions 422, 423, source extensions/drain extensions 426, 427, and a channel region between the two and provided by the superlattice 425. The source/drain silicide layers 430, 431 and the source/drain contacts 432, 433 overlie the source/drain regions, as will be appreciated by those skilled in the art. The regions indicated by dashed lines 434, 435 are selectively remaining portions, which are initially formed together with the superlattice 425 and are later re-doped. In other embodiments, these remaining superlattice regions 434, 435 may not exist, as will be appreciated by those skilled in the art. As shown, a gate 435 includes a gate insulating layer 437 adjacent to the channel provided by the superlattice 425, and a gate electrode layer 436 on the gate insulating layer. As shown, the MOSFET 420 also provides side wall spacers 440, 441.

The aforementioned techniques allow some of the base semiconductor layers and non-semiconductor monolayers closest to the substrate to be isolated from nitrogen during nitrogen annealing by utilizing the oxygen monolayer and/or carbon in the base silicon portion, which is attracted by the oxygen from the surface. On the other hand, annealing a hydrogen terminated MST superlattice in a nitrogen environment without using carbon will result in a uniform distribution of nitrogen throughout the MST stack.

In other words, the method of the present invention utilizes carbon to block/isolate part or all of the nitrogen dose into the upper unblocked intercalated oxygen monolayer. This can advantageously increase the total nitrogen content in the upper unblocked superlattice layer. For example, it has been demonstrated that a seven-layer MST superlattice stack with 1.58E15 atoms/cm ² of carbon can generate sufficient drive to attract 0.5E15 atoms/cm ² of nitrogen during a nitrogen anneal at 900 ^° C. By adding carbon to some of the lower oxygen monolayers and/or base silicon portions, the applicants theorize (but the applicants do not wish to be bound by such theory) that nitrogen absorbed during the nitrogen anneal will be attracted to all of the oxygen in all seven monolayers/base silicon portions, but will be trapped in the upper MST layers that do not contain carbon due to the carbon blocking atoms in the lower MST layers. In the example of seven layers, if the lower four oxygen monolayers and/or base silicon portions were already doped with carbon, then the nitrogen would be trapped in the upper three oxygen monolayers and/or base silicon portions, causing those layers to receive a total dose that would otherwise be distributed throughout the seven layers.

Relative to mobility enhancement (e.g., in the channel of a MOSFET transistor), localized enhancement may be greater because the nitrogen content is higher near the surface. In silicon-on-insulator (SOI) applications, the goal may be to have a sufficient number of carbon-containing layers beneath several carbon-free layers in the MST superlattice so that the carbon-free layers become insulating due to the increased nitrogen content.

Those familiar with the art to which the present invention belongs will benefit from the contents disclosed in this specification and the attached drawings to conceive various modifications and other implementations. Therefore, it should be understood that the present invention is not limited to the specific implementation described in this specification, and the relevant modifications and implementations fall within the scope defined by the following patent application scope.

21,21’: substrate 25,25’: superlattice 45a~45n,45a’~45n’: layer group 46,46’: substrate semiconductor single layer 46a~46n,46a’~46n’: substrate semiconductor part 50,50’: band modification layer 52,52’: top cap layer 121,121’,221,221’,321: substrate 125,125’,225,225’,325,425: superlattice 146a,146a’,146b,146b’,146c,146c’,146d,146d’,146e,146e’,246a,246a’,246b,246b’,246c,246c’,246d,246d’,246e,246e,346a,346b,346c,346d,346e: base silicon part 150a,150a’,150b,150b’,150c,150c’,150d,150d’,150e,150e’,150f,150f’,250a,250a’,250b,250b’,250c,250c’,250d,250d’,250e,250e’,250f,250f’,350a,350b,350c,350d,350e,350f: oxygen monolayer 152,152’,252,252’,352: top cap layer 153,153’,253,253’,353: nitrogen 154,154',254,254',354: Nitride layer 420: Semiconductor element 421: Semiconductor substrate 422: Source region 423: Drain region 426: Source extension 427: Drain extension 430: Source silicide layer 431: Drain silicide layer 432: Source contact 433: Drain contact 434,435: Residual superlattice region 435: Gate 436: Gate electrode layer 437: Gate insulation layer 440,441: Sidewall spacer

FIG. 1 is an enlarged schematic cross-sectional view of a superlattice for a semiconductor device according to an exemplary embodiment.

FIG. 2 is a perspective schematic atomic diagram of a portion of the superlattice shown in FIG. 1 .

FIG. 3 is an enlarged schematic cross-sectional view of a superlattice according to another exemplary embodiment.

FIG. 4A is a diagram showing the energy band structures of both the conventional bulk silicon and the 4/1 silicon/oxygen superlattice shown in FIG. 1-2 calculated from the Gamma point (G).

FIG. 4B is a diagram showing the energy band structures of both the conventional bulk silicon and the 4/1 silicon/oxygen superlattice shown in FIG. 1-2 calculated from the Z point.

FIG. 4C is a diagram showing the energy band structures of the conventional bulk silicon and the 5/1/3/1 silicon/oxygen superlattice shown in FIG. 3 calculated from the G point and the Z point.

5-9 illustrate schematic cross-sectional views of superlattices having different non-semiconductor material layers in accordance with various exemplary embodiments.

FIG. 10 is a flow chart showing a method for fabricating a semiconductor device including any of the superlattices shown in FIGS. 5 to 9 according to an exemplary embodiment.

FIG. 11 is a schematic cross-sectional view of an exemplary semiconductor device that can be fabricated according to the method of FIG. 10 .

420:Semiconductor components

421: Semiconductor substrate

422: Source region

423: Drain area

426: Source extension

427: Drain extension

430: Source silicide layer

431: Drain silicide layer

432: Source contact

433: Drain contact

434,435: Residual superlattice region

435: Gate

436: Gate electrode layer

437: Gate insulation layer

440,441: Lateral wall partitions

Claims (16)

A semiconductor element, comprising: a superlattice on a semiconductor substrate, the superlattice comprising a plurality of stacked layer groups, each layer group comprising a plurality of stacked base semiconductor monolayers, which define a base semiconductor portion, and at least one non-semiconductor monolayer constrained in a lattice of an adjacent base semiconductor portion; wherein the first at least one non-semiconductor monolayer constrained in the lattice of a first pair of adjacent base semiconductor portions comprises a first non-semiconductor material, and wherein the second at least one non-semiconductor monolayer constrained in the lattice of a second pair of adjacent base semiconductor portions comprises a second non-semiconductor material different from the first non-semiconductor material; and wherein at least one base semiconductor portion comprises a carbon dopant, and at least another base semiconductor portion has no carbon dopant. A semiconductor device as claimed in claim 1, wherein the first non-semiconductor material comprises oxygen and nitrogen. A semiconductor element as claimed in claim 1, wherein the second non-semiconductor material includes at least one of carbon and oxygen. A semiconductor device as claimed in claim 1, wherein the third at least one non-semiconductor single layer constrained in the crystal lattice of the third pair of adjacent base semiconductor portions comprises a third non-semiconductor material different from the first non-semiconductor material and the second non-semiconductor material. A semiconductor device as claimed in claim 1, wherein the first non-semiconductor material comprises nitrogen, and wherein the first at least one non-semiconductor monolayer is located above the second at least one non-semiconductor monolayer in the superlattice. The semiconductor device of claim 1, wherein the at least one base semiconductor portion containing carbon doping is between the first at least one non-semiconductor single layer and the second at least one non-semiconductor single layer. A semiconductor device as claimed in claim 1, wherein the base semiconductor monolayers comprise silicon. A semiconductor device as claimed in claim 1, further comprising a source region and a drain region separated from each other and defining a channel within the superlattice, and a gate overlying the channel. A method for making a semiconductor device, the method comprising: forming a superlattice on a semiconductor substrate, the superlattice comprising a plurality of stacked layer groups, each layer group comprising a plurality of stacked base semiconductor monolayers, which define a base semiconductor portion, and at least one non-semiconductor monolayer constrained in a lattice of an adjacent base semiconductor portion; wherein the non-semiconductor monolayer constrained in a first pair of adjacent base semiconductor portions The first at least one non-semiconductor monolayer in the crystal lattice of the semiconductor portion comprises a first non-semiconductor material, and the second at least one non-semiconductor monolayer constrained in the crystal lattice of the second pair of adjacent base semiconductor portions comprises a second non-semiconductor material different from the first non-semiconductor material; and at least one base semiconductor portion comprises a carbon dopant, and at least another base semiconductor portion does not have a carbon dopant. A method as claimed in claim 9, wherein the first non-semiconductor material comprises oxygen and nitrogen. A method as claimed in claim 9, wherein the second non-semiconductor material comprises at least one of carbon and oxygen. The method of claim 9, wherein the third at least one non-semiconductor monolayer constrained within the crystal lattice of the third pair of adjacent substrate semiconductor portions comprises a third non-semiconductor material different from the first non-semiconductor material and the second non-semiconductor material. The method of claim 9, wherein the first non-semiconductor material comprises nitrogen, and wherein the first at least one non-semiconductor monolayer is located above the second at least one non-semiconductor monolayer in the superlattice. The method of claim 9, wherein the at least one base semiconductor portion comprising carbon doping is between the first at least one non-semiconductor monolayer and the second at least one non-semiconductor monolayer. A method as claimed in claim 9, wherein the base semiconductor monolayers comprise silicon. The method of claim 9 further includes forming a separate source region and a drain region defining a channel within the superlattice, and a gate overlying the channel.