TWI851225B - Semiconductor device and method of forming the same - Google Patents

Abstract

The semiconductor device includes a substrate, a stack disposed on the substrate, a first common source line and a second common source line disposed in the stack and connected to the substrate. The stack includes insulating layers and conductive layers alternately arranged. The first common source line and the second common source line are extended along a first direction and are arranged in a second direction that is perpendicular to the first direction. The first common source line includes a first segment and a second segment spaced apart by a first common source line cut. The second common source line includes a third segment and a fourth segment spaced apart by a second common source line cut. The first common source line cut is shifted relative to the second common source line cut in the first direction. A method of forming the semiconductor device is also disclosed.

Description

Semiconductor device and method for manufacturing the same

The present disclosure relates to a semiconductor device and a method for manufacturing the same.

In recent years, the structure of semiconductor devices has been constantly changing, and the storage capacity of semiconductor devices has been increasing. Memory devices are used in storage components of many products (such as digital cameras, mobile phones, and computers). As these applications increase, the demand for memory devices focuses on small size and large storage capacity. In order to meet this condition, a memory device with high component density and small size and a manufacturing method thereof are required.

Therefore, it is desirable to develop three-dimensional (3D) memory devices with a greater number of multiple stacking planes to achieve greater storage capacity and improved quality while maintaining a small size of the memory device.

An embodiment of the present disclosure provides a semiconductor device, including a substrate, a stack disposed on the substrate, a first common source line disposed in the stack and connected to the substrate, and a second common source line disposed in the stack and connected to the substrate. The stack includes a plurality of insulating layers and a plurality of conductive layers arranged alternately. The first common source line extends along a first direction, and the first common source line includes a first segment, a second segment, and a first common source line cut for separating the first segment from the second segment. The second common source line extends along the first direction, and includes a third section, a fourth section, and a second common source line cut for separating the third section from the fourth section, wherein the first common source line and the second common source line are arranged along the second direction, the second direction is orthogonal to the first direction, and the second common source line cut is offset relative to the first common source line cut in the first direction.

In some embodiments of the present disclosure, the second common source line is directly adjacent to the first common source line.

In some embodiments of the present disclosure, the semiconductor device further includes a third common source line, the third common source line includes a fifth segment, a sixth segment, and a third common source line cut for separating the fifth segment and the sixth segment, wherein the second common source line is between the third common source line and the first common source line, and the third common source line cut is offset relative to the second common source line cut in a first direction.

In some embodiments of the present disclosure, the third common source line cut is aligned in the first direction or offset relative to the first common source line cut.

In some embodiments of the present disclosure, each of the first common source line cut and the second common source line cut includes a first isolation structure located at a top portion of the stack and a second isolation structure located at a bottom portion of the stack.

In some embodiments of the present disclosure, the second width of the second isolation structure is greater than the first width of the first isolation structure, and the first width and the second width are measured along the second direction.

In some embodiments of the present disclosure, the stack includes a ground select line region, a series select line region, and a word line region between the ground select line region and the series select line region on a substrate, a first isolation structure is disposed in the series select line region, and a second isolation structure is disposed in the ground select line region.

In some embodiments of the present disclosure, the conductive layer includes a word line in the word line region, and the word line extends in the first common source line cut and the second common source line cut.

Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including forming a stack on a substrate, forming a plurality of second isolation structures at the bottom of the stack, forming a plurality of first isolation structures at the top of the stack, and forming a plurality of grooves in the stack. The stack includes a plurality of insulating layers and a plurality of sacrificial layers arranged alternately. The second isolation structure includes a first ground selection line cut and a second ground selection line cut. The first isolation structure includes a first series selection line cut on the first ground selection line cut and a second series selection line cut on the second ground selection line cut. The groove includes a first groove cut through the first ground selection line cut and the first series selection line cut, and a second groove cut through the second ground selection line cut and the second series selection line cut. The method for manufacturing a semiconductor device further includes forming a first common source line in a first groove and forming a second common source line in a second groove, wherein the first common source line and the second common source line extend along a first direction, the first common source line and the second common source line are arranged along a second direction, the second direction is orthogonal to the first direction, and the first ground selection line cutting is offset relative to the second ground selection line cutting in the first direction.

In some embodiments of the present disclosure, a portion of the sacrificial layer between the first isolation structure and the second isolation structure is retained after the groove is formed.

The common source line is cut into a plurality of sections by a common source line cut, wherein the common source line cut includes a first isolation structure and a second isolation structure. The positions of the common source line cuts including the first isolation structure and the second isolation structure are offset in adjacent common source lines. Stress generated by oxide expansion caused by heat treatment can be released by the offset common source line cuts without accumulation, thereby avoiding the common source line bending phenomenon during the heat treatment process.

The following will clearly illustrate the spirit of the present disclosure with drawings and detailed descriptions. After understanding the preferred embodiments of the present disclosure, any person with ordinary knowledge in the relevant technical field can make changes and modifications based on the techniques taught by the present disclosure without departing from the spirit and scope of the present disclosure.

Referring to FIG. 1 to FIG. 5, FIG. 1 and FIG. 5 are cross-sectional views of a semiconductor device according to some embodiments of the present disclosure, FIG. 2 is a top view along plane A-A in FIG. 1, FIG. 3 is a top view along plane B-B in FIG. 1, and FIG. 4 is a top view along plane C-C in FIG. 1. More specifically, the cross-sectional position of FIG. 1 is along line segment D-D in FIG. 2, and the cross-sectional position of FIG. 5 is along line segment E-E in FIG. 2.

The semiconductor device 100 includes a substrate 110 and a stack of a plurality of insulating layers 120 and a plurality of conductive layers 130 alternately arranged on the substrate 110. The semiconductor device 100 further includes a plurality of vertical channel structures 200 arranged parallel to the normal direction of the substrate 110, wherein the vertical channel structures 200 pass through the stack of the insulating layers 120 and the conductive layers 130 and extend into the substrate 110.

The conductive layer 130 includes one or more conductive materials, such as a filling metal such as tungsten. In some embodiments, one or more conductive layers 130 located at the top of the semiconductor device 100 are used as string select lines (SSL), one or more conductive layers 130 located at the bottom of the semiconductor device 100 are used as ground select lines (GSL), and other conductive layers 130 are used as word lines (WL) of the semiconductor device 100. Since these conductive layers 130 surround the vertical channel structure 200, the semiconductor device 100 can also be called a gate-all-around (GAA) semiconductor device.

The semiconductor device 100 further includes a common source line 300, which is used to divide the vertical channel structures 200 into a plurality of different regions according to different operation requirements. For example, in an operation block 10, as shown in FIGS. 2-4, the operation block 10 includes a plurality of sub-blocks 12, 14, 16, 18, and the sub-blocks 12, 14, 16, 18 are defined by the common source line 300.

The common source lines 300 located at the boundary of the operation block 10, such as the common source line 300a and the common source line 300e, are continuous, while the common source lines 300 located between the common source line 300a and the common source line 300e, such as the common source line 300b, the common source line 300c, and the common source line 300d, are cut into a plurality of sections 310.

Referring to FIG. 2 , at the top of the semiconductor device 100 (i.e., the SSL region), the common source line 300 b, the common source line 300 c, and the common source line 300 d are cut by the first isolation structure 320. Since the first isolation structure 320 is formed in the SSL region of the semiconductor device 100, the first isolation structure 320 can also be referred to as a serial selection line (SSL) cut. Each conductive layer 130 in the SSL region is divided into a plurality of regions corresponding to the sub-blocks 12, 14, 16, and 18 by the common source line 300 b, the common source line 300 c, the common source line 300 d, and the first isolation structure 320.

Referring to FIG. 3 , in the middle portion (i.e., the WL region) of the semiconductor device 100, the common source line 300b, the common source line 300c, and the common source line 300d are cut into a plurality of segments 310, and these segments 310 are not connected. In the conductive layer 130 in the WL region, the common source line 300b, the common source line 300c, and the common source line 300d are connected. That is, the space between the segments 310 of the common source line 300b, the common source line 300c, and the common source line 300d is filled with the conductive layer 130.

Referring to FIG. 4 , at the bottom of the semiconductor device 100 (i.e., the GSL region), the common source line 300 b, the common source line 300 c, and the common source line 300 d are cut by a plurality of second isolation structures 330. Since the second isolation structure 330 is formed in the GSL region of the semiconductor device 100, the second isolation structure 330 can also be referred to as a ground selection line (GSL) cut. Each conductive layer 130 in the GSL region is divided into a plurality of regions corresponding to the sub-blocks 12, 14, 16, and 18 by the common source line 300 b, the common source line 300 c, the common source line 300 d, and the second isolation structure 330.

5 , a pair of first isolation structures 320 and second isolation structures 330 are disposed on opposite sides of each segment 310 of the common source line 300, wherein the first isolation structure 320 is disposed in the SSL region and directly contacts the segment 310 of the common source line 300, and the second isolation structure 330 is disposed in the GSL region and directly contacts the segment 310 of the common source line 300. The stack of the insulating layer 120 and the conductive layer 130 exists between the first isolation structure 320 and the second isolation structure 330 , and in the WL region, the stack of the insulating layer 120 and the conductive layer 130 directly contacts the segment 310 of the common source line 300 .

As shown in FIG5 , the space between the sections 310 of two adjacent common source lines 300 is filled, from bottom to top, with the second isolation structure 330, the stack of the insulating layer 120 and the conductive layer 130, and the first isolation structure 320. In other words, the combination of the second isolation structure 330, the stack of the insulating layer 120 and the conductive layer 130, and the first isolation structure 320 may be collectively referred to as a common source line cut 340.

Referring to FIGS. 2 to 5 , the positions of the common source line cuts 340 on two adjacent common source lines 300 are offset to prevent the common source line 300 from bending during the heat treatment process. The common source line 300 extends along a first direction D1, and the common source line 300 is arranged along a second direction D2, wherein the second direction D2 is orthogonal to the first direction D1. The common source line cuts 340 are arranged in the common source line 300b, the common source line 300c, and the common source line 300d. The common source line cuts 340 in the common source line 300b are offset relative to the common source line cuts 340 in the common source line 300c in the first direction D1. The common source line cut 340 in the common source line 300c is offset relative to the common source line cut 340 in the common source line 300d in the first direction D1. The common source line cut 340 in the common source line 300b may be aligned with or offset relative to the common source line cut 340 in the common source line 300d in the first direction D1.

In addition, the length L or the interval P of each segment 310 in the common source line 300 may be the same or different, as long as the positions of the common source line cuts 340 in two adjacent common source lines 300 are offset from each other.

Referring back to FIG. 1 , the width W1 of each first isolation structure 320 may be equal to or slightly greater than the width W3 of each common source line 300. In some embodiments, the width W1 of each second isolation structure 330 may be greater than the width W1 of each first isolation structure 320, so that the bottoms of adjacent sections 310 in the common source line 300 can be completely cut and separated from each other, thereby preventing the occurrence of unexpected electrical short circuits. The width W1, the width W2, and the width W3 are measured in the second direction D2.

In addition, a bottom surface of the second isolation structure 330 is lower than a top surface of the substrate 110 , and a bottom surface of the common source line 300 is lower than a bottom surface of the second isolation structure 330 .

Since a lot of heat treatment processes are used in the process of manufacturing the semiconductor device 100, these heat treatment processes may cause thermal expansion of oxides, such as the oxides in the vertical channel structure 200 or the oxides in the common source line cut 340. By offsetting the common source line cut 340 in the adjacent common source line 300, the stress generated by the thermal expansion of the oxide can be released without accumulation. Therefore, the risk of bending of the common source line 300 can be reduced.

Referring to FIG. 6 to FIG. 14 , they are cross-sectional views of different manufacturing stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. As shown in FIG. 6 , a first stack consisting of an insulating layer 120 and a sacrificial layer 140 is formed on a substrate 110, and a second isolation structure 330 is formed in the first stack consisting of the insulating layer 120 and the sacrificial layer 140.

The substrate 110 includes a first polysilicon layer 111 , a first oxide layer 112 disposed on the first polysilicon layer 111 , a second polysilicon layer 113 disposed on the first oxide layer 112 , a second oxide layer 114 disposed on the second polysilicon layer 113 , and a third polysilicon layer 115 disposed on the second oxide layer 114 .

In some embodiments, the thickness of the second polysilicon layer 113 is less than the thickness of the first polysilicon layer 111 and the third polysilicon layer 115. In some embodiments, the first polysilicon layer 111, the second polysilicon layer 113 and the third polysilicon layer 115 may be doped with N-type dopants, such as phosphorus or arsenic. In some other embodiments, the first polysilicon layer 111, the second polysilicon layer 113 and the third polysilicon layer 115 may be doped with P-type dopants, such as boron or germanium.

The insulating layer 120 and the sacrificial layer 140 are alternately stacked on the substrate 110, wherein the bottom layer in the first stack is the insulating layer 120. The material of the insulating layer 120 is different from the material of the sacrificial layer 140. In some embodiments, the insulating layer 120 is an oxide layer, such as a silicon dioxide layer, and the sacrificial layer 140 is a nitride layer, such as a silicon nitride layer.

The second isolation structure 330 (i.e., GSL cut) is formed in the first stack composed of the insulating layer 120 and the sacrificial layer 140. The material of the second isolation structure 330 is also different from the material of the sacrificial layer 140. In some embodiments, the material of the second isolation structure 330 can be an oxide, such as silicon dioxide. In some embodiments, one end of each second isolation structure 330 is inserted into the third polysilicon layer 115. In some other embodiments, one end of each second isolation structure 330 can terminate at the third polysilicon layer 115.

7 , a second stack of insulating layers 120 and sacrificial layers 140 is formed on the first stack of insulating layers 120 and sacrificial layers 140, thereby forming a stack of alternating insulating layers 120 and sacrificial layers 140 on the substrate 110. The topmost layer in the stack is the insulating layer 120.

8 , a plurality of vertical channel structures 200 are formed through the stack of the insulating layer 120 and the sacrificial layer 140, and the vertical channel structures 200 extend into the substrate 110. The vertical channel structures 200 are arranged parallel to the normal direction of the substrate 110. In some embodiments, the vertical channel structures 200 stop in the first polysilicon layer 111.

In some embodiments, each vertical channel structure 200 includes a storage layer 202, a channel layer 204, and an insulating column 206. The channel layer 204 is sandwiched between the storage layer 202 and the insulating column 206. In some embodiments, the storage layer 202 is a multi-layer structure, such as an oxide-nitride-oxide (ONO) layer that can capture electrons. The material of the channel layer 204 can be a material including polysilicon, and the material of the insulating column 206 can be a dielectric material. Each vertical channel structure 200 further includes a conductive plug 208, which is disposed on the insulating column 206 and contacts the channel layer 204. In some embodiments, the top surfaces of the conductive plug 208, the storage layer 202, the channel layer 204, and the uppermost insulating layer 120 are flush. The top surface of the insulating pillar 206 is lower than the top surface of the channel layer 204, and the sidewall of the conductive plug 208 is in contact with the channel layer 204.

9, a plurality of first isolation structures 320 are formed on the upper portion of the stack of the insulating layer 120 and the sacrificial layer 140. The material of the first isolation structure 320 is different from the material of the sacrificial layer 140. In some embodiments, the material of the first isolation structure 320 may be an oxide, such as silicon dioxide. In some embodiments, one end of each first isolation structure 320 stops in one of the insulating layers 120.

10, an etching process is performed to form a plurality of grooves 150 through the stack of the insulating layer 120 and the sacrificial layer 140, and after the etching process is completed, the grooves 150 terminate at the third polysilicon layer 115. Then, another etching process is performed to deepen the grooves 150 so that the grooves 150 extend into the second polysilicon layer 113. The etching process used to form the grooves 150 is a dry etching process.

Please refer to FIG. 2 for example. The grooves 150 also extend along the first direction D1 and are arranged along the second direction D2. Part of the grooves 150, such as the grooves 150 corresponding to the common source line 300b, the common source line 300c, and the common source line 300d, will pass through the corresponding second isolation structure 330 (i.e., GSL cutting) and the first isolation structure 320 thereon (i.e., SSL cutting), and part of the sacrificial layer 140 between the first isolation structure 320 and the second isolation structure 330 will remain after the grooves 150 are formed.

Referring to FIG. 11 , a wet etching process is performed to remove the second polysilicon layer 113 (see FIG. 10 ) and thereby expose a portion of the vertical channel structure 200. Next, a series of wet etching processes using different etchants are performed to remove the first oxide layer 112, the second oxide layer 114, and the storage layer 202 including the ONO structure (see FIG. 10 ). After the wet etching process is performed, a cavity 160 is formed between the first polysilicon layer 111 and the third polysilicon layer 115. The cavity 160 is connected to the groove 150. A portion of the channel layer 204 in the vertical channel structure 200 is exposed to the cavity 160.

In some embodiments, temporary spacers are formed on the sidewalls of the stack of the insulating layer 120 and the sacrificial layer 140 to protect the insulating layer 120 and the sacrificial layer 140 from being damaged during the wet etching process for removing the storage layer 202.

12, additional polysilicon material 116 is epitaxially grown in cavity 160 (see FIG. 11) and fills cavity 160. Polysilicon material 116 may be doped with N-type dopants, such as phosphorus or arsenic, or polysilicon material 116 may be doped with P-type dopants, such as boron or germanium. The remaining third polysilicon layer 115, polysilicon material 116, and first polysilicon layer 111 may be collectively referred to as a doped polysilicon layer 118.

After the doped polysilicon layer 118 is formed, an etch-back process is performed to remove a portion of the doped polysilicon layer 118, thereby deepening the recess 150 again. Then, an oxidation process, such as a thermal oxidation process, is performed to convert the surface of the doped polysilicon layer 118 into silicon oxide, so as to form a fourth oxide layer 119 on the surface of the doped polysilicon layer 118. In some embodiments, the fourth oxide layer 119 has a U-shaped cross-section and is connected to the bottommost insulating layer 120.

Referring to FIG. 13 , a replacement process is performed to replace the sacrificial layer 140 (see FIG. 12 ) with the conductive layer 130. The replacement process includes an etching process for removing the sacrificial layer 140. Specifically, the sacrificial layer 140 is a silicon nitride layer, and the etching process is performed using an etchant having a faster etching rate for the nitride than for the oxide (such as the insulating layer 120). In this way, the insulating layer 120, which is an oxide layer, can be retained after the removal of the sacrificial layer 140. Furthermore, since the sidewalls of the doped polysilicon layer 118 are protected by the fourth oxide layer 119, the doped polysilicon layer 118 will not be damaged by this etching process.

A plurality of conductive layers 130 are formed between the insulating layers 120 and surround the vertical channel structure 200. Each conductive layer 130 includes one or more conductive materials, such as a filling metal such as tungsten.

In some embodiments, one or more conductive layers 130 at the top of the semiconductor device 100 serve as string select lines (SSL) of the semiconductor device 100, and these string select lines are traversed by the first isolation structure 320 (i.e., SSL cut). One or more conductive layers 130 at the bottom of the semiconductor device 100 serve as ground select lines (GSL) of the semiconductor device 100, and these ground select lines are traversed by the second isolation structure 330 (i.e., GSL cut). The remaining conductive layers 130 serve as word lines (WL) of the semiconductor device 100, and these word lines extend laterally between the first isolation structure 320 and the second isolation structure 330.

14, after the conductive layer 130 is fabricated, an etching process is performed to recess the conductive layer 130 so that the sidewalls of the conductive layer 130 are recessed relative to the sidewalls of the insulating layer 120. After the etching process is performed, the sidewalls of the conductive layer 130 may be flat, concave, or convex.

Additional oxide material is deposited in the groove 150 (see FIG. 13 ) and on the sidewalls of the conductive layer 130, the insulating layer 120, and the fourth oxide layer 119 (see FIG. 13 ). An etching process is then performed to remove a portion of the oxide material and remove the bottom of the fourth oxide layer 119 to open the fourth oxide layer 119 to expose the doped polysilicon layer 118 from the opened fourth oxide layer 119. The remaining oxide material may be referred to as an isolation spacer 350.

A deposition process is performed to fill the common source line 300 in the groove 150. The isolation spacer 350 is located between the second isolation structure 330 and the conductive layer 130. The bottom surface of the isolation spacer 350 is lower than the top surface of the doped polysilicon layer 118. The common source line 300 can be doped polysilicon. In other embodiments, the common source line 300 can be a conductor, such as tungsten. In other embodiments, the common source line 300 can be a combination of doped polysilicon and tungsten. The common source line 300 is deposited upward from the doped polysilicon layer 118 , wherein the doped polysilicon layer 118 serves as a common source plane of the semiconductor device 100 .

The common source line is cut into a plurality of sections by a common source line cut, wherein the common source line cut includes a first isolation structure and a second isolation structure. The positions of the common source line cuts including the first isolation structure and the second isolation structure are offset in adjacent common source lines. Stress generated by oxide expansion caused by heat treatment can be released by the offset common source line cuts without accumulation, thereby avoiding the common source line bending phenomenon during the heat treatment process.

Although the present disclosure has been disclosed as above by way of embodiments, it is not intended to limit the present disclosure. Anyone skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the definition of the attached patent application scope.

10: Operation block 12,14,16,18: Sub-block 100: Semiconductor device 110: Substrate 111: First polysilicon layer 112: First oxide layer 113: Second polysilicon layer 114: Second oxide layer 115: Third polysilicon layer 116: Polysilicon material 118: Doped polysilicon layer 119: Fourth oxide layer 120: Insulation layer 130: Conductive layer 140: Sacrificial layer 150: Recess 160: Cavity 200: Vertical channel structure 202: Storage layer 204: Channel layer 206: Insulation column 208: Conductive plug 300, 300a, 300b, 300c, 300d, 300e: Common source line 310: Segment 320: First isolation structure 330: Second isolation structure 340: Common source line cut 350: Isolation spacer A-A, B-B, C-C: Plane D-D, E-E: Line segment D1: First direction D2: Second direction L: Length P: Pitch W1, W2, W3: Width

In order to make the purpose, features, advantages and embodiments of the present disclosure more clearly understandable, the detailed description of the attached figures is as follows: FIG. 1 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. FIG. 2 is a top view along plane A-A in FIG. 1. FIG. 3 is a top view along plane B-B in FIG. 1. FIG. 4 is a top view along plane C-C in FIG. 1. FIG. 5 is a cross-sectional view along line segment E-E in FIG. 2. FIG. 6 to FIG. 14 are cross-sectional views of different manufacturing stages of the method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

100:Semiconductor devices

110: Substrate

120: Insulation layer

130: Conductive layer

200: Vertical channel structure

300: shared source line

320: First isolation structure

330: Second isolation structure

A-A, B-B, C-C: plane

D1: First direction

D2: Second direction

W1,W2,W3:Width

Claims (10)

A semiconductor device comprises: a substrate; a stack disposed on the substrate, the stack comprising a plurality of insulating layers and a plurality of conductive layers arranged alternately; a first common source line disposed in the stack and connected to the substrate, the first common source line extending along a first direction, the first common source line comprising a first section, a second section, and a first common source line cut for separating the first section from the second section; and A second common source line is disposed in the stack and connected to the substrate, the second common source line extends along the first direction, the second common source line includes a third section, a fourth section, and a second common source line cut for separating the third section from the fourth section, wherein the first common source line and the second common source line are arranged along a second direction, the second direction is orthogonal to the first direction, and the second common source line cut is offset relative to the first common source line cut in the first direction. A semiconductor device as described in claim 1, wherein the second common source line is directly adjacent to the first common source line. The semiconductor device as described in claim 1 further includes a third common source line, which includes a fifth segment, a sixth segment, and a third common source line cut for separating the fifth segment and the sixth segment, wherein the second common source line is between the third common source line and the first common source line, and the third common source line cut is offset relative to the second common source line cut in the first direction. A semiconductor device as described in claim 3, wherein the third common source line cut is aligned in the first direction or offset relative to the first common source line cut. A semiconductor device as described in claim 1, wherein each of the first common source line cut and the second common source line cut includes a first isolation structure located at the top of the stack and a second isolation structure located at the bottom of the stack. A semiconductor device as described in claim 5, wherein a second width of the second isolation structure is greater than a first width of the first isolation structure, and the first width and the second width are measured along the second direction. A semiconductor device as described in claim 5, wherein the stack includes a ground selection line region, a series selection line region, and a word line region between the ground selection line region and the series selection line region on the substrate, the first isolation structure is arranged in the series selection line region, and the second isolation structure is arranged in the ground selection line region. A semiconductor device as described in claim 7, wherein the conductive layers include a word line in the word line region, and the word line extends in the first common source line cut and the second common source line cut. A method for manufacturing a semiconductor device, comprising: forming a stack on a substrate, the stack comprising a plurality of insulating layers and a plurality of sacrificial layers arranged alternately; forming a plurality of second isolation structures at the bottom of the stack, the second isolation structures comprising a first ground selection line cut and a second ground selection line cut; forming a plurality of first isolation structures at the top of the stack, the first isolation structures comprising a first series selection line cut on the first ground selection line cut and a second series selection line cut on the second ground selection line cut; forming a plurality of grooves in the stack, the grooves comprising a first groove through the first ground selection line cut and the first series selection line cut, and a second groove through the second ground selection line cut and the second series selection line cut; and A first common source line is formed in the first groove and a second common source line is formed in the second groove, wherein the first common source line and the second common source line extend along a first direction, the first common source line and the second common source line are arranged along a second direction, the second direction is orthogonal to the first direction, and the first ground selection line cutting is offset relative to the second ground selection line cutting in the first direction. The method of claim 9, wherein portions of the sacrificial layers between the first isolation structures and the second isolation structures are retained after forming the grooves.