TWI851083B - Electronic apparatus and memory data repairing method thereof - Google Patents

Abstract

A memory data repairing method used in an electronic apparatus to repair data of a flash memory, in which the electronic apparatus includes a control circuit and the flash memory includes a memory array having storage blocks. The memory data repairing method includes steps outlined below. A data reading process is performed on stored data of the storage blocks by the control circuit. One of the storage blocks is determined to have a bit flip error and is determined to be an error block by the control circuit according to the data reading process. A memory data repair process is performed when a number of the bit flip error of the error block is larger than a predetermined error threshold value to control the flash memory writes a calibration data corresponding to the stored data generated by the data reading process to the error block.

Description

Electronic device and memory data repair method thereof

The present invention relates to flash memory repair technology, and more particularly to an electronic device having a flash memory data repair mechanism and a memory data repair method thereof.

In memory, data is stored in digital form. More specifically, data is stored as bits containing 0 and 1. However, in flash memory, due to the characteristics of its own hardware, bit flipping occurs, causing data that was originally 0 to become 1, or data that was originally 1 to become 0. The data error caused by this phenomenon is called a bit flip error.

Bit reversal errors are often corrected after the data is read out through an error checking and correcting mechanism. However, as the number of times the flash memory is used and the time increases, the number of bit reversal error data often exceeds a preset threshold value, and data correction can no longer be performed. Some technologies use the method of backing up the main block data in the flash memory in the backup block so that the data can be read from the backup block when the main block is damaged. However, such a configuration will increase the hardware cost, and the problem of too many bit reversal error data that cannot be corrected still exists.

In view of the problems of the prior art, one purpose of the present invention is to provide a memory device with a flash memory data repair mechanism and a memory data repair method thereof to improve the prior art.

The present invention includes an electronic device for repairing data of a flash memory, wherein the flash memory includes a memory array having a plurality of storage blocks. The electronic device includes a control circuit. The control circuit is configured to execute a memory data repair method for the flash memory. The memory data repair method includes: executing a data reading procedure for the storage data of the storage block; judging that one of the storage blocks corresponding to the storage data has a bit flip error and is an error block according to the data reading procedure; and performing a flash memory data repair procedure when the number of bit flip errors of the error block is greater than a preset error threshold value, so as to control the flash memory to write the correction data generated by the data reading procedure corresponding to the storage data into the error block.

The present invention also includes a memory data repair method, which is applied to an electronic device to repair data in a flash memory. The electronic device includes a control circuit, and the flash memory includes a memory array having a plurality of storage blocks. The memory data repair method includes: executing a data reading procedure on the storage data of the storage block by the control circuit; judging that one of the storage blocks corresponding to the storage data has a bit inversion error and is an error block according to the data reading procedure by the control circuit; and performing a memory data repair procedure when the number of bit inversion errors of the error block is greater than a preset error threshold value to control the flash memory to write the correction data generated by the data reading procedure corresponding to the storage data into the error block.

The features, implementation and effects of this case are described in detail below with reference to the diagrams for a preferred embodiment.

One purpose of the present invention is to provide an electronic device with a flash memory data repair mechanism and a memory data repair method thereof, which determines the existence of an error block through a data reading procedure, and then performs a memory data repair procedure when the number of error data in the error block is greater than a preset error threshold value, and writes the correction data into the error block to achieve the purpose of repairing the storage block.

Please refer to Figure 1. Figure 1 shows a block diagram of an electronic device 100 having a flash memory data repair mechanism in one embodiment of the present invention. The electronic device 100 includes: a flash memory 110, a control circuit 120, and a random access memory 180. In one embodiment, the flash memory 110, the control circuit 120, and the random access memory 180 are respectively disposed in different chips.

The flash memory 110, the control circuit 120 and the random access memory 180 can be implemented with different architectures according to actual needs, so that the control circuit 120 performs data reading, data writing and data erasing operations on the flash memory 110. For the data reading operation, due to the characteristics of the flash memory 110 itself, the stored digital data will have a bit inversion phenomenon, so that the data originally 0 becomes 1, or the data originally 1 becomes 0, and a bit inversion error is generated in the read data. Therefore, the electronic device 100 of the present invention has a flash memory data repair mechanism to achieve the purpose of not only correcting the read data but also repairing the stored data.

The following will use a sample architecture to explain the flash memory data repair mechanism of the electronic device 100.

In this embodiment, the flash memory 110 includes a memory array 130, a repair circuit 140, a cache circuit 150, and a slave circuit 160. The flash memory device 110 may be a NAND flash memory, but the present invention is not limited thereto. The control circuit 120 includes a master circuit 170.

The control circuit 120 controls the storage data SD stored in the plurality of storage blocks in the memory array 130 in the flash memory 110 to execute a data reading procedure. The data reading procedure will be described below.

In one embodiment, the storage data SD may be a part of a boot code for booting a computer system, and the boot code may be stored in the form of an image file. However, the present invention is not limited thereto.

The master circuit 170 of the control circuit 120 is configured to generate a data read instruction (not shown). The master circuit 170 may include a control logic circuit and a transmission interface (not shown), so that the control logic circuit generates a data read instruction and transmits it to the flash memory 110 through the transmission interface. The slave circuit 160 of the flash memory 110 is configured to receive and process the data read instruction. The slave circuit 160 may also include a control logic circuit and a transmission interface (not shown), so that the data read instruction is received through the transmission interface and processed by the control logic circuit, and then the storage data SD stored in the storage block is read according to the data read instruction.

Then, the flash memory 110 performs error checking on the stored data SD according to the verification mechanism, and performs error correction when the stored data SD is erroneous to generate correction data CD.

The repair circuit 140 is configured to execute a preset error checking and correction (ECC) algorithm to check whether there is a bit inversion error in the storage data SD read from the storage block, and to correct the storage data SD to generate correction data CD when the storage data SD is wrong. The cache circuit 150 is configured to receive the correction data CD for temporary storage.

Finally, the flash memory 110 transmits the calibration data CD to the control circuit 120 to complete the data reading process.

In more detail, the slave circuit 160 can retrieve the correction data CD from the cache circuit 150 and transmit it to the master circuit 170. The master circuit 170 can further store the correction data CD in the random access memory 180. In one embodiment, the random access memory 180 is, for example, but not limited to, a dynamic random access memory (DRAM).

After the data reading process is completed, the control circuit 120 determines that one of the storage blocks corresponding to the storage data SD has a bit inversion error and is an error block according to the data reading process.

In one embodiment, the control circuit 120 determines that the storage block corresponding to the storage data SD is an error block according to the error check state ES generated by the verification mechanism of the flash memory 110. The error check state ES can be generated by the repair circuit 140 while performing the error check algorithm to indicate the existence of the bit inversion error and the number of data with the bit inversion error, and then transmitted to the master circuit 170 through the slave circuit 160.

According to the error check status ES, the control circuit 120 performs a memory data repair procedure when the number of bit inversion errors in the error block is greater than a preset error threshold value, so as to control the flash memory 110 to write the correction data CD generated by the data read procedure corresponding to the storage data SD into the error block. The control circuit 120 can take the correction data CD from the random access memory 180 according to the virtual line path of Figure 1, and write it to the memory array 130 through the master circuit 170, the slave circuit 160, and the cache circuit 150.

In one embodiment, in the memory data repair process, the control circuit 120 controls the flash memory 110 to first erase the data of the error block, and then write the correction data CD into the error block. Therefore, the repaired storage block will store correct data and no longer have bit inversion errors.

The default error threshold value can be set to different values according to actual needs. In the most extreme case, the default error threshold value can be 0, that is, the flash memory data repair process is performed as long as there is a number of error data. However, in practice, due to the read and write life limit of the flash memory, the default error threshold value can be set to a value greater than 0. When the number of error data is not greater than this default error threshold value, the control circuit 120 will not perform the memory data repair process, but only correct the data by the aforementioned error check.

FIG2 shows a block diagram of an electronic device 200 in another embodiment of the present invention. Similar to the electronic device 100 in FIG1 , the electronic device 200 in FIG2 includes a flash memory 210, a control circuit 220, and a random access memory 280. However, in this embodiment, the flash memory 210 includes a memory array 230, a cache circuit 250, and a slave circuit 260. The control circuit 220 includes a master circuit 270 and a repair circuit 240.

Compared with the electronic device 100 in FIG. 1 , the electronic device 200 in FIG. 2 performs error checking on the storage data SD read from a storage block of the flash memory 210 by the repair circuit 240 in the control circuit 220 to generate the correction data CD and the error checking state ES. The rest of the operation of the electronic device 200 is the same or similar to the operation of the electronic device 100 and will not be described in detail here.

However, when performing the memory data repair process, due to environmental or electronic device 100 factors, it may be impossible to repair successfully. The following will explain the processing performed by the electronic device 100 in different situations.

In terms of environmental factors, the electronic device 100 may encounter occasional power outages during operation. In order to prevent the data repair of the flash memory from being affected by the power outage, the flash memory data repair process can be performed through a backup mechanism.

The following will explain the backup mechanism in the memory data repair process. It should be noted that the following operations are described based on the actions performed by the flash memory 110, but in fact, the slave circuit 160 in the flash memory 110 can control the components inside the flash memory 110 to complete it.

Please refer to FIG3A and FIG3B. FIG3A and FIG3B are schematic diagrams showing a memory array 130 in an embodiment of the present invention. As shown in FIG3, the memory array 130 includes storage blocks _ST1 - _STN and backup blocks _BA1 - _BA3 .

As shown in FIG3A , the storage data SD is stored in the storage block ST ₁ and has a bit inversion error, so the storage block ST ₁ is an error block. Before writing the correction data CD into the error block, the flash memory 110 first writes the correction data CD into one of the backup blocks BA ₁ to BA ₃ of the memory array 130, such as but not limited to the backup block BA ₁ for backup. After the backup is completed, the flash memory 110 records the error block as a repair block in the block status table TAB stored in the memory array 130.

The block status table TAB is configured to record the status of the storage blocks ST ₁ to ST _N. In one embodiment, the status of the storage blocks ST ₁ to ST _N includes, for example but not limited to, a good block that can still be read and written normally, a damaged block that cannot be read and written, and a repair block that is being repaired. In practice, the block status table TAB can be stored in a good block of the storage blocks ST ₁ to ST _N.

As shown in FIG3B , the flash memory 110 writes the calibration data CD backup block BA ₁ into the erased error block. After the calibration data CD is written, the memory 110 records the error block (storage block ST ₁ ) as a good block in the block status table TAB.

In the above process, when the flash memory 110 is powered off before the backup is completed and then the power is restored, the correction data CD is rewritten into the backup block BA ₁ for backup. When the flash memory 110 is powered off after the backup is completed and before the correction data is written into the error block and then the power is restored, the correction data CD is directly written from the backup block BA ₁ into the error block.

As for the factors of the electronic device 100 itself, since the flash memory 110 has a limited read and write life, the storage block in the memory array 130 will be damaged when the number of read and write times reaches the upper limit and can no longer be read and written, becoming a damaged block. In this case, the electronic device 100 cannot repair the damaged block, and the data in the damaged block needs to be moved.

The following will explain the mechanism of data migration. It should be noted that the following operations are described based on the actions performed by the flash memory 110, but in reality, the slave circuit 160 in the flash memory 110 can control the components inside the flash memory 110 to complete the operation.

Please refer to FIG. 4A to FIG. 4D. FIG. 4A to FIG. 4D respectively show schematic diagrams of the memory array 130 during data migration in an embodiment of the present invention. Similar to FIG. 3A and FIG. 3B, the memory array 130 of FIG. 4A to FIG. 4D includes storage blocks ST ₁ to ST _N and backup blocks BA ₁ to BA ₃ .

The storage blocks ST ₁ to ST _N that have data stored in them are indicated by dotted blocks, and the blocks that do not have data stored in them are indicated by blank blocks. The backup blocks BA ₁ to BA ₃ that have data stored in them that have been backed up and not yet written back to the storage blocks ST ₁ to ST _N are indicated by slashed blocks, and the blocks that have data stored in them that have been backed up and written back to the storage blocks ST ₁ to ST _N and the blocks that do not have data stored in them are indicated by blank blocks.

As shown in FIG. 4A , data SD ₁ -SD ₄ are stored in storage blocks ST ₁ -ST ₄ , and no data is stored in storage blocks after storage block ST ₅ .

In this embodiment, the storage block ST ₁ is an error block with a bit flip error. The flash memory 110 writes the correction data CD ₁ corresponding to the error block into one of the backup blocks BA ₁ to BA ₃ for backup. In this embodiment, the correction data CD ₁ is written into the backup block BA ₁ for backup.

The flash memory 110 marks the Mth storage block as a block to be repaired, and the block to be repaired is initially an error block (storage block ST ₁ , so M is 1).

When the number of failures of writing the correction data CD ₁ into the block to be repaired by the flash memory 110 is greater than a preset threshold value, for example but not limited to 3 times, the Mth storage block is recorded as a damaged block in the block status table TAB. In FIG. 4A , the block status table TAB is not shown, and only the storage block ST ₁ is marked as "damaged".

The flash memory 110 will perform the migration process. First, the flash memory 110 increments M by 1 (M is 2 at this time) to mark the Mth storage block as a block to be repaired. Therefore, the storage block ST ₂ is marked as a block to be repaired. In one embodiment, the storage block ST ₂ is adjacent to the storage block ST ₁ .

The flash memory 110 determines whether the block to be repaired stores existing data. When the block to be repaired (storage block ST ₂ ) stores existing data SD ₂ , the flash memory 110 writes the existing data SD ₂ into one of the backup blocks BA ₁ to BA ₃ of the flash memory 110 for backup. In one embodiment, the backup blocks BA ₁ to BA ₃ are ring buffers for sequential data writing. Therefore, the existing data SD ₂ is written into the backup block BA ₂ for backup.

As shown in FIG4B , the flash memory 110 writes the correction data CD ₁ into the block to be repaired (storage block ST ₂ ). The flash memory 110 further marks the existing data SD ₂ as the correction data CD ₂ to re-execute the migration process.

The flash memory 110 increments M by 1 (M is 3 at this time) to mark the Mth storage block as a block to be repaired. Therefore, the storage block ST ₃ is marked as a block to be repaired. In one embodiment, the storage block ST ₃ is adjacent to the storage block ST ₂ .

The flash memory 110 determines whether the block to be repaired stores existing data. When the block to be repaired (storage block ST ₃ ) stores existing data SD ₃ , the flash memory 110 writes the existing data SD ₃ into the backup block BA ₃ of the flash memory 110 for backup.

As shown in FIG4C , the flash memory 110 writes the correction data CD ₂ (existing data SD ₂ ) into the block to be repaired (storage block ST ₃ ). The flash memory 110 further marks the existing data SD ₃ as the correction data CD ₃ to re-execute the migration process.

The flash memory 110 increases M by 1 (M is 4 at this time) to mark the Mth storage block as a block to be repaired. Therefore, the storage block ST ₄ is marked as a block to be repaired.

The flash memory 110 determines whether the block to be repaired stores existing data. When the block to be repaired (storage block ST ₄ ) stores existing data SD ₄ , the flash memory 110 writes the existing data SD ₄ into the backup block BA ₁ of the flash memory 110 for backup.

As shown in FIG4D , the flash memory 110 writes the correction data CD ₃ (existing data SD ₃ ) into the block to be repaired (storage block ST ₄ ). The flash memory 110 further marks the existing data SD ₄ as the correction data CD ₄ to re-execute the migration process.

The flash memory 110 increases M by 1 (M is 5 at this time) to mark the Mth storage block as a block to be repaired. Therefore, the storage block ST ₅ is marked as a block to be repaired.

The flash memory 110 determines whether the block to be repaired stores existing data. If the block to be repaired (storage block ST ₅ ) does not store existing data, the flash memory 110 writes the correction data CD ₄ (existing data SD ₄ ) into the block to be repaired. At this time, the flash memory 110 has completed the migration process.

By means of the above mechanism, when the corresponding part of the storage block of the data stored in the flash memory 110 (e.g., the boot code stored in the form of an image file) is damaged and cannot be repaired, the data can be moved to achieve the effect of repair until the entire data is completely moved to a good storage block. Moreover, this method does not need to directly back up the entire data, but saves the number of backup blocks by moving the data one by one. For the embodiment of Figures 4A to 4D, the data that originally occupies four storage blocks only needs three backup blocks to complete the move.

Please refer to Figure 5. Figure 5 shows a flow chart of a memory data repair method 500 in an embodiment of the present invention.

In addition to the aforementioned devices, the present invention further discloses a memory data repair method 500, which is applied to, for example, but not limited to, the electronic device 100 of FIG. 1. An implementation example of the memory data repair method 500 is shown in FIG. 5, and includes the following steps.

In step S510: the control circuit 120 executes a data reading procedure on the storage data SD stored in the plurality of storage blocks included in the memory array 130 in the flash memory 110.

In step S520: the control circuit 120 determines according to the data reading procedure that one of the storage blocks corresponding to the storage data SD has a bit inversion error and is an error block.

In step S530: the control circuit 120 performs a memory data repair procedure when the number of bit inversion errors is greater than a preset error threshold value, so as to control the flash memory to write the correction data CD generated by the data reading procedure corresponding to the storage data SD into the error block.

Please refer to Figure 6. Figure 6 shows a flow chart of a flash memory data repair procedure 600 in one embodiment of the present invention. One embodiment of the flash memory data repair procedure 600 is shown in Figure 6, and includes the following steps.

In step S610: the control circuit 120 erases the data in the error block.

In step S620: the control circuit 120 writes the calibration data into the backup block for backup.

In step S630: the control circuit 120 marks the Mth storage block as a block to be repaired, and the block to be repaired is initially an error block.

In step S640: the control circuit 120 writes the correction data into the block to be repaired.

In step S650: the control circuit 120 determines whether the write fails.

In step S660: when writing fails, the control circuit 120 determines whether the number of failures is greater than the preset threshold value. If the number of failures is not greater than the preset threshold value, the process returns to step S640 to write again.

In step S670: If the number of failures is greater than the preset threshold value, the control circuit 120 performs the migration process.

In step S680: When the control circuit 120 determines that the write is successful in step S650, the process ends.

Please refer to Figure 7. Figure 7 shows a flow chart of a migration process 700 in an embodiment of the present invention. One embodiment of the migration process 700 is shown in Figure 7 and includes the following steps.

In step S710, the flash memory 110 increases the value of M by 1 to mark the Mth storage block as a block to be repaired.

In step S720, determine whether the block to be repaired stores existing data.

In step S730, when the block to be repaired stores existing data, the existing data is written into one of the backup blocks for backup.

In step S740, the correction data is written into the block to be repaired.

In step S750, the existing data is marked as calibration data to re-execute the migration process. Therefore, the process will return to step S710.

In step S760, when the block to be repaired does not store existing data, the correction data is written into the block to be repaired.

It should be noted that the above implementation is only an example. In other implementations, those skilled in the art can make changes without violating the spirit of the present invention. It should be understood that the steps mentioned in the above implementation, except for those whose sequence is specifically described, can be adjusted in sequence according to actual needs, and can even be executed simultaneously or partially simultaneously.

Although the embodiments of the present invention are described above, these embodiments are not intended to limit the present invention. Those with ordinary knowledge in the technical field may make changes to the technical features of the present invention based on the explicit or implicit content of the present invention. All these changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be subject to the scope of the patent application defined in this specification.

100, 200: Electronic devices

110, 210: Flash memory

120, 220: Control circuit

130, 230: memory array

140, 240: Repair circuits

150, 250: Cache circuit

160, 260: Slave end circuit

170, 270: Main end circuit

180, 280: Random Access Memory

500: Memory data repair method

S510~S530: Steps

600: Memory data repair process

S610~S680: Steps

700: Migration procedures

S710~S760: Steps

BA ₁ ~BA ₃ : Backup area

CD, CD ₁ ~ CD ₄ : Calibration data

ES: Error verification status

SD: Save data

SD ₁ ~SD ₄ : Data

ST ₁ ~ST _N : Storage block

TAB: Block status table

[Figure 1] shows a block diagram of an electronic device having a flash memory data repair mechanism in one embodiment of the present invention; [Figure 2] shows a block diagram of an electronic device in another embodiment of the present invention; [Figure 3A] and [Figure 3B] show schematic diagrams of a flash memory array in one embodiment of the present invention; [Figure 4A] to [Figure 4D] show schematic diagrams of a flash memory array during data migration in one embodiment of the present invention; [Figure 5] shows a flow chart of a memory data repair method in one embodiment of the present invention; [Figure 6] shows a flow chart of a flash memory data repair procedure in one embodiment of the present invention; and [Figure 7] shows a flow chart of a migration procedure in one embodiment of the present invention.

500: Memory data repair method

S510~S530: Steps

Claims (11)

An electronic device is used to repair data of a flash memory, wherein the flash memory includes a memory array having a plurality of storage blocks. The electronic device includes: a control circuit configured to execute a memory data repair method on the flash memory, wherein the memory data repair method includes: A data reading procedure is performed on a storage block of a storage data; according to the data reading procedure, it is determined that one of the storage blocks corresponding to the storage data has a bit inversion error and is an error block; and when the number of the bit inversion errors of the error block is greater than a preset error threshold value, a A memory data repair program is used to control the flash memory to write a correction data generated by the data reading program corresponding to the stored data into the error block, wherein the memory data repair program includes: writing the correction data into one of the plurality of backup blocks of the memory array for backup; after the backup is completed, recording the error block as a block to be repaired in a block status table stored in the memory array; writing the correction data from the backup blocks into the error block; and after the correction data is written into the error block, recording the block to be repaired as a good block in the block status table. The electronic device as described in claim 1, wherein the data reading procedure further comprises: reading the storage data from the flash memory; performing an error check on the storage data by the flash memory according to a verification mechanism, and performing an error correction to generate the correction data when the storage data is erroneous; and transmitting the correction data to the control circuit by the flash memory; wherein the control circuit determines that one of the storage blocks corresponding to the storage data is the error block according to an error verification state generated by the verification mechanism. The electronic device as described in claim 1, wherein the data reading procedure further comprises: reading the storage data from the flash memory; transmitting the storage data from the flash memory to the control circuit; and the control circuit performing an error check on the storage data according to a verification mechanism, and performing an error correction to generate the correction data when the storage data is erroneous; wherein the control circuit determines that one of the storage blocks corresponding to the storage data is the erroneous block according to an error verification state generated by the verification mechanism. The electronic device as described in claim 1, wherein the memory data repair procedure further comprises: when the flash memory experiences a power outage before the backup is completed and the power is restored, rewriting the correction data into one of the backup blocks of the flash memory; and when the flash memory experiences a power outage after the backup is completed and before the correction data is written into the error block and the power is restored, writing the correction data from the backup blocks into the error block. The electronic device as described in claim 1, wherein the memory data repair procedure further comprises: when the number of failures of writing the correction data into the error block is greater than a preset threshold value, the error block is recorded as a damaged block in the block status table, wherein the error block is the Mth storage block in the block status table; and a migration procedure is performed in the flash memory, which comprises: increasing the value of M by 1 to mark the Mth storage block The block is the block to be repaired; determining whether the block to be repaired stores an existing data; when the block to be repaired stores the existing data, writing the existing data into one of the backup blocks for backup; writing the correction data into the block to be repaired; marking the existing data as the correction data to re-execute the migration procedure; and when the block to be repaired does not store the existing data, writing the correction data into the block to be repaired. The electronic device as described in claim 1, wherein the memory data repair procedure further comprises: when the number of failures of writing the correction data into the error block is greater than a preset threshold value, writing the correction data into a first adjacent block adjacent to the error block, and moving an existing data stored in the first adjacent block to a second adjacent block adjacent to the first adjacent block. A memory data repair method is applied in an electronic device to repair data of a flash memory. The electronic device includes a control circuit. The flash memory includes a memory array having a plurality of storage blocks. The memory data repair method includes: the control circuit executes a storage data of the storage blocks a data reading procedure; the control circuit determines according to the data reading procedure that one of the storage blocks corresponding to the storage data has a bit inversion error and is an error block; and when the number of the bit inversion errors of the error block is greater than a preset error threshold value, a memory data repair procedure is performed to control The flash memory is controlled to write a correction data generated by the data reading process corresponding to the stored data into the error block, wherein the memory data repair process includes: the control circuit writes the correction data into one of the plurality of backup blocks of the memory array for backup; after the backup is completed, the control circuit A block status table stored in the memory array records the error block as a block to be repaired; the control circuit writes the correction data from the backup blocks into the error block; and after the correction data is written into the error block, the control circuit records the block to be repaired as a good block in the block status table. The memory data repair method as described in claim 7, wherein the data reading procedure further comprises: reading the storage data from the flash memory; performing an error check on the storage data by the flash memory according to a verification mechanism, and performing an error correction to generate the correction data when the storage data is erroneous; and transmitting the correction data to the control circuit by the flash memory; wherein the control circuit determines that one of the storage blocks corresponding to the storage data is the error block according to an error verification state generated by the verification mechanism. The memory data repair method as described in claim 7, wherein the data reading procedure further comprises: reading the storage data from the flash memory; transmitting the storage data to the control circuit from the flash memory; and performing an error check on the storage data by the control circuit according to a verification mechanism, and performing an error correction to generate the correction data when the storage data is erroneous; wherein the control circuit determines that one of the storage blocks corresponding to the storage data is the erroneous block according to an error verification state generated by the verification mechanism. The memory data repair method as described in claim 7, wherein the flash memory data repair procedure further comprises: when the flash memory experiences a power outage before the backup is completed and the power supply is restored, the control circuit rewrites the correction data into one of the backup blocks of the flash memory; and when the flash memory experiences a power outage after the backup is completed and before the correction data is written into the error block and the power supply is restored, the control circuit writes the correction data from the backup blocks into the error block. The memory data repair method as described in claim 7 further comprises: when the number of failures of writing the correction data into the error block is greater than a preset threshold value, recording the error block as a damaged block in the block status table, wherein the error block is the Mth of the storage blocks in the block status table; and performing a migration procedure in the flash memory, which comprises: increasing the value of M by 1 to mark the M+1th of the storage blocks for the block to be repaired; determining whether the block to be repaired stores an existing data; when the block to be repaired stores the existing data, writing the existing data into one of the backup blocks for backup; writing the correction data into the block to be repaired; marking the existing data as the correction data to re-execute the migration procedure; and when the block to be repaired does not store the existing data, writing the correction data into the block to be repaired.

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