TWI850679B - Electronic device and manufacturing method thereof - Google Patents

Abstract

An electronic device comprising a protective layer, an electronic unit and at least one anchor structure disposed in the protective layer, and a connecting member disposed on the protective layer. The electronic unit includes a first electronic unit and a second electronic unit electrically connected by the connecting member. The at least one anchor structure is located between the first electronic unit and the second electronic unit. The connecting member has a first conductive layer, wherein the first conductive layer contacts a surface of the first electronic unit, a surface of the anchor structure and a surface of the protective layer.

Description

Electronic device and method of manufacturing the same

The present invention relates to an electronic device and a manufacturing method thereof, and in particular to an electronic device including an electronic unit and a connector for electrically connecting the electronic unit and a manufacturing method thereof.

In order to protect the electronic unit, a packaging process is usually performed after the electronic unit is formed on the substrate to form an electronic device with a packaging structure. For example, the packaging structure can isolate the electronic unit from the influence of temperature and humidity in the environment, and can prevent the physical or mechanical damage to the electronic unit caused by external impact.

With the development of the semiconductor industry, the size of electronic devices continues to shrink and the number of electronic units installed in each unit area of electronic devices continues to increase. As the size of electronic devices decreases and the number of electronic units increases, the accuracy requirements for the alignment of electronic units in the manufacturing process of electronic devices become higher. The positional deviation of electronic units in each stage of the manufacturing process of electronic devices will result in the inability to form a good electrical connection between adjacent electronic units. Currently known technology is to improve the accuracy of electronic unit alignment by improving the alignment process when the electronic unit is bonded to the substrate. However, improving the alignment process when the electronic unit is bonded to the substrate cannot prevent the electronic unit that has been bonded to the substrate from being offset during the subsequent process of forming the packaging glue.

In view of the above problems, the present disclosure provides an electronic device and a manufacturing method thereof, wherein the electronic device has a limiting structure that can prevent the position of the electronic unit therein from shifting during the formation of a protective layer.

According to an embodiment of the present disclosure, an electronic device is provided, comprising a protective layer, an electronic unit and at least one limiting structure disposed in the protective layer, and a connector disposed on the protective layer. The electronic unit comprises a first electronic unit and a second electronic unit electrically connected via the connector. The at least one limiting structure is located between the first electronic unit and the second electronic unit. The connector has a first conductive layer, the first conductive layer contacts the surface of the first electronic unit, the surface of the limiting structure, and the surface of the protective layer.

According to an embodiment of the present disclosure, an electronic device is provided, including a protective layer; an electronic unit disposed in the protective layer, a first limiting structure, a second limiting structure and a connecting portion; and a connecting member disposed on the protective layer. The electronic unit includes a first electronic unit and a second electronic unit electrically connected through the connecting member. The first limiting structure and the second limiting structure are located between the first electronic unit and the second electronic unit, and the connecting portion connects the first limiting structure and the second limiting structure, and is combined with the first limiting structure and the second limiting structure to form a recessed portion having an inclined side wall or a curved side wall.

According to an embodiment of the present disclosure, a method for manufacturing an electronic device is provided, which includes: providing a substrate; providing a first electronic unit and a second electronic unit on the substrate; providing at least one limiting structure between the first electronic unit and the second electronic unit; providing a protective layer surrounding the at least one limiting structure, the first electronic unit, and the second electronic unit; and providing a connector that electrically connects the first electronic unit and the second electronic unit.

According to an embodiment of the present disclosure, a method for manufacturing an electronic device is provided, which includes: providing a substrate; providing at least one limiting structure on the substrate; providing a first electronic unit and a second electronic unit on the substrate, wherein the at least one limiting structure is between the first electronic unit and the second electronic unit; providing a protective layer surrounding the at least one limiting structure, the first electronic unit, and the second electronic unit; and providing a connector that electrically connects the first electronic unit and the second electronic unit.

The following disclosure provides many different embodiments or examples for implementing different features of the present invention. The following disclosure describes specific examples of various components and their arrangement to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the present disclosure describes a first feature component formed on or above a second feature component, it means that it may include an embodiment in which the first feature component and the second feature component are in direct contact, and it may also include an embodiment in which an additional feature component is formed between the first feature component and the second feature component, so that the first feature component and the second feature component may not be in direct contact.

Certain terms are used throughout the specification and claims to refer to specific components. Those skilled in the art will appreciate that the same component may be referred to by different names, and this document does not intend to distinguish between components that have the same function but different names. In the following specification and claims, the words "including" and "comprising" are open-ended terms and should be interpreted as "including but not limited to..."

The use of ordinal numbers such as "first", "second", etc. in the specification and claims to modify the claimed elements does not imply or represent any previous ordinal number of the claimed elements, nor does it represent the order of one claimed element to another claimed element, or the order of the manufacturing method. The use of ordinal numbers is only used to make a claimed element with a certain name clearly distinguishable from another claimed element with the same name. Therefore, the first element mentioned in the specification may be called the second element in the claims.

The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the accompanying drawings. Therefore, the directional terms used are used to illustrate and not to limit the present disclosure. It must be understood that the components specifically described or illustrated can exist in various forms known to those skilled in the art.

Some embodiments of the present disclosure are described below. Additional operations may be provided before, between, and/or after the steps described in these embodiments. Some of the steps described may be replaced or omitted in different embodiments. In addition, although some embodiments of the present disclosure are described below with several steps in a specific order, these steps may also be performed in other reasonable orders.

Furthermore, when an element or a film layer is referred to as being "on" or "connected to" another element or film layer, it may be directly on or directly connected to the other element or film layer, or there may be an intervening element or film layer between the two (indirect situation). Conversely, when an element is referred to as being "directly" "on" or "directly connected to" another element or film layer, there may not be an intervening element or film layer between the two. When referring to an element "coupled" to another element in the text, it may include the situation that "there may be other elements between the element and the other element to electrically connect the two", or it may include the situation that "there is no other element between the element and the other element to be directly electrically connected". When it is mentioned herein that one element is “directly coupled” to another element, it means that “the element is directly electrically connected to the other element without any other element existing between the element and the other element”.

Hereinafter, the terms "about" and "substantially" generally mean within 10%, within 5%, within 3%, within 2%, within 1%, or within 0.5% of a given value or range. The quantities given here are approximate quantities, that is, in the absence of specific description of "about" and "substantially", the meaning of "about" and "substantially" can still be implied. The term "range between a first value and a second value" means that the range includes the first value, the second value, and other values therebetween.

Furthermore, it should be understood that according to the embodiments of the present disclosure, a scanning electron microscope (SEM), an optical microscope (OM), a film thickness profiler (α-step), an elliptical thickness gauge, or other suitable methods may be used to measure the width, thickness or height of each element, and the spacing or distance between elements. Specifically, according to some embodiments, a scanning electron microscope may be used to obtain a cross-sectional structural image including the element to be measured, and the width, thickness, height or angle of each element, and the spacing or distance between elements may be measured.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the present disclosure embodiments.

The electronic device disclosed herein may include a display device, an antenna device, a sensing device, a touch display, a packaging device, a curved display, or a non-rectangular electronic device (free shape display), but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The antenna device may be, for example, a liquid crystal antenna, but is not limited thereto. The antenna device may, for example, include an antenna splicing device, but is not limited thereto. The packaging device may be a packaging device suitable for wafer-level package (WLP) technology or panel-level package (WLP) technology, such as a chip first process or a chip later process (RDL first) process, but is not limited thereto. It should be noted that the electronic device may be any combination of the aforementioned arrangements, but is not limited thereto. In addition, the shape of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device may include electronic components. The electronic components may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light-emitting diode or a photodiode. The light-emitting diode may, for example, include an organic light emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro LED, or a quantum dot light-emitting diode (quantum dot LED), but is not limited thereto. The electronic device may have peripheral systems such as a drive system, a control system, a light source system, a shelf system, etc. to support a display device, an antenna device, or a splicing device. The present disclosure will be described below using a packaging device, but the present disclosure is not limited thereto.

FIG. 1 is a schematic cross-sectional view of an electronic device 1 according to an embodiment of the present disclosure. As shown in FIG. 1, the electronic device 1 includes a protective layer 11, an electronic unit 13, a limiting structure 17, and a connector 15. The electronic unit 13 includes a first electronic unit 131 and a second electronic unit 133. The first electronic unit 131 has a first side 131S1, and the second electronic unit 133 has a first side 133S1. The first side 131S1 of the first electronic unit 131 is opposite to the first side 133S1 of the second electronic unit 133. The limiting structure 17 is located between the first electronic unit 131 and the second electronic unit 133. The first electronic unit 131, the second electronic unit 133 and the limiting structure 17 are arranged in the protective layer 11 and the connector 15 is arranged on the protective layer 11. The first electronic unit 131 and the second electronic unit 133 are electrically connected through the connector 15. In some embodiments, the electronic device 1 may further include a connection pad 19 arranged on the connector 15. The connection pad 19 can connect the electronic device 1 to other electronic components or external circuits. In some embodiments, the protective layer 11 can be any material that can be used as a packaging material. In some embodiments, the protective layer 11 can be epoxy resin. The surface of the first electronic unit 131, the surface of the second electronic unit 133, the surface of the limiting structure 17 and the surface of the protective layer 11 can be coplanar. The above configuration can reduce the risk of interface cracking, thereby improving the reliability of the electronic device. The protective layer 11 is in direct contact with at least part of the side of the first electronic unit 131 and at least part of the side of the second electronic unit 133. By directly contacting at least part of the side of the first electronic unit 131 and at least part of the side of the second electronic unit 133, the protective layer 11 can reduce the impact of moisture and oxygen in the environment on the first electronic unit 131 and the second electronic unit 133, thereby improving the service life and reliability of the first electronic unit 131 and the second electronic unit 133, but is not limited to this.

FIG. 2 is a schematic cross-sectional view of a first electronic unit 131 according to an embodiment of the present disclosure. The structure of the first electronic unit 131 is described below in conjunction with FIG. 1 and FIG. 2. As shown in FIG. 2, the first electronic unit 131 includes a chip unit 1311, a first insulating layer 1315, and a second insulating layer 1317, wherein the chip unit 1311 includes a plurality of bonding pads 1313. The second insulating layer 1317 is disposed on the chip unit 1311, the first insulating layer 1315 is disposed between the chip unit 1311 and the second insulating layer 1317, and the first insulating layer 1315 and the second insulating layer 1317 expose the bonding pads 1313. According to some embodiments, a passivation layer may be included between the chip unit 1311 and the first insulating layer 1315, the material of the passivation layer may be different from that of the first insulating layer 1315, and the thickness of the passivation layer may be less than that of the first insulating layer 1315. The second insulating layer 1317 may have the same or different thickness as the first insulating layer 1315. In some embodiments, the thickness of the second insulating layer 1317 may be greater than that of the first insulating layer 1315, as shown in FIG. 2, but the present disclosure is not limited thereto. The first insulating layer 1315 and the second insulating layer 1317 may include the same or different materials. In some embodiments, the first insulating layer 1315 and the second insulating layer 1317 may independently include a material having a Young's modulus between 1000 MPa and 20000 MPa. In some embodiments, the first insulating layer 1315 and the second insulating layer 1317 may respectively include a material having a linear thermal expansion coefficient (CTE) between 3 and 60 ppm/K. The material included in the first insulating layer 1315 and the second insulating layer 1317 may be an organic insulating material, an inorganic insulating material, or a combination thereof. Examples of materials included in the first insulating layer 1315 and the second insulating layer 1317 may independently include a polymer-based dielectric film, an organic polymer film, an ajinomoto build-film (ABF), and any combination thereof, but the present disclosure is not limited thereto. In some embodiments, the first insulating layer 1315 and the second insulating layer 1317 may independently include epoxy resin, benzocyclobutene (BCB), polyimide (PI), polybenzoxazole (PBO), silicon oxide ( _SiOx ), silicon nitride ( _SiNx ), silicon oxynitride ( _SiOxNy ), photosensitive polyimide ( _PSPI ), and any combination thereof. The second electronic unit 133 has a similar structure to the first electronic unit 131. That is, similar to the first electronic unit 131, the second electronic unit 133 also includes a chip unit, a first insulating layer, and a second insulating layer, and the chip unit includes a plurality of bonding pads. The materials, structures, and configurations of the chip unit, the first insulating layer, and the second insulating layer in the second electronic unit 133 are similar to the materials, structures, and configurations described above with reference to the first electronic unit 131, so they are not repeated here. In some embodiments, the chip units in the first electronic unit 131 and the second electronic unit 133 may have the same or different functions.

The connector 15 is disposed on the protective layer 11, the first electronic unit 131, the second electronic unit 133, and the limiting structure 17, and the second insulating layer 1317 is disposed between the first insulating layer 1315 and the connector 15. The connector 15 electrically connects the first electronic unit 131 and the second electronic unit 133 through the bonding pad 1313 of the first electronic unit 131 and the bonding pad of the second electronic unit 133. In some embodiments, the connector 15 may include a first conductive layer 151 and an insulating layer 153. In some embodiments, the insulating layer in the connector 15 may include any insulating material different from the protective layer 11. In some embodiments, the first conductive layer 151 may include a metal conductive material (e.g., aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), platinum (Pt), iridium (Ir), nickel (Ni), chromium (Cr), silver (Ag), gold (Au), tungsten (W), or an alloy thereof), a metal compound conductive material (e.g., aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), platinum (Pt), iridium (Ir), nickel (Ni), Chromium (Cr), silver (Ag), gold (Au), tungsten (W), magnesium (Mg), or compounds, alloys or any combination thereof, but the present disclosure is not limited thereto. In some embodiments, the first conductive layer 151 may include copper and titanium-copper alloy (TiCu). In some embodiments, the connector 15 may be, for example, a redistribution layer, wherein the connector 15 may include a thin film transistor, a capacitor, a diode or other suitable active or passive components, but is not limited thereto.

In some embodiments, the electronic device 1 may further include a connection pad 19. The connection pad 19 may be disposed above the first conductive layer 151 of the connector 15 and electrically connected to the first conductive layer 151 to electrically connect the first electronic unit 131 and the second electronic unit 133 to other electronic components or external circuits. In some embodiments, the connection pad 19 may include a metal conductive material (e.g., aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), platinum (Pt), iridium (Ir), nickel (Ni), chromium (Cr), silver (Ag), gold (Au), tungsten (W), or an alloy thereof), a metal compound conductive material (e.g., a compound including aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), platinum (Pt), iridium (Ir), nickel (Ni), chromium (Cr), silver (Ag), gold (Au), tungsten (W), magnesium (Mg), or an alloy thereof, an alloy thereof, or any combination thereof, but the present disclosure is not limited thereto. In some embodiments, the connection pad 19 may include the same conductive material as the first conductive layer 151, but the present disclosure is not limited thereto.

The limiting structure 17 may include a first limiting structure 171 disposed between the first electronic unit 131 and the second electronic unit 133. In some embodiments, the limiting structure 17 further includes a second limiting structure 172 disposed between the first electronic unit 131 and the second electronic unit 133 and an opening 175 between the first limiting structure 171 and the second limiting structure 172. The opening 175 exposes the surface of the protective layer 11 and separates the first limiting structure 171 and the second limiting structure 172 in space, as shown in FIG. 1, but the present disclosure is not limited thereto. In the embodiment where the limiting structure 17 has the opening 175, the first conductive layer 151 may contact the surface of the protective layer 11 in the opening 175. For example, in the embodiment shown in FIG. 1 , the first conductive layer 151 may contact at least part of the surface of the first electronic unit 131, at least part of the surface of the second electronic unit 133, at least part of the surface of the limiting structure 17, and at least part of the surface of the protective layer 11. In some embodiments, the limiting structure 17 may include a connecting portion 176 connecting the first limiting structure 171 and the second limiting structure 172 (as shown in FIG. 3B and FIG. 6 ). In the embodiment in which the limiting structure 17 has the connecting portion 176, the first conductive layer 151 may contact at least part of the surface of the first electronic unit 131, at least part of the surface of the second electronic unit 133, at least part of the surface of the limiting structure 17, but not the surface of the protective layer 11, as shown in FIG. 6 . In some embodiments, the limiting structure 17 may include a material having a Young's modulus between 1000 MPa and 20000 MPa. In some embodiments, the limiting structure 17 may include a material having a linear thermal expansion coefficient (CTE) between 3 and 60 ppm/K. In other embodiments, the limiting structure 17 may include a material having a linear thermal expansion coefficient (CTE) between 3 and 10 ppm/K. The material included in the limiting structure 17 may be an insulating material. Examples of the insulating material may include, but are not limited to, epoxy resin, silicone resin, and combinations thereof. In some embodiments, the limiting structure 17 may include a heat dissipation material or a heat dissipation particle filler to assist the chip units in the first electronic unit 131 and the second electronic unit 133 to dissipate heat, or assist in transferring the heat generated by the chip units in the first electronic unit 131 and the second electronic unit 133 to the connector 15. Examples of heat dissipation materials may include, but are not limited to, silicone resin or graphite. Examples of heat dissipation particle fillers may include, but are not limited to, aluminum oxide or boron nitride.

Figures 3A to 3C are schematic diagrams showing the configuration of the limit structure 17 in the electronic device according to the embodiment of the present disclosure. Figure 4 is a schematic cross-sectional diagram showing the electronic device 2 of other embodiments. Figure 5 is a schematic cross-sectional diagram showing the electronic device 3 of other embodiments. Figure 6 is a schematic cross-sectional diagram showing the electronic device 4 of other embodiments. The following is in conjunction with Figures 1, 4, 5, and 6, as well as Figures 3A to 3C, to further illustrate the relationship between the limit structure 17 and the electronic unit 13.

As shown in FIGS. 3A to 3C , the first electronic unit 131 has a first side 131S1 extending along a first direction D1 and a second side 131S2 extending along a second direction D2 perpendicular to the first direction D1, and the first side 131S1 is connected to the second side 131S2. The second electronic unit 133 has a first side 133S1 extending along the first direction D1 and a second side 133S2 extending along the second direction D2, and the first side 133S1 is connected to the second side 133S2, wherein the first side 131S1 of the first electronic unit 131 is opposite to the first side 133S1 of the second electronic unit 133.

The limiting structure 17 in the electronic device 1 and the electronic device 2 is further described below with reference to FIG. 3A , FIG. 1 and FIG. 4 .

In the embodiment shown in FIG. 3A , the limiting structure 17 includes a first limiting structure 171, a second limiting structure 172, and an opening 175. The first limiting structure 171 and the second limiting structure 172 extend along the first direction D1 and are disposed between the first electronic unit 131 and the second electronic unit 133, wherein the first limiting structure 171 is in direct contact with the first side 131S1 of the first electronic unit 131, and the second limiting structure 172 is in direct contact with the first side 133S1 of the second electronic unit 133. The opening 175 is located between the first limiting structure 171 and the second limiting structure 172 to separate the first limiting structure 171 and the second limiting structure 172 in space and expose a portion of the surface of the protective layer 11. In some embodiments, the opening 175 may have an inclined sidewall, as shown in FIG. 1, but the present disclosure is not limited thereto. In some embodiments, the opening 175 may have a concave curved sidewall, as shown in FIG. 4, but the present disclosure is not limited thereto. In other embodiments, the opening 175 may have a convex curved sidewall. When the opening 175 has a curved sidewall (a concave curved sidewall or a convex curved sidewall), the protective layer 11 may be reduced or prevented from being broken due to the first limiting structure 171 and/or the second limiting structure 172, or the problem of excessive stress in the contact area caused by the mismatch of the linear thermal expansion coefficients between the protective layer 11 and the first limiting structure 171 and/or the second limiting structure 172 may be reduced.

The first limiting structure 171 and the second limiting structure 172 can expose the top surface of the chip unit 1311 in the first electronic unit 131 and/or the chip unit in the second electronic unit 133, as shown in FIG. 1 and FIG. 4, but the present disclosure is not limited thereto. In other embodiments, the first limiting structure 171 and the second limiting structure 172 can extend from the side to cover the top surface of the first electronic unit 131 and/or the second electronic unit 133, as shown in FIG. 5.

FIG. 5 is a schematic cross-sectional view of an electronic device 3 according to another embodiment of the present disclosure. As shown in FIG. 5, the electronic device 3 includes a protective layer 11, an electronic unit 13, a connector 15, and a limiting structure 17. The limiting structure 17 includes a first limiting structure 171 and a second limiting structure 172. The first limiting structure 171 and the second limiting structure 172 extend along a first direction D1 and are disposed between the first electronic unit 131 and the second electronic unit 133. The first limiting structure 171 is in direct contact with the first side 131S1 of the first electronic unit 131, extends from the first side 131S1 to the opposite side of the first side 131S1 and covers the top surface of the chip unit 1311 of the first electronic unit 131. The second limiting structure 172 is in direct contact with the first side 133S1 of the second electronic unit 133, extending from the first side 133S1 to the opposite side of the first side 133S1 and covering the top surface of the chip unit of the second electronic unit 133. The protective layer 11, the electronic unit 13, and the connector 15 in the electronic device 3 are substantially similar or identical to the protective layer 11, the electronic unit 13, and the connector 15 in the electronic devices 1 and 2, and are not repeated here. According to some embodiments, the limiting structure 17 may include heat dissipation particles to achieve a good heat dissipation effect. For example, the thermal conductivity coefficient of the limiting structure 17 is, for example, greater than or equal to 0.35 W/m*K and less than or equal to 7W/m*K, but is not limited thereto. According to some embodiments, the thermal conductivity of the limiting structure 17 may be greater than that of the protective layer 11. For example, the thermal conductivity of the limiting structure 17 is 3 W/m*K, which is greater than the thermal conductivity of the protective layer 11, which is 0.2 W/m*K, but the present invention is not limited thereto.

In the embodiment shown in FIG. 3A , the limiting structure 17 further includes a third limiting structure 173 and a fourth limiting structure 174, wherein the third limiting structure 173 directly contacts the second side 131S2 of the first electronic unit 131, and the fourth limiting structure 174 directly contacts the second side 133S2 of the second electronic unit 133. In some embodiments, the side surface of the third limiting structure 173 that is not in direct contact with the second side 131S2 of the first electronic unit 131 and the side surface of the fourth limiting structure 174 that is not in direct contact with the second side 133S2 of the second electronic unit 133 may be an inclined side surface or a curved side surface. When the side of the third limiting structure 173 that is not in direct contact with the second side 131S2 of the first electronic unit 131 and the side of the fourth limiting structure 174 that is not in direct contact with the second side 133S2 of the second electronic unit 133 are inclined sides or curved sides, the problem of excessive stress in the contact area caused by the third limiting structure 173 and/or the fourth limiting structure 174 being broken or avoided can be further reduced or avoided, or the problem of excessive stress in the contact area caused by the mismatch of the linear thermal expansion coefficients between the protective layer 11 and the third limiting structure 173 and/or the fourth limiting structure 174 can be reduced.

The limiting structure 17 in the electronic device 4 is further described below with reference to FIG. 3B and FIG. 6 .

In the embodiments shown in FIG. 3B and FIG. 6 , the limiting structure 17 includes a first limiting structure 171, a second limiting structure 172, and a connecting portion 176. The connecting portion 176 is between the first electronic unit 131 and the second electronic unit 133 and connects the first limiting structure 171 and the second limiting structure 172. The thickness of the connecting portion 176 is less than that of the first limiting structure 171 and the second limiting structure 172. In some embodiments, the connecting portion 176 can be combined with the first limiting structure 171 and the second limiting structure 172 to form a recessed portion having an inclined side wall or a curved side wall. FIG. 6 shows a state in which the connecting portion 176 is combined with the first limiting structure 171 and the second limiting structure 172 to form a recessed portion having a curved side wall. In the embodiment shown in FIG. 6 , the connecting portion 176, the first limiting structure 171 and the second limiting structure 172 have the same width in the second direction D2. When the first limiting structure 171 and the first side 131S1 of the first electronic unit 131 are directly in contact with each other and the first limiting structure 171 and the connecting portion 176 are directly in contact with each other, the connecting portion 176 is combined with the first limiting structure 171 and the second limiting structure 172 to form a concave portion with a curved sidewall, as shown in FIG. 6 . In another embodiment, when the first limiting structure 171 is in direct contact with the first side 131S1 of the first electronic unit 131 and the first limiting structure 171 is in direct contact with the connecting portion 176 to form an inclined plane, the connecting portion 176 is combined with the first limiting structure 171 and the second limiting structure 172 to form an inclined side wall. In this embodiment, the limiting structure 17 is located between the protective layer 11 and the connecting member 15, so that the connecting member 15 does not contact the surface of the protective layer 11. In the embodiment shown in FIG. 3B , the limiting structure 17 further includes a third limiting structure 173 and a fourth limiting structure 174, wherein the third limiting structure 173 directly contacts the second side 131S2 of the first electronic unit 131, and the fourth limiting structure 174 directly contacts the second side 133S2 of the second electronic unit 133. The third limiting structure 173 and the fourth limiting structure 174 in this embodiment have similar structures and advantages to the third limiting structure 173 and the fourth limiting structure 174 described with reference to FIG. 3A , and thus will not be described in detail here.

In other embodiments, the first limiting structure 171 to the fourth limiting structure 174 may include a plurality of sub-limiting structures. FIG. 3C is a schematic diagram showing the configuration of the limiting structure 17 in an electronic device according to another embodiment of the present disclosure. In the embodiment shown in FIG. 3C, the first limiting structure 171 may include two first sub-limiting structures 1711 and a first gap 1713 disposed between the two first sub-limiting structures 1711, and the two first sub-limiting structures 1711 are spatially separated by the first gap 1713. The second limiting structure 172 may include two second sub-limiting structures 1721 and a second gap 1723 disposed between the two second sub-limiting structures 1721, and the two second sub-limiting structures 1721 are spatially separated by the second gap 1723. The third limiting structure 173 may include two third sub-limiting structures 1731 and a third gap 1733 disposed between the two third sub-limiting structures 1731, and the two third sub-limiting structures 1731 are spatially separated by the third gap 1733. The fourth limiting structure 174 may include two fourth sub-limiting structures 1741 and a fourth gap 1743 disposed between the two fourth sub-limiting structures 1741, and the two fourth sub-limiting structures 1741 are spatially separated by the fourth gap 1743. Although FIG. 3C discloses that each of the first limiting structure 171 to the fourth limiting structure 174 includes a plurality of sub-limiting structures, the present disclosure is not limited thereto. In some embodiments, at least one of the first to fourth limiting structures 171 to 174 has a structure similar to the limiting structure described in conjunction with FIG. 3A and/or FIG. 3B (excluding the sub-limiting structure). Although FIG. 3C discloses an embodiment in which the first limiting structure 171 includes two first sub-limiting structures 1711 and a first gap 1713, the second limiting structure 172 includes two second sub-limiting structures 1721 and a second gap 1723, the third limiting structure 173 includes two third sub-limiting structures 1731 and a third gap 1733, and the fourth limiting structure 174 includes two fourth sub-limiting structures 1741 and a fourth gap 1743, the present disclosure is not limited thereto. In some embodiments, at least one of the first to fourth limiting structures 171 to 174 may include three or more sub-limiting structures and two or more gaps.

Although FIGS. 3A to 3C disclose that the limiting structure 17 includes the first limiting structure 171 to the fourth limiting structure 174, the present disclosure is not limited thereto. In some embodiments, the limiting structure 17 may include only the first limiting structure 171. In other embodiments, the limiting structure 17 may include only the first limiting structure 171 and one of the second limiting structures 172 to the fourth limiting structure 174. In other embodiments, the limiting structure 17 may further include other limiting structures 177 that are parallel to the first limiting structure 171 and the second limiting structure 172 but are not disposed between the first electronic unit 131 and the second electronic unit 133, as shown in FIG. 9A.

The first limiting structure 171 is further described below with reference to FIGS. 3A to 3C. The side of the first limiting structure 171 that contacts the first side 131S1 has a first width W1 in the first direction D1, and the first side 131S1 of the first electronic unit 131 has a second width W2 in the first direction D1, and the first width W1 and the second width W2 meet the following relationship: Furthermore, the first width W1 and the second width W2 satisfy the following relationship: When the width of the side of the first limiting structure 171 in contact with the first side 131S1 of the first electronic unit 131 and the width of the first side 131S1 of the first electronic unit 131 satisfy the above relationship, the first limiting structure 171 disposed between the first electronic unit 131 and the second electronic unit 133 can fix the first electronic unit 131 without significantly increasing the manufacturing cost of the electronic device. The proportional relationship and advantages between the width of the side where the second limiting structure 172 contacts the first side 133S1 of the second electronic unit 133 and the width of the first side 133S1 of the second electronic unit 133 are similar to the proportional relationship and advantages between the width of the side where the first limiting structure 171 contacts the first side 131S1 and the width of the first side 131S1 of the first electronic unit 131, and therefore will not be elaborated here.

In some embodiments, the third limiting structure 173 may have a third width W3 in the second direction D2, the second side 131S2 of the first electronic unit 131 may have a fourth width W4 in the second direction D2, and the third width W3 and the fourth width W4 meet the following relationship: 0.2≦W3⁄W4＜1. Further, the third width W3 and the fourth width W4 meet the following relationship: 0.2≦W3⁄W4＜0.8. When the width of the side of the third limiting structure 173 in contact with the second side 131S2 of the first electronic unit 131 satisfies the above relationship, the third limiting structure 173 can fix the first electronic unit 131 without significantly increasing the manufacturing cost of the electronic device. The ratio relationship and advantages between the width of the side contacted by the fourth limiting structure 174 and the second side 133S2 of the second electronic unit 133 and the width of the second side 133S2 of the second electronic unit 133 are similar to the ratio relationship and advantages between the width of the side contacted by the third limiting structure 173 and the second side 131S2 and the width of the second side 131S2 of the first electronic unit 131, so they will not be elaborated here.

Continuing to refer to FIG. 1, FIG. 4 and FIG. 6, the first electronic unit 131 may have a second thickness T2 in a third direction D3 perpendicular to the first direction D1 and the second direction D2, the second electronic unit 133 may have a third thickness T3 in the third direction D3, and the first limiting structure 171 may have a first thickness T1 in the third direction D3. The third direction D3 may be, for example, a normal direction of the electronic device 1. Here, the first thickness T1 refers to the maximum thickness of the first limiting structure 171 in the third direction D3, the second thickness T2 refers to the sum of the thicknesses of the chip unit 1311, the first insulating layer 1315, and the second insulating layer 1317 in the first electronic unit 131 in the third direction D3, and the third thickness T3 refers to the sum of the thicknesses of the chip unit, the first insulating layer, and the second insulating layer in the second electronic unit 133 in the third direction D3. The second thickness T2 may be greater than or equal to the third thickness T3 of the second electronic unit 133, and the first thickness T1 and the second thickness T2 meet the following relationship: ≦T1≦T2. Furthermore, the first thickness T1 and the second thickness T2 satisfy the following relationship: ≦T1≦T2.

When the thickness of the first limiting structure 171 and the thickness of the first electronic unit 131 satisfy the above relationship, the first limiting structure 171 disposed between the first electronic unit 131 and the second electronic unit 133 can fix the first electronic unit 131 and the second electronic unit 133 without significantly increasing the manufacturing cost of the electronic device. The second limiting structure 172 to the fourth limiting structure 174 can have a thickness similar to that of the first limiting structure 171, and thus will not be described in detail herein.

Another aspect of the present disclosure provides a method for manufacturing an electronic device. FIG. 7 is a flow chart showing a method for manufacturing an electronic device according to an embodiment of the present disclosure. FIG. 8A, FIG. 9A, and FIG. 10A are schematic top views of an electronic device at an intermediate stage of the method for manufacturing an electronic device according to an embodiment of the present disclosure. FIG. 8B, FIG. 9B, FIG. 9C, and FIG. 10B to FIG. 14 are schematic cross-sectional views of an electronic device at an intermediate stage of the method for manufacturing an electronic device according to an embodiment of the present disclosure. The following describes a method for manufacturing an electronic device according to an embodiment of the present disclosure in conjunction with FIG. 7 and FIG. 8A to FIG. 14.

As shown in FIG. 7 , the manufacturing method of the electronic device disclosed herein includes step S201 of providing a substrate; step S203 of providing a first electronic unit and a second electronic unit on the substrate; step S205 of providing a limiting structure between the first electronic unit and the second electronic unit; step S207 of providing a protective layer surrounding the limiting structure, the first electronic unit, and the second electronic unit; and step S209 of providing a connector electrically connecting the first electronic unit and the second electronic unit.

The substrate 10 provided in step S201 (refer to FIG. 8A and FIG. 8B ) may include a flexible substrate, a rigid substrate, or a combination thereof, but is not limited thereto. In some embodiments, the substrate may be a light-transmitting substrate, a semi-transmitting substrate, or an opaque substrate. According to some embodiments, the material of the substrate may include glass, quartz, sapphire, ceramic, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polypropylene (PP), stainless steel, alloy steel, carbon fiber, glass fiber, other suitable materials, or any combination thereof, but the present disclosure is not limited thereto. In some embodiments, the substrate may further include a conductive layer, an insulating layer, a dielectric layer, a display medium layer, an air layer, a vacuum layer, or any combination thereof, but the present disclosure is not limited thereto.

FIG. 8A is a schematic top view of an electronic device in step S203 of a method for manufacturing an electronic device according to an embodiment of the present disclosure. FIG. 8B is a schematic cross-sectional view of the electronic device shown in FIG. 8A along line A-A'. Referring to FIG. 8A and FIG. 8B, an electronic unit 13 including a first electronic unit 131 and a second electronic unit 133 is provided on a substrate 10 in step S203. In some embodiments, the step S203 of providing the electronic unit 13 on the substrate includes the step of transferring a plurality of first electronic units 131 and second electronic units 133 onto the substrate 10. In some embodiments, the electronic unit 13 may be provided on the substrate 10 in the form of a matrix.

8A and 8B, the first electronic unit 131 and the second electronic unit 133 provided on the substrate 10 are separated by a distance, and the bonding pad 1313 of the first electronic unit 131 corresponds to the bonding pad 1333 of the second electronic unit 133. The first electronic unit 131 has a first side 131S1 and a second side 131S2 connected to the first side 131S1, wherein the first side 131S1 extends along the first direction D1 and has a second width W2 in the first direction D1, and the second side 131S2 extends along the second direction D2 and has a fourth width W4 in the second direction D2. The second electronic cell 133 has a first side 133S1 and a second side 133S2 connected to the first side 133S1, wherein the first side 133S1 is along the first direction D1 and opposite to the first side 131S1 of the first electronic cell 131, and the second side 131S2 extends along the second direction D2. The width of the first side 133S1 of the second electronic cell 133 and the width of the second side 133S2 may be the same as the first side 131S1 and the second side 131S2. The first electronic cell 131 may have a second thickness T2 in the third direction D3, the second electronic cell 133 may have a third thickness T3 in the third direction D3, and the second thickness T2 of the first electronic cell 131 may be greater than or equal to the third thickness T3 of the second electronic cell 133.

FIG. 9A is a schematic top view of an electronic device in step S205 of a method for manufacturing an electronic device according to an embodiment of the present disclosure. FIG. 9B and FIG. 9C are schematic cross-sectional views of the electronic device shown in FIG. 9A along line A-A'. Referring to FIG. 9A , step S205 of providing a limiting structure between the first electronic unit and the second electronic unit may include providing a first limiting structure 171 and a second limiting structure 172 extending along a first direction D1 and a third limiting structure 173 and a fourth limiting structure 174 extending along a second direction D2, wherein the first limiting structure 171 directly contacts the first side 131S1 of the first electronic unit 131, the second limiting structure 172 directly contacts the first side 133S1 of the second electronic unit 133, the third limiting structure 173 directly contacts the second side 131S2 of the first electronic unit 131, and the fourth limiting structure 174 directly contacts the second side 133S2 of the second electronic unit 133, but the present disclosure is not limited thereto. In some embodiments, step S205 only provides one of the first limiting structure 171 and the second limiting structure 172 between the first electronic unit and the second electronic unit, but does not include providing the other three of the first limiting structure 171 to the fourth limiting structure 174. In other embodiments, step S205 may further include providing another limiting structure 177 that is parallel to the first limiting structure 171 and the second limiting structure 172 but is not disposed between the first electronic unit 131 and the second electronic unit 133. The other limiting structure 177 may directly contact the sides of the first electronic unit 131 and the second electronic unit 133, but the present disclosure is not limited thereto. In some embodiments, the step of providing the limiting structure 17 includes providing an opening 175 extending along the first direction D1 between the first limiting structure 171 and the second limiting structure 172, wherein the first conductive layer 151 contacts the surface of the protective layer 11 in the opening 175, and the opening 175 has an inclined side wall, as shown in FIG. 9B, but the present disclosure is not limited thereto. In other embodiments, the opening 175 may have a curved side wall, as shown in FIG. 9C.

FIG. 10A is a schematic top view of an electronic device in step S205 of a method for manufacturing an electronic device according to another embodiment of the present disclosure. FIG. 10B is a schematic cross-sectional view of the electronic device shown in FIG. 10A along line A-A'. The difference between the embodiment shown in FIG. 10A and the embodiment shown in FIG. 9A is that in the embodiment shown in FIG. 10A, the limiting structure 17 includes a connecting portion 176 located between the first limiting structure 171 and the second limiting structure 172 and connecting the first limiting structure 171 and the second limiting structure 172 instead of the opening 175. The thickness of the connecting portion 176 is less than that of the first limiting structure 171 and the second limiting structure 172. In some embodiments, the connecting portion 176 may be combined with the first limiting structure 171 and the second limiting structure 172 to form a recessed portion having an inclined side wall or a curved side wall, as shown in FIG. 10B .

In some embodiments, the first to fourth limiting structures 171 to 174 and other limiting structures 177 of the limiting structure 17 may be formed simultaneously in step S205. The step S205 of providing the limiting structure 17 may include using a needle coating process, an ink-jet printing coating, a screen printing coating, a relief/gravure printing coating, a transfer printing coating, a chemical vapor deposition process (chemical vapor deposition, CVD), a physical vapor deposition process (physical vapor deposition, PVD), an atomic layer deposition (atomic layer deposition, ALD) process, a high-density plasma chemical vapor deposition (high-density plasma CVD, HDPCVD) process, other suitable methods or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the step S205 of providing the limiting structure 17 may include covering the limiting structure 17 on the first electronic unit 131 and the second electronic unit 133 by hot pressing, and then providing it through a grinding process or a coating process combined with an etching process, but is not limited thereto. In some embodiments, the material used to form the limiting structure 17 may include a material having a Young's modulus between 1000 MPa and 20000 MPa. In some embodiments, the material used to form the limiting structure 17 may include a material having a linear thermal expansion coefficient (CTE) between 3 and 60 ppm/K. In a further embodiment, the material used to form the limiting structure 17 may include a material having a linear thermal expansion coefficient (CTE) between 3 and 10 ppm/K. The material used to form the limiting structure 17 may be an insulating material. In some embodiments, examples of the insulating material may include but are not limited to epoxy resin, silicone resin, and combinations thereof. The positional relationship, width ratio, and thickness ratio between the limiting structure 17 provided in step S205 and the first electronic unit 131 and the second electronic unit 133 are as described above, and are not further described here.

Figures 11 to 13 are cross-sectional schematic diagrams of the electronic device in step S207 and step S209 of the method for manufacturing an electronic device according to an embodiment of the present disclosure. Figure 11 is an example of performing step S207 on the structure shown in Figure 9B, but the present disclosure is not limited to this. In some embodiments, step S207 can be performed on the structure shown in Figure 9C or Figure 10B. Step S207 provides a protective layer 11 on the substrate 10 on which the limiting structure 17, the first electronic unit 131 and the second electronic unit 133 are formed. The protective layer surrounds the limiting structure 17, the first electronic unit 131 and the second electronic unit 133. More specifically, the protective layer 11 is in direct contact with the side of the limiting structure 17, the side of at least part of the first electronic unit 131, and the side of at least part of the second electronic unit 133. By directly contacting the side of at least part of the first electronic unit 131 and at least part of the second electronic unit 133, the protective layer 11 can reduce the impact of moisture and oxygen in the environment on the electronic unit 13, thereby improving the service life and reliability of the electronic unit 13. In some embodiments, the protective layer 11 can be formed of any material used as a packaging material. In some embodiments, the protective layer 11 can be formed of epoxy resin. In some embodiments, the step S207 of providing the protective layer 11 may include forming the protective layer 11 using a dispensing process, a transfer molding process, other suitable methods or a combination thereof. Then, step S209 may be performed, and the step S209 of providing the connector 15 electrically connecting the first electronic unit 131 and the second electronic unit 133 includes the steps of forming a photoresist material layer 50, forming an insulating layer 153, and filling a conductive material. The step of forming the photoresist material layer 50 includes forming a carrier 30 on the structure so that the first electronic unit 131, the second electronic unit 133, the limiting structure 17 and the protective layer 11 are located between the carrier 30 and the substrate 10 to obtain an intermediate structure. After the intermediate structure is inverted, the substrate 10 is removed, and a photoresist material layer 50 is formed so that the first electronic unit 131, the second electronic unit 133, the limiting structure 17 and the protective layer 11 are located between the carrier 30 and the photoresist material layer 50, as shown in FIG11. The photoresist material layer 50 can be formed by a heat press lamination process, a spin coating process, a spinless coating process, an ink-jet printing coating process, or other suitable methods or combinations thereof, but the present disclosure is not limited thereto.

The formation of the insulating layer 153 includes patterning the photoresist material layer 50 to expose the bonding pad 1313 of the first electronic unit 131, the bonding pad 1333 of the second electronic unit 133, and the surface of the limiting structure 17, and curing the patterned photoresist material layer 50 to form the insulating layer 153. The step of patterning the photoresist material layer 50 may include a dry etching process, a wet etching process, and a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the patterned photoresist material layer 50 exposes at least a portion of the surface of the protective layer 11, as shown in FIG. 12, but the present disclosure is not limited thereto. In other embodiments, the patterned photoresist material layer 50 does not expose the surface of the protective layer 11. The step of curing the patterned photoresist layer 50 may include a photocuring process, a thermal curing process, or a combination thereof, but the present disclosure is not limited thereto.

Then, the first conductive layer 151 electrically connecting the first electronic unit 131 and the second electronic unit 133 is formed by filling the conductive material between the insulating layers 153 to complete the preparation of the connector 15. The manufacture of the electronic device can be completed by removing the carrier 30 after forming the connector 15, as shown in FIG. 13. The above-mentioned manufacturing method avoids or reduces the position displacement, detachment or damage that may occur to the first electronic unit 131 and/or the second electronic unit 133 during the formation of the protective layer 11 by providing a limiting structure 17. Therefore, the possibility that the first electronic unit 131 and/or the second electronic unit 133 cannot provide a good electrical connection through the connector 15 due to position displacement, detachment or damage can be reduced.

The above only provides the manufacturing method of the electronic device of some embodiments of the present disclosure, and the manufacturing method of the electronic device of the present disclosure is not limited to the sequence and steps disclosed above. In some embodiments, some steps in the above-mentioned manufacturing method of the electronic device can be omitted. For example, the steps of forming the carrier 30 and/or inverting the intermediate structure can be omitted in the manufacturing method of the electronic device. In other embodiments, the process sequence in the manufacturing method of the electronic device of the present disclosure can be changed. Figure 14 is a flow chart showing a manufacturing method of an electronic device according to another embodiment of the present disclosure. Figures 15 and 16 are schematic top views of the electronic device at the intermediate stage of the manufacturing method of the electronic device according to another embodiment of the present disclosure.

Referring to FIG. 14, a method for manufacturing an electronic device according to another embodiment of the present disclosure may include a step of providing a substrate (S301); a step of providing a limiting structure on the substrate (S303); a step of providing a first electronic unit and a second electronic unit on the substrate (S305); a step of providing a protective layer surrounding the limiting structure, the first electronic unit, and the second electronic unit (S307); and a step of providing a connector electrically connecting the first electronic unit and the second electronic unit (S309). The difference between the method for manufacturing an electronic device of this embodiment and the method for manufacturing an electronic device shown in FIG. 7 is that in the embodiment shown in FIG. 7, the limiting structure is provided after the first electronic unit and the second electronic unit, while in this embodiment, the limiting structure is provided before the first electronic unit and the second electronic unit. Specifically, refer to FIG. 15 , which is a top view schematic diagram of the electronic device in step S303 of the method for manufacturing the electronic device according to an embodiment of the present disclosure. As shown in FIG. 15 , the limiting structure 17 can be formed on the substrate 10 before the first electronic unit 131 and the second electronic unit 133 by using a needle coating process, an ink-jet printing coating, a screen printing coating, a relief/gravure printing coating, a transfer printing coating, heat and lamination, a chemical vapor deposition process (chemical vapor deposition, CVD), a physical vapor deposition process (physical vapor deposition, PVD), an atomic layer deposition (atomic layer deposition, ALD) process, a high-density plasma chemical vapor deposition (high-density plasma CVD, HDPCVD) process, other suitable methods or a combination thereof.

FIG. 16 is a schematic top view of an electronic device in step S305 of a method for manufacturing an electronic device according to an embodiment of the present disclosure. As shown in FIG. 16 , the first electronic unit 131 and the second electronic unit 133 are provided on the substrate 10 after the limiting structure 17 is formed, and the first limiting structure 171 and the second limiting structure 172 are located on the first electronic unit 131 and the second electronic unit 133. Except for the order in which the electronic unit 13 and the limiting structure 17 are provided, the process, materials and advantages used in this embodiment are the same as those of the above embodiment, so they are not repeated here. In this embodiment, the limiting structure 17 can not only avoid or reduce the position displacement, detachment or damage of the first electronic unit 131 and/or the second electronic unit 133 that may occur during the formation of the protective layer 11, but also be used as an alignment element to avoid or reduce the displacement of the electronic unit 13 when it is provided on the substrate.

The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand and can easily design or modify other processes and structures based on the present disclosure to achieve the same purpose and/or the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not deviate from the spirit and scope of the present disclosure. Various changes, substitutions or modifications may be made to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The features of the embodiments may be mixed and matched as they please as long as they do not violate the spirit of the invention or conflict with each other. In addition, each claim item of the present disclosure may be a separate embodiment, and the scope of the present disclosure includes the combination of each claim item and each embodiment of the present disclosure.

1,2,3,4: electronic device 10: substrate 11: protective layer 13: electronic unit 131: first electronic unit 1311: chip unit 1313, 1333: bonding pad 1315: first insulating layer 1317: second insulating layer 133: second electronic unit 131S1, 133S1: first side 131S2, 133S2: second side 15: connector 151: first conductive layer 153: insulating layer 17: limit structure 171: first limit structure 172: second limit structure 173: third limit structure 174: fourth limit structure 1711,1721,1731,1741: sub-limit structure 1713,1723,1733,1743: gap 175: opening 176: connection part 177: other limit structures 19: connection pad 30: carrier 50: photoresist material layer T1,T2,T3: thickness W1,W2,W3,W4: width S201-S209, S301-S309: steps D1,D2,D3: direction

The disclosure may be more fully understood from the following detailed description when read together with the accompanying drawings. It is noteworthy that, in accordance with standard practice in the industry, the features are not drawn to scale. In fact, for the sake of clarity, the sizes of various features may be arbitrarily enlarged or reduced. FIG. 1 is a schematic cross-sectional view of an electronic device according to an embodiment of the disclosure. FIG. 2 is a schematic cross-sectional view of an electronic unit according to an embodiment of the disclosure. FIG. 3A to FIG. 3C are schematic views of the configuration of the limit structure in the electronic device according to the embodiment of the disclosure. FIG. 4 is a schematic cross-sectional view of an electronic device according to another embodiment of the disclosure. FIG. 5 is a schematic cross-sectional view of an electronic device according to another embodiment of the disclosure. FIG. 6 is a schematic cross-sectional view of an electronic device according to another embodiment of the present disclosure. FIG. 7 is a flow chart of a method for manufacturing an electronic device according to an embodiment of the present disclosure. FIG. 8A, FIG. 9A, and FIG. 10A are schematic top views of an electronic device at an intermediate stage of a method for manufacturing an electronic device according to an embodiment of the present disclosure. FIG. 8B, FIG. 9B, FIG. 9C, and FIG. 10B to FIG. 13 are schematic cross-sectional views of an electronic device at an intermediate stage of a method for manufacturing an electronic device according to an embodiment of the present disclosure. FIG. 14 is a flow chart of a method for manufacturing an electronic device according to another embodiment of the present disclosure. FIG. 15 and FIG. 16 are schematic top views of an electronic device at an intermediate stage of a method for manufacturing an electronic device according to another embodiment of the present disclosure.

1: Electronic devices

11: Protective layer

13: Electronic unit

131: First electronic unit

133: Second electronic unit

131S1,133S1: First side

15: Connectors

151: First conductive layer

153: Insulation layer

17: Limiting structure

171: First limit structure

172: Second limit structure

175: Open mouth

19:Connection pad

T1, T2, T3: thickness

Claims (20)

An electronic device includes: a protective layer; a plurality of electronic units disposed in the protective layer, the plurality of electronic units including a first electronic unit and a second electronic unit; a connector disposed on the protective layer, wherein the first electronic unit and the second electronic unit are electrically connected through the connector; and at least one limiting structure disposed in the protective layer and located between the first electronic unit and the second electronic unit, wherein the connector has a first conductive layer, the first conductive layer contacts the first conductive layer. A surface of the electronic unit, a surface of the at least one limiting structure, and a surface of the protective layer, wherein the first electronic unit has a first side extending along a first direction, and the at least one limiting structure is in direct contact with the first side of the first electronic unit, the at least one limiting structure has a first width W1 in the first direction, the first side of the first electronic unit has a second width W2 in the first direction, and the first width W1 and the second width W2 meet the following relationship:

An electronic device as claimed in claim 1, wherein the first electronic unit comprises: a chip unit, wherein the chip unit comprises a plurality of bonding pads; a first insulating layer disposed on the chip unit; and a second insulating layer disposed between the first insulating layer and the connector, wherein the first insulating layer and the second insulating layer expose the plurality of bonding pads. The electronic device of claim 1 further comprises another limiting structure located between the first electronic unit and the second electronic unit, wherein the second electronic unit has a first side extending along the first direction, and the other limiting structure is in direct contact with the first side of the second electronic unit. The electronic device of claim 3 further comprises an opening located between the at least one limiting structure and the other limiting structure, the first conductive layer contacts the surface of the protective layer in the opening, and the opening has an inclined side wall. The electronic device of claim 3 further comprises an opening located between the at least one limiting structure and the other limiting structure, the first conductive layer contacts the surface of the protective layer in the opening, and the opening has a curved side wall. The electronic device of claim 1, wherein the first width W1 and the second width W2 satisfy the following relationship:

In the electronic device of claim 1, the at least one limiting structure has a first thickness T1 in a third direction perpendicular to the first direction, the first electronic unit has a second thickness T2 in the third direction, and the first thickness T1 and the second thickness T2 satisfy the following relationship:

As in claim 7, the first thickness T1 and the second thickness T2 further satisfy the following relationship:

An electronic device as claimed in claim 1, wherein the at least one limiting structure includes a plurality of sub-limiting structures. An electronic device includes: a protective layer; a plurality of electronic units disposed in the protective layer, the plurality of electronic units including a first electronic unit and a second electronic unit; a connector disposed on the protective layer, wherein the first electronic unit and the second electronic unit are electrically connected through the connector; a first limiting structure and a second limiting structure disposed in the protective layer and located between the first electronic unit and the second electronic unit; and a connecting portion disposed in the protective layer and connected to the first electronic unit. The first limiting structure and the second limiting structure, wherein the connecting portion is combined with the first limiting structure and the second limiting structure to form a recessed portion having an inclined side wall or a curved side wall, wherein the first electronic unit has a first side extending along a first direction, the first limiting structure has a first width W1 in the first direction, the first side of the first electronic unit has a second width W2 in the first direction, and the first width W1 and the second width W2 meet the following relationship:

A method for manufacturing an electronic device includes: providing a substrate; providing a first electronic unit and a second electronic unit on the substrate; providing at least one limiting structure between the first electronic unit and the second electronic unit; providing a protective layer surrounding the at least one limiting structure, the first electronic unit, and the second electronic unit; and providing a connector, wherein the first electronic unit and the second electronic unit are electrically connected through the connector, wherein the first electronic unit has a first side extending along a first direction, the at least one limiting structure has a first width W1 in the first direction, the first side of the first electronic unit has a second width W2 in the first direction, and the first width W1 and the second width W2 meet the following relationship:

A method for manufacturing an electronic device as claimed in claim 11, wherein the at least one limiting structure is in direct contact with the first side of the first electronic unit. A method for manufacturing an electronic device as claimed in claim 12, wherein the method further includes providing another limiting structure between the first electronic unit and the second electronic unit, wherein the second electronic unit has a first side extending along the first direction, and the other limiting structure is in direct contact with the first side of the second electronic unit. A method for manufacturing an electronic device as claimed in claim 12, wherein the method further includes providing an opening between the at least one limiting structure and another limiting structure, the connector includes a first conductive layer, the first conductive layer contacts a surface of the protective layer in the opening, and the opening has an inclined side wall. A method for manufacturing an electronic device as claimed in claim 12, wherein the method further includes providing an opening between the at least one limiting structure and another limiting structure, the connector includes a first conductive layer, the first conductive layer contacts a surface of the protective layer in the opening, and the opening has a curved sidewall. A method for manufacturing an electronic device includes: providing a substrate; providing at least one limiting structure on the substrate; providing a first electronic unit and a second electronic unit on the substrate, wherein the at least one limiting structure is located between the first electronic unit and the second electronic unit; providing a protective layer surrounding the at least one limiting structure, the first electronic unit, and the second electronic unit; and providing a connector, wherein the first electronic unit and the second electronic unit are electrically connected through the connector, wherein the first electronic unit has a first side extending along a first direction, the at least one limiting structure has a first width W1 in the first direction, the first side of the first electronic unit has a second width W2 in the first direction, and the first width W1 and the second width W2 meet the following relationship:

A method for manufacturing an electronic device as claimed in claim 16, wherein the at least one limiting structure is in direct contact with the first side of the first electronic unit. A method for manufacturing an electronic device as claimed in claim 16, wherein the method further includes providing another limiting structure between the first electronic unit and the second electronic unit, wherein the second electronic unit has a first side extending along the first direction, and the other limiting structure is in direct contact with the first side of the second electronic unit. A method for manufacturing an electronic device as claimed in claim 16, wherein the method further includes providing an opening between the at least one limiting structure and another limiting structure, the connector includes a first conductive layer, the first conductive layer contacts a surface of the protective layer in the opening, and the opening has an inclined side wall. A method for manufacturing an electronic device as claimed in claim 16, wherein the method further includes providing an opening between the at least one limiting structure and another limiting structure, the connector includes a first conductive layer, the first conductive layer contacts a surface of the protective layer in the opening, and the opening has a curved sidewall.

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