TWI850116B - Capacitance measurement circuit - Google Patents

Abstract

A capacitance measurement circuit includes a charge to voltage converter (CVC) that includes at least one first variable capacitor, an excitation signal generation circuit, a differential amplifier, a first switch circuit, and at least one second variable capacitor, wherein a parasitic capacitance from a sensing capacitance sensed by a capacitance sensor is reduced by the at least one first variable capacitor. The excitation signal generation circuit is arranged to generate and connect a first excitation signal to the capacitance sensor, and generate and connect a second excitation signal to the at least one first variable capacitor, wherein the first excitation signal and the second excitation signal are out-of-phase, and a voltage amplitude of the first excitation signal is different from a voltage amplitude of the second excitation signal. The inverting input terminal of the differential amplifier is arranged to receive the sensing capacitance from the capacitance sensor.

Description

Capacitance measurement circuit

The present invention relates to capacitance measurement, and in particular to a capacitance to digital converter (CDC) and a charge to voltage converter (CVC) therein.

For a capacitance measurement circuit (e.g., a capacitance-to-digital converter including a charge-to-voltage converter and a voltage-to-digital converter (e.g., an analog-to-digital converter (ADC))), a variable capacitor in the charge-to-voltage converter can be used to reduce/offset a parasitic capacitance value in a sensed capacitance value of a capacitance to be measured, or to adjust an input dynamic range for subsequent signal conversion, wherein the capacitance to be measured is sensed by a charge conversion circuit of a front-end circuit of the capacitance-to-digital converter. However, if the parasitic capacitance value is much larger than the capacitance value of the variable capacitor, the parasitic capacitance value may not be reduced/offset by the variable capacitor. If the parasitic capacitance value is too large to be reduced/offset, the voltage amplitude of the output voltage of the charge-to-voltage converter may exceed the input voltage range of the analog-to-digital converter, causing the analog-to-digital converter to not operate normally.

Therefore, one of the purposes of the present invention is to provide a capacitance measuring circuit that can generate multiple excitation signals with different voltage amplitudes to an external capacitance sensor and at least one internal compensation capacitor, to solve the above-mentioned problem.

According to an embodiment of the present invention, a capacitance measuring circuit is provided. The capacitance measuring circuit may include a charge-to-voltage converter, and the charge-to-voltage converter may include at least one first variable capacitor, an excitation signal generating circuit, a differential amplifier, a first switching circuit, and at least one second variable capacitor, wherein a parasitic capacitance value in a sensed capacitance value measured by a capacitance sensor is reduced by the at least one first variable capacitor. The excitation signal generating circuit may be used to generate and connect a first excitation signal to a first end of the capacitance sensor, and to generate and connect a second excitation signal to the at least one first variable capacitor, wherein the first excitation signal and the second excitation signal are in antiphase, and a voltage amplitude of the first excitation signal is different from a voltage amplitude of the second excitation signal. The differential amplifier has an inverting input terminal, a non-inverting input terminal, an inverting output terminal and a non-inverting output terminal, wherein the inverting input terminal is used to receive a sensed capacitance value from a second terminal of the capacitance sensor, the first switch circuit is coupled between the inverting input terminal and the non-inverting output terminal of the differential amplifier, and the first switch circuit and at least one second variable capacitor are connected in parallel between the inverting input terminal and the non-inverting output terminal of the differential amplifier.

In addition, the charge-to-voltage converter can be used to generate an output voltage according to the sensed capacitance value, and the capacitance measuring circuit can be a capacitance-to-digital converter and further include an analog-to-digital converter, wherein the analog-to-digital converter can be used to convert the output voltage into a digital pulse current.

One of the advantages of the present invention is that the capacitance measuring circuit of the present invention (which includes a charge-to-voltage converter and an analog-to-digital converter) can generate a plurality of excitation signals with different voltage amplitudes to an external capacitance sensor and a capacitance measuring circuit of at least one internal compensation capacitor, respectively. In the case that the parasitic capacitance value in the sensed capacitance value of the capacitor to be measured is much larger than the capacitance value of at least one compensation capacitor, the charge-to-voltage converter of the present invention can utilize the at least one compensation capacitor to successfully reduce/offset the parasitic capacitance value by using the excitation signals with different voltage amplitudes. In this way, the voltage amplitude of the output voltage of the charge-to-voltage converter will not exceed the input dynamic range of the analog-to-digital converter, which allows the analog-to-digital converter to operate normally.

100,300,400: Charge to voltage converter

102,200: Excitation signal generating circuit

104: Differential amplifier

106,306,308,310,312,406,408: Switching circuit

108: At least one variable capacitor

110: At least one compensation capacitor

112: Self-calibration capacitor

114,116,302,304,402,404:Drive circuit

118: Slew rate limiter

150: Capacitor sensor

Φ _R : Clock signal

V _OUT+ : First differential output voltage

V _OUT- : Second differential output voltage

C _S : Sensing capacitance value

V _EXC : Excitation voltage signal

V _EXC1 : First excitation signal

V _EXC2 : Second excitation signal

V _EXC1 ': First limiting excitation signal

V _EXC2 ': Second limiting excitation signal

V _OUT : Output voltage

202: Low voltage differential regulator

204: Scaling circuit

206: P-type transistor

208:Amplifier

210: Select circuit

212,214: Buffer

216,218,503:Multiplexer

VREF: reference voltage

GND: Ground voltage

R1, R2: resistors

V_SCAL_1~V_SCAL_N: scaling voltage

SEL_S,SEL_S’: Select signal

:控制訊號

:Control signal

500: Capacitance measurement circuit

501: Temperature sensor

502: Subtraction circuit

504: Integrator circuit

506: Feedback circuit

510:Analog to digital converter

Figure 1 is a schematic diagram of a charge-to-voltage converter according to the first embodiment of the present invention.

Figure 2 is a schematic diagram of an excitation signal generating circuit according to an embodiment of the present invention.

Figure 3 is a schematic diagram of a charge-to-voltage converter according to the second embodiment of the present invention.

Figure 4 is a schematic diagram of a charge-to-voltage converter according to the third embodiment of the present invention.

Figure 5 is a schematic diagram of a capacitance measurement circuit according to an embodiment of the present invention.

FIG. 1 is a schematic diagram of a charge to voltage converter (CVC) 100 according to a first embodiment of the present invention. As shown in FIG. 1 , the charge to voltage converter 100 may include an excitation signal generating circuit 102, a differential amplifier 104, a switching circuit 106, at least one variable capacitor 108, at least one compensation capacitor 110, a self-calibration capacitor 112, a plurality of driving circuits 114 and 116, and a slew rate (SR) limiter 118, wherein a supply voltage VDD may be supplied to the charge to voltage converter 100, and at least one compensation capacitor 110 may be at least one variable capacitor. In addition, the capacitance sensor 150 is located outside the charge-to-voltage converter 100, wherein the capacitance sensor 150 has a two-terminal connection structure and can be used to sense a sensing capacitance value _CS . The capacitance sensor 150 can be used as a variable element, and the dynamic range of the sensing capacitance value _CS can change with changes in the external environment. The charge-to-voltage converter 100 can be used to generate an output voltage V _OUT (which is a differential output generated by V _OUT+ and V _OUT− ) according to a sensed capacitance value _CS . For example, the sensed capacitance value _CS may include an actual capacitance value to be measured (expressed as “ _CS ′” for simplicity) and a parasitic capacitance value _CP (i.e., _CS =CS _′ + _CP ), wherein at least one compensation capacitor 110 can be used to reduce/offset the parasitic capacitance value _CP from the sensed capacitance value _CS . In addition, when the capacitance sensor 150 is not coupled to the charge-to-voltage converter 100 (i.e., there is no capacitance to be measured), the charge-to-voltage converter 100 may have a floating connection problem. To solve this problem, the self-calibration capacitor 112 can be used to perform a self-calibration operation for the charge-to-voltage converter 100.

The excitation signal generating circuit 102 can be used to generate a first excitation signal V _EXC1 and connect the first excitation signal V _EXC1 to a first terminal of the capacitor sensor 150 through the driving circuit 114 and the slew rate limiter 118, and generate a second excitation signal V _EXC2 and connect the second excitation signal V _EXC2 to at least one compensation capacitor 110 through the driving circuit 116 and the slew rate limiter 118, wherein the first excitation signal V _EXC1 and the second excitation signal V _EXC2 are out-of-phase and non-overlapping, and the voltage amplitude of the first excitation signal V _EXC1 is different from that of the second excitation signal V The voltage amplitude of the first excitation signal V _EXC1 is lower than the voltage amplitude of _{the second excitation signal V EXC2 .} For better understanding, the first excitation signal V _EXC1 may be K1 times the excitation voltage signal V _EXC (i.e., V _EXC1 =K1 * V _EXC ), and the second excitation signal V _EXC2 may be K2 times the excitation voltage signal V _EXC (i.e., V _EXC2 =K2 * V _EXC ). For example, when the parasitic capacitance value _CP is much larger than the capacitance value of at least one compensation capacitor 110, the excitation signal generating circuit 102 may be used to set the voltage amplitude of the first excitation signal V _EXC1 to be lower than the voltage amplitude of the second excitation signal V _EXC2 (i.e., K1<K2).

For details, please refer to FIG. 2 , which is a schematic diagram of an excitation signal generating circuit 200 according to an embodiment of the present invention, wherein the excitation signal generating circuit 102 shown in FIG. 1 can be implemented by the excitation signal generating circuit 200 . As shown in FIG. 2 , the excitation signal generating circuit 200 may include a low dropout regulator (LDO regulator) 202 and a scaling circuit 204. The low dropout regulator 202 may be used to regulate the supply voltage VDD to generate an excitation voltage signal _VEXC (i.e., the input and output of the low dropout regulator 202 are the supply voltage VDD and the excitation voltage signal _VEXC , respectively), and may include a P-type transistor 206 and an amplifier 208. The excitation voltage signal _{VEXC may be a square wave having a frequency value in the frequency range from 32kHz to 500kHz (e.g., a square wave having 32kHz). The excitation voltage signal VEXC} may be a square wave having a frequency value in the frequency range from 32kHz to 500kHz (e.g., a square wave having 32kHz). The high voltage level of _EXC (denoted as "V _EXC+ ") is different from the supply voltage VDD, and the low voltage level of the excitation voltage signal V _EXC (denoted as "V _EXC- ") is different from a ground voltage GND. The P-type transistor 206 has a source terminal coupled to the supply voltage VDD and a drain terminal coupled to the scaling circuit 204. The amplifier 208 has an inverting input terminal (marked as "-" in FIG. 2 ), a non-inverting input terminal (marked as "+" in FIG. 2 ), and an output terminal, wherein the non-inverting input terminal is coupled to a reference voltage VREF, the inverting input terminal is coupled to the scaling circuit 204, and the output terminal is coupled to a gate terminal of the P-type transistor 206. The excitation voltage signal V _EXC is output from the drain terminal of the P-type transistor 206 to the scaling circuit 204.

The scaling circuit 204 can be used to perform a plurality of scaling operations on the excitation voltage signal V _EXC to generate a first excitation signal V _EXC1 and a second excitation signal V _EXC2 . Specifically, the scaling circuit 204 can include a plurality of resistors R1 and R2, a selection circuit 210, and a plurality of buffers 212 and 214, wherein the first excitation signal V _EXC1 and the second excitation signal V _EXC2 can be generated through a configuration between the resistor R1, the resistor R2, and the selection circuit 210. The resistor R1 has a first end coupled to the ground voltage GND and a second end coupled to the inverting input terminal of the amplifier 208. The resistor R2 has a first end coupled to the second end of the resistor R1 and a second end coupled to the drain terminal of the P-type transistor 206. The selection circuit 210 is coupled to the first end of the resistor R2. By changing the ratio between the resistance value of the resistor R1 and the resistance value of the resistor R2, the selection circuit 210 can obtain a plurality of scaling voltages V_SCAL_1~V_SCAL_N (including the first excitation signal _VEXC1 and the second excitation signal _VEXC2 ), where N is an integer greater than 1 (ie, N>1). For example, the setting parameters of the scaling voltages V_SCAL_1-V_SCAL_N may be stored in a register (not shown in FIG. 2 ), and for any one of the first excitation signal V _EXC1 and the second excitation signal V _EXC2 , the selection circuit 210 may be used to select a scaling voltage from the scaling voltages V_SCAL_1-V_SCAL_N from the register.

The selection circuit 210 may include a plurality of N-to-1 multiplexers (MUXs; for example, a plurality of multiplexers 216 and 218), wherein the multiplexer 216 may be used to receive the scaled voltages V_SCAL_1 to V_SCAL_N and output a scaled voltage (for example, the first excitation signal V _EXC1 ) among the scaled voltages V_SCAL_1 to V_SCAL_N to the buffer 212 according to a selection signal SEL_S, and the multiplexer 218 may be used to receive the scaled voltages V_SCAL_1 to V_SCAL_N and output a scaled voltage (for example, the second excitation signal V _EXC2 ) among the scaled voltages V_SCAL_1 to V_SCAL_N according to the selection signal SEL_S. ) is output to the buffer 214, and the selection signal SEL_S may indicate a ratio between the voltage amplitude of the first excitation signal V _EXC1 and the voltage amplitude of the second excitation signal V _EXC2 (eg, a ratio between K1 and K2). For example, when the selection signal SEL_S indicates that the ratio between K1 and K2 is 8 (e.g., K2=8*K1), the selection circuit 210 can select a scaled voltage equal to K1* _VEXC from the scaled voltages V_SCAL_1~V_SCAL_N and output the scaled voltage to the buffer 212, and select another scaled voltage equal to 8*K1* _VEXC from the scaled voltages V_SCAL_1~V_SCAL_N and output the other scaled voltage to the buffer 214.

The buffer 212 can be used to receive the first excitation signal V _EXC1 from the selection circuit 210 (especially the multiplexer 216), and connect the first excitation signal V _EXC1 to the first end of the capacitor sensor 150 through the driving circuit 114 and the slew rate limiter 118. The buffer 214 can be used to receive the second excitation signal V _EXC2 from the selection circuit 210 (especially the multiplexer 218), and connect the second excitation signal V _EXC2 to at least one compensation capacitor 110 through the driving circuit 116 and the slew rate limiter 118.

Referring back to FIG. 1 , since the scaled voltage (e.g., the first excitation signal V _EXC1 and the second excitation signal V _EXC2 ) may have poor driving capability, the driving circuit 114 may be used to self-excite the signal generating circuit 102/200 (especially, the buffer 212) to receive the first excitation signal V _EXC1 and drive the capacitor sensor 150 according to the first excitation signal V _EXC1 , and the driving circuit 116 may be used to self-excite the signal generating circuit 102/200 (especially, the buffer 214) to receive the second excitation signal V _EXC2 and drive at least one compensation capacitor 110 according to the second excitation signal V _EXC2 . In this embodiment, each of the driver circuits 114 and 116 is a push-pull driver, wherein the push-pull driver is a digital driver circuit composed of a P-type transistor and an N-type transistor connected in series, but the present invention is not limited thereto. In some embodiments, each of the driver circuits 114 and 116 may include a plurality of switches (e.g., a plurality of transmission gates). In some embodiments, the driver circuits 114 and 116 may be a combination of a push-pull driver and a plurality of switches, wherein one of the driver circuits 114 and 116 is a push-pull driver and the other of the driver circuits 114 and 116 may include a plurality of transmission gates.

In the case where the first excitation signal V _EXC1 and the second excitation signal V _EXC2 are directly driven by the circuits 114 and 116 to connect to the capacitor sensor 150 and at least one compensation capacitor 110, the square wave may rise and fall sharply between a high voltage level and a low voltage level, which may cause electromagnetic interference (EMI) and interfere with nearby electronic components. To solve this problem, the slew rate limiter 118 can be used to perform slew rate limiting operations on the first excitation signal V _EXC1 and the second excitation signal V _EXC2 , respectively, to generate and connect a first limited excitation signal V _EXC1 to the first end of the capacitor sensor 150, and to generate and connect a second limited excitation signal V _EXC2 to the first end of the capacitor sensor 150. ' to at least one compensation capacitor 110.

The differential amplifier 104 has an inverting input terminal (marked as "-" in FIG. 1), a non-inverting input terminal (marked as "+" in FIG. 1), a non-inverting output terminal (i.e., a terminal outputting a first differential output voltage V _OUT+ ) and an inverting output terminal (i.e., a terminal outputting a second differential output voltage V _OUT- ), wherein the inverting input terminal can be coupled to at least one compensation capacitor 110, the self-calibration capacitor 112 and the capacitance sensor 150, and can be used to receive the sensed capacitance value C _S from a second terminal of the capacitance sensor 150; the non-inverting input terminal can be coupled to a common-mode voltage (marked as "VCM" in FIG. 1); and the output voltage V _OUT is the voltage difference between the inverting output terminal and the non-inverting output terminal of the differential amplifier 104 (i.e., V _OUT =V _OUT+ −V _OUT− ). The switch circuit 106 can be coupled between the inverting input terminal and the non-inverting output terminal of the differential amplifier 104, wherein the switch circuit 106 is controlled by a control signal in-phase with the first excitation signal V _EXC1 (i.e., the control signal is in-phase with the second excitation signal V _EXC2 ). For example, the control signal may be a clock signal Φ _R , wherein the clock signal Φ _R may be a square wave having a frequency value in a frequency range from 32 kHz to 500 kHz (e.g., a square wave having 32 kHz), a high voltage level of the clock signal Φ _R may be the supply voltage VDD, and a low voltage level of the clock signal Φ _R may be the ground voltage GND.

其中V_EXC1係第一激勵訊號V_EXC1的電壓振幅，C_S係感測電容值C_S，V_EXC2係第二激勵訊號V_EXC2的電壓振幅，C_DAC係至少一補償電容110的電容值，以及C_i係至少一可變電容108的電容值。 In this embodiment, it is assumed that the switch circuit 106 is closed when the clock signal Φ _R is at a high voltage level (for example, the supply voltage VDD), and that the switch circuit 106 is open when the clock signal Φ _R is at a low voltage level (for example, the ground voltage GND). In addition, the switch circuit 106 and at least one variable capacitor 108 are connected in parallel between the inverting input terminal and the non-inverting output terminal of the differential amplifier 104. At least one compensation capacitor 110 may have a plurality of capacitance values to be selected. For example, at least one compensation capacitor 110 may be configured to be a certain value equal to or close to the parasitic capacitance value _CP (e.g., a capacitance value selected from a plurality of capacitance values) to reduce/offset the parasitic capacitance according to the second excitation signal _VEXC2 . Through the configuration between the differential amplifier 104, the switch circuit 106 and the at least one variable capacitor 108, the output voltage _VOUT may be obtained by the following formula:

Wherein V _EXC1 is the voltage amplitude of the first excitation signal V _EXC1 , _CS is the sensing capacitance _CS , V _EXC2 is the voltage amplitude of the second excitation signal V _EXC2 , C _DAC is the capacitance of at least one compensation capacitor 110 , and _Ci is the capacitance of at least one variable capacitor 108 .

其中V_EXC係激勵電壓訊號V_EXC的電壓振幅。在感測電容值C_S中的寄生電容值C_P遠大於(例如10倍於)至少一補償電容110的電容值的情況下，可藉由激勵訊號產生電路102/200來將K2設置為K1的10倍(例如K2=10 * K1)，如此一來，寄生電容值C_P可成功地被至少一補償電容110所減少/抵銷。 In addition, when the first excitation signal V _EXC1 is K1 times the excitation voltage signal V _EXC (ie, V _EXC1 =K1 * V _EXC ) and the second excitation signal V _EXC2 is K2 times the excitation voltage signal V _EXC (ie, V _EXC2 =K2 * V _EXC ), the above formula can be simplified as follows:

Wherein V _EXC is the voltage amplitude of the excitation voltage signal V _EXC . When the parasitic capacitance value C _P in the sense capacitance value C _S is much larger (e.g., 10 times) than the capacitance value of at least one compensation capacitor 110, the excitation signal generating circuit 102 / 200 can be used to set K2 to 10 times of K1 (e.g., K2=10*K1), so that the parasitic capacitance value C _P can be successfully reduced/offset by at least one compensation capacitor 110.

FIG. 3 is a schematic diagram of a charge-to-voltage converter 300 according to a second embodiment of the present invention, wherein the difference between the charge-to-voltage converter 300 shown in FIG. 3 and the charge-to-voltage converter 100 shown in FIG. 1 is that the driving circuits 114 and 116 in the charge-to-voltage converter 100 are modified to be implemented by the driving circuits 302 and 304 of the charge-to-voltage converter 300, respectively. When the voltage level of the scaling voltage (e.g., the first excitation signal V _EXC1 ) is lower than the threshold voltage level of the P-type transistor and/or the N-type transistor, the P-type transistor and/or the N-type transistor in the push-pull driver may not operate normally, which causes the push-pull driver to fail to operate normally and therefore fail to have driving capability. To solve this problem, multiple switches (e.g., multiple transmission gates) that are not affected by the voltage level of the scaling voltage can be embedded in each of the driving circuits 302 and 304 of the charge-to-voltage converter 300.

Specifically, the driving circuit 302 may include a plurality of switch circuits 306 and 308, wherein the switch circuit 306 has a first end and a second end, wherein the first end of the switch circuit 306 is used for the self-excitation signal generating circuit 102 to receive the high voltage level of the first excitation signal V _EXC1 (expressed as “V _EXC1+ ”), and the switch circuit 306 is controlled by a control signal (e.g., a clock signal Φ _R ) in phase with the first excitation signal V _EXC1 to connect the high voltage level of the first excitation signal V _EXC1 to the second end of the switch circuit 306. Assume that when the clock signal Φ _R is at a high voltage level (ie, the first excitation signal V _EXC1 is also at a high voltage level), the switch circuit 306 is closed, and when the clock signal Φ _R is at a low voltage level (ie, the first excitation signal V _EXC1 is also at a low voltage level), the switch circuit 306 is opened.

所控制，以將第一激勵訊號V_EXC1的低電壓位準連接至開關電路308的第二端。假設當控制訊號

位於高電壓位準(亦即第一激勵訊號V_EXC1位於低電壓位準)時開關電路308係關閉的，以及當控制訊號

位於低電壓位準(亦即第一激勵訊號V_EXC1位於高電壓位準)時開關電路308係開啟的。電容感測器150係透過迴轉率限制器118來耦接於開關電路306的第二端以及開關電路308的第二端。 The switch circuit 308 has a first terminal and a second terminal, wherein the first terminal of the switch circuit 308 is used to receive the low voltage level (denoted as "V _EXC1- ") of the first excitation signal V _EXC1 from the excitation signal generating circuit 102, and the switch circuit 308 is driven by a control signal that is inverted from the first excitation signal V _EXC1.

is controlled to connect the low voltage level of the first excitation signal V _EXC1 to the second end of the switch circuit 308. Assuming that the control signal

When the first excitation signal V EXC1 is at a high voltage level (i.e., the first excitation signal V _EXC1 is at a low voltage level), the switch circuit 308 is closed, and when the control signal

When the first excitation signal V EXC1 is at a low voltage level (ie, the first excitation signal V _EXC1 is at a high voltage level), the switch circuit 308 is turned on. The capacitance sensor 150 is coupled to the second terminal of the switch circuit 306 and the second terminal of the switch circuit 308 through the slew rate limiter 118 .

所控制，以將第二激勵訊號V_EXC2的高電壓位準連接至開關電路310的第二端。假設當控制訊號

位於高電壓位準(亦即第二激勵訊號V_EXC2亦位於高電壓位準)時開關電路310係關閉的，以及當控制訊號

位於低電壓位準(亦即第二激勵訊號V_EXC2亦位於低電壓位準)時開關電路310係開啟的。 The driving circuit 304 may include a plurality of switch circuits 310 and 312. The switch circuit 310 has a first terminal and a second terminal. The first terminal of the switch circuit 310 is used to receive the high voltage level (expressed as "V _EXC2+ ") of the second excitation signal V _EXC2 from the excitation signal generating circuit 102, and the switch circuit 310 is controlled by a control signal that is inverted from the first excitation signal V _EXC1.

is controlled to connect the high voltage level of the second excitation signal V _EXC2 to the second end of the switch circuit 310. Assuming that the control signal

When the second excitation signal V EXC2 is at a high voltage level (i.e., the second excitation signal V _EXC2 is also at a high voltage level), the switch circuit 310 is closed, and when the control signal

When the voltage level is low (ie, the second excitation signal V _EXC2 is also at a low voltage level), the switch circuit 310 is turned on.

The switch circuit 312 has a first end and a second end, wherein the first end of the switch circuit 312 is used for the self-excitation signal generating circuit 102 to receive the low voltage level of the second excitation signal V _EXC2 (denoted as “V _EXC2− ”), and the switch circuit 312 is controlled by a control signal (e.g., a clock signal Φ _R ) in phase with the first excitation signal V _EXC1 to connect the low voltage level of the second excitation signal V _EXC2 to the second end of the switch circuit 312. Assuming that the switch circuit 312 is closed when the clock signal _ΦR is at a high voltage level (i.e., the second excitation signal _VEXC2 is at a low voltage level), and the switch circuit 312 is opened when the clock signal _ΦR is at a low voltage level (i.e., the second excitation signal _VEXC2 is at a high voltage level), at least one compensation capacitor 110 is coupled to the second end of the switch circuit 310 and the second end of the switch circuit 312 through the slew rate limiter 118.

FIG. 4 is a schematic diagram of a charge-to-voltage converter 400 according to a third embodiment of the present invention, wherein the difference between the charge-to-voltage converter 400 shown in FIG. 4 and the charge-to-voltage converter 100 shown in FIG. 1 is that the driving circuits 114 and 116 in the charge-to-voltage converter 100 are modified to be implemented by the driving circuits 402 and 404 of the charge-to-voltage converter 400, respectively. In this embodiment, since the scaling range (e.g., reduction range) corresponding to the first excitation signal V _EXC1 is too small, the voltage level of the first excitation signal V _EXC1 is not large enough to drive the push driver, while the second excitation signal V _EXC2 can still drive the push driver normally. To solve this problem, the driver circuit 402 includes a plurality of switches (e.g., a plurality of transmission gates, such as a plurality of switch circuits 406 and 408) that are not affected by the voltage level of the scaling voltage, and the driver circuit 404 can still be implemented by the push driver. Since a person skilled in the art can be familiar with the operation of the charge-to-voltage converter 400 through the relevant paragraphs of the instructions of the charge-to-voltage converter 100 shown in FIG. 1 and the charge-to-voltage converter 300 shown in FIG. 3 , a detailed description will not be repeated here for the sake of brevity.

FIG. 5 is a schematic diagram of a capacitance measuring circuit 500 according to an embodiment of the present invention, wherein the capacitance measuring circuit 500 is a capacitance to digital converter (CDC). As shown in FIG. 5 , the capacitance measuring circuit 500 may include at least the charge to voltage converter 100 shown in FIG. 1 and an analog to digital converter (ADC) 510, and further includes a temperature sensor 501 and a 2 to 1 multiplexer (e.g., multiplexer 503), wherein the analog to digital converter 510 may be used to convert the output voltage V _OUT into a digital pulse stream D_S. In the present embodiment, the analog-to-digital converter 510 is a sigma-delta ADC, but the present invention is not limited thereto. In fact, the analog-to-digital converter 510 may adopt any analog-to-digital converter architecture that can convert the output voltage V _OUT into a digital pulse current D_S, and these alternative designs all fall within the scope of the present invention.

In addition, since the dynamic range of the sensing capacitance value C _S may change with the external environment, the temperature sensor 501 can be used to sense the ambient temperature to generate the temperature data TEM_D. The multiplexer 503 can be used to receive the output voltage V _OUT from the charge-to-voltage converter 100, receive the temperature data TEM_D from the temperature sensor 501, and output one of the output voltage V _OUT and the temperature data TEM_D to the analog-to-digital converter 510 according to a selection signal SEL_S', wherein the analog-to-digital converter 510 can fine-tune the sensing capacitance value C _S according to the temperature data TEM_D.

The analog-to-digital converter 510 may include at least a subtraction circuit 502, an integrator circuit 504, and a feedback circuit 506. The subtraction circuit 502 may be used to receive the output voltage V _OUT from the charge-to-voltage converter 100 and generate an output voltage V _OUT subtracts a feedback signal F_S to generate a processed signal P_S. The integrator circuit 504 may be coupled to the subtractor circuit 502 and may be used to integrate the processed signal P_S to generate a digital pulse stream D_S. The feedback circuit 506 may be coupled to the subtractor circuit 502 and the integrator circuit 504 and may be used to obtain the feedback signal F_S from the digital pulse stream D_S and transmit the feedback signal F_S to the subtractor circuit 502. Since the trigonometric analog-to-digital converter is well known to those skilled in the art, the details of the analog-to-digital converter 510 are not described herein for brevity.

In summary, the capacitance measurement circuit of the present invention (which includes a charge-to-voltage converter and an analog-to-digital converter) can generate multiple excitation signals with different voltage amplitudes to an external capacitance sensor and a capacitance measurement circuit of at least one internal compensation capacitor, respectively. When the parasitic capacitance value in the sensed capacitance value of the capacitor to be measured is much larger than the capacitance value of at least one compensation capacitor, the charge-to-voltage converter of the present invention can utilize the at least one compensation capacitor to successfully reduce/offset the parasitic capacitance value by using the excitation signals with different voltage amplitudes. In this way, the voltage amplitude of the output voltage of the charge-to-voltage converter will not exceed the input dynamic range of the analog-to-digital converter, which allows the analog-to-digital converter to operate normally.

The above is only the preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100,: Charge to voltage converter

102: Excitation signal generating circuit

104: Differential amplifier

106: Switching circuit

108: At least one variable capacitor

110: At least one compensation capacitor

112: Self-calibration capacitor

114,116:Drive circuit

118: Slew rate limiter

150: Capacitor sensor

Φ _R : Clock signal

V _OUT+ : First differential output voltage

V _OUT- : Second differential output voltage

C _S : Sensing capacitance value

V _EXC : Excitation voltage signal

V _EXC1 : First excitation signal

V _EXC2 : Second excitation signal

V _EXC1 ': First limiting excitation signal

V _EXC2 ': Second limiting excitation signal

V _OUT : Output voltage

Claims (17)

A capacitance measuring circuit comprises: a charge-to-voltage converter, comprising: at least one first variable capacitor, wherein a parasitic capacitance value in a sensed capacitance value measured by a capacitance sensor is reduced by the at least one first variable capacitor; an excitation signal generating circuit, for generating and connecting a first excitation signal to a first end of the capacitance sensor, and generating and connecting a second excitation signal to the at least one first variable capacitor, wherein the first excitation signal and the second excitation signal are in anti-phase, and a voltage amplitude of the first excitation signal is different from a voltage amplitude of the second excitation signal; a differential amplifier having an inverting input terminal, a non-inverting input terminal, an inverting output terminal and a non-inverting output terminal, wherein the inverting input terminal is used to receive the sensed capacitance value from a second terminal of the capacitance sensor; a first switching circuit coupled between the inverting input terminal and the non-inverting output terminal of the differential amplifier; and at least one second variable capacitor, wherein the first switching circuit and the at least one second variable capacitor are connected in parallel between the inverting input terminal and the non-inverting output terminal of the differential amplifier. As described in item 1 of the patent application scope, the capacitance measurement circuit, wherein the voltage amplitude of the first excitation signal is smaller than the voltage amplitude of the second excitation signal. As described in the first item of the patent application scope, the excitation signal generating circuit includes: a low voltage difference regulator for regulating a supply voltage to generate an excitation voltage signal, wherein the supply voltage is supplied to the charge-to-voltage converter; and a scaling circuit for performing multiple scaling operations on the excitation voltage signal to generate and connect the first excitation signal to the first end of the capacitance sensor, and generate and connect the second excitation signal to the at least one first variable capacitor. As described in item 3 of the patent application scope, the capacitance measuring circuit, wherein the low voltage difference regulator comprises: a P-type transistor having a source terminal coupled to the supply voltage and a drain terminal coupled to the scaling circuit; and an amplifier having an inverting input terminal, a non-inverting input terminal and an output terminal, wherein the non-inverting input terminal is coupled to a first reference voltage, the inverting input terminal is coupled to the scaling circuit, and the output terminal is coupled to a gate terminal of the P-type transistor; wherein the excitation voltage signal is output from the drain terminal of the P-type transistor to the scaling circuit. As described in item 4 of the patent application scope, the capacitance measuring circuit includes: a first resistor having a first end coupled to a second reference voltage and a second end coupled to the inverting input end of the amplifier; a second resistor having a first end coupled to the second end of the first resistor and a second end coupled to the drain end of the P-type transistor; and a selection circuit coupled to the first end of the second resistor; wherein the first excitation signal and the second excitation signal are generated through a configuration between the first resistor, the second resistor and the selection circuit. As described in item 5 of the patent application scope, the scaling circuit further comprises: a first buffer for receiving the first excitation signal from the selection circuit and connecting the first excitation signal to the first end of the capacitance sensor; and a second buffer for receiving the second excitation signal from the selection circuit and connecting the second excitation signal to the at least one first variable capacitor. As described in item 5 of the patent application scope, the charge-to-voltage converter further comprises: a first driving circuit for receiving the first excitation signal from the excitation signal generating circuit and driving the capacitance sensor according to the first excitation signal; and a second driving circuit for receiving the second excitation signal from the excitation signal generating circuit and driving the at least one first variable capacitor according to the second excitation signal. A capacitance measuring circuit as described in Item 7 of the patent application, wherein each of the first drive circuit and the second drive circuit is a push-pull drive. As described in Item 7 of the patent application scope, the capacitance measuring circuit, wherein each of the first driving circuit and the second driving circuit includes a plurality of switches. The capacitance measuring circuit as described in item 9 of the patent application, wherein the first driving circuit comprises: a second switching circuit having a first end and a second end, wherein the first end of the second switching circuit is used to receive a high voltage level of the first excitation signal from the excitation signal generating circuit, the second switching circuit is controlled by a first control signal to connect the high voltage level of the first excitation signal to the second end of the second switching circuit, and the first control signal is in phase with the first excitation signal; and a third switching circuit having a first end and a second end. The third switch circuit has a first end and a second end, wherein the first end of the third switch circuit is used to receive a low voltage level of the first excitation signal from the excitation signal generating circuit, the third switch circuit is controlled by a second control signal to connect the low voltage level of the first excitation signal to the second end of the third switch circuit, and the second control signal is inversely proportional to the first excitation signal; wherein the first end of the capacitance sensor is coupled to the second end of the second switch circuit and the second end of the third switch circuit. The capacitance measuring circuit as described in item 9 of the patent application, wherein the second driving circuit comprises: a second switching circuit having a first end and a second end, wherein the first end of the second switching circuit is used to receive a high voltage level of the second excitation signal from the excitation signal generating circuit, the second switching circuit is controlled by a first control signal to connect the high voltage level of the second excitation signal to the second end of the second switching circuit, and the first control signal is in antiphase with the first excitation signal; and a third switching circuit having a first end and a second end. The third switch circuit has a first end and a second end, wherein the first end of the third switch circuit is used for the excitation signal generating circuit to receive a low voltage level of the second excitation signal, the third switch circuit is controlled by a second control signal to connect the low voltage level of the second excitation signal to the second end of the third switch circuit, and the second control signal and the second excitation signal are in phase; wherein the at least one first variable capacitor is coupled to the second end of the second switch circuit and the second end of the third switch circuit. As described in item 7 of the patent application scope, the capacitance measuring circuit, wherein one of the first driving circuit and the second driving circuit is a push-pull driver, and the other of the first driving circuit and the second driving circuit includes a plurality of switches. The capacitance measuring circuit as described in item 12 of the patent application scope, wherein the first driving circuit includes the plurality of switches, and the second driving circuit is the push-pull driver. As described in the first item of the patent application scope, the charge-to-voltage converter further includes: a slew rate limiter for performing a slew rate limiting operation on the first excitation signal and the second excitation signal respectively to generate a first limited excitation signal and a second limited excitation signal. As described in the first item of the patent application scope, the charge-to-voltage converter further comprises: a self-calibration capacitor for performing a self-calibration operation for the charge-to-voltage converter. As described in item 1 of the patent application scope, the charge-to-voltage converter is used to generate an output voltage according to the sensed capacitance value; and the capacitance measurement circuit is a capacitance-to-digital converter, and further includes: an analog-to-digital converter for converting the output voltage into a digital pulse current. The capacitance measuring circuit as described in claim 16, wherein the analog-to-digital converter is a delta-integral analog-to-digital converter, and the delta-integral analog-to-digital converter at least comprises: a subtraction circuit for receiving the output voltage from the charge-to-voltage converter and subtracting a feedback signal from the output voltage to generate a processed signal; an integrator circuit coupled to the subtraction circuit and used to integrate the processed signal to generate the digital pulse stream; and a feedback circuit coupled to the integrator circuit and the subtraction circuit and used to obtain the feedback signal from the digital pulse stream and transmit the feedback signal to the subtraction circuit.

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