TWI849885B - Semiconductor device and method of fabricating the same - Google Patents

Abstract

A semiconductor device includes a staircase structure and an extension part. The stacked structure is located on a dielectric substrate. The staircase structure includes a plurality of conductive layers and a plurality of insulating layers stacked alternately on each other. The extension part is located at an end of the lower stair part of the staircase structure. The resistance value of the extension part is different from the resistance value of the plurality of conductive layers.

Description

Semiconductor device and method for manufacturing the same

The present invention relates to an integrated circuit and a method for manufacturing the same, and in particular to a semiconductor element and a method for manufacturing the same.

Non-volatile memory has the advantage that the stored data will not disappear after power failure, so it is widely used in personal computers and other electronic devices. The three-dimensional memories commonly used in the industry include NOR memory and NAND memory. In addition, another type of three-dimensional memory is AND memory, which can be applied to multi-dimensional memory arrays and has high integration and high area utilization, and has the advantages of fast operation speed. Therefore, the development of three-dimensional memory devices has gradually become the current trend. However, there are still many challenges related to three-dimensional memory devices.

The present invention provides a semiconductor element that can have a charge conduction path to reduce arc effects and prevent the various material layers and components on the dielectric substrate from being damaged by plasma bombardment.

According to an embodiment of the present invention, a semiconductor element includes a step structure and an extension portion. The step structure is located on a dielectric substrate. The step structure includes a plurality of conductive layers and a plurality of insulating layers stacked alternately with each other. The extension portion is at the end of the lower step of the step structure. The extension portion and the plurality of conductive layers have different resistance values.

According to an embodiment of the present invention, a method for manufacturing a semiconductor element includes the following steps. Forming a step structure on a dielectric substrate, wherein the step structure includes a plurality of conductor layers and a plurality of insulating layers alternately stacked with each other. Forming an extension portion at the end of the lower step of the step structure. The extension portion and the plurality of conductor layers have different resistance values.

Based on the above, in an embodiment of the present invention, one or more semiconductor layers located at the bottom of the stacked structure can be used as a conduction path for electric charge to reduce arcing effect and prevent the material layers and components on the dielectric substrate from being damaged by plasma bombardment, thereby improving the yield of the process. In addition, the one or more semiconductor layers can be replaced in a subsequent process to form one or more conductive layers, which can then be used as a gate layer or a dummy gate layer.

10. A ⁽ⁱ⁾ , A ⁽ⁱ⁺¹⁾ : memory array

12: Charge storage layer

14, 114: Tunneling layer

16, 116: Channel column

20: Memory unit

24: Insulation filling layer

28: Insulation Pillar

32a: First conductor column/source column

32b: Second conductor column/drain column

36, 37: barrier layer

38: Gate layer/conductor layer/word line

38g, 138g: Conductive layer

38v, 138v: Connector

40, 140: Charge storage structure

50, 100: Dielectric substrate

50s: Surface

54, 92, 104, 142: Insulation layer

60: Arrow

94, 94 _T : semiconductor layer

95: Mask layer

96: Communication Department

106: Middle layer

107: Dielectric layer

108: Opening

110: Protective layer

112: Storage layer

117: Connecting opening

119, 121: Horizontal opening

124: Insulation filling layer

128: Insulation Pillar

132a, 132b: Conductor column

133: Separation groove

136: Barrier layer

137: Barrier layer

138: Gate layer/conductor layer/word line

BP: Lower part

COA1, COA2: Contact window

DV: Support column

EP: Extension

GSK, SK1, SK2: stacking structure

H1, H2: height

LP: Low-level

OP1: Open mouth

SC: Step structure

SLT:Separation wall

TP: High-end department

UP: Upper part

VC: Vertical Column

W: Diameter

I-I’, II-II’: tangent

BLOCK, BLOCK ⁽ⁱ⁾ , BLOCK ⁽ⁱ⁺¹⁾ : block

BL _n , BL _n+1 : bit line

SP ⁽ⁱ⁾ _n , SP ⁽ⁱ⁾ _n+1 , SP ⁽ⁱ⁺¹⁾ _n , SP ⁽ⁱ⁺¹⁾ _n+1 : source pillar

DP ⁽ⁱ⁾ _n , DP ⁽ⁱ⁾ _n+1 , DP ⁽ⁱ⁺¹⁾ _n , DP ⁽ⁱ⁺¹⁾ _n+1 : drain column

WL ⁽ⁱ⁾ _m , WL ⁽ⁱ⁾ _m+1 , WL ⁽ⁱ⁺¹⁾ _m , WL ⁽ⁱ⁺¹⁾ _m+1 : character line

FIG. 1A illustrates a circuit diagram of a 3D AND flash memory array according to some embodiments.

FIG1B shows a partial three-dimensional view of the memory array of the portion in FIG1A .

Figures 1C and 1D show cross-sectional views of the cut line I-I’ of Figure 1B.

FIG. 1E shows a top view of the tangent line II-II’ of FIG. 1B , FIG. 1C , and FIG. 1D .

Figures 1F to 1I show cross-sectional schematic diagrams of various step structures.

Figures 2A to 2I are cross-sectional schematic diagrams of a manufacturing process of a memory element according to an embodiment of the present invention.

Figures 3A and 3B show top views of several ladder structures of memory devices according to an embodiment of the present invention.

Figures 4A to 4F are schematic cross-sectional diagrams showing a process of manufacturing a memory device according to another embodiment of the present invention.

Figures 5A and 5B show top views of several ladder structures of a memory element according to another embodiment of the present invention.

FIG. 1A shows a circuit diagram of a 3D AND flash memory array according to some embodiments. FIG. 1B shows a partial three-dimensional view of a portion of the memory array in FIG. 1A . FIG. 1C and FIG. 1D show cross-sectional views of the cut line I-I’ of FIG. 1B . FIG. 1E shows a top view of the cut line II-II’ of FIG. 1B , FIG. 1C , and FIG. 1D .

FIG1A is a schematic diagram of two blocks BLOCK ⁽ⁱ⁾ and BLOCK ⁽ⁱ⁺¹⁾ of a vertical AND memory array 10 arranged in rows and columns. Block BLOCK ⁽ⁱ⁾ includes a memory array A ⁽ⁱ⁾ . A column (e.g., the m+1th column) of the memory array A ⁽ⁱ⁾ is a set of AND memory cells 20 having a common word line (e.g., WL ⁽ⁱ⁾ _m+1 ). The AND memory cells 20 in each column (e.g., the m+1th column) of the memory array A ⁽ⁱ⁾ correspond to a common word line (e.g., WL ⁽ⁱ⁾ _m+1 ) and are coupled to different source poles (e.g., SP ⁽ⁱ⁾ _n and SP ⁽ⁱ⁾ _n+1 ) and drain poles (e.g., DP ⁽ⁱ⁾ _n and DP ⁽ⁱ⁾ _n+1 ), so that the AND memory cells 20 are logically arranged in a row along the common word line (e.g., WL ⁽ⁱ⁾ _m+1 ).

A row (e.g., the nth row) of the memory array A ⁽ⁱ⁾ is a set of AND memory cells 20 having a common source column (e.g., SP ⁽ⁱ⁾ _n ) and a common drain column (e.g., DP ⁽ⁱ⁾ _n ). The AND memory cells 20 of each row (e.g., the nth row) of the memory array A ⁽ⁱ⁾ correspond to different word lines (e.g., WL ⁽ⁱ⁾ _m+1 and WL ⁽ⁱ⁾ _m ) and are coupled to a common source column (e.g., SP ⁽ⁱ⁾ _n ) and a common drain column (e.g., DP ⁽ⁱ⁾ _n ). Therefore, the AND memory cells 20 of the memory array A ⁽ⁱ⁾ are logically arranged in a row along the common source column (e.g., SP ⁽ⁱ⁾ _n ) and the common drain column (e.g., DP ⁽ⁱ⁾ _n ). In the physical layout, depending on the manufacturing method applied, the rows or columns may be twisted, arranged in a honeycomb pattern or otherwise for high density or other reasons.

In FIG. 1A , in block BLOCK ⁽ⁱ⁾ , the AND memory cells 20 in the nth row of the memory array A ⁽ⁱ⁾ share a common source column (e.g., SP ⁽ⁱ⁾ _n ) and a common drain column (e.g., DP ⁽ⁱ⁾ _n ). The AND memory cells 20 in the n+1th row share a common source column (e.g., SP ⁽ⁱ⁾ _n+1 ) and a common drain column (e.g., DP ⁽ⁱ⁾ _n+1 ).

A common source column (e.g., SP ⁽ⁱ⁾ _n ) is coupled to a common source line (e.g., SL _n ); a common drain column (e.g., DP ⁽ⁱ⁾ _n ) is coupled to a common bit line (e.g., BL _n ). A common source column (e.g., SP ⁽ⁱ⁾ _n+1 ) is coupled to a common source line (e.g., SL _n+1 ); a common drain column (e.g., DP ⁽ⁱ⁾ _n+1 ) is coupled to a common bit line (e.g., BL _n+1 ).

Similarly, block BLOCK ⁽ⁱ⁺¹⁾ includes a memory array A ⁽ⁱ⁺¹⁾ that is similar to the memory array A ⁽ⁱ⁾ in block BLOCK ⁽ⁱ⁾ . A row (e.g., the m+1th row) of the memory array A ⁽ⁱ⁺¹ ) is a set of AND memory cells 20 having a common word line (e.g., WL ⁽ⁱ⁺¹⁾ _m+1 ). Each row (e.g., the m+1th row) of the memory array A ⁽ⁱ⁺ 1) corresponds to the common word line (e.g., WL ⁽ⁱ⁺¹⁾ _m+1 ) and is coupled to different source poles (e.g., SP ⁽ⁱ⁺¹⁾ _n and SP ⁽ⁱ⁺¹⁾ _n+1 ) and drain poles (e.g., DP ⁽ⁱ⁺¹⁾ _n and DP ⁽ⁱ⁺¹⁾ _n+1 ). A row (e.g., the nth row) of the memory array A ⁽ⁱ⁺¹⁾ is a set of AND memory cells 20 having a common source pole (e.g., SP ⁽ⁱ⁺¹⁾ _n ) and a common drain pole (e.g., DP ⁽ⁱ⁺¹⁾ _n ). The AND memory cells 20 of each row (e.g., the nth row) of the memory array A ⁽ⁱ⁺¹⁾ correspond to different word lines (e.g., WL ⁽ⁱ⁺¹⁾ _m+1 and WL ⁽ⁱ⁺¹⁾ _m ) and are coupled to a common source pole (e.g., SP ⁽ⁱ⁺¹⁾ _n ) and a common drain pole (e.g., DP ⁽ⁱ⁺¹⁾ _n ). Therefore, the AND memory cells 20 of the memory array A ⁽ⁱ⁺¹⁾ are logically arranged in a row along a common source pole (eg, SP ⁽ⁱ⁺¹⁾ _n ) and a common drain pole (eg, DP ⁽ⁱ⁺¹⁾ _n ).

Block BLOCK ⁽ⁱ⁺¹⁾ and block BLOCK ⁽ⁱ⁾ share a source line (e.g., SL _n and SL _n+1 ) and a bit line (e.g., BL _n and BL _n+1 ). Therefore, source line SL _n and bit line BL _n are coupled to the n-th row AND memory cell 20 in AND memory array A ⁽ⁱ⁾ of block BLOCK ⁽ i), and are coupled to the n-th row AND memory cell 20 in AND memory array A (i ^{+1) of block BLOCK ( i+1)} . Similarly, source line SLn ₊₁ and bit line BLn ₊₁ are coupled to the n+1th row AND memory cell 20 in AND memory array A ⁽ⁱ⁾ of block BLOCK ⁽ⁱ⁾ , and are coupled to the n+1th row AND memory cell 20 in AND memory array A ⁽ⁱ⁺¹⁾ in block BLOCK ⁽ⁱ⁺¹⁾ .

Referring to FIG. 1B to FIG. 1D , the memory array 10 may be disposed on the internal connection structure of the semiconductor die, for example, disposed above one or more active elements (such as transistors) formed on the semiconductor substrate. Therefore, the dielectric substrate (or dielectric layer) 50 is, for example, a dielectric layer formed above the internal connection structure on the silicon substrate, such as a silicon oxide layer. The memory array 10 may include a stacked structure GSK, a plurality of channel pillars 16, a plurality of first conductive pillars (also referred to as source pillars) 32a and a plurality of second conductive pillars (also referred to as drain pillars) 32b and a plurality of charge storage structures 40.

1B , a stacked structure GSK is formed on a dielectric substrate 50. The stacked structure GSK includes a plurality of gate layers (also referred to as word lines or conductor layers) 38 and a plurality of insulating layers 54 vertically stacked on a surface 50s of the dielectric substrate 50. In the Z direction, these gate layers 38 are electrically isolated by the insulating layers 54 disposed therebetween. The gate layers 38 extend in a direction parallel to the surface of the dielectric substrate 50. The gate layers 38 of the step region may have a step structure SC, as shown in FIGS. 1F to 1I . Therefore, the lower gate layer 38 is longer than the upper gate layer 38, and the end of the lower gate layer 38 extends laterally beyond the end of the upper gate layer 38. A contact window (not shown) for connecting the gate layer 38 can be landed at the end of the gate layer 38 to connect each layer of the gate layer 38 to each wire.

Referring to FIG. 1B to FIG. 1D , the memory array 10 further includes a plurality of channel pillars 16. In some embodiments, the channel pillars 16 may have a ring-shaped profile when viewed from above. The material of the channel pillars 16 may be a semiconductor, such as undoped polysilicon.

1B to 1D , the memory array 10 further includes an insulating column 28, a plurality of first conductive columns 32a, and a plurality of second conductive columns 32b. In this example, the first conductive column 32a serves as a source column; and the second conductive column 32b serves as a drain column. The first conductive column 32a, the second conductive column 32b, and the insulating column 28 each extend in a direction (i.e., the Z direction) perpendicular to the surface (i.e., the XY plane) of the gate layer 38. The first conductive column 32a and the second conductive column 32b are separated by the insulating column 28 and surrounded by the insulating filling layer 24. The first conductive column 32a and the second conductive column 32b are electrically connected to the channel column 16. The first conductive pillar 32a and the second conductive pillar 32b include doped polysilicon or metal material. The insulating pillar 28 is, for example, silicon nitride or silicon oxide, and the insulating filling layer 24 is, for example, silicon oxide.

1C and 1D , the charge storage structure 40 is disposed between the channel pillar 16 and a plurality of gate layers (or conductor layers) 38. The charge storage structure 40 may include a tunneling layer (or a gap-engineered tunneling oxide layer) 14, a charge storage layer 12, and a blocking layer 36. The charge storage layer 12 is located between the tunneling layer 14 and the blocking layer 36. In some embodiments, the tunneling layer 14 and the blocking layer 36 include silicon oxide. The charge storage layer 12 includes silicon nitride, or other materials that can capture charges. In some embodiments, as shown in FIG. 1C , a portion of the charge storage structure 40 (tunneling layer 14 and charge storage layer 12) extends continuously in a direction perpendicular to the gate layer 38 (i.e., the Z direction), and another portion of the charge storage structure 40 (blocking layer 36) surrounds the gate layer 38. In other embodiments, as shown in FIG. 1D , the charge storage structure 40 (tunneling layer 14, charge storage layer 12, and blocking layer 36) surrounds the gate layer 38.

1E, the charge storage structure 40, the channel pillar 16, and the source pillar 32a and the drain pillar 32b are surrounded by the gate layer 38 and define the memory cell 20. The memory cell 20 can perform 1-bit operation or 2-bit operation by different operation methods. For example, when a voltage is applied to the source pillar 32a and the drain pillar 32b, since the source pillar 32a and the drain pillar 32b are connected to the channel pillar 16, electrons can be transmitted along the channel pillar 16 and stored in the entire charge storage structure 40, so that the memory cell 20 can be operated with 1 bit. In addition, for the operation using Fowler-Nordheim tunneling, electrons or holes can be captured in the charge storage structure 40 between the source column 32a and the drain column 32b. For the operation of source side injection, channel-hot-electron injection or band-to-band tunneling hot carrier injection, electrons or holes can be locally captured in the charge storage structure 40 of one of the two adjacent source columns 32a and drain columns 32b, so that the memory cell 20 can be operated in a single-bit cell (SLC, 1 bit) or a multi-bit cell (MLC, greater than or equal to 2 bits).

During operation, when a voltage is applied to the selected word line (gate layer) 38, for example, when a voltage higher than the corresponding starting voltage ( _Vth ) of the corresponding memory cell 20 is applied, the channel region of the channel column 16 intersecting the selected word line 38 is turned on, allowing current to enter the drain column 32b from the bit line _BLn or BLn ₊₁ (shown in FIG. 1B), and flow through the turned-on channel region to the source column 32a (for example, in the direction indicated by the arrow 60), and finally flow to the source line _SLn or SLn ₊₁ (shown in FIG. 1B).

Figures 1F to 1I show cross-sectional schematic diagrams of various step structures.

Referring to FIG. 1F to FIG. 1I , in some embodiments of the present invention, the conductive layer 38 of the high-level portion TP of the ladder structure SC can be used as a word line. The conductive layer 38g of the low-level portion LP of the ladder structure SC can be used to close the leakage path. The end of the low-level portion LP is connected to the extension portion EP. The extension portion EP has a different resistance value from the adjacent conductive layer 38g. The conductive layer 38g is, for example, tungsten. The extension portion EP can be a semiconductor, such as polysilicon.

Referring to FIG. 1F and FIG. 1G , in some embodiments, the extension portion EP and the adjacent conductive layer 38g can be electrically isolated from each other by the blocking layer 36 of the charge storage structure 40. Referring to FIG. 1H and FIG. 1I , in other embodiments, the extension portion EP and the adjacent gate layer 38 can be electrically isolated from each other by the blocking layer 36 of the charge storage structure 40, the charge storage layer 12, and the tunneling layer 14.

Referring to FIG. 1F and FIG. 1H , the extension portion EP may have a multi-layer structure. Referring to FIG. 1G and FIG. 1I , the extension portion EP may also be a single layer. Each extension portion EP is connected to a conductor layer 38g of the low-level portion LP. In addition, the conductor layers 38g of the low-level portion LP are electrically connected to each other through the connecting portion 38v. In some embodiments, a barrier layer 37 may also be included between the conductor layers 38g of the low-level portion LP. The barrier layer is located between the conductor layer 38g and the blocking layer 36. The material of the barrier layer 37 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof.

Figures 2A to 2I are cross-sectional schematic diagrams of a manufacturing process of a memory element according to an embodiment of the present invention.

Referring to FIG. 2A , a dielectric substrate 100 is provided. The dielectric substrate 100 is, for example, a dielectric layer of an internal connection structure formed on a silicon substrate, and its material is, for example, silicon oxide. A plurality of insulating layers 92 and a plurality of semiconductor layers 94 are alternately stacked on the dielectric substrate 100. The insulating layer 92 is, for example, a silicon oxide layer. The semiconductor layer 94 is, for example, a doped polysilicon layer. In this embodiment, there are 3 insulating layers 92 and 2 semiconductor layers 94, but the present invention is not limited thereto. In other embodiments, more or fewer insulating layers 92 and more or fewer semiconductor layers 94 may be formed according to actual needs.

Referring to FIG. 2B , a mask layer 95 is formed on a dielectric substrate 100. The mask layer 95 has an opening. The opening can be in various shapes such as circular, elliptical, square, rectangular, etc. Afterwards, an etching process is performed to transfer the opening to the multiple insulating layers 92 and multiple semiconductor layers 94 below to form an opening OP1. The opening OP1 can be a connecting opening or a connecting trench. The opening OP1 can expose the bottommost semiconductor layer 94.

Referring to Figures 2B and 2C, the mask layer 95 is removed. Then, another semiconductor layer 94T is formed on the insulating layer 92. The semiconductor layer 94T also fills the opening OP1 to form a connecting portion 96. In addition, the semiconductor layer 94T can be grounded to serve as a discharge path. The insulating layer 92 and the semiconductor layers 94 and 94T together form the lower BP of the stacking structure SK1.

Referring to FIG. 2C , an upper portion UP of the stacked structure SK1 is formed on the lower portion BP of the stacked structure SK1. In the present embodiment, the upper portion UP of the stacked structure SK1 is composed of insulating layers 104 and intermediate layers 106 that are sequentially and alternately stacked on the lower portion BP of the stacked structure SK1. The insulating layer 104 is, for example, a silicon oxide layer. The intermediate layer 106 is, for example, a silicon nitride layer. The intermediate layer 106 can be used as a sacrificial layer and is completely or partially removed in subsequent processes. In the present embodiment, the stacked structure SK1 has 7 layers of insulating layers 104 and 6 layers of intermediate layers 106, but the present invention is not limited thereto. In other embodiments, more layers of insulating layers 104 and more layers of intermediate layers 106 may be formed according to actual needs.

Referring to FIG. 2D , the upper portion UP of the stacking structure SK1 is patterned, while the lower portion BP of the stacking structure SK1 is not patterned to form a step structure SC. The lengths of the plurality of intermediate layers 106 gradually increase from top to bottom, and the lengths of the plurality of semiconductor layers 94 are substantially the same. Thereafter, a dielectric layer 107 is formed on the dielectric substrate 100. The dielectric layer 107 covers the step structure SC. The dielectric layer 107 may have a flat surface by a chemical mechanical polishing process. The bottommost insulating layer 104 of the upper portion UP of the stacking structure SK1 completely covers the lower portion BP of the stacking structure SK1.

Referring to FIG. 2E , a lithography and etching process is performed to form a plurality of openings 108 in the stacked structure SK1 in the array region (not shown). The opening 108 extends from the upper portion UP to the lower portion BP of the stacked structure SK1. The opening 108 has a circular profile, but the present invention is not limited thereto. In other embodiments, the opening 108 may have a profile of other shapes, such as a polygon (not shown). The etching process may be a dry etching process. In the dry etching process, the semiconductor layer 94T may be used as a conduction path for the charge.

Referring to FIG. 2E , a protective layer 110 is formed on the sidewalls of the semiconductor layer 94 and the intermediate layer 106. The protective layer 110 is, for example, a silicon oxide layer. The protective layer 110 may be formed by a dry thermal oxidation process, a wet thermal oxidation process, or a combination thereof. Next, a channel column 116 is formed in the opening 108. The material of the channel column 116 may be a semiconductor, such as undoped polysilicon. The method for forming the channel column 116 is, for example, to form a channel material on the stacked structure SK1 and in the opening 108. Next, an etching back process is performed to partially remove the channel material to form the channel column 116.

Referring to FIG. 2E , an insulating filling layer 124 and an insulating column 128 are formed in the opening 108. The material of the insulating filling layer 124 is, for example, silicon oxide, and the method of forming it is, for example, low-temperature thermal oxidation. The material of the insulating column 128 is, for example, silicon nitride, and the method of forming it is, for example, chemical vapor deposition. When the insulating filling layer 124 fills the opening 108, before the opening 108 is completely filled, an insulating material different from the insulating filling layer 124 is filled to completely seal the opening 108. The insulating material is etched back to expose the surface of the insulating filling layer 124 through a dry etching or wet etching process, and the insulating material remaining in the center of the opening 108 forms an insulating column 128.

Referring to FIG. 2E , a patterning process, such as lithography and etching process, is performed to form a hole (not shown) in the insulating filling layer 124. Then, conductive pillars 132a and 132b are formed in the hole. The conductive pillars 132a and 132b can be used as a source pillar and a drain pillar, respectively, and are electrically connected to the channel pillar 116, respectively. The conductive pillars 132a and 132b can be formed by forming a conductive layer on the insulating filling layer 124 and in the hole, and then etching back. The conductive pillars 132a and 132b are, for example, doped polysilicon. The conductive pillars 132a and 132b, the channel pillar 116, the insulating pillar 128, and the insulating filling layer 124 can be collectively referred to as a vertical pillar VC.

Referring to Figures 2E to 2H, a replacement process is performed to replace the multi-layer intermediate layer 106 and a portion of the semiconductor layer 94 with a multi-layer conductive layer 138 and a plurality of charge storage structures 140. First, referring to Figure 2E, a patterning process is performed on the stacked structure SK1, such as a lithography and etching process, to form a separation trench 133 (referred to as a "slit" in some embodiments). The separation trench 133 extends from the upper part UP of the stacked structure SK1 to the lower part BP. Thereafter, a multi-stage etching process is performed. First, a first-stage etching process is performed to remove a portion of the semiconductor layer 94 to form a plurality of horizontal openings 119 and a connecting opening 117. The first stage etching process may include a wet etching process. The wet etching process may use an etchant containing ammonium hydroxide and hydrogen peroxide, such as chemical etchant SC1. The multiple horizontal openings 119 may have approximately the same or different lengths. The length of the multiple horizontal openings 119 is longer than the length of the bottom middle layer 106. Parts of the multiple semiconductor layers 94 are left at the ends of the multiple horizontal openings 119 to form multiple extensions EP.

Referring to FIG. 2G , the second stage etching process of the multi-stage etching process is performed to remove a portion of the plurality of middle layers 106 to form a plurality of horizontal openings 121. The second stage etching process is, for example, a wet etching process. The etchant used in the wet etching process is, for example, hot phosphoric acid. During the etching process, since the insulating layer 104 and the protective layer 110 are made of different materials from the middle layer 106, the protective layer 110 can be used as a stop layer.

2H, multiple charge storage structures 140 (including tunneling layer 114, multiple storage layers 112, multiple blocking layers 136), multiple barrier layers 137, and multiple conductor layers 138 are formed in multiple horizontal openings 121 and 119. Tunneling layer 114 is, for example, silicon oxide. Storage layer 112 is, for example, silicon oxynitride, silicon nitride, or a combination thereof. Blocking layer 136 is, for example, silicon oxide, a material with a high dielectric constant greater than or equal to 7, or a combination thereof. The high dielectric constant material with a dielectric constant greater than or equal to 7 is, for example _, aluminum _oxide ( _Al2O3 ), ferrous oxide ( _HfO2 ), luminium oxide ( _La2O5 ), transition metal oxide, luminium oxide or a combination thereof. The material of the barrier layer 137 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof. The conductive layer 138 is, for example, tungsten.

The tunneling layer 114, the storage layer 112, the blocking layer 136, the barrier layer 137 and the conductive layer 138 are formed by, for example, sequentially forming a tunneling material, a storage material, a blocking material, a barrier material and a conductive material in the separation trench 133, the horizontal openings 121, 119 and the connecting opening 117. The thickness of the tunneling material, the storage material, the blocking material, the barrier material and the conductive material is sufficient to completely fill the horizontal openings 121, 119 and the connecting opening 117. The height H1 of the horizontal opening 119 is less than or equal to the height H2 of the horizontal opening 121. The diameter (or width) W of the connecting opening 117 is less than or equal to the heights H2 and H1 of the horizontal openings 121 and 119. Then, an etching back process is performed to remove the storage material, blocking material, barrier material and conductor material in the separation trench 133 to form a tunneling layer 114, a storage layer 112, a blocking layer 136, a barrier layer 137 and a conductor layer 138 in multiple horizontal openings 121, 119 and a connecting opening 117. Thus, a stacking structure SK2 and a step structure SC are formed. The length of the conductor layer 138 of the high-level portion TP of the step structure SC gradually increases from top to bottom. The conductor layer 138g of the low-level portion LP of the step structure SC is adjacent to the extension portion EP and is separated from each other by the charge storage structure 140.

Referring to FIG. 2H , a separation wall SLT is formed in the separation trench 133. The stacked structure SK2 is divided into a plurality of blocks by the separation wall SLT. In some embodiments, the separation wall SLT may include an insulating layer 142. The method for forming the separation wall SLT includes filling an insulating material on the stacked structure SK2 and in the separation trench 133, and then removing excess insulating material by an etching back process or a planarization process. In other embodiments, the separation wall SLT further includes a filling layer (not shown) surrounded by the insulating layer 142. The filling layer may provide sufficient support to prevent the separation wall SLT from bending. The insulating layer 142 is, for example, silicon oxide, and the filling layer is, for example, polycrystalline silicon.

Referring to FIG. 2I , a plurality of contact windows COA1 and COA2 are formed on the dielectric substrate 100. The contact window COA2 is landed on the conductive layer 138 of the high-level portion TP of the step structure SC and is electrically connected thereto. The contact window COA1 is landed on the topmost conductive layer 138g of the low-level portion LP of the step structure SC and is electrically connected thereto.

In the present invention, the barrier layer 137 and the conductive layer 138 of the upper portion UP of the stacking structure SK2 serve as multiple word lines of a memory array. The stacking structure SK2 in the array region includes multiple memory cells. These memory cells are connected in parallel to each other via conductive pillars 132a and 132b to form a memory string. The conductive layer 138 of the upper portion UP of the stacking structure SK2 is electrically connected to the upper internal connection structure to be formed subsequently via the contact window COA2. The conductive layer 138g of the lower portion BP of the stacking structure SK2 is connected to each other via the connecting portion 138v, and is electrically connected to the upper internal connection structure to be formed subsequently via the contact window COA1. The conductive layer 138g can be used as a gate or a dummy gate. In some embodiments, there is no contact window landed or electrically connected to the extension EP at the end of the low-level portion LP of the step structure SC, as shown in FIG. 3A and FIG. 3B.

Figures 3A and 3B show top views of several ladder structures of memory devices according to an embodiment of the present invention.

Referring to Figures 3A and 3B, the connecting portion 138v may be a connecting hole (as shown in Figure 3A) or a connecting wall (as shown in Figure 3B). The shape of the connecting portion 138v may be circular (as shown in Figure 3A), strip-shaped (as shown in Figure 3B) or elliptical (not shown), but not limited thereto. Referring to Figure 3B, in the embodiment where the connecting portion 138v is a strip-shaped connecting wall, the extending direction of the connecting wall may be perpendicular to the extending direction of the partition wall SLT, but not limited thereto.

Referring to FIGS. 3A and 3B , the connecting portion 138v may be disposed at an appropriate position. The connecting portion 138v may be disposed in the conductive layer 138 of the high-level portion TP (not shown) or in the conductive layer 138g and the insulating layer 92 of the low-level portion LP (shown in FIG. 2I ).

Since the contact window COA2 is arranged on the upper surface of the conductive layer 138 of the high-level part TP. The contact window COA1 is arranged on the upper surface of the uppermost conductive layer 138g of the low-level part LP. The connecting portion 138v is located between the lower surface of the uppermost conductive layer 138g and the upper surface of the lowermost conductive layer 138g. The position of the connecting portion 138v does not affect the setting of the contact window COA1. Therefore, in the direction perpendicular to the dielectric substrate 100, the connecting portion 138v can be misaligned with the position of the contact window COA1 or COA2, partially overlapped, or completely overlapped.

3A and 3B , in some embodiments, a support column DV (as shown in FIGS. 2E to 2I ) is further provided in the step structure SC to prevent the step structure SC from collapsing during the gate replacement process. For simplicity, FIG. 2E only shows a single support column DV, but the present invention is not limited thereto, and the step structure SC may include a plurality of support columns DV, as shown in FIGS. 3A and 3B . The support column DV may be formed simultaneously when the vertical column VC (as shown in FIGS. 2E to 2I ) is formed, so the support column DV may have substantially the same height as the vertical column VC, that is, extending from the top surface of the dielectric layer 107 to the insulating layer 92. Alternatively, the support column DV can also be formed at the same time as the through hole connecting the lower internal connection structure and the upper internal connection structure is formed. In other words, the support column DV extends at least from the top layer to the bottom layer of the ladder structure SC. Therefore, in order not to affect the setting of the support column DV, the position of the connecting portion 138v is staggered with the position of the support column DV, and does not overlap, as shown in Figures 3A and 3B.

Figures 4A to 4F are schematic cross-sectional diagrams showing a process of manufacturing a memory device according to another embodiment of the present invention.

Referring to FIG. 4A , a stacking structure SK1 is formed on a dielectric substrate 100. The stacking structure SK1 of FIG. 4A is similar to the stacking structure SK1 of the above-mentioned embodiment, but does not include the connecting portion 96. The method for forming the stacking structure SK1 includes sequentially forming a lower BP and an upper UP. The lower BP includes a plurality of insulating layers 92 and a plurality of semiconductor layers 94 stacked alternately. The bottom semiconductor layer 94 can be grounded to serve as a conduction path for charges. The upper UP includes a plurality of insulating layers 104 and a plurality of intermediate layers 106 stacked alternately. The materials of the insulating layer 92, the semiconductor layer 94, the insulating layer 104, and the intermediate layer 106 are as described in the above embodiment.

Referring to FIG. 4B , the upper portion UP and the lower portion BP of the stacked structure SK1 are patterned to form a step structure SC. In this embodiment, the length of the middle layer 106 of the step structure SC gradually increases from top to bottom, and the length of the semiconductor layer 94 gradually increases from top to bottom. Thereafter, a dielectric layer 107 is formed on the dielectric substrate 100. The dielectric layer 107 covers the step structure SC.

Referring to FIG. 4C , a vertical column VC is formed in the stacking structure SK1 in the array region according to the above method.

Referring to FIG. 4C to FIG. 4F , a replacement process is performed to replace the multi-layer intermediate layer 106 and the semiconductor layer 94 with a multi-layer conductor layer 138 and a plurality of charge storage structures 140. First, referring to FIG. 4C , a patterning process is performed on the stacked structure SK1, such as a lithography and etching process, to form a separation groove 133. Then, referring to FIG. 4D , an etching process, such as a wet etching process, is performed to remove a portion of the plurality of intermediate layers 106 and a portion of the semiconductor layer 94 at the same time, thereby forming a plurality of horizontal openings 121 and 119. A portion of the semiconductor layer 94 is left at the end of the lowest horizontal opening 119 to form an extension portion EP.

Referring to FIG. 4E , multiple charge storage structures 140 (including tunneling layers 114, multiple storage layers 112, multiple barrier layers 136), multiple barrier layers 137, and multiple conductor layers 138 are formed in multiple horizontal openings 121 and 119 according to the above method. Thus, a stacking structure SK2 and a step structure SC are formed. The lengths of the conductor layer 138 of the high-level portion TP and the conductor layer 138g of the low-level portion LP of the step structure SC gradually increase from top to bottom. The conductor layer 138g of the low-level portion LP of the step structure SC is adjacent to the extension portion EP and is separated from each other by the charge storage structure 140. Next, a separation wall SLT is formed in the separation groove 133.

Referring to FIG. 4F , multiple contact windows COA1 and COA2 are formed on the dielectric substrate 100 according to the above method. The contact window COA2 is landed on the conductive layer 138 of the high-level portion TP of the step structure SC and is electrically connected thereto. The contact window COA1 is landed on the conductive layer 138g of the low-level portion LP of the step structure SC and is electrically connected thereto.

In the present invention, the barrier layer 137 and the conductive layer 138 of the upper part UP of the stacked structure SK2 serve as multiple word lines of a memory array. The stacked structure SK2 includes multiple memory cells. These memory cells are connected in parallel to each other via conductive pillars 132a and 132b to form a memory string. The conductive layer 138 of the upper part UP is electrically connected to the upper internal connection structure formed subsequently via the contact window COA2. The lower part BP has a single conductive layer 138g, and is electrically connected to the upper internal connection structure formed subsequently via the contact window COA1. The conductive layer 138g can serve as a gate or a virtual gate. In some embodiments, no contact window is landed or electrically connected to the extension portion EP at the end of the low-step portion LP of the step structure SC, as shown in FIG. 5A and FIG. 5B .

Figures 5A and 5B show top views of several ladder structures of a memory element according to another embodiment of the present invention.

The top view of FIG. 5A and FIG. 5B is similar to the top view of FIG. 3A and FIG. 3B, but there is no connecting part in the step structure SC of FIG. 5A and FIG. 5B. The high-step portion TP has more steps, and the low-step portion LP adjacent to the extension portion EP has fewer steps or even only one step.

The above embodiments are explained using AND flash memory as an example. The present invention can also be used in 3D NOR flash memory and 3D NAND flash memory. The embodiments of the present invention can be used not only in flash memory, but also in various components with a ladder structure.

In an embodiment of the present invention, one or more semiconductor layers located at the bottom of the stacked structure can be used as a conduction path for electric charge to reduce arcing effect and prevent the material layers and components on the dielectric substrate from being damaged by plasma bombardment, thereby improving the yield of the process. In addition, the one or more semiconductor layers can be replaced in a subsequent process to form one or more conductive layers, which can then be used as a gate layer or a dummy gate layer.

16: Channel column

28: Insulation Pillar

32b: Second conductor column/drain column

24: Insulation filling layer

TP: High-end department

LP: Low-level

50: Dielectric substrate

12: Charge storage layer

14: Tunneling layer

36: Barrier layer

37: Barrier layer

40: Charge storage structure

38v: Communication Department

EP: Extension

54: Insulation layer

38: Gate layer/conductor layer/word line

38g: Conductive layer

SC: Step structure

Claims (20)

A semiconductor element comprises: a step structure located on a dielectric substrate, wherein the step structure comprises a plurality of conductor layers and a plurality of insulating layers alternately stacked with each other; and an extension portion at the end of the lower step of the step structure, wherein the extension portion and the plurality of conductor layers have different resistance values, the conductor layer of the lower step is adjacent to the extension portion, and the lower step and the extension portion are close to one side of the dielectric substrate in the step structure, and the conductor layer of the lower step and the extension portion are alternately stacked with some of the insulating layers of the plurality of insulating layers. A semiconductor element as described in claim 1, wherein the resistance value of the extension portion is higher than the resistance value of the multiple conductive layers. A semiconductor element as described in claim 1, wherein the extension portion comprises a semiconductor material and the plurality of conductive layers comprise a metal material. The semiconductor element as described in claim 1 further includes: a connecting portion located in the low-level portion and electrically connecting the multiple conductive layers of the low-level portion. A semiconductor element as described in claim 4, wherein the width of the connecting portion is smaller than the thickness of the multiple conductive layers. The semiconductor device as described in claim 4 further includes: a support column extending through the multiple conductive layers and the multiple insulating layers of the step structure. A semiconductor element as described in claim 6, wherein the connecting portion is staggered with the supporting column. A semiconductor element as described in claim 4, wherein the connecting portion includes a connecting hole or a connecting wall. The semiconductor element as described in claim 8 further includes: a partition wall extending through the step structure, wherein the extension direction of the connecting wall is different from the extension direction of the partition wall. The semiconductor device as described in claim 1 further includes: a channel column extending through the step structure; a plurality of conductive columns located in the channel column and electrically connected to the channel column; and a charge storage layer located between the plurality of conductive layers and the channel column. A semiconductor device as described in claim 10, wherein the charge storage layer is also located between the extension portion and the lower step portion of the step structure. A semiconductor element as described in claim 1, wherein among the plurality of conductive layers, the thickness of the conductive layer connected to the extension portion is not greater than the thickness of the conductive layer not connected to the extension portion. The semiconductor device as described in claim 1 further includes: a plurality of contact windows landed on the plurality of conductive layers, wherein the plurality of contact windows are not landed on the extension portion. A method for manufacturing a semiconductor element comprises: forming a step structure on a dielectric substrate, wherein the step structure comprises a plurality of conductor layers and a plurality of insulating layers alternately stacked with each other; and forming an extension portion at the end of a lower step of the step structure, wherein the extension portion and the plurality of conductor layers have different resistance values, the conductor layer of the lower step is adjacent to the extension portion, and the lower step and the extension portion are on a side of the step structure close to the dielectric substrate, and the conductor layer of the lower step and the extension portion are alternately stacked with some of the insulating layers of the plurality of insulating layers. The manufacturing method of the semiconductor element as described in claim 14, wherein forming the step structure includes: forming a plurality of semiconductor layers and a plurality of insulating layers alternately stacked on the dielectric substrate; patterning the plurality of semiconductor layers and the plurality of insulating layers to form the step structure; and partially replacing the plurality of semiconductor layers with the plurality of conductive layers, with a portion of the plurality of semiconductor layers remaining at the end of the lower horizontal opening to form the extension portion. The method for manufacturing a semiconductor element as described in claim 15 further includes: forming a first connecting portion connecting the plurality of semiconductor layers; removing the first connecting portion to form a connecting opening; and forming a conductive material in the connecting opening to form a second connecting portion. A method for manufacturing a semiconductor element as described in claim 16, wherein the connecting opening comprises a connecting opening or a connecting trench, and the second connecting portion comprises a connecting hole or a connecting wall. The method for manufacturing a semiconductor device as described in claim 17 further includes: forming a channel column extending through the step structure; forming a plurality of conductive columns in the channel column and electrically connected to the channel column; and forming a charge storage layer between the plurality of conductive layers and the channel column and between the plurality of conductive layers and the extension. The method for manufacturing a semiconductor element as described in claim 17 further includes: forming a partition wall extending through the step structure, wherein the extension direction of the connecting wall is different from the extension direction of the partition wall. The method for manufacturing a semiconductor device as described in claim 14 further includes: forming a plurality of contact windows to land on the plurality of conductive layers of the step structure.