TWI849052B - Lithographic apparatus and method with a thermal control system - Google Patents

Abstract

A device comprising a compartment, said compartment comprising a wafer stage configured to hold a semiconductor wafer on a clamp, wherein the wafer stage is configured to follow a route within the compartment in operational use, the device comprising: a first component having a first surface facing a first portion of the route; a second component having a second surface facing a second portion of the route; a thermal control system operative to maintain a first temperature of the first surface and a second temperature of the second surface at a common set-point magnitude.

Description

Lithography apparatus and method with thermal control system

The present invention relates to a lithography device and a lithography method.

A lithographic apparatus is a machine that applies a desired pattern to a substrate, usually to a target portion of the substrate. A lithographic apparatus may be used, for example, in the manufacture of integrated circuits (ICs). In that case, a patterned device (which is alternatively referred to as a mask or reticle) may be used to produce a circuit pattern to be formed on individual layers of the IC. This pattern may be transferred to a target portion (e.g., a portion containing a die, a die, or several dies) on a substrate (e.g., a silicon wafer). Transfer of the pattern is usually performed by imaging onto a layer of radiation-sensitive material (resist) provided on the substrate. In general, a single substrate will contain a network of sequentially patterned adjacent target portions. Lithography is widely recognized as one of the key steps in the fabrication of ICs and other devices and/or structures.

In order to reduce the minimum printable size, imaging may be performed using radiation with a short wavelength. Therefore, it has been proposed to use an EUV radiation source that provides EUV radiation in the range of, for example, 13 nm to 14 nm. It has further been proposed to use EUV radiation with a wavelength less than 10 nm, for example in the range of 5 nm to 10 nm, such as 6.7 nm or 6.8 nm. This radiation is called extreme ultraviolet (EUV) radiation or soft x-ray radiation.

Overlay error indicates the deviation between the actual location of the scaled mask pattern imaged onto the wafer and the desired location. There is a critical value for this error, beyond which the imaging results are unacceptable. The magnitude is in nanometers (in EUV) and is shrinking with each new generation of EUV scanners. The process involves placing the next patterned layer in a stack of dozens of layers onto the previously patterned layer, which together will ultimately form an integrated electronic circuit. A lateral displacement of one layer relative to another can cause the layers to not connect properly, rendering the circuit unacceptable for operational use.

International Patent Application Publication WO 2018/041599 is incorporated herein by reference. The publication discloses an EUV lithography apparatus having a projection system configured to project a radiation beam patterned by a mask through a slit onto an exposure area on a substrate held on a substrate stage. The substrate stage is a component at a substrate stage and is in physical contact with the substrate, and can be physically and functionally integrated with an electrostatic chuck that clamps the substrate to the substrate stage. The electrostatic chuck has a cooling system for running away heat generated at the chuck. The lithography apparatus is operated in a scanning mode, in which the mask and the substrate are scanned simultaneously during projection. The radiation beam used to project a pattern onto a substrate transfers a large amount of heat to the substrate, which causes localized heating of the substrate. The localized expansion of the substrate caused by the heating reduces the accuracy of the pattern already existing on the substrate overlying the projected pattern. To address this problem, the lithography apparatus disclosed in WO 2018/041599 includes a cooling device located between the projection system and the substrate. The cooling device provides localized cooling of the substrate near the area where the patterned radiation beam is incident on the substrate through the gap. In some embodiments, a pre-exposure calibration operation can be performed to ensure that the amount of cooling provided to the substrate by the cooling device is within a desired range. Since calibration operations do not need to be performed at high frequency, calibration operations can utilize measurements obtained from the substrate stage cooling system in addition to or instead of measurements obtained from sensors near the cooling surface of the cooling device.

It is desirable not to remove more heat from the substrate than is added by the radiation beam. Therefore, WO 2018/041599 discloses that in some embodiments, a heat shield is provided to reduce cooling in an area adjacent to the exposure area. In one embodiment, the heat shield has one or more channels to allow cooling and/or heating of the heat shield by flowing a temperature regulating fluid through the channels. The flow of the temperature regulating fluid through the one or more channels can be configured to maintain the heat shield at an ambient temperature such as, for example, about 22°C.

However, there remains the problem of ensuring that the amount of cooling provided by the cooling device is balanced with (i.e. compensated for) the amount of heating by the radiation beam. The substrate stage is configured to follow a path within a compartment of a lithography apparatus. The problem is that the surface facing the substrate held on the fixture can be at different temperature levels. This means that each surface causes a different unknown heat load to the substrate.

This unknown heat load can adversely affect the calibration operation and thus the heat extraction by the cooling device. The resulting uncompensated radiation beam heating can reduce the accuracy of the projected pattern overlying the pattern already present on the substrate, i.e. increase overlay errors.

Furthermore, in addition to the localized expansion of the substrate caused by the heating of the radiation beam, unknown thermal loads can also directly cause undesired localized expansion of the substrate, which further increases the overlay error.

The heat extraction of the cooling device needs to be accurately controlled to compensate for the radiation beam heating. In addition, the overlay error caused by the undesired expansion of the substrate needs to be reduced.

According to a first aspect of the invention, a lithography apparatus is provided, which is configured to project a patterned radiation beam via projection optics onto a target portion of a semiconductor wafer on a fixture held at a wafer stage in a compartment, wherein the wafer stage is configured to follow a route within the compartment during operational use of the lithography apparatus, and wherein the lithography apparatus comprises: - a first component having a first surface facing a first portion of the route; - a second component having a second surface facing a second portion of the route; - a thermal control system operable to maintain a first temperature of the first surface and a second temperature of the second surface at a common set point value.

According to a second aspect of the present invention, a lithography method is provided, comprising: - projecting a patterned radiation beam via projection optics onto a target portion of a semiconductor wafer on a fixture held at a wafer stage in a compartment of a lithography apparatus, wherein the lithography apparatus comprises: - a first component having a first surface facing a first portion of a route in the compartment; and - a second component having a second surface facing a second portion of the route in the compartment; - transporting the wafer stage along the route in the compartment; and - operating a thermal control system to maintain a first temperature of the first surface and a second temperature of the second surface at a common set point value.

FIG1 schematically depicts a lithography apparatus 100. The apparatus comprises:

-   Source module SO;

- an illumination system (illuminator) IL configured to condition a radiation beam B (e.g. EUV radiation);

- a support structure (e.g., a mask stage) MT constructed to support a patterned device (e.g., a mask or a reticle) MA and connected to a first positioner PM configured to accurately position the patterned device;

- a substrate stage (e.g. wafer stage) WT constructed to hold a substrate (e.g. anti-etchant coated wafer) W and connected to a second positioner PW configured to accurately position the substrate; and

- A projection system (e.g. a reflective projection system) PS, which is configured to project the pattern imparted to the radiation beam B by the patterning device MA onto a target portion C (e.g. comprising one or more dies) of the substrate W.

Illumination systems may include various types of optical components for directing, shaping, or controlling radiation, such as refractive, reflective, magnetic, electromagnetic, electrostatic, or other types of optical components, or any combination thereof.

The support structure MT holds the patterned device MA in a manner that depends on the orientation of the patterned device, the design of the lithography apparatus, and other conditions, such as, for example, whether the patterned device is held in a vacuum environment. The support structure may use mechanical, vacuum, electrostatic, or other clamping techniques to hold the patterned device. The support structure may include, for example, a frame or table, which may be fixed or movable as desired. The support structure may ensure that the patterned device is in a desired position, for example, relative to a projection system.

The term "patterned device" should be interpreted broadly to refer to any device that can be used to impart a pattern to a radiation beam in its cross-section so as to produce a pattern in a target portion of a substrate. The pattern imparted to the radiation beam may correspond to a specific functional layer in a device (e.g., an integrated circuit) produced in the target portion.

Patterned devices can be transmissive or reflective. Examples of patterned devices include masks, programmable mirror arrays, and programmable LCD panels. Masks are well known in lithography, and include mask types such as binary, alternating phase shift, and attenuated phase shift, as well as various hybrid mask types. One example of a programmable mirror array uses a matrix arrangement of mirror facets, each of which can be individually tilted so as to reflect an incident radiation beam in different directions. The tilted mirrors impart a pattern in the radiation beam reflected by the mirror array.

Similar to the illumination system, the projection system may include various types of optical components, such as refractive, reflective, magnetic, electromagnetic, electrostatic or other types of optical components, or any combination thereof, appropriate to the exposure radiation used or to other factors such as the use of a vacuum. A vacuum may be required for EUV radiation since other gases may absorb too much radiation. Therefore, a vacuum environment may be provided to the entire beam path by means of vacuum walls and a vacuum pump.

As depicted here, the device is of the reflective type (eg, using a reflective mask).

The lithography apparatus may be of a type having two (dual stage) or more substrate stages (and/or two or more mask stages). In such "multi-stage" machines, the additional stages may be used in parallel, or a preparatory step may be performed on one or more stages while one or more other stages are being used for exposure.

Referring to FIG. 1 , an illuminator IL receives an extreme ultraviolet radiation beam from a source module SO. Methods for generating EUV light include, but are not necessarily limited to, converting a material having at least one element (e.g., xenon, lithium, or tin) into a plasma state using one or more emission lines in the EUV range. In one such method, often referred to as laser produced plasma "LPP," the desired plasma may be generated by irradiating a fuel (e.g., a droplet, stream, or cluster of material having an element emitting the desired spectrum) with a laser beam. The source module SO may be part of an EUV radiation system including a laser (not shown in FIG. 1 ) for providing a laser beam for exciting the fuel. The resulting plasma emits output radiation, such as EUV radiation, which is collected using a radiation collector disposed in the source module. For example, when a _CO2 laser is used to provide the laser beam for fuel excitation, the laser and source module can be separate entities.

In these cases, the laser is not considered to form part of the lithography apparatus, and the radiation beam is delivered from the laser to the source module by means of a beam delivery system comprising, for example, suitable steering mirrors and/or a beam expander. In other cases, for example when the source is a discharge produced plasma EUV generator (often referred to as a DPP source), the source may be an integral part of the source module.

The illuminator IL may include an adjuster for adjusting the angular intensity distribution of the radiation beam. Typically, at least the outer radial extent and/or the inner radial extent (typically referred to as σ outer and σ inner, respectively) of the intensity distribution in a pupil plane of the illuminator may be adjusted. In addition, the illuminator IL may include various other components, such as a faceted field mirror device and a faceted pupil mirror device. The illuminator may be used to adjust the radiation beam to have a desired uniformity and intensity distribution in its cross-section.

A radiation beam B is incident on a patterned device (e.g., a mask) MA held on a support structure (e.g., a mask stage) MT and is patterned by the patterned device. After reflection from the patterned device (e.g., a mask) MA, the radiation beam B passes through a projection system PS which focuses the beam onto a target portion C of a substrate W. By means of a second positioner PW and a position sensor PS2 (e.g., an interferometer device, a linear encoder or a capacitive sensor), the substrate stage WT can be accurately moved, for example, in order to position different target portions C in the path of the radiation beam B. Similarly, a first positioner PM and a further position sensor PS1 can be used to accurately position the patterned device (e.g., a mask) MA relative to the path of the radiation beam B. The patterned device (eg, mask) MA and the substrate W may be aligned using the mask alignment marks M1, M2 and the substrate alignment marks P1, P2.

An EUV pellicle (e.g., a pellicle PE) is provided to protect the patterned device from particle contamination within the system. Such a pellicle is provided at the locations shown and/or at other locations. Another EUV pellicle SPF may be provided as a spectral purity filter that is operable to filter out unwanted radiation wavelengths (e.g., DUV). These unwanted wavelengths may affect the photoresist on the wafer W in an undesirable manner. The SPF may also help prevent projection optics within the projection system PS from being contaminated by particles released during degassing, as appropriate (or alternatively, a pellicle may be provided in place of the SPF for this operation). Any of these EUV pellicles may include any of the EUV pellicles disclosed herein.

The depicted apparatus can be used in a variety of modes. In a scanning mode, the patterned device support (e.g., mask stage) MT and the substrate stage WT are scanned synchronously while the pattern imparted to the radiation beam is projected onto a target portion C (i.e., a single dynamic exposure). The speed and direction of the substrate stage WT relative to the patterned device support (e.g., mask stage) MT can be determined by the magnification (reduction) and image inversion characteristics of the projection system PS. In the scanning mode, the maximum size of the exposure field limits the width of the target portion in a single dynamic exposure (in the non-scanning direction), while the length of the scanning motion determines the height of the target portion (in the scanning direction). As is well known in the art, other types of lithography apparatus and operating modes are possible. For example, stepping modes are known. In so-called "maskless" lithography, the programmable patterned device remains stationary but with a changing pattern, and the substrate stage WT is moved or scanned.

Combinations and/or variations on the modes of use described above or entirely different modes of use may also be used.

FIG2 shows in more detail an embodiment of a lithography apparatus, which includes a radiation system 42, an illumination system IL, and a projection system PS. The radiation system 42 as shown in FIG2 is of the type that uses a laser to generate plasma as a radiation source. EUV radiation can be generated by an extremely hot plasma generated from, for example, xenon (Xe), lithium (Li), or tin (Sn). In one embodiment, Sn is used to generate plasma so as to emit radiation in the EUV range.

The radiation system 42 embodies the function of the source SO in the apparatus of Figure 1. The radiation system 42 comprises a source chamber 47 which in this embodiment substantially encloses not only the EUV radiation source but also a collector 50 which in the example of Figure 2 is a normal incidence collector, such as a multi-layer mirror.

As part of the LPP radiation source, the laser system 61 is constructed and arranged to provide a laser beam 63, which is delivered by a beam delivery system 65 through an aperture 67 provided in the collector 50. In addition, the radiation system includes a target material 69, such as Sn or Xe, supplied by a target material supply 71. In this embodiment, the beam delivery system 65 is configured to establish a beam path that is generally focused on a desired plasma formation location 73.

In operation, target material 69, which may also be referred to as fuel, is supplied in the form of droplets by target material supply 71. A trap 72 is provided on the opposite side of source chamber 47 to capture fuel that, for whatever reason, does not become plasma. When this droplet of target material 69 reaches plasma formation position 73, laser beam 63 impinges on the droplet, and EUV radiation emitting plasma is formed inside source chamber 47. In the case of pulsed lasers, this involves timing the pulses of laser radiation to coincide with the passage of the droplet through position 73. These conditions produce a highly ionized plasma having an electron temperature of several 10 ⁵ K. High energy radiation generated during deexcitation and recombination of the plasma includes the desired EUV emitted from the plasma at location 73. The plasma formation location 73 and the aperture 52 are located at the first and second foci of the collector 50, respectively, and the EUV radiation is focused by the normal incidence collector mirror 50 to an intermediate focus IF.

A radiation beam emanating from source chamber 47 traverses illumination system IL via reflectors 53, 54 as indicated in FIG2 by radiation beam 56. The reflectors direct beam 56 via pellicle PE onto a patterned device (e.g. a reticle or mask) positioned on a support (e.g. a reticle stage or mask stage) MT. A patterned beam 57 is formed which is imaged by projection system PS via reflective elements 58, 59 onto a substrate carried by a wafer stage or substrate stage WT. The substrate W is held on substrate stage WT by an electrostatic clamp CL. The substrate stage WT and its clamp CL are accommodated in a wafer stage compartment WSC.

The projection system PS has the projection optics mounted in a container (box) providing a specific low pressure environment. This container is called the projection optics box (POB). The POB and the wafer stage compartment WSC are separate environments. During exposure, the photoresist may outgas due to the radiation received from the POB. These gases should not reach the projection optics because they may contaminate the surface of the mirror (POB contains reflective optical components in EUV). The contamination may then interfere with the imaging. Therefore, a dynamic gas lock DGL (not shown in the figure) is provided to reduce this contamination.

More elements than shown may typically be present in the illumination system IL and the projection system PS. For example, instead of the two elements 58 and 59 shown in FIG. 2 , there may be one, two, three, four or even more reflective elements.

As will be appreciated by those skilled in the art, reference axes X, Y, and Z may be defined to measure and describe the geometry and behavior of the device, its various components, and the radiation beams 55, 56, 57. At each component of the device, a local reference coordinate system may be defined for the X, Y, and Z axes. The Z axis is generally coincident with the direction of the optical axis O at a given point in the system and is generally perpendicular to the plane of the patterned device (reduction mask) MA when describing spatial relations relative to the patterned device and perpendicular to the plane of the substrate W when describing spatial relations relative to the substrate W. In the source module (device) 42, the X axis is generally coincident with the direction of the fuel stream (69, described below), and the Y axis is orthogonal to that direction, which is indicated from the page, as indicated. On the other hand, near the support structure MT holding the magnification mask MA, the local X-axis is generally transverse to the scanning direction aligned with the local Y-axis. For convenience, in this area of the schematic diagram Figure 2, the X-axis is pointed out from the page, again as labeled. Such designations are known in the art and will be adopted herein for convenience. In principle, any reference coordinate system can be chosen to describe the device and its behavior.

In addition to producing the desired EUV radiation, the plasma may also produce radiation of other wavelengths, such as radiation in the infrared, visible, ultraviolet (UV) and deep ultraviolet (DUV) ranges. Infrared (IR) radiation from the laser beam 63 may also be present. Non-EUV wavelengths are not desired in the illumination system IL and the projection system PS, and various measures may be deployed to block non-EUV radiation. As schematically depicted in FIG2 , for IR, DUV and/or other undesired wavelengths, a spectral purity filter SPF may be applied upstream of the virtual source point IF. In the particular example shown in FIG. 2 , two spectral purity filters are depicted, one within the source chamber 47 and one at the output of the projection system PS.

FIG. 3 illustrates the steps for exposing a target portion (e.g., a die) on a substrate W in a dual stage lithography apparatus. Two substrate stages (also referred to as wafer stages) are configured to follow a path within a wafer stage compartment (WSC in FIG. 2 ) during operational use of the lithography apparatus. The substrate begins in a pre-aligner and is transferred to a substrate stage that holds the substrate in a fixture. The substrate is then transported along the path indicated by steps 200, 202, 204, 210, 212, 214, 216, 218, 210, and 220.

The vacuum pre-aligner VPA is a component of the wafer handler. The pre-aligner is a robot that places the substrate W' in the correct orientation (in the local X-Y plane) so that the substrate W' is correctly oriented and ready for the measurement operation MEA when it is transferred to the substrate stage at step 200.

The steps performed at the metrology station MEA are in the left dashed box, while the right dashed box shows the steps performed at the exposure station EXP. Sometimes, one of the substrate tables WTa, WTb will be at the exposure station and the other at the metrology station, as described above. At step 200, a new substrate W' is loaded from the vacuum pre-aligner VPA by a mechanism not shown in the figure. The two substrates (one substrate at the metrology station and the other substrate at the exposure station) are processed in parallel to increase the throughput of the lithography apparatus.

Reference is initially made to a newly loaded substrate W', which may be a previously unprocessed substrate, which is prepared for the first exposure in the apparatus using a new photoresist. However, in general, the lithography process described will be only one step in a series of exposure and processing steps, so that the substrate W' has passed through this apparatus and/or other lithography apparatuses several times and may also be subject to subsequent processes. With particular regard to the problem of improving overlay performance, the task is to ensure that the new pattern is applied exactly in the correct position on a substrate that has already undergone one or more cycles of patterning and processing. These processing steps gradually introduce distortions in the substrate, which distortions must be measured and corrected to achieve satisfactory overlay performance.

Pre- and/or post-patterning steps may be performed in other lithography apparatuses (as just mentioned), and may even be performed in different types of lithography apparatuses. For example, some layers in a device manufacturing process that are extremely demanding in terms of parameters such as resolution and overlay may be performed in more advanced lithography tools than other layers that are less demanding. Thus, some layers may be exposed in an immersion-type lithography tool, while other layers are exposed in a "dry" tool or in a vacuum tool. Some layers may be exposed in a tool operating at DUV wavelengths, while other layers are exposed using EUV wavelength radiation.

At 202, alignment metrology using substrate marks P1 (depicted as four crosses) and an image sensor (not shown) is used to measure and record the alignment of the substrate relative to substrate stage WTa/WTb. Additionally, alignment sensor AS is used to measure a number of alignment marks across substrate W'. In one embodiment, these measurements are used to create a "wafer grid" that very accurately maps the distribution of the marks across the substrate, including any distortion relative to a nominal rectangular grid.

At step 204, a level sensor LS is also used to measure a wafer height (Z) map relative to the X-Y position. Typically, the height map is used only to achieve accurate focus of the exposed pattern. Primarily, the height map is used only to achieve accurate focus of the exposed pattern. The height map may also be used for other purposes.

When the substrate W' is loaded, recipe data 206 is received which defines the exposure to be performed and also defines the properties of the wafer and the previously generated pattern and the pattern to be generated on the wafer. The measurements of the wafer position, wafer grid and height map performed at 202, 204 are added to these recipe data so that the complete set of recipe data and measurement data 208 can be passed to the exposure station EXP. The measurements of alignment data (for example) include the X position and Y position of the alignment target formed in a fixed or nominally fixed relationship with the product pattern that is the product of the lithography process. These alignment data obtained just before exposure are used to generate an alignment model, which has parameters that fit the model to the data. These parameters and the alignment model will be used during the exposure operation to correct the position of the pattern applied in the current lithography step. The model in use interpolates the positional deviations between the measured positions. Known alignment models may contain four, five or six parameters which together define the translation, rotation and scaling of the "ideal" grid at different scales. Advanced models using more parameters are known.

At 210, wafers W' and W are exchanged so that the measured substrate W' becomes substrate W entering exposure station EXP. In the example apparatus of FIG. 1, this exchange is performed by exchanging substrate stages WTa and WTb within the apparatus so that substrates W, W' remain accurately clamped and positioned on their supports to preserve the relative alignment between the substrate stages and the substrates themselves. Therefore, once the stages have been exchanged, in order to utilize the measurement information 202, 204 for substrate W (formerly W') to control the exposure step, it is necessary to determine the relative position between projection system PS and substrate stage WTb (formerly WTa). At step 212, a zoom reticle alignment is performed using reticle alignment marks (not shown). In steps 214, 216, and 218, a scanning motion and radiation is applied to successive target locations across the substrate W to complete exposure of multiple patterns.

By using the alignment data and height maps obtained at the metrology station in performing the exposure step, these patterns are accurately aligned relative to the desired locations, and in particular, relative to features previously placed on the same substrate. The exposed substrate, now labeled "W" is unloaded from the apparatus at step 220 to undergo etching or other processes based on the exposed patterns.

Those skilled in the art will recognize that the above description is a simplified overview of the many very detailed steps involved in one example of a real manufacturing situation. For example, rather than measuring alignment in a single pass, there will often be separate stages of coarse and fine metrology using the same or different marks. Coarse and/or fine alignment metrology steps may be performed before or after height measurement, or interleaved.

Embodiments may include a scanner with a cooling hood or cooling device. The scanner has components whose surfaces are sometimes in line of sight of the wafer. The components are all thermally regulated so that they adopt the same temperature.

Lithography scanners have cooling devices for extracting heat from the wafer that is generated by the wafer's absorption of imaging radiation.

The cooling power of the cooling components needs to be controlled very accurately and the required cooling power depends on many parameters.

The values of these parameters may vary depending on the scenario and are accounted for in the wafer heat feed forward (WHFF) model described below.

The mismatch between the extracted and generated heat causes thermally induced deformation of the wafer, which results in overlay errors: undesired lateral displacement of portions of the imaged pattern relative to the desired portions.

The cooling device needs to be calibrated relative to the imaged radiation received at the wafer. An example of a calibration mechanism used involves monitoring the difference between the temperature of the cooling water at the inlet of the electrostatic chuck and the temperature of the cooling water at the outlet of the chuck.

The temperature difference indicates the heat absorbed (or released) by the cooling water during its passage through the wafer holder. Ideally, the temperature difference of the cooling water between the inlet and outlet represents the mismatch between the heat extracted by the cooling device and the heat generated in the wafer by the radiation received by the self-imaging radiation beam.

However, the cooling water of the wafer holder is exposed to parasitic heat loads in addition to the heat load from the exposure radiation. An example of a component in a scanner that represents a parasitic heat load is a component that has a surface facing the wafer stage in its path through the wafer stage compartment. As a result, the parasitic heat load interferes with the control of heat extraction by the cooling device.

FIG4 schematically depicts an example of a bottom-up view of the interior of a wafer stage compartment of a lithography apparatus. This is the view from the viewpoint of the wafer. The wafer handler WH is on the left. The vacuum pre-aligner VPA shown in FIG3 is a component of the wafer handler. The measurement station MEA has a wafer stage heat shield having two components WS-HS-A and WS-HS-B. The exposure station EXP has a wafer stage heat shield having two components WS-HS-C and WS-HS-D. Also, at the exposure station EXP, the cooling hood heat shield assembly CH-HS is shown adjacent to the projection optics box orifice assembly POB-H. Exposure is performed through the gap between the cooling hood heat shield CH-HS and the projection optics box aperture POB-H. These components face different parts of the route followed by the wafer stage, as described with reference to FIG.

The metrology frame MF is shown by cross-hatched elements. The metrology frame is a trusted subsystem that acts as a reference for metrology components, such as components that accurately measure the position of the wafer stage and measure the topography of the wafer. The metrology frame is a mechanically extremely rigid structure that is maintained at a stable and precise temperature in order to minimize inaccuracies in measurements due to thermally induced deformations of the metrology frame.

Figure 5 schematically depicts a cross-sectional view of the contents of the wafer stage compartment of the lithography apparatus. The metrology frame MF is again shown cross-hatched. The wafer handler has an assembly WH above the wafer W. The wafer handler also has an assembly in the form of a vacuum pre-aligner VPA below the wafer. Across the measurement station MEA and the exposure station EXP, the wafer stage heat shield assemblies WS-HS-A and WS-HS-B are displayed above the wafer W supported by the clamp CL. In the exposure station EXP, the cooling hood heat shield assembly CH-HS and the projection optics box orifice assembly POB-H are displayed above another wafer W, which is supported by its respective clamp CL. In the absence of operation of the embodiments described below, the surfaces of components WH, WS-HS-A/B/C/D, CH-HS, and POB-H may have different temperatures, resulting in a number of parasitic heat loads to the wafer. The parasitic heat loads interfere with the control of heat extraction by the cooling device, which will now be described with reference to Figures 6 and 7.

6 schematically depicts a cross-sectional view of an exposure of a wafer on a cooled fixture, wherein a cooling device is used to compensate for radiation beam heating. A cooling hood CH and its heat shield CH-HS (such as the cooling element and heat shield disclosed in WO 2018/041599) are provided to provide a localized cooling power P _CH to the wafer W. The purpose of cooling is to balance the localized cooling power P _CH with the radiation beam heating power P _EUV .

The cooling hood CH is used to remove heat from the wafer W to prevent slippage and reduce the original overlap effect. In order to transfer heat from the wafer to the cooling hood, hydrogen gas is provided between the cooling hood fingers (which are the parts of the cooling hood that are closest to the wafer) and the wafer W through the cooling hood to transfer heat.

The required cooling power of the cooling hood CH is determined by the following equation: Where h is the heat transfer coefficient (depending on pressure, temperature and flight height and TAC), A is the surface area and ΔT _{CH - wafer} is the temperature difference between the cooling hood and the wafer. The flight height is the distance between the (stationary) cooling hood and the wafer on the (moving) wafer stage WT. TAC is the thermal adaptation coefficient of two surfaces and is a physical quantity that characterizes the behavior of gas or vapor particles when they collide with a solid or liquid bulk surface. The value of the adaptation coefficient depends on the surface properties and state and on the composition and pressure of the gas mixture in the environment and on other parameters.

The power that needs to be extracted from the wafer is different for each product layer and ideally should be perfectly balanced with the EUV power and fed into the wafer heating feed forward model (WHFF model). The WHFF model allows one to predict the temperature difference to be neutralized by activating the cooling hood heater or the cooler (928 in FIG. 9). The model can also predict the raw stack effect (934 in FIG. 9) which can be corrected by the optical system of the POB (918 in FIG. 9).

Inputs to the WHFF model may include: • EUV power; • reticle reflectance profile; • effective IR power in the wafer/fixture; • cooling hood power P _CH ; • scan speed; • fixture cooling water flow rate; and • DGL load profile.

Any mismatch in power between the model and reality may contribute to the stacking error.

To reduce the overlay error due to power mismatch, the cooling mask power is calibrated relative to the EUV power. This calibration is performed by a power measurement in the fixture. Since the system can drift, the balance is continuously monitored.

By comparing the measured temperature difference ΔT above the fixture with the modeled value of the WHFF model, any imbalance can be corrected, at least when the imbalance is caused by the cooling hood and not by unknown parasitic heat loads.

The cooling water CW is used to thermally control the fixture CL. By monitoring the temperature of the cooling water T _out -T _in (ΔT between the incoming cooling water and the outgoing cooling water), information about how much heat P _CH is extracted by the cooling hood CH can be determined.

When the flow rate is known and stable, the temperature difference ΔT above the fixture CL is a measure of the cooling hood power P _CH . In an ideal case, there is no parasitic heat load to the wafer and the measured power in the fixture is a balance between EUV and the cooling hood. Different parasitic heat loads act on the wafer/chuck and these parasitic heat loads will interfere with the power measurement and these parasitic heat loads are now described with reference to FIG. 7 .

7 schematically depicts a cross-sectional view of exposure of a wafer on a cooled chuck, wherein cooling devices are used to compensate for radiation beam heating, and wherein there is parasitic wafer and chuck heating.

FIG. 7 includes all the elements of FIG. 6 , but adds parasitic heat loads. The hydrogen used to transport heat from the wafer W to the cooling hood CH can be dispersed in the compartment and also transports heat from the surface facing the wafer W and the fixture CL. This causes a heat load. For example, the wafer stage heat shield assemblies WS-HS-C and WS-HS-D shown in FIGS. 4 and 5 have a surface that can provide power P _{WS - HS} to the fixture via the wafer. In addition, for example, the POB orifice assembly POB-H shown in FIGS. 4 and 5 has a surface that can provide power P _{POB - H} to the fixture via the wafer. In addition, the metrology frame MF shown in FIGS. 4 and 5 and the sensor attached thereto have a surface that can provide power P _MF to the fixture via the wafer. This can be the case if the fixture CL is thermally controlled with a temperature set point that is different from the temperature set point of the metrological frame MF.

As the wafer carrier WT travels on its path through the wafer carrier compartment, it passes other components having surfaces facing respective portions of the path. These surfaces may cause parasitic heat loads. For example, the wafer handler WH may provide power P _WH to the fixture via the wafer. Similarly, when the wafer is oriented and thermally conditioned on the vacuum pre-aligner VPA, the surface of the vacuum pre-aligner may provide power P _VPA (not shown) to the fixture via the wafer as it is transferred from the VPA to the fixture.

The parasitic heat load is summed as a parasitic power P _PAR through the wafer and the fixture, and is added to the fixture cooling power P _CL caused by the imbalance of the radiation beam heating power P _EUV and the cooling cover power P _CH . The powers P _PAR and _PCL caused by the heat load are integrated into one cooling water CW temperature difference T _out -T _in . This makes it impossible to use the cooling water CW temperature difference T _out -T _in to distinguish the actual source of the imbalance. The second problem with the parasitic heat load is that it will directly heat the wafer during exposure, which causes thermal expansion and additional overlay error.

Embodiments of the present invention create a miniature environment in the wafer stage compartment to eliminate parasitic heat loads. This in turn enables on-line (in operational use) calibration and accurate control of cooling hood power.

Parasitic heat loads can be eliminated by providing the same (or very close to the same) stable temperature to the surface facing the wafer from time to time.

Such surfaces include the wafer holder at the wafer stage, and the heat shield in the wafer stage compartment of the lithography apparatus around which the wafer stage moves.

Preferably, the temperature of each of these surfaces is actively controlled to maintain a temperature set point regardless of the varying thermal loads that these surfaces themselves receive during operational use of the lithography apparatus.

To allow for in-line cooling mask calibration, parasitic heat loads are removed from the equation. This is accomplished by means of a thermal mini-environment in the wafer stage compartment. Basically, this means that most or all of the wafer facing surfaces (including the fixture and wafer handler) are actively controlled to the same temperature level. This is called active thermal control.

As discussed above, in the absence of active thermal control, all surfaces facing a wafer stage such as that shown in Figure 4 can be at different temperature levels. This means that each surface causes a different unknown heat load to the wafer (either via hydrogen conduction or radiation). This has an adverse effect on both on-line calibration and direct stacking effects.

In the initial state, all wafer facing surfaces may have different temperature offsets.

In the isothermal regime, all surfaces are calibrated to the same temperature relative to each other, but this temperature may be different from the metrology frame. There is a significant surface area that is still offset (cross-hatched in Figure 4), which still causes parasitic thermal loads to the wafer/chuck.

In the best thermal match state, by lowering the set point of the wafer facing surfaces to the set point of the metrology frame (22°C), there is no longer a temperature difference between either of the surfaces. At this point, all parasitic heat loads from the wafer facing surfaces are minimized.

To ensure that the temperature of each wafer facing surface remains stable under the varying loads applied during exposure, active thermal control is used. This means that each module gets a separate control loop with, for example, a cooling water heater or chiller to maintain a set point, similar to the fixture. This approach is repeated for all wafer facing surfaces. To enable active control of all surfaces to the same set point, for example exactly 22°C, the cooling water can be pre-cooled approximately 100 mK below 22°C. For chilled water cooling, there are several options such as: • Individual Peltier elements per branch; • One single Peltier element, pre-cooling all branches; • Individual cabinets at a reduced set point; and • A single cabinet with multiple outlets, each at a different temperature.

Figure 8 schematically depicts the implementation of active thermal control using a thermal control system according to one embodiment of the present invention.

The cabinet CAB pumps the cooling water in a loop through the components in the wafer carrier compartment via the manifold MAN. These components are the vacuum pre-aligner VPA, the electrostatic chuck CL, the mirror block MB, the wafer carrier heat shield WS-HS (represented in FIG. 4 as WS-HS-A/B/C/D, each with independent thermal control), the cooling cover heat shield CH-HS and the POB orifice POB-H. A separate active thermal control unit ACTU is placed outside the vacuum VAC and holds all heaters H to control the cooling water set point for each branch individually. There are several additional temperature sensors required for the control (each of which is depicted by a circle enclosing a cross). The sensors are used to control the incoming cooling water temperature by measuring the cooling water temperature difference _ΔTH across the individual heaters H. The sensors on the modules are used to suppress dynamic heat loads in the system by measuring the cooling water temperature difference _ΔTC across the individual modules. Alternatively (not shown), the sensors can be located in the return branch of the module. The valve V is used to set the flow rate for calibration under the control of the ATCU.

The top assembly VPA, CL, MB is independently thermally controlled. They are operable to maintain the temperature at a common set point value (22°C in this example), but how they control the water temperature is separate from the ATCU. Because they also use water to actively control the wafer temperature, the feedback loop in this example must be faster than the ATCU controller can provide (which has a heater mounted on the assembly). Together, the ATCU and independent temperature controllers make up the thermal control system.

FIG. 9 schematically depicts an implementation of radiation beam heating compensation using a cooling hood and active thermal control of other components according to one embodiment of the present invention.

The lithography apparatus is configured to project a patterned radiation beam via projection optics 918 onto a target portion of a semiconductor wafer 916 on a fixture 910 held at a wafer stage in a chamber (WSC in FIG. 2 ). The wafer stage is configured to follow a path within the chamber (as described with reference to FIG. 3 ) during operational use of the lithography apparatus. A vacuum is maintained in the chamber, which is critical for use with EUV lithography, where there is an opening between the wafer stage chamber and the POB. The vacuum also has the effect of removing unwanted hydrogen used with cooling devices to reduce parasitic heat transfer from other components in the chamber to the wafer and fixture.

The lithography apparatus has a first component, such as a cooling device heat shield component (CH-HS in Figures 4 to 7), which has a first surface 908 facing a first portion of the routing. The cooling device heat shield is configured to shield at least a portion of the cooling device from the wafer stage.

The lithography apparatus has a second component, such as a wafer stage heat shield assembly (WS-HS-A/B/C/D in FIGS. 4 and 5 ), which has a second surface 912 facing the second portion of the routing.

The thermal control systems 902, 906 are operable to maintain a first temperature of the first surface 908 and a second temperature of the second surface 912 at a common set point magnitude 900, in this example 22° C. This has the effect of reducing parasitic thermal loads and variations in parasitic thermal loads, which improves cooling device cooling calibration, thereby reducing overlay errors.

If there is a temperature offset between the set point of the fixture and the common set point of the first surface and the second surface, the parasitic thermal load will be constant and can be modeled or accounted for by calibration. However, the thermal control system 904 can be operated to maintain the third temperature of the fixture 910 at the common set point value 900. This has the beneficial effect of causing the parasitic thermal load to tend towards zero because all or most of the surfaces facing the wafer (including the fixture below the wafer and the component surfaces above the wafer) are thermally controlled using the common set point value. A common set point value means that the set points are the same, or within the range of thermal control tolerances of the surfaces. Preferably, the instance of the common set point used to control each component or surface is the same. Alternatively, instances of the common set point may preferably differ by less than 0.05° C., or more preferably by less than 0.005° C. Thus, instances of the common set point should be close enough that the parasitic heat load is reduced to significantly less than the fixture cooling power, preferably less than 5% of the fixture cooling power, and more preferably less than 1% of the fixture cooling power.

Additionally or alternatively, surfaces of other heat shield components (such as POB orifices as described with reference to Figures 4 and 5) or metrology frames (such as MF as described with reference to Figures 4 and 5) may be maintained at a common set point magnitude 900. These surfaces have the effect of reducing parasitic heat loads and variations in parasitic heat loads.

A cooling device 914 (CH in FIGS. 6 and 7) is positioned below the projection optics (PS in FIG. 2) and is configured to extract heat generated by absorption of radiation from the target portion. The cooling device has the effect of reducing stack-pair errors, as described above. The heat extraction _PCH of the cooling device 914 shielded by its thermal shield 908 is controlled based on a measurement 920 of the fixture cooling, ΔT 922. This is useful because direct measurements of the cooling device power, such as measuring the coolant liquid of the cooling device, do not accurately reflect the localized cooling on the wafer. Once a common set point is reached at the surface facing the wafer stage path, the measurement of fixture cooling provides a simple measurement of the imbalance between the cooling device power and the radiation beam heating power. In this example, the measurement of fixture cooling includes the measurement of the cooling water CW temperature gradient ( _Tout - _Tin , as shown in Figure 7) and the mass flow rate. Such measurements have the advantage of being relatively simple.

The lithography apparatus is operable to control the projection system 918 based on the heat extraction _PCH of the cooling device to adjust 938 the patterned radiation beam to compensate for substrate deformation using a WHFF model 930. The WHFF model 930 and its input data 924 are described above with reference to FIG. 6. The WHFF model calculates x, y and z exposure corrections 934, which are used to adjust 938 the patterned radiation beam. Adjusting the patterned radiation beam has the effect of reducing the overlap error. The integrity of the adjustment is maintained by controlling the temperature to a common set point at the surface facing the wafer stage path.

The lithography apparatus further includes a wafer pre-aligner (VPA in FIG. 5 ) operable to orient and thermally condition the wafer prior to transfer of the wafer to the fixture 910. The thermal control system is operable to maintain a fourth temperature of the wafer pre-aligner at a common set point magnitude 900. This is not shown in FIG. 9 , but is substantially the same as the control 906 of the wafer handler thermal shield assembly surface 912. Controlling the temperature of the pre-aligner in this manner has the effect of reducing parasitic heat loads on the wafer and fixture.

The embodiments remove nearly all parasitic heat loads from the wafer facing surface toward the fixture. The embodiments also reduce the direct heat load effects on the wafer facing surface that cause thermal expansion of the wafer, thereby further reducing overlay error.

As used herein, the terms "radiation" and "beam" cover all types of electromagnetic radiation, including ultraviolet (UV) radiation (e.g., having a wavelength of or about 365 nm, 355 nm, 248 nm, 193 nm, 157 nm or 126 nm) and extreme ultraviolet (EUV) radiation (e.g., having a wavelength in the range of 5 nm to 20 nm), as well as particle beams, such as ion beams or electron beams.

The term "lens", when the context permits, may refer to any one or combination of various types of optical components, including refractive, reflective, magnetic, electromagnetic, and electrostatic optical components.

The breadth and scope of the present invention shall not be limited by any of the above-described exemplary embodiments, but shall be defined solely in accordance with the following claims and their equivalents. Clause 1. A lithography apparatus configured to project a patterned radiation beam via projection optics onto a target portion of a semiconductor wafer held on a fixture at a wafer stage in a compartment, wherein the wafer stage is configured to follow a path within the compartment during operational use of the lithography apparatus, and wherein the lithography apparatus comprises: - a first component having a first surface facing a first portion of the path; - a second component having a second surface facing a second portion of the path; - a thermal control system operable to maintain a first temperature of the first surface and a second temperature of the second surface at a common set point value. Item 2. A lithography apparatus as in Item 1, wherein the thermal control system is operable to maintain a third temperature of the fixture at the common set point value. Item 3. A lithography apparatus as in Item 1 or Item 2, further comprising a cooling device positioned below the projection optics and configured to extract heat generated by absorption of the radiation from the target portion, wherein heat extraction of the cooling device is controlled based on measurements of cooling of the fixture. Item 4. A lithography apparatus as in Item 3, wherein the measurements of cooling of the fixture include measurements of a cooling water temperature gradient and mass flow rate. Item 5. A lithography apparatus as in Item 3 or Item 4, wherein the lithography apparatus is operable to control the projection system using a model to adjust the patterned radiation beam based on the heat extraction of the cooling device to compensate for substrate deformation. Item 6. A lithography apparatus as in any preceding item, further comprising a wafer pre-aligner, the wafer pre-aligner being operable to orient and thermally condition the wafer prior to transfer of the wafer to the fixture, and wherein the thermal control system is operable to maintain a fourth temperature of the wafer pre-aligner at the common set point value. Item 7. A lithography apparatus as in any preceding item, wherein during operational use of the lithography apparatus, a vacuum is maintained in the compartment. Item 8. A lithography apparatus as in any preceding item, wherein a component comprises a device cooling device thermal shield configured to shield at least a portion of the cooling device from the wafer stage. Item 9. A lithography apparatus as in any preceding item, wherein a component comprises a thermal shield. Item 10. A lithography apparatus as in any preceding item, wherein a component comprises a metrology frame. Item 11. A lithography method comprising: - projecting a patterned radiation beam via projection optics onto a target portion of a semiconductor wafer on a fixture held at a wafer stage in a compartment of a lithography apparatus, wherein the lithography apparatus comprises: - a first component having a first surface facing a first portion of a route in the compartment; and - a second component having a second surface facing a second portion of the route in the compartment; - transporting the wafer stage along the route in the compartment; and - operating a thermal control system to maintain a first temperature of the first surface and a second temperature of the second surface at a common set point value. Item 12. The lithography method of Item 11, further comprising operating the thermal control system to maintain a third temperature of the fixture at the common set point value. Item 13. The lithography method of item 11 or item 12, further comprising operating a cooling device positioned below the projection optics to extract heat generated by absorption of the radiation from the target portion, wherein the heat extraction of the cooling device is controlled based on measurements of cooling of the fixture. Item 14. The lithography method of item 13, wherein the measurements of cooling of the fixture include measurements of a cooling water temperature gradient and mass flow rate. Item 15.   The lithography method of item 13 or item 14, comprising using a model to control the projection system to adjust the patterned radiation beam based on the heat extraction of the cooling device to compensate for substrate deformation. Item 16. The lithography method of any of Items 11 to 15, further comprising orienting and thermally conditioning the wafer using a wafer pre-aligner prior to transferring the wafer to the fixture, and operating the thermal control system to maintain a fourth temperature of the wafer pre-aligner at the common set point value. Item 17. The lithography method of any of Items 11 to 16, further comprising maintaining a vacuum in the chamber. Item 18. The lithography method of any of Items 11 to 17, wherein an assembly comprises a device cooling device thermal shield configured to shield at least a portion of the cooling device from the wafer stage. Item 19. The lithography method of any of Items 11 to 18, wherein an assembly comprises a thermal shield. Clause 20. A lithography method as in any one of clauses 11 to 19, wherein a component comprises a metrology frame.

42: radiation system 47: source chamber 50: collector/normal incidence collector mirror 52: aperture 53: reflector 54: reflector 55: radiation beam 56: radiation beam 57: patterned beam/radiation beam 58: reflective element 59: reflective element 61: laser system 63: laser beam 65: beam delivery system 67: aperture 69: target material/fuel stream 71: target material supply 72: interceptor 73: plasma formation position 100: lithography apparatus 200: step 202: step/measurement information 204: Step/Measurement Information 206: Recipe Data 208: Measurement Data 210: Step 212: Step 214: Step 216: Step 218: Step 220: Step 900: Common Set Point Value 902: Thermal Control System 904: Thermal Control System 906: Thermal Control System/Control 908: First Surface 910: Fixture 912: Second Surface/Wafer Handler Thermal Shield Surface 914: Cooling Device 916: Semiconductor Wafer 918: Projection Optics 920: Measurement 922: ΔT 924: Input data 928: Temperature difference 930: Wafer heat feed forward (WHFF) model 934: x, y and z exposure correction 938: Adjustment ATCU: Active thermal control unit B: Radiation beam C: Target part CAB: Cabinet CH: Cooling cover CH-HS: Cooling cover heat shield assembly/heat shield CL: Electrostatic fixture CW: Cooling water EXP: Exposure station H: Heater IF: Intermediate focus/virtual source point IL: Illumination system/illumination M1: Mask alignment mark M2: Mask alignment mark MA: Patterned device/multiplied mask MAN: Manifold MB: Mirror block MEA: Measurement operation/Measuring station MF: Metrology frame MT: Support structure/support P1: Substrate alignment mark P2: Substrate alignment mark PE: Protective film PM: First positioner POB-H: Projection optics box aperture assembly PS: Projection system PS1: Position sensor PS2: Position sensor PW: Second positioner P _CH : Localized cooling power/heat/cooling mask power P _CL : Fixture cooling power P _EUV : Radiation beam heating power P _MF : Power P _PAR : Parasitic power P _POB-H : Power P _WH : Power P _WS-HS :PowerSO:Source moduleSPF:Spectral purity filterV:ValveVAC:VacuumVPA:Vacuum pre-alignerW:Substrate/waferW':SubstrateW'':Exposed substrateWH:Wafer handler/assemblyWSC:Wafer stage compartmentWH-HS:Wafer stage heat shieldWS-HS-A:Assembly/wafer stage heat shield assemblyWS-HS-B:Assembly/wafer stage heat shield assemblyWS-HS-C:Assembly/wafer stage heat shield assemblyWS-HS-D:Assembly/wafer stage heat shield assemblyWT:Substrate stage/wafer _stageΔTH :Cooling water temperature _{differenceΔTC} :Cooling water temperature difference

Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying schematic drawings, in which corresponding reference numerals indicate corresponding parts, and in which:

FIG1 schematically depicts a lithography apparatus having reflective projection optics;

FIG. 2 is a more detailed view of the apparatus of FIG. 1 with a wafer stage compartment;

FIG. 3 schematically illustrates the measurement and exposure process in a dual-stage lithography apparatus according to known practice and modified according to an embodiment of the present invention;

FIG. 4 schematically depicts a bottom-up view of the interior of a wafer stage compartment of a lithography apparatus;

FIG5 schematically depicts a cross-sectional view of the contents of a wafer stage compartment of a lithography apparatus;

FIG6 schematically depicts a cross-sectional view of an exposure of a wafer on a cooled fixture, wherein a cooling device is used to compensate for radiation beam heating;

FIG. 7 schematically depicts a cross-sectional view of exposure of a wafer on a cooled fixture, wherein a cooling device is used to compensate for radiation beam heating, and wherein there is parasitic wafer and fixture heating;

FIG8 schematically depicts an implementation of active thermal control using a thermal control system according to an embodiment of the present invention; and

FIG. 9 schematically depicts an implementation of radiation beam heating compensation using a cooling hood and active thermal control of other components according to one embodiment of the present invention.

900: Common set point value

902: Thermal control system

904: Thermal control system

906: Thermal control system/control

908: First surface

910: Clamp

912: Second surface/wafer processor heat shielding assembly surface

914: Cooling device

916:Semiconductor wafer

918: Projection optics

920: Measurement

922:△T

924: Input data

928: Temperature difference

930: Wafer Heat Feed Forward (WHFF) Model

934: x, y and z exposure correction

938:Adjustment

P _CH : Localized cooling power/heat/cooling cover power

P _CL : Fixture cooling power

P _EUV : Radiation beam heating power

P _PAR : Parasitic Power

Claims (21)

An active thermal control device includes a compartment including a wafer stage configured to hold a semiconductor wafer on a fixture, wherein the wafer stage is configured to follow a route within the compartment during operational use, the device including: a first component having a first surface facing a first portion of the route; a second component having a second surface facing a second portion of the route, wherein the first component and the second component are heat shield components; and a thermal control system operable to maintain a first temperature of the first surface and a second temperature of the second surface at a common set point value. A device as claimed in claim 1, wherein the thermal control system is operable to maintain a third temperature of the fixture at the common set point value. A device as claimed in claim 1 or claim 2, further comprising a cooling device positioned below the projection optics, a patterned radiation beam being projected through the projection optics onto a target portion of the semiconductor wafer, the cooling device being configured to extract heat generated by absorption of the radiation from the target portion, wherein heat extraction by the cooling device is controlled based on a measurement of cooling of the fixture. A device as claimed in claim 3, wherein the measurements of cooling of the fixture include measurements of a cooling water temperature gradient and mass flow rate. A device as claimed in any one of claims 1 to 2, wherein the thermal shielding components include a cooling device thermal shield configured to shield at least a portion of the cooling device from the wafer stage. A device as claimed in any one of claims 1 to 2, wherein the thermal shielding components include a wafer stage thermal shield. A device as claimed in any one of claims 1 to 2, further comprising a metrology frame, wherein the thermal control system is operated to maintain a temperature of a surface of the metrology frame at the common set point value. A lithography apparatus comprising an active thermal control device as claimed in any one of claims 1 to 7. A lithography apparatus as claimed in claim 8, wherein the lithography apparatus is operable to control the projection optics using a model based on the heat extraction of the cooling device to adjust the patterned radiation beam to compensate for substrate deformation. A lithography apparatus as claimed in any one of claims 8 to 9, further comprising a wafer pre-aligner operable to orient and thermally condition the wafer prior to transfer of the wafer to the fixture, and wherein the thermal control system is operable to maintain a fourth temperature of the wafer pre-aligner at the common set point value. A lithography apparatus as claimed in any one of claims 8 to 9, wherein a vacuum is maintained in the compartment during operation of the lithography apparatus. A lithography method comprising: projecting a patterned radiation beam via projection optics onto a target portion of a semiconductor wafer on a fixture held at a wafer stage in a compartment of a lithography apparatus, wherein the lithography apparatus comprises: a first component having a first surface facing a first portion of a route in the compartment; and a second component having a second surface facing a second portion of the route in the compartment, wherein the first component and the second component are heat shield components; transporting the wafer stage along the route in the compartment; and operating a thermal control system to maintain a first temperature of the first surface and a second temperature of the second surface at a common set point value. The lithography method of claim 12, further comprising operating the thermal control system to maintain a third temperature of the fixture at the common set point value. A lithography method as claimed in claim 12 or claim 13, further comprising operating a cooling device positioned below the projection optical element to extract heat generated by absorption of the radiation from the target portion, wherein the heat extraction of the cooling device is controlled based on a measurement of cooling of the fixture. The lithography method of claim 14, wherein the measurements of the cooling of the fixture include measurements of a cooling water temperature gradient and a mass flow rate. A lithography method as claimed in claim 14, comprising using a model to control the projection system to adjust the patterned radiation beam based on the heat extraction of the cooling device to compensate for substrate deformation. A lithography method as in any of claims 12 to 13, further comprising using a wafer pre-aligner to orient and thermally condition the wafer before the wafer is transferred to the fixture, and operating the thermal control system to maintain a fourth temperature of the wafer pre-aligner at the common set point value. A lithography method as claimed in any one of claims 12 to 13, further comprising maintaining a vacuum in the chamber. A lithography method as in any one of claims 12 to 13, wherein the heat shield assemblies include a cooling device heat shield configured to shield at least a portion of the cooling device from the wafer stage. A lithography method as claimed in any one of claims 12 to 13, wherein the heat shielding components include a wafer stage heat shielding member. A lithography method as in any one of claims 12 to 13, wherein the lithography apparatus further comprises a metrology frame, the method further comprising operating the thermal control system to maintain a temperature of a surface of the metrology frame at the common set point value.