TWI848793B - Control circuit and method for use in stackable multiphase power converter - Google Patents

Abstract

A conversion control circuit controls plural stackable sub-converters which are coupled in parallel to generate an output power to a load, the conversion control circuit includes: a current sharing terminal, wherein a current sharing signal is configured to be connected to the current sharing terminals, in parallel, of the plurality of the conversion control circuits; and a current sharing circuit, configured to generate or receive the current sharing signal which is generated according to an output current of the output power; wherein the conversion control circuit adjusts the power stage circuit according to the current sharing signal for current sharing among the plural stackable sub-converters.

Description

Control circuit and method for stackable multi-phase power converter

The present invention relates to a power converter, in particular to a stackable multi-phase power converter. The present invention also relates to a stackable conversion control circuit for controlling the stackable multi-phase power converter.

Stackable multiphase power converters can provide high-efficiency DC/DC power conversion to meet the needs of high load current and fast transient response. Therefore, in high performance computing (HPC) applications, stackable multiphase power converters are widely used in CPU, GPU, and artificial intelligence. When the load current increases, the number of phases of the stackable multiphase power converter will increase; when the load is light, the number of phases will be reduced to save energy.

FIG1 shows a stackable multi-phase power converter of the prior art: US 11,081,954 "Phase shedding control method for a multi-phase switching converter having a daisy chain topology configuration". The prior art utilizes a daisy chain topology configuration to control a stackable multi-phase power converter.

The disadvantage of the daisy chain topology configuration shown in the prior art of Figure 1 is that it has poor fault tolerance and poor current sharing. When any conversion control circuit in the daisy chain topology fails, the entire power converter will shut down.

Compared to the above-mentioned prior art, the present invention provides a control circuit for controlling a stackable multi-phase power converter, which has fewer control signals, can be achieved in a simpler and more reliable way, and has a better current balancing effect. The control signal of the present invention is connected in parallel to the stackable control circuit of the stackable multi-phase power converter, rather than using a daisy chain topology.

In one aspect, the present invention provides a conversion control circuit for controlling a stackable multi-phase power converter, wherein the stackable multi-phase power converter includes a plurality of stackable sub-converters, wherein each of the plurality of stackable sub-converters includes a power stage circuit and a corresponding conversion control circuit, wherein the plurality of power stage circuits corresponding to the plurality of stackable sub-converters are coupled in parallel with each other to generate an output power to a load, wherein the conversion control circuit is used to control at least one switch of the power stage circuit to switch the corresponding An inductor is used to generate the output power supply, and the conversion control circuit includes: a current balancing terminal, wherein a current balancing signal is coupled to a plurality of the current balancing terminals of the plurality of the conversion control circuits connected in parallel; and a current balancing circuit, used to generate or receive the current balancing signal at the current balancing terminal, wherein the current balancing signal is generated according to an output current of the output power supply; wherein the conversion control circuit is used to adjust the power stage circuit according to the current balancing signal to perform current balancing between the plurality of stackable sub-converters.

In a preferred embodiment, the conversion control circuit is configured as a master circuit or a slave circuit; wherein the master circuit is used to generate the current balancing signal, and the slave circuit is used to receive the current balancing signal.

In a preferred embodiment, the stackable sub-converter is a multi-stage buck converter.

In a preferred embodiment, the stackable sub-converter is a three-stage buck converter.

In a preferred embodiment, the conversion control circuit further includes a reference voltage for adjusting an output voltage of the output power source; wherein the reference voltage corresponding to the slave circuit is adjusted according to the current sharing signal to perform current sharing.

In a preferred embodiment, before the reference voltage of the slave circuit is adjusted for current sharing, the reference voltage corresponding to the slave circuit is lower than the reference voltage corresponding to the master circuit.

In a preferred embodiment, the conversion control circuit further includes a feedback voltage divider, a reference voltage, an error amplifier, a ramp signal and a modulation comparator, which are configured as a feedback loop to adjust an output voltage of the output power source; wherein an offset value of the feedback voltage divider or an input offset value of the error amplifier is adjusted according to the current balancing signal to perform current balancing.

In a preferred embodiment, the conversion control circuit further comprises: a synchronization terminal, wherein a synchronization signal is coupled to a plurality of synchronization terminals of a plurality of the conversion control circuits connected in parallel; wherein the synchronization signal comprises a plurality of pulses, the plurality of pulses are continuously counted into a count value, wherein the synchronization signal comprises a reset signal for resetting and starting the count value; wherein when the count value is related to a phase sequence number of the conversion control circuit, the conversion control circuit enables the power stage circuit to generate the output power; wherein the master control circuit is used to generate the synchronization signal via the synchronization terminal, and the slave circuit is used to receive the synchronization signal via the synchronization terminal.

In a preferred embodiment, the conversion control circuit further includes an inductive flow detection circuit for generating an inductive flow detection signal according to the corresponding portion of the output current generated by the stackable sub-converter; wherein the current sharing signal is equal to the inductive flow detection signal of the main control circuit.

In a preferred embodiment, the conversion control circuit further includes an identification terminal for setting the phase sequence number, wherein the phase sequence number is determined according to an electrical parameter level on the identification terminal.

In a preferred embodiment, the conversion control circuit is further determined to operate as the master circuit or the slave circuit based on the phase sequence number.

In a preferred embodiment, the conversion control circuit further includes a certain current source coupled to a resistor via the identification terminal, wherein the phase sequence number is determined according to a voltage level of the identification terminal.

In a preferred embodiment, a pulse of the synchronization signal having a higher voltage level is used to indicate the reset signal.

In a preferred embodiment, the reset signal is generated when the count value reaches a start-up phase number, wherein the start-up phase number increases as a load current consumed by the load increases.

In a preferred embodiment, the stackable subconverter is activated by triggering a corresponding pulse of the synchronization signal.

In a preferred embodiment, the conversion control circuit of the three-stage buck converter generates a pulse width modulation (PWM) signal to control the power stage circuit to generate the output power, wherein the conversion control circuit adjusts the pulse width of the PWM signal to balance the voltage of a Flying Chi capacitor of the three-stage buck converter to half of an input voltage of the stackable multi-phase power converter.

In a preferred embodiment, the stackable sub-converter operates in a current mode control.

In a preferred embodiment, in a heavy load state, the stackable multi-phase power converter operates in a constant frequency switching mode.

In a preferred embodiment, the conversion control circuit is configured as an integrated circuit, the synchronization end corresponds to a synchronization pin of the integrated circuit, and the current sharing end corresponds to a current sharing pin of the integrated circuit.

In another aspect, the present invention provides a control method for controlling a stackable multi-phase power converter, wherein the stackable multi-phase power converter includes a plurality of stackable sub-converters, wherein each of the plurality of stackable sub-converters includes a power stage circuit, wherein the plurality of power stage circuits corresponding to the plurality of stackable sub-converters are coupled in parallel to each other to generate an output power to a load, wherein the power stage circuit includes at least one switch to switch an inductor to generate the output power, wherein one of the plurality of stackable sub-converters is configured as a master stackable The invention relates to a stackable sub-converter, and another one of the plurality of stackable sub-converters is configured as a slave stackable sub-converter. The control method comprises: controlling the at least one switch of the power stage circuit to switch the corresponding inductor; controlling the master stackable sub-converter to generate a current sharing signal according to an output current of the output power source; controlling the slave stackable sub-converter to receive the current sharing signal; and each of the plurality of stackable sub-converters adjusts the corresponding power stage circuit according to the current sharing signal to perform current sharing among the plurality of stackable sub-converters.

In a preferred embodiment, the control method further includes: generating a reference voltage for adjusting an output voltage of the output power source; and adjusting the reference voltage of the slave stackable sub-converter according to the current sharing signal to perform current sharing.

In a preferred embodiment, before the reference voltage of the slave stackable sub-converter is adjusted for current sharing, the reference voltage of the slave stackable sub-converter is lower than the reference voltage of the master stackable sub-converter.

In a preferred embodiment, the conversion control circuit further includes a feedback voltage divider, a reference voltage, an error amplifier, a ramp signal and a modulation comparator, which are configured as a feedback loop to adjust an output voltage of the output power source; the control method further includes: compensating an input offset value of the feedback voltage divider or the error amplifier of the slave stackable sub-converter according to the current sharing signal to perform current sharing.

In a preferred embodiment, the control method further includes: controlling the master stackable sub-converter to generate a synchronization signal; controlling the slave stackable sub-converter to receive the synchronization signal; wherein the synchronization signal includes a plurality of pulses, the plurality of pulses are continuously counted into a count value, wherein the synchronization signal includes a reset signal for resetting and starting the count value; and when the count value is related to a corresponding phase sequence number, enabling a corresponding power stage circuit to generate the output power.

In a preferred embodiment, the control method further includes: generating an inductive flow detection signal according to the corresponding portion of the output current generated by the stackable sub-converter; wherein the current sharing signal is equal to the inductive flow detection signal of the master stackable sub-converter.

The following will be explained in detail through specific embodiments to make it easier to understand the purpose, technical content, features and effects of the present invention.

10,20,30,40: Power stage circuit

100:Conversion control circuit

1015: Stackable multi-phase power converter

102A, 102B: Stackable multi-phase power converter

102C1,102C2: Integrated circuit

103,104,105,107,108,111,112:Resistance

106: Stackable subconverter

109,131:Capacitor

110: Stackable multi-phase power converter

113: Operational amplifier

114,121:Amplifier

116,115,117: Transistor

125:Unit gain buffer

130: Error amplifier

136: Fixed current source

137: Inverter

141: Operational amplifier

141,142: Resistor

145: Switch

15,25,35,45: conversion control circuit

150,180: Comparator

151: Single pulse generator

1510,1520,1530,1540: Stackable subconverter

155: Single pulse generator

16,26,36,46:Driver

160: Buffer

161:Signal generating circuit

17,27,37,47:Resistance

170:Multiplexer

171,172: Comparator

1710: Stackable subconverter

173,174,177,178: Adder

176: Output voltage regulation circuit

179: Feichi capacitor balancing circuit

185: Current flow measurement circuit

195: Reference adjustment circuit

1N:Driver

205: Multi-stage switching control circuit

210: Constant current source

215: Modulation circuit

220:Analog-to-digital converter

225: Synchronous generation circuit

230:Counter

235: Inverter

236: Reset generation circuit

240: Delay unit

245: Local generation circuit

250: Digital comparator

260: Flip-flop

310: Comparison circuits

311: Interleave time register

315: Comparator

317: Inverter

319: And the gate

320:Analog-to-digital converter

322: Interleave timer

325: Flip-flop

330: Digital comparator

331,450: Pulse generator

335: Flip-flop

350: Single pulse generator

360: Buffer

370:Multiplexer

410:Analog-to-digital converter

415:Logic controller

420: Phase number register

435: Comparator

438: And the gate

50: Power stage circuit

503:Conversion control circuit

510,610: Comparator

517,617,717,817: Transistor

520,620:Multiplexer

53: Pulse width modulation timing circuit

55,65,75,85: conversion control circuit

56: Master-slave decision circuit

560: Pulse mixer

57,57’: Synchronous circuit

58: Phase enabling circuit

59,59’: Reset circuit

5N: Conversion control circuit

680: Comparator

71,72:Resistance

710,720: Buffer

715,725:Diode

750: Transistor

77: Capacitor

80: Power stage circuit

90: On-time timing circuit

91: Single pulse generator

92: Latch circuit

93: And the gate

94: Inductor

95: Minimum off time timing circuit

99: Load

CFLY: Feichi Capacitor

CK: Oscillation signal

CLK: clock signal

CMP: Comparison signal

CS+, CS-: current flow detection signal

ENB:Signal

FSW:Signal

G1,G2,G3,G4: driving signal

I115,I116,I117: Current

IBUS: current sharing signal

ICS: output current signal

ID#: Identification terminal

ID_N: Phase sequence number

Io0,Io2,Io3,Io4,IoN: output current

IOS: offset current

IS#: Current sharing terminal

ISUM: load current

ISW: Switching current signal

IX: Number of start phases

L1, L2, L3, LN: Inductor

MS: Master signal

MST: Master control circuit

N: integer

N_max: Maximum number of phases

N0: Power stage circuit

NX: count value

PWM1: During the first phase

PWM2: Second phase period

QH: Bridge switch

QL: Downbridge switch

R#: Reset terminal

R_PLS: Master reset generates signal

R_PLSL: slave reset generation signal

R1, R2, R3: resistors

RAMP: Ramp signal

RAMP1, RAMP2: Ramp signal

RDY: ready signal

RMC: Merge ramp signal

RST: Reset signal

RSTn: Inverted local reset signal

RX: local reset signal

S_PLS: Synchronous signal generation

S1, S2, SN: slave circuit

SID: identification signal

SLOPE1, SLOPE2: ramp signal

SPWM: pulse width modulation control signal

SW: Switch node

SW0~SW7: switch nodes

SX: local synchronization signal

SY: Interlaced local synchronization signal

SYNC: synchronization signal

t0~t7: Time point

t0’,t1’: time point

Ton: conduction time

Ton1, Ton2, Ton3, Ton4: PWM pulse width

TPW: Pulse period

TX: Interleaved cycle

VA: Amplify signal

Vadj: Adjust the signal

VCFLY: Voltage on the Feichi capacitor

VCOM1, VCOM2: Error signal

VCP,VCN: Feichi capacitor voltage

Verr: Error amplification signal

VFB: Feedback voltage

VH: higher voltage level

VIBUS: Voltage of current sharing signal

VICS: voltage of output current signal

VIN: Input voltage

VL: lower voltage level

VO: output voltage

VR: Reference voltage

VREF: reference voltage

Vst1, Vst2, Vst3, Vst4, VstN: voltage on the identification terminal

VT1: Threshold voltage

VTH: Threshold value

Y#: Synchronous end

Figure 1 shows a prior art stackable multi-phase power converter.

FIG2A shows a schematic diagram of a preferred embodiment of the stackable multi-phase power converter of the present invention.

FIG2B shows a schematic diagram of another preferred embodiment of the stackable multi-phase power converter of the present invention.

FIG2C shows a schematic diagram of a more specific embodiment of a stackable sub-converter in the stackable multi-phase power converter of the present invention.

FIG3 shows a specific block diagram of a preferred embodiment of the conversion control circuit of the present invention (FIG. 2A).

FIG4 shows a waveform diagram of a preferred embodiment of the stackable 4-phase power converter of the present invention as shown in FIG2A.

FIG5 shows a switching waveform diagram of a preferred embodiment of an 8-phase power converter using a stackable control circuit according to the present invention.

FIG6 shows a schematic diagram of a preferred embodiment of the stackable sub-converter and pulse width modulation timing circuit of the stackable multi-phase power converter of the present invention.

FIG7 shows a schematic diagram of a preferred embodiment of the synchronization circuit for generating a synchronization signal of the present invention.

FIG8 is a schematic diagram showing a preferred embodiment of a phase enabling circuit for generating a ready signal of the present invention.

FIG9 shows a schematic diagram of a preferred embodiment of the reset circuit for generating a reset signal of the present invention.

FIG10 shows a schematic diagram of another preferred embodiment of the stackable multi-phase power converter of the present invention.

FIG11 shows the phase switching waveform diagram of a preferred embodiment 4 of the conversion control circuit shown in FIG10 of the present invention.

FIG12 is a schematic diagram showing a preferred embodiment of the synchronization circuit of the present invention corresponding to FIG10 and FIG11 for generating a synchronization signal of a mixed reset signal.

FIG13 shows a schematic diagram of a preferred embodiment of the reset circuit for generating a local reset signal corresponding to FIG10, FIG11 and FIG12 of the present invention.

FIG14 shows a schematic diagram of a preferred embodiment of the pulse mixer of the present invention corresponding to the synchronous circuit of FIG10 , FIG11 and FIG12 .

FIG15 shows a block diagram of a preferred embodiment of the stackable multi-phase power converter of the present invention.

FIG16 shows the phase switching waveform diagram of the preferred embodiment 4 of the present invention corresponding to FIG15.

FIG17 is a schematic diagram showing a preferred embodiment of a stackable sub-converter of the stackable multi-phase power converter of the present invention.

FIG18 shows a schematic diagram of a preferred embodiment of the current flow detection circuit of the conversion control circuit of the present invention.

FIG19 shows a schematic diagram of a preferred embodiment of the reference adjustment circuit of the conversion control circuit of the present invention.

FIG20 shows a schematic diagram of a preferred embodiment of a multi-stage switching control circuit for generating drive signals G1, G2, G3, and G4 in the conversion control circuit of the present invention.

FIG. 21A shows a schematic diagram of a preferred embodiment of a modulation circuit for generating pulse width modulation signals PWM1 and PWM2 in the conversion control circuit of the present invention.

FIG. 21B shows a schematic diagram of a preferred embodiment of a modulation circuit for generating pulse width modulation signals PWM1 and PWM2 in the conversion control circuit of the present invention.

FIG22 is a schematic diagram showing a preferred embodiment of a synchronous generation circuit for generating a synchronous generation signal in the conversion control circuit of the present invention.

FIG. 23 shows a schematic diagram of a preferred embodiment of a reset generation circuit for generating a master reset generation signal in the conversion control circuit of the present invention.

FIG. 24 shows a schematic diagram of a preferred embodiment of a local generation circuit for generating a local synchronization signal, a local reset signal and a master control signal in the conversion control circuit of the present invention.

The figures in this invention are schematic, and are mainly intended to show the coupling relationship between the circuits and the relationship between the signal waveforms. The circuits, signal waveforms and frequencies are not drawn in proportion. For the sake of clarity, many practical details will be described in the following description, but this is not intended to limit the scope of the patent application of this invention.

FIG2A shows a schematic diagram of a preferred embodiment of the stackable multi-phase power converter of the present invention. The stackable multi-phase power converter 102A includes power stage circuits 10, 20, 30 and 40, which are coupled in parallel to generate an output power (e.g., corresponding to an output voltage VO) to supply power to a load 99. In one embodiment, the power stage circuits 10, 20, 30 and 40 operate in staggered phases. Specifically, the power stage circuits 10, 20, 30 and 40 are used to switch inductors L1, L2, L3 and LN to achieve staggered switching power conversion, where N is an integer greater than 1.

In one embodiment, the power stage circuit is a buck converter, however, this is not intended to limit the scope of the invention. The power stage circuit may also be configured as other switching power converters, such as a boost converter, a buck-boost converter, a flyback converter, etc.

The stackable multi-phase power converter further includes conversion control circuits 15, 25, 35 and 45, which are respectively used to control the switching of the corresponding power stage circuits 10, 20, 30 and 40. In one embodiment, the stackable multi-phase power converter further includes a corresponding number of drivers (16, 26, 36, 46), wherein each driver is respectively coupled between the corresponding conversion control circuit and the power stage circuit to drive the switch of the power stage circuit.

In one embodiment, each conversion control circuit 15, 25, 35 and 45 is programmable to be configured as a master circuit or a slave circuit, and the staggered phase sequence number can also be programmable. Please continue to refer to Figure 2A. In one embodiment, each conversion control circuit 15, 25, 35 and 45 includes an identification terminal ID# for setting the phase sequence number ID_N. In one embodiment, a certain current source in the conversion control circuit is used to coordinate with a resistor to determine the phase sequence number ID_N of the conversion control circuit. Resistors 17, 27, 37, and 47 are respectively coupled to the conversion control circuits 15, 25, 35, and 45 to set the phase sequence number ID_N of the corresponding conversion control circuits, wherein the phase sequence number ID_N is determined according to the voltage level on the identification terminal ID#. In one embodiment, the conversion control circuit determines the corresponding phase sequence number ID_N by detecting the voltage on the identification terminal ID# (e.g., Vst1, Vst2, Vst3, and Vst4).

In one embodiment, the identification terminal ID# of the conversion control circuit 15 is coupled to the ground potential to set its phase sequence number ID_N to 0 (that is, the resistor 17 can be omitted and short-circuited). In one embodiment, the phase sequence number ID_N is further used to determine whether the conversion control circuit is configured as a master circuit or a slave circuit. In one embodiment, the identification terminal ID# of the conversion control circuit 15 is coupled to the ground potential to set its phase sequence number ID_N to 0, thereby setting the conversion control circuit 15 as a master circuit (represented by MST in FIG. 2A ). In one embodiment, the relationship between the resistance values R27, R37, and R47 of the resistors 27, 37, and 47 is: R27<R37<R47, thereby setting the phase sequence numbers ID_N of the conversion control circuits 25, 35, and 45 to 1, 2, and 3. In one embodiment, the phase sequence number ID_N other than 0 (master control circuit) will determine the conversion control circuit (e.g. 25, 35, 45) as a slave circuit (represented by S1, S2, SN in FIG. 2A ).

Please continue to refer to Figure 2A. In one embodiment, each conversion control circuit 15, 25, 35, 45 includes a synchronization terminal Y# for transmitting and receiving a synchronization signal SYNC.

In one embodiment, all synchronization terminals Y# (i.e., the synchronization terminals Y# of the conversion control circuits 15, 25, 35, or 45) are coupled to each other, or from another point of view, all synchronization terminals Y# are coupled to each other in parallel. In one embodiment, the master circuit (i.e., the conversion control circuit 15) generates and transmits the synchronization signal SYNC via the corresponding synchronization terminal Y#. On the other hand, the slave circuit (i.e., the conversion control circuit 25, 35, or 45) is used to receive the synchronization signal SYNC via the corresponding synchronization terminal Y#.

Please continue to refer to Figure 2A. In one embodiment, each conversion control circuit 15, 25, 35 and 45 includes a reset terminal R# for transmitting and receiving a reset signal RST.

In one embodiment, all reset terminals R# (i.e., reset terminals R# of conversion control circuits 15, 25, 35, or 45) are coupled to each other, or from another point of view, all synchronization terminals Y# are coupled to each other in parallel. In one embodiment, the master circuit (i.e., conversion control circuit 15) generates and transmits a reset signal RST via the corresponding reset terminal R#. On the other hand, the slave circuit (i.e., conversion control circuit 25, 35, or 45) is used to receive the reset signal RST via the respective corresponding reset terminal R#.

FIG2B shows another preferred embodiment of the stackable multi-phase power converter of the present invention. The stackable multi-phase power converter 102B is similar to the stackable multi-phase power converter 102A, except that the identification terminal ID# of the conversion control circuit in the stackable multi-phase power converter 102B is omitted. In this embodiment, the phase sequence number ID_N can be set by other means, such as: a pre-programmed single or multiple write programmable memory circuit, or a digital communication interface (such as an integrated bus circuit I ² C).

FIG2C shows a schematic diagram of a more specific embodiment of a stackable sub-converter 102C in the stackable multi-phase power converter of the present invention. The stackable sub-converter is responsible for power transmission of one phase of the stackable multi-phase power converter. A plurality of stackable sub-converters are coupled in the manner shown in FIG2A to configure a stackable multi-phase power converter.

In one embodiment, the conversion control circuit (e.g., 5N) is integrated into an integrated circuit. In one embodiment, the conversion control circuit (e.g., 5N) and the driver (e.g., 1N) can be integrated into an integrated circuit (e.g., 102C1). In one embodiment, the conversion control circuit, the driver, and the power stage circuit (e.g., N0) can be integrated into an integrated circuit (e.g., 102C2).

FIG3 shows a specific block diagram of a preferred embodiment (FIG. 2A) of the conversion control circuit of the present invention. In this embodiment, the conversion control circuit 503 includes a master-slave decision circuit 56, a synchronization circuit 57, a phase enabling circuit 58, a reset circuit 59, and a pulse width modulation (PWM) timing circuit 53.

The master-slave decision circuit 56 is used to generate a master signal MS according to the voltage VstN on the identification terminal ID# of the conversion control circuit 503, thereby indicating that the conversion control circuit 503 is a master circuit or a slave circuit. In one embodiment, the enable state represents the master circuit. The reset circuit 59 is used to generate a local reset signal RX according to the reset signal RST, wherein when the conversion control circuit is configured as a master circuit (for example, indicated by the enable state of the master signal MS, the same below), the reset circuit 59 generates a reset signal RST at the reset terminal R#. When the conversion control circuit 503 is configured as a slave circuit (for example, indicated by the disable state of the master signal MS, the same below), the reset circuit 59 receives the reset signal RST via the reset terminal R#.

The synchronization circuit 57 is used to generate the local synchronization signal SX according to the synchronization signal SYNC. When the conversion control circuit 503 is configured as a master circuit, the synchronization circuit 57 generates the synchronization signal SYNC at the synchronization terminal Y#. When the conversion control circuit is configured as a slave circuit, the synchronization circuit 57 receives the synchronization signal SYNC via the synchronization terminal Y#.

The phase enabling circuit 58 is used to generate a ready signal RDY according to the local reset signal RX, the voltage VstN on the identification terminal ID#, the local synchronization signal SX and the master control signal MS. The pulse width modulation timing circuit 53 is used to generate a pulse width modulation control signal SPWM according to the local synchronization signal SX and the ready signal RDY, and the driver 1N is used to drive the upper bridge switch QH and the lower bridge switch QL according to the pulse width modulation control signal SPWM.

FIG4 shows a waveform diagram of a preferred embodiment of the stackable 4-phase power converter of the present invention as shown in FIG2A. In one embodiment, the synchronization signal SYNC includes a complex pulse to continuously generate a count value NX in the conversion control circuit. In one embodiment, each conversion control circuit enables the corresponding power stage circuit to generate output power when the count value NX is related to the phase sequence number ID_N. For example, in a preferred embodiment, each conversion control circuit enables the corresponding power stage circuit to generate output power to the load 99 when the count value NX is equal to the phase sequence number ID_N.

In this embodiment, the reset signal RST is used to reset and start the count value NX in each multi-phase cycle. This configuration ensures the stable operation of the stackable multi-phase power converter of the present invention.

Please continue to refer to FIG. 4. In a specific embodiment, when the count value NX is related to the phase sequence number ID_N, the ready signal RDY is enabled, and when the ready signal RDY is enabled, the conversion control circuit enables the corresponding power stage circuit to generate output power to the load 99.

In this embodiment, the phase sequence ID_N of the conversion control circuits 15, 25, 35, and 45 are set to 0, 1, 2, and 3, respectively. Please continue to refer to Figure 4, and the operation of the stackable multi-phase power converter 102A will be described in the following embodiment.

Time point t0: The synchronization signal SYNC and the reset signal RST are generated (for example, by the conversion control circuit 15). At this time, the count value NX of each conversion control circuit 15, 25, 35, 45 is set to 0.

Time point t1: Since the count value NX is 0 and equal to the phase sequence number ID_N of the conversion control circuit 15, the falling edge of the synchronization signal SYNC triggers the conversion control circuit 15 to enable the power stage circuit 10, thereby generating output power to the load 99. Specifically, for example, by controlling the upper bridge switch of the power stage circuit 10 to be turned on, the switching node SW0 is electrically connected to the input voltage VIN within a conduction time Ton. At the same time, the falling edge of the synchronization signal SYNC triggers the count value NX to be added to 1. It should be noted that the conduction time Ton is determined by the pulse width modulation timing circuit 53.

Time point t2: The rising edge of the synchronization signal SYNC is used to latch the state of the ready signal RDY. Since the phase sequence number ID_N of the conversion control circuit 25 is set to 1, the ready signal RDY of the conversion control circuit 25 is enabled.

Time point t3: The falling edge of the synchronization signal SYNC triggers the conversion control circuit 25 (the count value NX is 1) to enable the power stage circuit 20, thereby generating output power to the load 99, for example, by controlling the upper bridge switch of the power stage circuit 20 to conduct, so that the switching node SW1 is electrically connected to the input voltage VIN within a conduction time Ton. At the same time, the falling edge of the synchronization signal SYNC triggers the count value NX to be added to 2.

Time point t4: The rising edge of the synchronization signal SYNC is used to latch the state of the ready signal RDY. Since the phase sequence number ID_N of the conversion control circuit 35 is set to 2, the ready signal RDY of the conversion control circuit 35 is enabled.

Time point t5: The falling edge of the synchronization signal SYNC triggers the conversion control circuit 35 (the count value NX is 2) to enable the power stage circuit 30, thereby generating output power to the load 99, for example, by controlling the upper bridge switch of the power stage circuit 30 to conduct, so that the switching node SW2 is electrically connected to the input voltage VIN within a conduction time Ton. At the same time, the falling edge of the synchronization signal SYNC triggers the count value NX to be added to 3.

Time point t6: The rising edge of the synchronization signal SYNC is used to latch the state of the ready signal RDY. Since the phase sequence number ID_N of the conversion control circuit 45 is set to 3, the ready signal RDY of the conversion control circuit 45 is enabled.

Time point t7: The falling edge of the synchronization signal SYNC triggers the conversion control circuit 45 (the count value NX is 3) to enable the power stage circuit 40, thereby generating output power to the load 99, for example, by controlling the upper bridge switch of the power stage circuit 40 to conduct, so that the switching node SW3 is electrically connected to the input voltage VIN within a conduction time Ton. At the same time, the falling edge of the synchronization signal SYNC triggers the count value NX to be added to 4.

When the count value NX is equal to or higher than a maximum value, a reset signal RST is generated. In this embodiment, the maximum value is 4. Therefore, when the count value NX is 4, the rising edge of the synchronization signal SYNC is used to trigger the reset signal RST to reset the counter (for example, at time t0').

In one embodiment, although the synchronization signal SYNC and the reset signal RST are generated simultaneously, the pulse width of the reset signal RST is shorter than the pulse width of the synchronization signal SYNC.

In one embodiment, when the count value NX reaches the start-up phase number IX, a reset signal RST is generated. The start-up phase number IX increases as the load current ISUM consumed by the load 99 increases. For example, in the 4-phase power converter shown in FIG. 4 , when the load current ISUM drops to a certain level, the start-up phase number IX is reduced from 4 (the maximum phase number of the 4-phase power converter) to 3. In this embodiment, the fourth phase stackable sub-converter (i.e., the conversion control circuit 45 and the power stage circuit 40) is phase-cut and stops switching, while the first, second and third phase stackable sub-converters (i.e., the conversion control circuits 15, 25, 35 and the power stage circuits 10, 20, 30) continue to operate and switch to generate output power to the load. As the level of load current ISUM continues to decrease, the number of starting phases IX can be further reduced to 2 or 1.

The total number of phases (maximum number of phases) in the stackable multi-phase power converter using the stackable control circuit according to the present invention can be any positive integer. FIG. 5 shows a switching waveform diagram of a preferred embodiment of an 8-phase power converter using the stackable control circuit according to the present invention. The 8-phase power converter uses 8 control circuits, the configuration of which is similar to FIG. 2A or FIG. 2B and N is equal to 8, to control the corresponding number of power stage circuits, thereby generating output power to the load. It should be noted that the on-time of multi-phase switching can be non-overlapping (such as SW0~SW3 shown in Figure 4) or overlapping (such as the voltage of switching nodes SW0~SW7 shown in Figure 5). Whether the on-time of multi-phase switching overlaps is determined by the feedback control loop of the output power supply and the corresponding control circuit and power stage circuit.

In one embodiment, the stackable multi-phase power converter (e.g., 102A, 102B in FIG. 2A and FIG. 2B, and FIG. 4 or FIG. 5) is a constant on-time (COT) power converter. The multi-phase constant on-time power converter (e.g., 102A) is activated by the triggering of the pulse of the synchronization signal SYNC. Specifically, in one embodiment, each phase of the stackable sub-converter (i.e., a control circuit and a corresponding power stage circuit) corresponds to a constant on-time power converter, and the upper bridge switch corresponding to the power stage circuit is turned on by the triggering of the corresponding pulse, wherein the pulse is related to the phase sequence number ID_N of the synchronization signal SYNC.

FIG6 shows a schematic diagram of a preferred embodiment of the stackable sub-converter (106) and the pulse width modulation timing circuit (53) of the stackable multi-phase power converter of the present invention. The pulse width modulation timing circuit 53 of the conversion control circuit is used to control the power stage circuit 50. In one embodiment, the pulse width modulation timing circuit 53 includes an on-time timing circuit 90, a single pulse generator 91, a latch circuit 92, a gate 93 and a minimum off-time timing circuit 95.

When the pulse width modulation control signal SPWM is triggered (for example, to control the upper bridge switch QH to be turned on and the lower bridge switch QL to be turned off), the on-time timing circuit 90 is used to control the on-time Ton of the signal on the switching node SW (for example, SW0 shown in FIG. 4 ). In one embodiment, the on-time Ton decreases as the input voltage VIN of the stackable multi-phase power converter increases. In one embodiment, the on-time Ton increases as the output current of the load 99 increases, thereby improving the load transient response. The minimum off-time timing circuit 95 is used to provide a minimum off-time to the pulse width modulation control signal SPWM (which can also be a signal on the switching node SW). When the ready signal RDY is enabled, the local synchronization signal SX is turned on by the single pulse generator 91. The local synchronization signal SX is generated according to the falling edge of the pulse corresponding to the synchronization signal SYNC.

FIG7 shows a schematic diagram of a preferred embodiment of the synchronization circuit 57 of the present invention for generating the synchronization signal SYNC. Resistors 141 and 142 are configured as a voltage divider to generate a feedback voltage VFB according to an output power source (e.g., an output voltage VO). The error amplifier 130 (e.g., a transconductance amplifier) is used to generate an amplified signal VA by amplifying the difference between a reference voltage VREF and the feedback voltage VFB. The feedback voltage VFB is added to the ramp signal RAMP to generate a combined ramp signal RMC. The combined ramp signal RMC is coupled to the comparator 150 to be compared with the amplified signal VA to generate a comparison signal CMP. In one embodiment, the ramp signal RAMP is generated according to a current signal (corresponding to a load current ISUM), wherein the current signal (ISUM) is the sum of all phase inductor currents of a stackable multi-phase power converter.

The comparison signal CMP triggers the single pulse generator 155 to generate the synchronous generation signal S_PLS. The buffer 160 is used to buffer the synchronous generation signal S_PLS.

The master-slave decision circuit 56 includes a comparator 180 for generating a master control signal MS when the voltage of the identification terminal ID# is lower than a threshold voltage VT1 (e.g., 0.5 volts). When the conversion control circuit is configured as a master control circuit, the master control signal MS enables the buffer 160 to output the synchronization signal SYNC through the synchronization terminal Y#. The pulse width of the synchronization generation signal S_PLS determines the pulse width of the synchronization signal SYNC.

Under the control of the master control signal MS, the synchronization signal SYNC and the synchronization generation signal S_PLS are selected by the multiplexer 170 (represented by MUX in the figure) to generate the local synchronization signal SX and the clock signal CLK. When the conversion control circuit is configured as a slave circuit, the multiplexer 170 selects the synchronization signal SYNC passing through the synchronization terminal Y# to generate the local synchronization signal SX and the clock signal CLK. The clock signal CLK is related to the rising edge of the synchronization signal SYNC. From a point of view, the clock signal CLK and the synchronization signal SYNC have the same characteristics. In one embodiment, when the conversion control circuit is configured as a master control circuit, the synchronous generation signal S_PLS is used to generate the synchronization signal SYNC on the synchronization terminal Y#, and the multiplexer 170 selects the synchronous generation signal S_PLS to generate the local synchronization signal SX and the clock signal CLK.

FIG8 shows a schematic diagram of a preferred embodiment of the phase enabling circuit 58 of the present invention for generating a ready signal RDY. In one embodiment, a constant current source 210 outputs a constant current (e.g., 50 microamperes) to an identification terminal ID#. The constant current flows through a resistor (e.g., 10k~80k ohms) connected to the identification terminal ID# to generate a voltage VstN (e.g., 0.5~4 volts), thereby setting the phase sequence number ID_N. An analog-to-digital converter 220 (represented by A/D in the figure) is electrically connected to the identification terminal ID# to convert the voltage VstN to generate a phase sequence number ID_N (e.g., 0~7, corresponding to SW0~SW7 in the embodiment of FIG5 ). The counter 230 generates a count value NX according to, for example, the triggering of the rising edge of the local synchronization signal SX. The counter 230 is reset under the control of the local reset signal RX. The local reset signal RX is generated according to the reset signal RST. In one embodiment, the inverter 235 is further used to generate an inverted local reset signal RSTn to reset the inverter 230. The digital comparator 250 (e.g., an XNOR gate) is used to compare the count value NX with the phase sequence number ID_N to determine whether the count value NX reaches the phase sequence number ID_N. According to the comparison result of the digital comparator 250, the flip-flop 260 is used to generate a ready signal RDY when the count value NX reaches the phase sequence number ID_N. The flip-flop 260 is triggered and latched by the clock signal CLK. In one embodiment, the clock signal CLK is delayed by the delay unit 240 to trigger the flip-flop 260. From one point of view, the ready signal RDY enables the corresponding power stage circuit to generate output power.

FIG9 shows a schematic diagram of a preferred embodiment of the reset circuit 59 for generating the reset signal RST of the present invention. The analog-to-digital converter (A/D) 320 is used to convert the load current ISUM into the start phase number IX. The digital comparator 330 (e.g., XNOR gate) is used to compare the count value NX with the start phase number IX to determine whether the count value NX reaches the start phase number IX. In this embodiment, the output end of the digital comparator 330 is electrically connected to the flip-flop 335 to generate the reset signal RST when the count value NX reaches the start phase number IX.

Please continue to refer to FIG. 9. When the count value NX reaches the maximum phase number (i.e., N_max), the comparison circuit 310 further sets the flip-flop 335 to generate a reset signal RST. For example, in a 4-phase power converter, the maximum phase number is 4, and the start-up phase number IX can be 4, 3, 2, or 1. In an 8-phase power converter, the maximum phase number is 8, and the start-up phase number IX can be any integer from 1 to 8.

The output of the flip-flop 335 is synchronized with the clock signal CLK and is used to trigger the single pulse generator 350 to generate the master reset signal R_PLS. The master signal MS is used to enable the buffer 360 to output the reset signal RST according to the master reset signal R_PLS. Under the control of the master signal MS, the reset signal RST and the master reset signal R_PLS are selected by the multiplexer 370 (represented by MUX in the figure) to generate the local reset signal RX. When the conversion control circuit is configured as a slave circuit, the multiplexer 370 selects the reset signal RST passing through the reset terminal R# to generate the local reset signal RX. On the other hand, when the conversion control circuit is configured as a master circuit, the multiplexer 370 selects the master reset signal R_PLS to generate the local reset signal RX.

FIG10 shows another preferred embodiment of the stackable multi-phase power converter of the present invention. The stackable multi-phase power converter 110 of FIG10 is similar to the stackable multi-phase power converter 102B of FIG2B, except that the conversion control circuit (e.g., 55, 65, 75, 85) of the stackable multi-phase power converter 110 does not include a dedicated reset terminal. In this embodiment, the local reset signal RX is selectively generated according to the synchronization signal SYNC. The local reset signal RX is used to reset the count value NX in each multi-phase cycle to achieve the same operation as the reset signal RST and the corresponding local reset signal RX of the aforementioned embodiments (e.g., FIG3, FIG8).

FIG11 shows a phase switching waveform diagram of a preferred embodiment 4 of the conversion control circuit of the present invention as shown in FIG10. In this embodiment, the synchronization signal SYNC includes a plurality of pulses to continuously generate a count value NX in each conversion control circuit. When the count value NX is related to the phase sequence number ID_N (i.e., the ready signal RDY is enabled), the conversion control circuit enables the corresponding stackable power stage circuit to generate output power to the load 99. In this embodiment, the local reset signal RX (also a reset signal in this embodiment) is used to reset the count value NX. As shown in FIG11, in this embodiment, a pulse with a higher voltage level (e.g., VH) in the synchronization signal SYNC is used to indicate a reset signal. The other pulses of the synchronization signal SYNC may be pulses with a lower voltage level (e.g., VL). From one point of view, the reset signal in the present embodiment is modulated or mixed in the complex pulses of the synchronization signal SYNC. When the voltage level of the synchronization signal SYNC is higher than a threshold value VTH, a local reset signal RX is generated.

FIG12 shows a schematic diagram of a preferred embodiment of the present invention corresponding to FIG10 and FIG11 for generating a synchronization signal SYNC of a mixed reset signal of the synchronization circuit 57'. The operation of the synchronization circuit 57' is similar to the synchronization circuit 57 shown in FIG7. In this embodiment, the synchronization circuit 57' further includes a pulse mixer 560 for adding the synchronization generation signal S_PLS and the master reset generation signal R_PLS to generate the synchronization signal SYNC, so that the reset signal in this embodiment is modulated or mixed in the complex pulse of the synchronization signal SYNC.

FIG13 shows a schematic diagram of a preferred embodiment of the reset circuit 59' for generating a local reset signal RX corresponding to FIG10, FIG11 and FIG12 of the present invention. The operation of the reset circuit 59' is similar to the reset circuit 59 shown in FIG9. In this embodiment, the reset circuit 59' further includes a comparator 680 for receiving a synchronization signal SYNC to generate a local reset signal RX when the conversion control circuit is configured as a slave circuit. When the voltage level of the synchronization signal SYNC is higher than a threshold value VTH, the local reset signal RX is generated.

FIG14 shows a schematic diagram of a preferred embodiment of the pulse mixer 560 of the synchronous circuit 57' of the present invention corresponding to FIG10, FIG11 and FIG12.

In one embodiment, when the conversion control circuit is configured as a master control circuit, the master control signal MS enables buffers 710 and 720, and transistor 750 is turned on to provide a resistive load, thereby biasing the multiplexer configured by diodes 715 and 725, wherein the on-resistance of transistor 750 can be configured to be relatively high to maintain the high accuracy of the voltage level of the complex pulse of the synchronization signal SYNC. The buffer 710 receives the master reset generation signal R_PLS to generate a pulse with a higher voltage level of the synchronization signal SYNC, and the buffer 720 receives the synchronization generation signal S_PLS to generate a pulse with a lower voltage level of the synchronization signal SYNC. Diodes 715 and 725 are configured as multiplexers to automatically select the buffer output with a higher voltage in buffers 710 and 720 to generate a synchronization signal SYNC. In one embodiment, the power supply (VH) of buffer 710 is higher than the power supply (VL) of buffer 720.

On the other hand, when the conversion control circuit is configured as a slave circuit, the master control signal MS disables buffers 710 and 720, and transistor 750 is turned off, so that the end of the pulse mixer 560 used to generate the synchronization signal SYNC is in a high impedance state.

FIG. 15 shows a block diagram of a preferred embodiment of the stackable multi-phase power converter (1015) of the present invention. The stackable multi-phase power converter 1015 is similar to the embodiments of FIG. 10 and FIG. 2A.

As shown in FIG. 15 , the stackable multi-phase power converter 1015 includes stackable sub-converters 1510, 1520, 1530, and 1540. In this embodiment, each sub-converter further includes a current sharing terminal IS# for transmitting or receiving a current sharing signal IBUS.

In one embodiment, all current sharing terminals IS# (i.e., IS# of stackable sub-converters 1510, 1520, 1530, and 1540) are electrically connected to each other, or in another viewpoint, are coupled in parallel. In one embodiment, the master stackable sub-converter (e.g., stackable sub-converter 1510) is used to generate and transmit a current sharing signal IBUS via the corresponding current sharing terminal IS#. On the other hand, the slave stackable sub-converters (e.g., stackable sub-converters 1520, 1530, and 1540) are used to receive the current sharing signal IBUS via their respective corresponding current sharing terminals IS#.

The master stackable sub-converter and the slave stackable sub-converter are electrically connected to the output voltage VO to adjust the output voltage VO through a respective feedback loop of each stackable sub-converter, wherein the respective feedback loop includes a reference voltage VREF and an error amplifier. The reference voltage VREF and the error amplifier are used to adjust the output voltage VO.

In this embodiment, the master stackable sub-converter outputs a current sharing signal IBUS according to the level of its output current (Io0). Each slave stackable sub-converter inputs and compares the current sharing signal IBUS with its output current (i.e., Io2, Io3, or Io4) to adjust the reference voltage VREF of the voltage feedback loop of the corresponding slave stackable sub-converter, thereby achieving current sharing.

In one embodiment, the conversion control circuit is configured as an integrated circuit, the synchronization terminal Y# corresponds to a synchronization pin of the integrated circuit, and the current sharing terminal IS# corresponds to a current sharing pin of the integrated circuit.

Please refer to FIG. 9, FIG. 11 and FIG. 15 at the same time. In this embodiment, when the count value NX reaches the start-up phase number IX, the master reset generation signal R_PLS is generated. The start-up phase number IX increases with the increase of the load current ISUM of the load 99. When the current balance is achieved, since the current balancing signal IBUS is proportional to the load current ISUM, the stackable sub-converter can determine the start-up phase number IX according to the level of the current balancing signal IBUS.

FIG. 16 shows a phase switching waveform diagram of a preferred embodiment 4 of the present invention corresponding to FIG. 15 . The stackable sub-converters 1510, 1520, 1530 and 1540 have different PWM pulse widths, namely, Ton1, Ton2, Ton3 and Ton4. The pulse widths of the PWM signals of the stackable sub-converters 1510, 1520, 1530 and 1540 (corresponding to the signals on the switching nodes SW0, SW1, SW2 and SW3 shown in FIG. 16 ) can be adjusted independently. In this embodiment, under heavy load and medium load conditions (i.e., during non-discontinuous conduction mode operation), the PWM signal of each stackable sub-converter can be a fixed switching frequency.

FIG17 shows a schematic diagram of a preferred embodiment of a stackable sub-converter (1710) of the stackable multi-phase power converter of the present invention. The stackable sub-converter 1710 can be a multi-stage buck converter, such as a 3-stage buck converter. The stackable sub-converter 1710 includes a conversion control circuit 100, which is coupled to a synchronization signal SYNC, a current sharing signal IBUS, and an identification signal SID via a synchronization terminal Y#, a current sharing terminal IS#, and an identification terminal ID#, respectively. The conversion control circuit 100 is further used to receive the input voltage VIN, the output voltage VO, the current sensing signals CS+ and CS-, the flying capacitor voltages VCP and VCN to generate the driving signals G1, G2, G3, and G4. The driving signals G1, G2, G3, and G4 drive the transistors 517, 617, 717, and 817 respectively to switch the flying capacitor CFLY and the inductor 94, thereby converting the input voltage VIN to generate the output voltage VO. When switching steady state, the voltage VCFLY on the flying capacitor is charged and balanced at the level of VIN/2.

During the first phase (PWM1), the drive signals G1 and G3 are used to turn on the transistors 517 and 717, and the voltage "VIN-VCFY-VO" is applied to the inductor 94 to generate the output current IoN and the output voltage VO. During the second phase (PWM2), the drive signals G2 and G4 are used to turn on the transistors 617 and 817, and the voltage "VCFY-VO" is applied to the inductor 94 to generate the output current IoN and the output voltage VO. Since the voltage of the flying capacitor CFLY reduces the voltage applied to the inductor 94, the ripple current is significantly reduced and the efficiency of the buck converter is improved. For the three-level buck converter, the operation details are as follows: "Three Level Buck Converter with Control and Soft Startup" (ECCE). In one embodiment, resistors 71, 72 and capacitor 77 are electrically connected to inductor 94 to sense the output current according to the DC resistance (DCR) of inductor 94. The current sensing signals CS+ and CS- (differential voltage) are related to the level of the output current IoN. It should be noted that the output current IoN corresponds to the output current Io1, Io2, Io3 or Io4 of the aforementioned stackable sub-converter, and the switching node SW corresponds to the switching node SW0, SW1, SW2 or SW4 of the aforementioned stackable sub-converter.

Referring to FIG. 16 and FIG. 17 , in the three-stage buck converter shown in FIG. 17 , the switching node voltage (e.g., SW0) can be switched between V1 and V2. In one embodiment, V1 and V2 can be VIN and VIN/2, respectively, or can be VIN/2 and ground, respectively.

FIG18 is a schematic diagram of a preferred embodiment of the current flow sensing circuit 185 of the conversion control circuit 100 of the present invention. The current flow sensing circuit 185 is used to generate the output current signal ICS and the current equalizing signal IBUS of the present invention. The operational amplifier 141 and the resistors 108, 111, 103, and 104 are configured as a differential amplifier. The current flow sensing signals CS+ and CS- are coupled to the differential amplifier to generate the switching current signal ISW. In one embodiment, the switching current signal ISW is used for current mode control of the power converter. It should be noted that the current flow sensing signals CS+ and CS- are proportional to the switching current (e.g., IoN) of the corresponding stackable sub-converter. The operational amplifier 113 and the resistors 105 and 112 are configured as an amplifier circuit to receive the switching current signal ISW and generate the output current signal ICS through a low-pass filter, wherein the low-pass filter is configured by the resistor 107 and the capacitor 109. When the conversion control circuit 100 of the stackable sub-converter operates as a master control circuit, the master control signal MS controls the switch 145 to conduct, so as to conduct the output current signal ICS to the current equalizing terminal IS# as the current equalizing signal IBUS. In other words, the current equalizing signal IBUS is related to the switching current of the master stackable sub-converter.

FIG. 19 shows a schematic diagram of a preferred embodiment of the reference adjustment circuit 195 of the conversion control circuit 100 of the present invention. The reference adjustment circuit 195 is used to generate the adjustable reference voltage VREF of the present invention for current balancing. The reference voltage VR, the unit gain buffer 125, the resistor R3 and the current I117 are used to generate the adjustable reference voltage VREF. The adjustable reference voltage VREF can be expressed by the following formula 1: VREF=VR+I117 x R3 (Formula 1)

In the present embodiment, the reference voltage VR is a fixed voltage. The current I117 is the source-drain current of the transistor 117, which is generated by the mirror image of the current I116 of the transistor 116. The current I116 is generated according to the current I115 of the transistor 115. The current I115 is related to the current equalizing signal IBUS, the output current signal ICS and the offset current IOS. Specifically, in the present embodiment, the current I115 is related to the voltage difference between the current equalizing signal IBUS and the output current signal ICS, and is generated by the subtraction circuit configured by the amplifiers 114 and 121, the transistor 115, and the resistors R1 and R2. The current I115 can be expressed by the following formula 2: I115=[(VIBUS-VICS)-(IOS x R2)]/(R1+R2) (Formula 2)

In Formula 2, VIBUS is the voltage level of the current sharing signal IBUS, and VICS is the voltage level of the output current signal ICS. It should be noted that if (IOS x R2) is higher than (VIBUS-VICS), the current I115 will be equal to 0. Therefore, the offset current IOS provides a minimum current level so that the slave circuit also participates in the current sharing. Capacitor 131 provides loop compensation for the current sharing loop. Switch 135, fixed current source 136 and inverter 137 are used to configure a preset circuit to provide an initial reference voltage VREF for the slave circuit (when MS=0). In one embodiment, before the current sharing is adjusted, the initial reference voltage VREF of the slave circuit is lower than the reference voltage VREF of the master circuit. Before current sharing adjustment, the initial reference voltage VREF of the slave circuit can be expressed by the following formula 3: VREF=VR-I136 x R3 (that is, when MS=0 and I117=0) (Formula 3)

Therefore, during the current sharing operation, the reference voltage VREF of the master circuit is equal to the reference voltage VR. During the current sharing operation, the reference voltage VREF of the slave circuit can be expressed by the following formula 4: VREF=VR+(I117-I136)x R3 (Formula 4)

FIG. 20 shows a schematic diagram of a preferred embodiment of a multi-stage switching control circuit 205 for generating drive signals G1, G2, G3, and G4 in the conversion control circuit 100 of the present invention. The stackable sub-converter is triggered by the pulse of the local synchronization signal SX. In other words, each stackable sub-converter is triggered by the pulse corresponding to the synchronization signal SYNC. The local synchronization signal SX is related to the synchronization signal SYNC. The pulse width modulation circuit (PWM circuit) 154 controls the on-time of the pulse width modulation signals PWM1 and PWM2 according to the output voltage VO, the reference voltage VREF, the switching current signal ISW, the input voltage VIN, and the flying capacitor voltages VCP and VCN. The on time of the pulse width modulation signals PWM1 and PWM2 increases with the increase of the output current of the output voltage VO, and the signal generating circuit 161 generates the driving signals G1, G2, G3, and G4 according to the pulse width modulation signals PWM1 and PWM2. When the ready signal RDY is enabled, the local synchronization signal SX will turn on the pulse width modulation signal PWM1 (i.e., the first phase period of the multi-stage converter) through the single pulse generator 151. After the phase of the local synchronization signal SX is shifted by 180 degrees, the staggered local synchronization signal SY will turn on the pulse width modulation signal PWM2 (i.e., the second phase period of the multi-stage converter). The local synchronization signal SX is generated according to the falling edge of the synchronization signal SYNC. It should be noted that the generation of the ready signal RDY can refer to the embodiment of FIG8 .

FIG. 21A shows a schematic diagram of a preferred embodiment of a modulation circuit 215 for generating pulse width modulation signals PWM1 and PWM2 in the conversion control circuit 100 of the present invention. The adder 177 is used to generate the difference between VIN/2 (half of the input voltage VIN) and the cross-voltage (VCP-VCN) of the flying capacitor, and generates the adjustment signal Vadj through the flying capacitor balancing circuit 179. The adder 178 and the output voltage adjustment circuit 176 are configured as an error amplifier to generate the error amplified signal Verr according to the attenuated output voltage VO/k and the reference voltage VREF. The error amplified signal Verr and the adjustment signal Vadj are generated through the adder 173 to generate the error signal VCOM1. The adder 174 generates an error signal VCOM2 according to the difference between the error amplified signal Verr and the adjustment signal Vadj. The comparator 171 is used to compare the error signal VCOM1 with the ramp signal RAMP1 to generate a pulse width modulation signal PWM1. The comparator 172 is used to compare the error signal VCOM2 with the ramp signal RAMP2 to generate a pulse width modulation signal PWM2. The switching current signal ISW and the ramp signal SLOPE1 are used to form the ramp signal RAMP1. The switching current signal ISW and the ramp signal SLOPE2 are used to form the ramp signal RAMP2. The power stage circuit 80 of the stackable sub-converter generates an output voltage VO according to the pulse width modulation signals PWM1 and PWM2, wherein VO=k*VREF. The power stage circuit 80 includes, for example, the signal generating circuit 161 shown in FIG. 20 and the power stage 85 shown in FIG. 17.

In addition, the cross-voltage VCFLY of the Flying Chi capacitor CFLY is balanced at VIN/2 (half of the input voltage VIN) through the loop adjustment of the pulse width modulation signals PWM1 and PWM2.

FIG21B shows a schematic diagram of a preferred embodiment of a modulation circuit 215 for generating pulse width modulation signals PWM1 and PWM2 in the conversion control circuit 100 of the present invention. FIG21B further shows another possible adjustment method for current balancing. In addition to achieving current balancing by adjusting the reference voltage VREF of the slave circuit, it is also possible to adjust the offset value of the feedback circuit (for example, injecting the offset current into the 1/k voltage divider), or adjust the input offset value of the error amplifier of the slave circuit to achieve current balancing.

FIG. 22 shows a schematic diagram of a preferred embodiment of a synchronization generation circuit 225 for generating a synchronization generation signal S_PLS in the conversion control circuit 100 of the present invention. The synchronization generation signal S_PLS is used to generate a synchronization signal SYNC when the stackable sub-converter operates as a master control circuit. The interleaving time register 311 is used to store the value indicated by the interleaving period TX (as shown in FIG. 16 ). When the synchronization generation signal S_PLS is generated by the pulse generator 331, the synchronization generation signal S_PLS will clear the interleaving timer 322 through the inverter 317 and the gate 319. After the pulse period TPW (as shown in FIG. 16 ) of the synchronous generation signal S_PLS, the staggered timer 322 starts timing according to the oscillation signal CK. When the value of the staggered time is equal to the value stored in the staggered time register 311, the comparator 315 triggers the pulse generator 331 to generate the next synchronous generation signal S_PLS. The flip-flop 325 is used to generate the signal ENB to the gate 319, thereby limiting the maximum switching frequency of the master circuit and the slave circuit to the frequency of the signal FSW. The signal FSW is used to set the flip-flop 325, and the local reset signal RX is used to clear the flip-flop 325. It should be noted that the value stored in the interleaving time register 311 is programmable and adjustable.

FIG. 23 shows a schematic diagram of a preferred embodiment of a reset generating circuit 236 for generating a master reset generating signal R_PLS in the conversion control circuit 100 of the present invention. The logic controller 415 is used to detect the level of the current averaging signal IBUS (via the analog-to-digital converter 410) and determine the start phase number IX, which is stored in the phase number register 420. The output of the comparator 435 is electrically connected to the pulse generator 450 through the AND gate 438, thereby generating the master reset generating signal R_PLS when the count value NX reaches the start phase number IX.

FIG. 24 shows a schematic diagram of a preferred embodiment of a local generating circuit 245 for generating a local synchronization signal SX, a local reset signal RX and a master control signal MS in the conversion control circuit 100 of the present invention. A comparator 510 is coupled to the identification terminal ID# to generate the master control signal MS when the voltage level of the identification signal SID is lower than the threshold voltage VT1. Another comparator 610 is used to detect the synchronization signal SYNC to generate the slave reset generation signal R_PLSL when the voltage level of the synchronization signal SYNC is higher than the threshold VTH.

The synchronization signal SYNC and the synchronization generation signal S_PLS are electrically connected to the multiplexer 520 to generate the local synchronization signal SX and the clock signal CLK according to the control of the master control signal MS. When the conversion control circuit is configured as a slave circuit, the multiplexer 520 receives the synchronization signal SYNC to generate the local synchronization signal SX and the clock signal CLK. The clock signal CLK is related to the rising edge of the synchronization signal SYNC. The local synchronization signal SX is related to the falling edge of the synchronization signal SYNC.

The master reset generation signal R_PLS and the slave reset generation signal R_PLSL are electrically connected to the multiplexer 620 to generate the local reset signal RX according to the control of the master signal MS. When the conversion control circuit is configured as a slave circuit, the multiplexer 620 receives the slave reset generation signal R_PLSL to generate the local reset signal RX.

The present invention has been described above with reference to the preferred embodiments. However, the above description is only for the purpose of making it easier for those familiar with the present technology to understand the content of the present invention, and is not intended to limit the scope of the present invention. The various embodiments described are not limited to individual applications, but can also be used in combination. For example, two or more embodiments can be used in combination, and a part of the configuration in one embodiment can also be used to replace the corresponding configuration in another embodiment. In addition, under the same spirit of the present invention, those familiar with the present technology can think of various equivalent changes and various combinations. For example, the present invention refers to "processing or calculating or generating an output result according to a certain signal", which is not limited to the signal itself, but also includes, when necessary, converting the signal into voltage-current, current-voltage, and/or ratio, and then processing or calculating the converted signal to generate an output result. It can be seen that under the same spirit of the present invention, those familiar with the present technology can think of various equivalent changes and various combinations, and there are many combinations, which are not listed here one by one. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

10, 20, 30, 40: Power stage circuit 102A: Stackable multi-phase power converter 15, 25, 35, 45: Conversion control circuit 16, 26, 36, 46: Driver 17, 27, 37, 47: Resistor 99: Load ID#: Identification terminal ID_N: Phase sequence number L1, L2, L3, LN: Inductor MST: Master circuit N: Integer R#: Reset terminal RST: Reset signal S1, S2, SN: Slave circuit SW0, SW1, SW2, SWN: Switching node SYNC: Synchronization signal VO: Output voltage Vst1, Vst2, Vst3, Vst4: Voltage on the identification terminal Y#: Synchronization terminal

Claims (27)

A conversion control circuit for controlling a stackable multi-phase power converter, wherein the stackable multi-phase power converter includes a plurality of stackable sub-converters, wherein each of the plurality of stackable sub-converters includes a power stage circuit and a corresponding conversion control circuit, wherein the plurality of power stage circuits corresponding to the plurality of stackable sub-converters are coupled in parallel to each other to generate an output power to a load, wherein the conversion control circuit is used to control at least one switch of the power stage circuit to switch a corresponding inductor, thereby generating the output power, and the conversion control circuit includes: a current balancing terminal, wherein a current balancing signal is coupled to the plurality of current balancing terminals of the plurality of conversion control circuits connected in parallel to each other; and A current balancing circuit is used to generate or receive the current balancing signal at the current balancing end, wherein the current balancing signal is generated according to an output current of the output power source; wherein the conversion control circuit is used to adjust the power stage circuit according to the current balancing signal to perform current balancing between the plurality of stackable sub-converters. A conversion control circuit as described in claim 1, wherein the conversion control circuit is configured as a master circuit or a slave circuit; wherein the master circuit is used to generate the current equalization signal, and the slave circuit is used to receive the current equalization signal. A conversion control circuit as described in claim 1, wherein the stackable sub-converter is a multi-stage buck converter. A conversion control circuit as described in claim 3, wherein the stackable sub-converter is a three-stage buck converter. The conversion control circuit as described in claim 2 further includes a reference voltage for adjusting an output voltage of the output power source; wherein the reference voltage corresponding to the slave circuit is adjusted according to the current sharing signal to perform current sharing. A conversion control circuit as described in claim 5, wherein before the reference voltage of the slave circuit is adjusted for current sharing, the reference voltage corresponding to the slave circuit is lower than the reference voltage corresponding to the master control circuit. The conversion control circuit as described in claim 2 further includes a feedback voltage divider, a reference voltage, an error amplifier, a ramp signal and a modulation comparator, which are configured as a feedback loop to adjust an output voltage of the output power supply; wherein an offset value of the feedback voltage divider or an input offset value of the error amplifier is adjusted according to the current balancing signal to perform current balancing. A conversion control circuit as described in claim 2, wherein the conversion control circuit further comprises: a synchronization terminal, wherein a synchronization signal is coupled to a plurality of synchronization terminals of a plurality of the conversion control circuits connected in parallel; wherein the synchronization signal comprises a plurality of pulses, the plurality of pulses are continuously counted into a count value, wherein the synchronization signal comprises a reset signal for resetting and starting the count value; wherein when the count value is related to a phase sequence number of the conversion control circuit, the conversion control circuit enables the power stage circuit to generate the output power; wherein the master control circuit is used to generate the synchronization signal via the synchronization terminal, and the slave circuit is used to receive the synchronization signal via the synchronization terminal. A conversion control circuit as described in claim 2, wherein the conversion control circuit further includes an inductive flow detection circuit for generating an inductive flow detection signal based on the corresponding portion of the output current generated by the stackable sub-converter; wherein the current sharing signal is equal to the inductive flow detection signal of the main control circuit. The conversion control circuit as described in claim 8 further includes an identification terminal for setting the phase sequence number, wherein the phase sequence number is determined based on an electrical parameter level on the identification terminal. The conversion control circuit as described in claim 10 further determines whether the conversion control circuit operates as the master circuit or the slave circuit based on the phase sequence number. A conversion control circuit as described in claim 10, wherein the conversion control circuit further includes a certain current source coupled to a resistor via the identification end, wherein the phase sequence number is determined according to a voltage level of the identification end. A conversion control circuit as described in claim 8, wherein a pulse of the synchronization signal having a higher voltage level is used to indicate the reset signal. A switching control circuit as described in claim 8, wherein the reset signal is generated when the count value reaches an activation phase number, wherein the activation phase number increases as a load current consumed by the load increases. A conversion control circuit as described in claim 8, wherein the stackable sub-converter is activated by triggering a corresponding pulse of the synchronization signal. A conversion control circuit as described in claim 4, wherein the conversion control circuit of the three-stage buck converter generates a pulse width modulation (PWM) signal to control the power stage circuit to generate the output power, wherein the conversion control circuit adjusts the pulse width of the PWM signal to balance the voltage of a Flying Chi capacitor of the three-stage buck converter at half of an input voltage of the stackable multi-phase power converter. A conversion control circuit as described in claim 1, wherein the stackable sub-converter operates in a current mode control. A conversion control circuit as described in claim 8, wherein in a heavy load state, the stackable multi-phase power converter operates in a constant frequency switching mode. A conversion control circuit as described in claim 8, wherein the conversion control circuit is configured as an integrated circuit, the synchronization end corresponds to a synchronization pin of the integrated circuit, and the current sharing end corresponds to a current sharing pin of the integrated circuit. A control method for controlling a stackable multiphase power converter, wherein the stackable multiphase power converter includes a plurality of stackable sub-converters, wherein each of the plurality of stackable sub-converters includes a power stage circuit, wherein the plurality of power stage circuits corresponding to the plurality of stackable sub-converters are coupled in parallel to each other to generate an output power to a load, wherein the power stage circuit includes at least one switch to switch an inductor to generate the output power, wherein one of the plurality of stackable sub-converters is configured as a master stackable sub-converter, and another one of the plurality of stackable sub-converters is configured as a slave stackable sub-converter, the control method comprising: Controlling the inductor corresponding to the at least one switch of the power stage circuit; Controlling the master stackable sub-converter to generate a current sharing signal according to an output current of the output power source; Controlling the slave stackable sub-converter to receive the current sharing signal; and Each of the plurality of stackable sub-converters adjusts the corresponding power stage circuit according to the current sharing signal to perform current sharing among the plurality of stackable sub-converters. The control method as described in claim 20 further includes: generating a reference voltage for adjusting an output voltage of the output power source; and adjusting the reference voltage of the slave stackable sub-converter according to the current sharing signal to perform current sharing. A control method as described in claim 21, wherein before the reference voltage of the slave stackable sub-converter is adjusted for current sharing, the reference voltage of the slave stackable sub-converter is lower than the reference voltage of the master stackable sub-converter. The control method as described in claim 20, wherein the conversion control circuit further includes a feedback voltage divider, a reference voltage, an error amplifier, a ramp signal and a modulation comparator, configured as a feedback loop to adjust an output voltage of the output power supply; the control method further includes: Compensating an input offset value of the feedback voltage divider or the error amplifier of the slave stackable sub-converter according to the current sharing signal to perform current sharing. The control method as described in claim 20 further includes: Controlling the master stackable sub-converter to generate a synchronization signal; Controlling the slave stackable sub-converter to receive the synchronization signal; wherein the synchronization signal includes a complex pulse wave, and the complex pulse wave is continuously counted into a count value, wherein the synchronization signal includes a reset signal for resetting and starting the count value; and When the count value is related to a corresponding phase sequence number, enabling a corresponding power stage circuit to generate the output power. The control method as described in claim 20 further comprises: Generating an inductive flow detection signal according to the corresponding portion of the output current generated by the stackable sub-converter; wherein the current sharing signal is equal to the inductive flow detection signal of the master stackable sub-converter. A control method as described in claim 24, wherein the stackable sub-converter is activated by triggering a corresponding pulse of the synchronization signal. A control method as described in claim 24, wherein in a heavy load state, the stackable multi-phase power converter operates in a constant frequency switching mode.

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