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TWI848771B - Transistor structure - Google Patents

Transistor structure Download PDF

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TWI848771B
TWI848771B TW112126592A TW112126592A TWI848771B TW I848771 B TWI848771 B TW I848771B TW 112126592 A TW112126592 A TW 112126592A TW 112126592 A TW112126592 A TW 112126592A TW I848771 B TWI848771 B TW I848771B
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transistor structure
extension portion
active region
gate
extension
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TW112126592A
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Chinese (zh)
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TW202505768A (en
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林孟漢
吉田宏
林天祿
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力晶積成電子製造股份有限公司
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A transistor structure including a substrate, a gate, a first doped region, a second doped region, and a gate dielectric layer is provided. The substrate includes an active region. The active region has a first side and a second side opposite to each other. The gate is located on the substrate of the active region. The gate electrode includes a main portion, a first extension portion, and a second extension portion. The first extension portion and the second extension portion are connected to the main portion. The first extension portion is located on the first side and overlaps the active region. The second extension portion is located on the second side and overlaps the active region. The first doped region and the second doped region are located in the active region and located in the substrate on two sides of the gate. The gate dielectric layer is located between the gate and the substrate.

Description

電晶體結構Transistor structure

本發明是有關於一種半導體結構，且特別是有關於一種電晶體結構。The present invention relates to a semiconductor structure, and in particular to a transistor structure.

在積體電路中，電晶體元件是主要元件之一。電晶體元件包含閘極以及位在閘極兩側的基底中的源極區與汲極區。然而，在一些電晶體元件中，相較於主動區中的閘極的中央區域，電晶體元件在主動區中的閘極的邊緣區域具有較低的通道電阻，因此容易產生電流雙峰(current double hump)效應，而對電晶體元件的電性造成不良影響。In integrated circuits, transistors are one of the main components. A transistor includes a gate and a source region and a drain region in the substrate on both sides of the gate. However, in some transistors, the edge region of the gate in the active region has a lower channel resistance than the central region of the gate in the active region, which easily generates a current double hump effect, which adversely affects the electrical properties of the transistor.

本發明提供一種電晶體結構，其可有效地降低電流雙峰效應，進而避免電流雙峰效應對電晶體結構的電性造成不良影響。The present invention provides a transistor structure, which can effectively reduce the current double peak effect, thereby avoiding the adverse effect of the current double peak effect on the electrical properties of the transistor structure.

本發明提出一種電晶體結構，包括基底、閘極、第一摻雜區、第二摻雜區與閘介電層。基底包括主動區。主動區具有彼此相對的第一側與第二側。閘極位在主動區的基底上。閘極包括主體部、第一延伸部與第二延伸部。第一延伸部與第二延伸部連接於主體部。第一延伸部位在第一側且重疊於主動區。第二延伸部位在第二側且重疊於主動區。第一摻雜區與第二摻雜區位在主動區中且位在閘極的兩側的基底中。閘介電層位在閘極與基底之間。The present invention proposes a transistor structure, including a substrate, a gate, a first doped region, a second doped region and a gate dielectric layer. The substrate includes an active region. The active region has a first side and a second side opposite to each other. The gate is located on the substrate of the active region. The gate includes a main body, a first extension and a second extension. The first extension and the second extension are connected to the main body. The first extension is on the first side and overlaps the active region. The second extension is on the second side and overlaps the active region. The first doped region and the second doped region are located in the active region and in the substrate on both sides of the gate. The gate dielectric layer is located between the gate and the substrate.

依照本發明的一實施例所述，在上述電晶體結構中，第一延伸部與第二延伸部可位在主體部的相對兩側。According to an embodiment of the present invention, in the transistor structure, the first extension portion and the second extension portion may be located at opposite sides of the main body.

依照本發明的一實施例所述，在上述電晶體結構中，第一延伸部與第二延伸部可位在主體部的同一側。According to an embodiment of the present invention, in the transistor structure, the first extension portion and the second extension portion may be located on the same side of the main body.

依照本發明的一實施例所述，在上述電晶體結構中，在第一側可只有一個第一延伸部，且在第二側可只有一個第二延伸部。According to an embodiment of the present invention, in the above transistor structure, there may be only one first extension portion on the first side, and there may be only one second extension portion on the second side.

依照本發明的一實施例所述，在上述電晶體結構中，第一延伸部可包括第一開口，且第一開口可重疊於主動區。第二延伸部可包括第二開口，且第二開口可重疊於主動區。According to an embodiment of the present invention, in the transistor structure, the first extension portion may include a first opening, and the first opening may overlap the active region. The second extension portion may include a second opening, and the second opening may overlap the active region.

依照本發明的一實施例所述，在上述電晶體結構中，第一開口可延伸至主體部中。第二開口可延伸至主體部中。According to an embodiment of the present invention, in the transistor structure, the first opening may extend into the main body, and the second opening may extend into the main body.

依照本發明的一實施例所述，在上述電晶體結構中，主體部可在第一方向上延伸且跨越主動區。第一摻雜區與第二摻雜區可在第二方向上排列。第二方向可相交於第一方向。According to an embodiment of the present invention, in the transistor structure, the main body may extend in a first direction and cross the active region. The first doped region and the second doped region may be arranged in a second direction. The second direction may intersect with the first direction.

依照本發明的一實施例所述，在上述電晶體結構中，第一側與第二側可在第一方向上排列。According to an embodiment of the present invention, in the transistor structure, the first side and the second side may be arranged in a first direction.

依照本發明的一實施例所述，在上述電晶體結構中，更可包括隔離結構。隔離結構位在基底中。隔離結構可在基底中定義出主動區。閘極更可位在隔離結構上。According to an embodiment of the present invention, the transistor structure may further include an isolation structure. The isolation structure is located in the substrate. The isolation structure may define an active region in the substrate. The gate may be located on the isolation structure.

依照本發明的一實施例所述，在上述電晶體結構中，第一延伸部更可重疊於隔離結構。第二延伸部更可重疊於隔離結構。According to an embodiment of the present invention, in the transistor structure, the first extension portion may be overlapped with the isolation structure, and the second extension portion may be overlapped with the isolation structure.

基於上述，在本發明所提出的電晶體結構中，主動區具有彼此相對的第一側與第二側。閘極包括主體部、第一延伸部與第二延伸部。第一延伸部與第二延伸部連接於主體部。第一延伸部位在第一側且重疊於主動區，且第二延伸部位在第二側且重疊於主動區，藉此閘極在主動區的鄰近於第一側的邊緣區域可具有較大的閘極長度(gate length)，且閘極在主動區的鄰近於第二側的邊緣區域可具有較大的閘極長度。因此，可提高電晶體結構在主動區的鄰近於第一側的邊緣區域的通道電阻，且可提高電晶體結構在主動區的鄰近於第二側的邊緣區域的通道電阻。如此一來，可有效地降低電流雙峰效應，進而避免電流雙峰效應對電晶體結構的電性造成不良影響。Based on the above, in the transistor structure proposed in the present invention, the active region has a first side and a second side opposite to each other. The gate includes a main body, a first extension and a second extension. The first extension and the second extension are connected to the main body. The first extension is on the first side and overlaps the active region, and the second extension is on the second side and overlaps the active region, whereby the gate can have a larger gate length in the edge region of the active region adjacent to the first side, and the gate can have a larger gate length in the edge region of the active region adjacent to the second side. Therefore, the channel resistance of the transistor structure in the edge region adjacent to the first side of the active region can be increased, and the channel resistance of the transistor structure in the edge region adjacent to the second side of the active region can be increased. In this way, the current double peak effect can be effectively reduced, thereby avoiding the adverse effects of the current double peak effect on the electrical properties of the transistor structure.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings.

圖1為根據本發明的一些實施例的電晶體結構的上視圖。圖2為沿著圖1中的I-I’剖面線、II-II’剖面線與III-III’剖面線的電晶體結構的剖面圖。在圖1的上視圖中，省略圖2中的部分構件，以清楚說明上視圖中的各構件之間的設置關係。圖3為根據本發明的另一些實施例的電晶體結構的上視圖。FIG. 1 is a top view of a transistor structure according to some embodiments of the present invention. FIG. 2 is a cross-sectional view of the transistor structure along the I-I’ section line, the II-II’ section line, and the III-III’ section line in FIG. 1 . In the top view of FIG. 1 , some components in FIG. 2 are omitted to clearly illustrate the arrangement relationship between the components in the top view. FIG. 3 is a top view of a transistor structure according to some other embodiments of the present invention.

請參照圖1與圖2，電晶體結構10包括基底100、閘極104、摻雜區106、摻雜區108與閘介電層110。基底100包括主動區AA。主動區AA具有彼此相對的第一側S1與第二側S2。在一些實施例中，第一側S1與第二側S2可在方向D1上排列。在一些實施例中，基底100可為半導體基底，如矽基底。1 and 2, the transistor structure 10 includes a substrate 100, a gate 104, a doped region 106, a doped region 108, and a gate dielectric layer 110. The substrate 100 includes an active region AA. The active region AA has a first side S1 and a second side S2 opposite to each other. In some embodiments, the first side S1 and the second side S2 may be arranged in a direction D1. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate.

在一些實施例中，電晶體結構10更可包括隔離結構102。隔離結構102位在基底100中。隔離結構102可在基底100中定義出主動區AA。在一些實施例中，隔離結構102例如是淺溝渠隔離(shallow trench isolation，STI)結構。在一些實施例中，隔離結構102的材料例如是氧化矽。In some embodiments, the transistor structure 10 may further include an isolation structure 102. The isolation structure 102 is located in the substrate 100. The isolation structure 102 may define an active area AA in the substrate 100. In some embodiments, the isolation structure 102 is, for example, a shallow trench isolation (STI) structure. In some embodiments, the material of the isolation structure 102 is, for example, silicon oxide.

閘極104位在主動區AA的基底100上。在一些實施例中，如圖1所示，閘極104更可位在隔離結構102上。在一些實施例中，閘極104的材料例如是金屬或摻雜多晶矽。The gate 104 is located on the substrate 100 in the active area AA. In some embodiments, as shown in FIG1 , the gate 104 may be further located on the isolation structure 102. In some embodiments, the material of the gate 104 is, for example, metal or doped polysilicon.

閘極104包括主體部P1、延伸部P2與延伸部P3。在一些實施例中，主體部P1可在方向D1上延伸且跨越主動區AA。延伸部P2與延伸部P3連接於主體部P1。延伸部P2位在第一側S1且重疊於主動區AA。在一些實施例中，如圖1所示，延伸部P2更可重疊於隔離結構102。延伸部P3位在第二側S2且重疊於主動區AA。在一些實施例中，如圖1所示，延伸部P3更可重疊於隔離結構102。在一些實施例中，在第一側S1可只有一個延伸部P2，且在第二側S2可只有一個延伸部P3。在一些實施例中，主體部P1、延伸部P2與延伸部P3可為一體成型。The gate 104 includes a main portion P1, an extension portion P2, and an extension portion P3. In some embodiments, the main portion P1 may extend in a direction D1 and cross the active area AA. The extension portion P2 and the extension portion P3 are connected to the main portion P1. The extension portion P2 is located on the first side S1 and overlaps the active area AA. In some embodiments, as shown in FIG. 1 , the extension portion P2 may further overlap the isolation structure 102. The extension portion P3 is located on the second side S2 and overlaps the active area AA. In some embodiments, as shown in FIG. 1 , the extension portion P3 may further overlap the isolation structure 102. In some embodiments, there may be only one extension portion P2 on the first side S1, and there may be only one extension portion P3 on the second side S2. In some embodiments, the main portion P1, the extension portion P2 and the extension portion P3 may be integrally formed.

摻雜區106與摻雜區108位在主動區AA中且位在閘極104的兩側的基底100中。在一些實施例中，摻雜區106可用作為源極區，且摻雜區108可用作為汲極區，但本發明並不以此為限。在另一些實施例中，摻雜區106可用作為汲極區，且摻雜區108可用作為源極區。在一些實施例中，摻雜區106與摻雜區108可在方向D2上排列。方向D2可相交於方向D1。在一些實施例中，方向D2可垂直於方向D1。The doped region 106 and the doped region 108 are located in the active region AA and in the substrate 100 on both sides of the gate 104. In some embodiments, the doped region 106 can be used as a source region, and the doped region 108 can be used as a drain region, but the present invention is not limited thereto. In other embodiments, the doped region 106 can be used as a drain region, and the doped region 108 can be used as a source region. In some embodiments, the doped region 106 and the doped region 108 can be arranged in a direction D2. The direction D2 can intersect with the direction D1. In some embodiments, the direction D2 can be perpendicular to the direction D1.

在本實施例中，如圖1所示，延伸部P2與延伸部P3可位在主體部P1的相對兩側。在圖1中，延伸部P2可位在主體部P1的鄰近於摻雜區106的一側，且延伸部P3可位在主體部P1的鄰近於摻雜區108的一側，但本發明並不以此為限。在另一些實施例中，在圖中雖未示出，延伸部P2可位在主體部P1的鄰近於摻雜區108的一側，且延伸部P3可位在主體部P1的鄰近於摻雜區106的一側。In this embodiment, as shown in FIG1 , the extension portion P2 and the extension portion P3 may be located on opposite sides of the main portion P1. In FIG1 , the extension portion P2 may be located on a side of the main portion P1 adjacent to the doping region 106, and the extension portion P3 may be located on a side of the main portion P1 adjacent to the doping region 108, but the present invention is not limited thereto. In other embodiments, although not shown in the figure, the extension portion P2 may be located on a side of the main portion P1 adjacent to the doping region 108, and the extension portion P3 may be located on a side of the main portion P1 adjacent to the doping region 106.

在另一些實施例中，如圖3所示，延伸部P2與延伸部P3可位在主體部P1的同一側。在圖3中，延伸部P2與延伸部P3可位在主體部P1的鄰近於摻雜區106的一側，但本發明並不以此為限。在另一些實施例中，在圖中雖未示出，延伸部P2與延伸部P3可位在主體部P1的鄰近於摻雜區108的一側。In some other embodiments, as shown in FIG3 , the extension portion P2 and the extension portion P3 may be located on the same side of the main portion P1. In FIG3 , the extension portion P2 and the extension portion P3 may be located on a side of the main portion P1 adjacent to the doped region 106, but the present invention is not limited thereto. In some other embodiments, although not shown in the figure, the extension portion P2 and the extension portion P3 may be located on a side of the main portion P1 adjacent to the doped region 108.

如圖2所示，閘介電層110位在閘極104與基底100之間。在一些實施例中，閘介電層110的材料例如是高介電常數(high dielectric constant，high-k)介電材料、氧化矽或氮氧化矽(SiON)。2 , the gate dielectric layer 110 is located between the gate 104 and the substrate 100. In some embodiments, the material of the gate dielectric layer 110 is, for example, a high dielectric constant (high-k) dielectric material, silicon oxide, or silicon oxynitride (SiON).

基於上述實施例可知，在電晶體結構10中，主動區AA具有彼此相對的第一側S1與第二側S2。閘極104包括主體部P1、延伸部P2與延伸部P3。延伸部P2與延伸部P3連接於主體部P1。延伸部P2位在第一側S1且重疊於主動區AA，且延伸部P3位在第二側S2且重疊於主動區AA，藉此閘極104在主動區AA的鄰近於第一側S1的邊緣區域可具有較大的閘極長度，且閘極104在主動區AA的鄰近於第二側S2的邊緣區域可具有較大的閘極長度。因此，可提高電晶體結構10在主動區AA的鄰近於第一側S1的邊緣區域的通道電阻，且可提高電晶體結構10在主動區AA的鄰近於第二側S2的邊緣區域的通道電阻。如此一來，可有效地降低電流雙峰效應，進而避免電流雙峰效應對電晶體結構10的電性造成不良影響。Based on the above embodiments, it can be known that in the transistor structure 10, the active region AA has a first side S1 and a second side S2 opposite to each other. The gate 104 includes a main portion P1, an extension portion P2 and an extension portion P3. The extension portion P2 and the extension portion P3 are connected to the main portion P1. The extension portion P2 is located at the first side S1 and overlaps the active region AA, and the extension portion P3 is located at the second side S2 and overlaps the active region AA, whereby the gate 104 can have a larger gate length in the edge region of the active region AA adjacent to the first side S1, and the gate 104 can have a larger gate length in the edge region of the active region AA adjacent to the second side S2. Therefore, the channel resistance of the transistor structure 10 in the edge region of the active region AA adjacent to the first side S1 can be increased, and the channel resistance of the transistor structure 10 in the edge region of the active region AA adjacent to the second side S2 can be increased. In this way, the current double peak effect can be effectively reduced, thereby avoiding the adverse effects of the current double peak effect on the electrical properties of the transistor structure 10.

圖4為根據本發明的另一些實施例的電晶體結構的上視圖。圖5為沿著圖4中的I-I’剖面線、II-II’剖面線與III-III’剖面線的電晶體結構的剖面圖。圖6為根據本發明的另一些實施例的沿著圖4中的I-I’剖面線、II-II’剖面線與III-III’剖面線的電晶體結構的剖面圖。在圖4的上視圖中，省略圖5中的部分構件，以清楚說明上視圖中的各構件之間的設置關係。圖7為根據本發明的另一些實施例的電晶體結構的上視圖。圖8為根據本發明的另一些實施例的電晶體結構的上視圖。圖9為根據本發明的另一些實施例的電晶體結構的上視圖。圖10為根據本發明的另一些實施例的電晶體結構的上視圖。圖11為根據本發明的另一些實施例的電晶體結構的上視圖。Fig. 4 is a top view of a transistor structure according to other embodiments of the present invention. Fig. 5 is a cross-sectional view of a transistor structure along the I-I’ section line, II-II’ section line and III-III’ section line in Fig. 4. Fig. 6 is a cross-sectional view of a transistor structure along the I-I’ section line, II-II’ section line and III-III’ section line in Fig. 4 according to other embodiments of the present invention. In the top view of Fig. 4, some components in Fig. 5 are omitted to clearly illustrate the arrangement relationship between the components in the top view. Fig. 7 is a top view of a transistor structure according to other embodiments of the present invention. Fig. 8 is a top view of a transistor structure according to other embodiments of the present invention. Fig. 9 is a top view of a transistor structure according to other embodiments of the present invention. Fig. 10 is a top view of a transistor structure according to some other embodiments of the present invention. Fig. 11 is a top view of a transistor structure according to some other embodiments of the present invention.

請參照圖1、圖2、圖4與圖5，圖4與圖5的電晶體結構20與圖1與圖2的電晶體結構10的差異如下。在電晶體結構20中，延伸部P2可包括開口OP1，且開口OP1可重疊於主動區AA，藉此可進一步地提高電晶體結構20在主動區AA的鄰近於第一側S1的邊緣區域的通道電阻。如此一來，可進一步地降低電流雙峰效應，進而避免電流雙峰效應對電晶體結構20的電性造成不良影響。在一些實施例中，如圖4所示，開口OP1更可重疊於隔離結構102。Please refer to FIG. 1 , FIG. 2 , FIG. 4 , and FIG. 5 . The difference between the transistor structure 20 of FIG. 4 and FIG. 5 and the transistor structure 10 of FIG. 1 and FIG. 2 is as follows. In the transistor structure 20 , the extension portion P2 may include an opening OP1 , and the opening OP1 may overlap the active region AA, thereby further improving the channel resistance of the transistor structure 20 in the edge region of the active region AA adjacent to the first side S1 . In this way, the current double peak effect can be further reduced, thereby avoiding the current double peak effect from causing adverse effects on the electrical properties of the transistor structure 20 . In some embodiments, as shown in FIG. 4 , the opening OP1 may further overlap the isolation structure 102 .

在電晶體結構20中，延伸部P3可包括開口OP2，且開口OP2可重疊於主動區AA，藉此可進一步地提高電晶體結構20在主動區AA的鄰近於第二側S2的邊緣區域的通道電阻。如此一來，可進一步地降低電流雙峰效應，進而避免電流雙峰效應對電晶體結構20的電性造成不良影響。在一些實施例中，如圖4所示，開口OP2更可重疊於隔離結構102。In the transistor structure 20, the extension portion P3 may include an opening OP2, and the opening OP2 may overlap the active region AA, thereby further improving the channel resistance of the transistor structure 20 in the edge region of the active region AA adjacent to the second side S2. In this way, the current double peak effect can be further reduced, thereby avoiding the current double peak effect from causing adverse effects on the electrical properties of the transistor structure 20. In some embodiments, as shown in FIG. 4 , the opening OP2 may further overlap the isolation structure 102.

在本實施例中，如圖5所示，開口OP1可貫穿閘極104與閘介電層110而暴露出基底100，且開口OP2可貫穿閘極104與閘介電層110而暴露出基底100，但本發明並不以此為限。在另一些實施例中，如圖6所示，開口OP1可貫穿閘極104而暴露出閘介電層110，且開口OP2可貫穿閘極104而暴露出閘介電層110。In this embodiment, as shown in FIG5 , the opening OP1 may penetrate the gate 104 and the gate dielectric layer 110 to expose the substrate 100, and the opening OP2 may penetrate the gate 104 and the gate dielectric layer 110 to expose the substrate 100, but the present invention is not limited thereto. In other embodiments, as shown in FIG6 , the opening OP1 may penetrate the gate 104 to expose the gate dielectric layer 110, and the opening OP2 may penetrate the gate 104 to expose the gate dielectric layer 110.

在圖4、圖7與圖8中，延伸部P2與延伸部P3可位在主體部P1的相對兩側，但本發明並不以此為限。在另一些實施例中，如圖9至圖11所示，延伸部P2與延伸部P3可位在主體部P1的同一側。In Figures 4, 7 and 8, the extension portion P2 and the extension portion P3 may be located on opposite sides of the main portion P1, but the present invention is not limited thereto. In other embodiments, as shown in Figures 9 to 11, the extension portion P2 and the extension portion P3 may be located on the same side of the main portion P1.

在圖4與圖9中，開口OP1只位在延伸部P2中，且開口OP2只位在延伸部P3中，但本發明並不以此為限。在另一些實施例中，如圖7、圖8、圖10與圖11所示，開口OP1可延伸至主體部P1中，且開口OP2可延伸至主體部P1中。In FIG. 4 and FIG. 9 , the opening OP1 is only located in the extension portion P2, and the opening OP2 is only located in the extension portion P3, but the present invention is not limited thereto. In other embodiments, as shown in FIG. 7 , FIG. 8 , FIG. 10 and FIG. 11 , the opening OP1 may extend into the main body portion P1, and the opening OP2 may extend into the main body portion P1.

此外，在圖1至圖3的電晶體結構10與圖4至圖11的電晶體結構20中，相同或相似的構件以相同的符號表示，於此不再說明。In addition, in the transistor structure 10 of FIGS. 1 to 3 and the transistor structure 20 of FIGS. 4 to 11 , the same or similar components are represented by the same symbols and will not be described again.

基於上述實施例可知，在電晶體結構20中，主動區AA具有彼此相對的第一側S1與第二側S2。閘極104包括主體部P1、延伸部P2與延伸部P3。延伸部P2與延伸部P3連接於主體部P1。延伸部P2位在第一側S1且重疊於主動區AA，且延伸部P3位在第二側S2且重疊於主動區AA，藉此閘極104在主動區AA的鄰近於第一側S1的邊緣區域可具有較大的閘極長度，且閘極104在主動區AA的鄰近於第二側S2的邊緣區域可具有較大的閘極長度。因此，可提高電晶體結構20在主動區AA的鄰近於第一側S1的邊緣區域的通道電阻，且可提高電晶體結構20在主動區AA的鄰近於第二側S2的邊緣區域的通道電阻。如此一來，可有效地降低電流雙峰效應，進而避免電流雙峰效應對電晶體結構20的電性造成不良影響。Based on the above embodiments, it can be known that in the transistor structure 20, the active region AA has a first side S1 and a second side S2 opposite to each other. The gate 104 includes a main portion P1, an extension portion P2 and an extension portion P3. The extension portion P2 and the extension portion P3 are connected to the main portion P1. The extension portion P2 is located at the first side S1 and overlaps the active region AA, and the extension portion P3 is located at the second side S2 and overlaps the active region AA, whereby the gate 104 can have a larger gate length in the edge region of the active region AA adjacent to the first side S1, and the gate 104 can have a larger gate length in the edge region of the active region AA adjacent to the second side S2. Therefore, the channel resistance of the transistor structure 20 in the edge region of the active region AA adjacent to the first side S1 can be increased, and the channel resistance of the transistor structure 20 in the edge region of the active region AA adjacent to the second side S2 can be increased. In this way, the current double peak effect can be effectively reduced, thereby avoiding the adverse effects of the current double peak effect on the electrical properties of the transistor structure 20.

綜上所述，在上述實施例的電晶體結構中，主動區具有彼此相對的第一側與第二側。閘極的第一延伸部位在第一側且重疊於主動區，且閘極的第二延伸部位在第二側且重疊於主動區，藉此可提高電晶體結構在主動區的鄰近於第一側的邊緣區域的通道電阻，且可提高電晶體結構在主動區的鄰近於第二側的邊緣區域的通道電阻。如此一來，可有效地降低電流雙峰效應，進而避免電流雙峰效應對電晶體結構的電性造成不良影響。In summary, in the transistor structure of the above embodiment, the active region has a first side and a second side opposite to each other. The first extension portion of the gate is on the first side and overlaps the active region, and the second extension portion of the gate is on the second side and overlaps the active region, thereby increasing the channel resistance of the transistor structure in the edge region adjacent to the first side of the active region, and increasing the channel resistance of the transistor structure in the edge region adjacent to the second side of the active region. In this way, the current double peak effect can be effectively reduced, thereby avoiding the adverse effects of the current double peak effect on the electrical properties of the transistor structure.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

10, 20:電晶體結構10, 20: Transistor structure

100:基底100: Base

102:隔離結構102: Isolation Structure

104:閘極104: Gate

106, 108:摻雜區106, 108: Mixed Area

110:閘介電層110: Gate dielectric layer

AA:主動區AA: Active Area

D1, D2:方向D1, D2: Direction

OP1, OP2:開口OP1, OP2: Open

P1:主體部P1: Main body

P2, P3:延伸部P2, P3: Extension

S1:第一側S1: First side

S2:第二側S2: Second side

圖1為根據本發明的一些實施例的電晶體結構的上視圖。 圖2為沿著圖1中的I-I’剖面線、II-II’剖面線與III-III’剖面線的電晶體結構的剖面圖。 圖3為根據本發明的另一些實施例的電晶體結構的上視圖。 圖4為根據本發明的另一些實施例的電晶體結構的上視圖。 圖5為沿著圖4中的I-I’剖面線、II-II’剖面線與III-III’剖面線的電晶體結構的剖面圖。 圖6為根據本發明的另一些實施例的沿著圖4中的I-I’剖面線、II-II’剖面線與III-III’剖面線的電晶體結構的剖面圖。 圖7為根據本發明的另一些實施例的電晶體結構的上視圖。 圖8為根據本發明的另一些實施例的電晶體結構的上視圖。 圖9為根據本發明的另一些實施例的電晶體結構的上視圖。 圖10為根據本發明的另一些實施例的電晶體結構的上視圖。 圖11為根據本發明的另一些實施例的電晶體結構的上視圖。 FIG. 1 is a top view of a transistor structure according to some embodiments of the present invention. FIG. 2 is a cross-sectional view of a transistor structure along the I-I’ section line, II-II’ section line, and III-III’ section line in FIG. 1. FIG. 3 is a top view of a transistor structure according to some other embodiments of the present invention. FIG. 4 is a top view of a transistor structure according to some other embodiments of the present invention. FIG. 5 is a cross-sectional view of a transistor structure along the I-I’ section line, II-II’ section line, and III-III’ section line in FIG. 4. FIG. 6 is a cross-sectional view of a transistor structure along the I-I’ section line, II-II’ section line, and III-III’ section line in FIG. 4 according to some other embodiments of the present invention. FIG. 7 is a top view of a transistor structure according to some other embodiments of the present invention. FIG8 is a top view of a transistor structure according to some other embodiments of the present invention. FIG9 is a top view of a transistor structure according to some other embodiments of the present invention. FIG10 is a top view of a transistor structure according to some other embodiments of the present invention. FIG11 is a top view of a transistor structure according to some other embodiments of the present invention.

10:電晶體結構 10: Transistor structure

102:隔離結構 102: Isolation structure

104:閘極 104: Gate

106,108:摻雜區 106,108: Mixed area

AA:主動區 AA: Active Area

D1,D2:方向 D1,D2: Direction

P1:主體部 P1: Main body

P2,P3:延伸部 P2, P3: Extension

S1:第一側 S1: First side

S2:第二側 S2: Second side

Claims (9)

一種電晶體結構，包括：基底，包括主動區，其中所述主動區具有彼此相對的第一側與第二側；閘極，位在所述主動區的所述基底上，其中所述閘極包括主體部、第一延伸部與第二延伸部，所述第一延伸部與所述第二延伸部連接於所述主體部，所述第一延伸部位在所述第一側且重疊於所述主動區，且所述第二延伸部位在所述第二側且重疊於所述主動區；第一摻雜區與第二摻雜區，位在所述主動區中且位在所述閘極的兩側的所述基底中；以及閘介電層，位在所述閘極與所述基底之間，其中所述第一延伸部包括第一開口，所述第一開口重疊於所述主動區，所述第二延伸部包括第二開口，且所述第二開口重疊於所述主動區。 A transistor structure includes: a substrate including an active region, wherein the active region has a first side and a second side opposite to each other; a gate located on the substrate of the active region, wherein the gate includes a main body, a first extension and a second extension, wherein the first extension and the second extension are connected to the main body, the first extension is located on the first side and overlaps the active region, and the second extension is located on the second side and overlaps the active region; a first doped region and a second doped region are located in the active region and in the substrate on both sides of the gate; and a gate dielectric layer is located between the gate and the substrate, wherein the first extension includes a first opening, the first opening overlaps the active region, and the second extension includes a second opening, and the second opening overlaps the active region. 如請求項1所述的電晶體結構，其中所述第一延伸部與所述第二延伸部位在所述主體部的相對兩側。 A transistor structure as described in claim 1, wherein the first extension portion and the second extension portion are located on opposite sides of the main body portion. 如請求項1所述的電晶體結構，其中所述第一延伸部與所述第二延伸部位在所述主體部的同一側。 A transistor structure as described in claim 1, wherein the first extension portion and the second extension portion are on the same side of the main body portion. 如請求項1所述的電晶體結構，其中在所述第一側只有一個所述第一延伸部，且在所述第二側只有一個所述第二延伸部。 A transistor structure as described in claim 1, wherein there is only one first extension portion on the first side, and there is only one second extension portion on the second side. 如請求項1所述的電晶體結構，其中所述第一開口延伸至所述主體部中，且所述第二開口延伸至所述主體部中。 A transistor structure as described in claim 1, wherein the first opening extends into the main body, and the second opening extends into the main body. 如請求項1所述的電晶體結構，其中所述主體部在第一方向上延伸且跨越所述主動區，所述第一摻雜區與所述第二摻雜區在第二方向上排列，且所述第二方向相交於所述第一方向。 A transistor structure as described in claim 1, wherein the main body extends in a first direction and crosses the active region, the first doped region and the second doped region are arranged in a second direction, and the second direction intersects with the first direction. 如請求項6所述的電晶體結構，其中所述第一側與所述第二側在所述第一方向上排列。 A transistor structure as described in claim 6, wherein the first side and the second side are arranged in the first direction. 如請求項1所述的電晶體結構，更包括：隔離結構，位在所述基底中，且在所述基底中定義出所述主動區，其中所述閘極更位在所述隔離結構上。 The transistor structure as described in claim 1 further includes: an isolation structure located in the substrate, and the active region is defined in the substrate, wherein the gate is further located on the isolation structure. 如請求項8所述的電晶體結構，其中所述第一延伸部更重疊於所述隔離結構，且所述第二延伸部更重疊於所述隔離結構。 A transistor structure as described in claim 8, wherein the first extension portion further overlaps the isolation structure, and the second extension portion further overlaps the isolation structure.
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TW201201357A (en) * 2010-06-30 2012-01-01 Samsung Electronics Co Ltd Gate electrode and gate contact plug layouts for integrated circuit field effect transistors
US20130143375A1 (en) * 2011-12-06 2013-06-06 Texas Instruments Incorporated On Current in One-Time-Programmable Memory Cells
US20170345929A1 (en) * 2012-10-15 2017-11-30 Texas Instruments Incorporated I-shaped gate electrode for improved sub-threshold mosfet performance
TW201919242A (en) * 2017-11-09 2019-05-16 南亞科技股份有限公司 Transistor device and semiconductor layout structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201201357A (en) * 2010-06-30 2012-01-01 Samsung Electronics Co Ltd Gate electrode and gate contact plug layouts for integrated circuit field effect transistors
US20130143375A1 (en) * 2011-12-06 2013-06-06 Texas Instruments Incorporated On Current in One-Time-Programmable Memory Cells
US20170345929A1 (en) * 2012-10-15 2017-11-30 Texas Instruments Incorporated I-shaped gate electrode for improved sub-threshold mosfet performance
TW201919242A (en) * 2017-11-09 2019-05-16 南亞科技股份有限公司 Transistor device and semiconductor layout structure

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