TWI848339B - Magnetic tunnel junction pillar formation for mram device - Google Patents

Abstract

A method of manufacturing an MRAM device includes forming an MTJ stack on a substrate, forming a hardmask layer on the MTJ stack, forming etch pattern pads on the hardmask, forming a spacer on the sides of the etch pattern pads to form first openings exposing the hardmask, patterning the MTJ stack by a first etch using the first openings to form a plurality of first MTJ pillars separated by first vias, filling the first vias with a first dielectric, removing the spacers from the etch pattern pads to form a plurality of second openings between the first dielectric and the etch pattern pads, patterning the plurality of first MTJ pillars by a second etch using the second openings to form a plurality of second MTJ pillars separated by second vias and filling the second vias with a second dielectric to encapsulate the plurality of second MTJ pillars.

Description

Magnetic tunneling junction pillar formation in magnetoresistive random access memory devices

The present invention relates to a magnetoresistive random access ("MRAM") memory device cell including a magnetic tunneling junction ("MTJ") stack and a method for manufacturing an MRAM device.

Current MRAM MTJ pillar formation requires aggressive IBE etching to remove metal residues on the MTJ sidewalls, which cause shorts. Too strong IBE may dig into the NBLOK and touch the Cu bottom contact, resulting in Cu exposure, migration, and oxidation. Large IBE openings during pillar formation will cause NBLOK loss due to loading effects. Therefore, previous solutions require gentle IBE to avoid excessive NBLOK loss. However, in the case of etching oxidation after oxidizing metal residues, the reduction of IBE budget will introduce significant MTJ sidewall damage.

An embodiment of the present invention relates to a method of manufacturing an MRAM device having a magnetic tunneling junction (MTJ) pillar, comprising: forming a plurality of layers defining an MTJ stack on a substrate; forming a metal hard mask layer on the MTJ stack; forming a plurality of etched pattern pads on the metal hard mask layer; forming a spacer on the side of the plurality of etched pattern pads to form a plurality of first openings exposing the hard mask layer; patterning the MTJ stack by a first etch using the first openings; to form a plurality of first MTJ columns separated by a first through hole; fill the first through holes with a first dielectric; remove the spacers from the plurality of etch pattern pads to form a plurality of second openings between the first dielectric and the plurality of etch pattern pads; pattern the plurality of first MTJ columns by a second etching using the second openings to form a plurality of second MTJ columns separated by a second through hole; and fill the second through holes with a second dielectric to encapsulate the plurality of second MTJ columns.

An embodiment of the present invention relates to an MRAM device having a magnetic tunneling junction (MTJ) pillar, comprising: a plurality of MTJ pillars located on a substrate; a first dielectric located between the MTJ pillar pairs defining two vias between each MTJ pillar pair; and a second dielectric filling the via pairs and encapsulating the plurality of MTJ pillars.

Other features and the structure and operation of various embodiments are described in detail below with reference to the accompanying drawings. In the drawings, similar figure numbers indicate identical or functionally similar elements.

10:Structure

12:BEOL substrate

14:BEOL metal layer

16:BEOL dielectric layer/through-hole dielectric layer

18: Micro-short column layer

20:MTJ stacking

21: First MTJ column

22: Seed layer

24: Magnetic free layer

26: Tunnel barrier layer

28: Reference layer

30: Hard mask stack/metal hard mask layer

32: Etched pattern pad

34: Spacer

35: First opening

36:Through hole

38: First dielectric layer/dielectric

40: Etching opening

41: Second MTJ column

42:Through hole

44: Top

46: Dielectric encapsulation layer

48:Metal contact layer

50: Second ILD or NBLOK layer

52: Final MRAM device

FIG. 1 is a cross-sectional view of a back-end process base layer formed below a magnetic tunneling junction (MTJ) stack of an MRAM device according to an embodiment.

FIG. 2 is a cross-sectional view of the MRAM device of FIG. 1 after additional manufacturing operations according to an embodiment.

FIG. 3 is a cross-sectional view of the MRAM device of FIG. 2 after additional manufacturing operations according to an embodiment.

FIG. 4 is a cross-sectional view of the MRAM device of FIG. 3 after additional manufacturing operations according to an embodiment.

FIG. 5 is a cross-sectional view of the MRAM device of FIG. 4 after additional manufacturing operations according to an embodiment.

FIG. 6 is a cross-sectional view of the MRAM device of FIG. 5 after additional manufacturing operations according to an embodiment.

FIG. 7 is a cross-sectional view of the MRAM device of FIG. 6 after additional manufacturing operations according to an embodiment.

FIG8 is a cross-sectional view of the MRAM device of FIG7 after additional manufacturing operations according to an embodiment.

FIG. 9 is a cross-sectional view of the MRAM device of FIG. 8 after additional manufacturing operations according to an embodiment.

The present invention describes an MRAM device including a magnetic tunneling junction ("MTJ") stack and a method of manufacturing the MRAM device. In particular, the present invention describes a two-step etching process, one step for removing MTJ stack material in a field region, and a second etching process performed using a small etch opening. The present invention describes an MRAM device composed of MTJ stack pillars having two different underline dielectric layers with different cross-sectional profiles in the same direction adjacent to the MTJ stack pillars.

Various embodiments of the present invention are described herein with reference to the relevant drawings. Alternative embodiments may be designed without departing from the scope of the present invention. It should be noted that various connections and positional relationships (e.g., above, below, adjacent, etc.) between elements are described in the following description and drawings. Unless otherwise specified, such connections and/or positional relationships may be direct or indirect, and the present invention is not intended to be limiting in this regard. Accordingly, coupling of entities may refer to direct or indirect coupling, and positional relationships between entities may be direct or indirect positional relationships. As an example of an indirect positional relationship, references in this description to forming layer "A" above layer "B" include the case where one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B", as long as the relevant characteristics and functionality of layer "A" and layer "B" are not substantially altered by the intermediate layers.

The following definitions and abbreviations will be used to interpret the scope of the application and this specification. As used herein, the terms "comprises/comprising", "includes/including", "has/having", "contains or containing" or any other variations thereof are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that includes a list of elements is not necessarily limited to those elements but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

For purposes of description hereinafter, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives shall relate to the described structures and methods as oriented in the drawings. The terms "overlying," "on top," "on top," "positioned over," or "positioned over" mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as interface structures, may be present between the first element and the second element. The term "directly contacting" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive, insulating, or semiconductor layer at the interface of the two elements. It should be noted that the term "selective to", such as "a first element is selective to a second element", means that the first element can be etched and the second element can act as an etch stop.

For the sake of brevity, the known techniques associated with semiconductor devices and integrated circuits ("ICs") may or may not be described in detail herein. In addition, the various tasks and process steps described herein may be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, the various steps in manufacturing semiconductor devices and semiconductor-based ICs are well known, and therefore for the sake of brevity, many known steps will only be briefly mentioned herein or will be omitted entirely without providing the details of the well-known processes.

Generally speaking, the various processes used to form microchips that will be packaged into ICs fall into four general categories, namely, film deposition, removal/etching, semiconductor doping, and patterning/lithography.

Deposition is any process by which material is grown, coated, or otherwise transferred onto a wafer. Available techniques include physical vapor deposition ("PVD"), chemical vapor deposition ("CVD"), electrochemical deposition ("ECD"), molecular beam epitaxy ("MBE"), and more recently atomic layer deposition ("ALD"). Another deposition technique is plasma enhanced chemical vapor deposition ("PECVD"), which is a process that uses the energy in the plasma to induce reactions at the wafer surface that would otherwise require the higher temperatures associated with conventional CVD. High energy ion bombardment during PECVD deposition can also improve the electrical and mechanical properties of the film.

Removal/etching is any process that removes material from a wafer. Examples include etching processes (wet or dry), chemical mechanical planarization ("CMP"), and the like. One example of a removal process is ion beam etching ("IBE"). Generally speaking, IBE (or polishing) refers to a dry plasma etching method that utilizes a remote wide beam ion/plasma source to remove substrate material by means of physically inert gases and/or chemically reactive gases. Similar to other dry plasma etching techniques, IBE has benefits such as etch rate, anisotropy, selectivity, uniformity, aspect ratio, and minimization of substrate damage. Another example of a dry removal process is reactive ion etching ("RIE"). Generally speaking, RIE uses a chemically reactive plasma to remove material deposited on a wafer. In the case of RIE, a plasma is generated by an electromagnetic field at low pressure (vacuum). High-energy ions from the RIE plasma erode the wafer surface and react with it to remove material.

Semiconductor doping is the modification of electrical properties by doping, for example, transistor source and drain, generally by diffusion and/or by ion implantation. These doping processes are followed by furnace annealing or rapid thermal annealing ("RTA"). Annealing is used to activate the implanted dopants. Films of both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various areas of a semiconductor substrate allows the conductivity of the substrate to be altered by applying a voltage. By creating structures of these various components, millions of transistors can be constructed and wired together to form the complex circuit systems of modern microelectronic devices.

Semiconductor lithography is the process of forming a three-dimensional relief image or pattern on a semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the pattern is formed from a photosensitive polymer called a photoresist. The lithography and etching pattern transfer steps are repeated many times to build the complex structures that make up the transistors and the many wires that connect the millions of transistors in the circuits. Each pattern printed on the wafer is aligned to the previously formed pattern, and conductors, insulators, and selective doping regions are slowly built up to form the final device.

Turning now to an overview of the technology more specifically related to aspects of the present invention, embedded DRAM ("eDRAM") is dynamic random access memory ("DRAM") integrated on the same die or multi-chip module ("MCM") of an application specific integrated circuit ("ASIC") or microprocessor. eDRAM has been implemented in silicon-on-insulator ("SOI") technology, which refers to the use of layered silicon-insulator-silicon substrates instead of conventional silicon substrates in semiconductor manufacturing. eDRAM technology has met with varying degrees of success, and demand for SOI technology as a server memory option has decreased in recent years.

Magnetoresistive random access memory ("MRAM") devices using magnetic tunneling junctions ("MTJ") are one option for replacing existing eDRAM technology. MRAM is a non-volatile memory, and this benefit is a driving factor that accelerates the development of this memory technology.

Referring now to the drawings where the same number represents the same or similar elements, and initially to FIG. 1 , an exemplary structure 10 is shown to which embodiments of the present invention may be applied. The structure 10 includes a back-end-of-line (“BEOL”) substrate 12 composed of a plurality of layers. Generally, the BEOL substrate 12 is the second part of IC fabrication where individual devices (transistors, capacitors, resistors, etc.) are interconnected with wiring on a wafer. As shown in FIG. 1 , the BEOL substrate 12 includes a BEOL metal layer 14 and a BEOL dielectric layer 16. The BEOL metal layer 14 may include, for example, Cu, TaN, Ta, Ti, TiN, or a combination thereof. The BEOL dielectric layer 16 may be composed of, for example, SiOx, SiNx, SiBCN, low-κ NBLOK, or any other suitable dielectric material.

The micro-short pillar layer 18 is formed on the BEOL metal layer 14. Initially, the micro-short pillar layer 18 may be formed by patterning the dielectric layer 16 by lithography. Then, vias are formed in the via dielectric layer 16 by, for example, RIE to remove space for subsequent filling of the micro-short pillar layer 18. In some embodiments, the micro-short pillar layer 18 may include materials such as W, Cu, TaN, Ta, Ti, TiN, TiOCN, TaOCN, or a combination of these materials. The micro-short pillar layer 18 may be formed by CVD, PVD, ALD, or a combination thereof. After the micro-short pillar layer 18 is formed, the structure is subjected to, for example, CMP to planarize the surface for further processing. The structure including the BEOL layer shown in FIG. 1 is the starting structure on which the MTJ stack is formed.

The MTJ stack 20 is formed on the through-hole dielectric layer 16 and the micro-short column layer 18. In some embodiments, the MTJ stack layer 20 includes a seed layer 22 formed on the through-hole dielectric layer 16. The seed layer 22 has a lattice and grain structure suitable for serving as a growth surface of a free layer of the MTJ stack 20. The seed layer 22 may be a metal seed layer composed of, for example, Ru, Ta, NiCr, or a combination of these materials.

In general, the MTJ stack 20 may include a magnetic free layer 24, a tunneling barrier layer 26, and a reference layer 28 having a fixed magnetic polarity. In general, the magnetic free layer 24 has a flippable magnetic moment or magnetization. In some embodiments, the tunneling barrier layer 26 is a barrier, such as a thin insulating layer between two conductive materials. Electrons pass through the tunneling barrier 26 by a quantum tunneling process. In some embodiments, the tunneling barrier layer 26 is composed of MgO. In some embodiments, each layer of the MTJ stack 20 may have a thickness of less than one angstrom to a few angstroms or nanometers. Examples of typical materials in the MTJ stack 20 may include MgO for the tunneling barrier layer 26, CoFeB for the free layer 24, and multiple layers of different materials including the reference layer 28. It should be understood that the MRAM materials forming the MTJ stack 20 are not limited to those materials or layers described above. That is, the MRAM material stack may be composed of any known stack of materials used in MRAM devices. In addition, it should be understood that any of the MTJ stacks 20 may include additional layers, omit certain layers, and each of the layers may include any number of sub-layers.

A hard mask stack 30 is deposited on the MTJ stack 20. In some embodiments, the hard mask stack 30 is composed of a layer of Ta or Ru and a layer of TaN. The hard mask stack 30 is then patterned by lithography and RIE. As shown in FIG. 2 , in some embodiments, the etch pattern layer is patterned to form an etch pattern pad 32 composed of an organic planarization layer (“OPL”) material, an oxide (such as SiNx, SiOx), SiARC, a photoresist, or a combination thereof. Initially, the material of the etch pattern pad 32 is deposited on the hard mask 30 and then etched by RIE or IBE to form the pattern of the pad 32 shown in FIG. 2 .

Referring now to FIG. 3 , a spacer 34 is formed on the sidewall of the etched pattern 32 and a first opening 35 is formed later. The spacer 34 may be formed of, for example, SiN, SiBCN or SiCN and is typically selected to have etching selectivity relative to the etched pattern pad 32.

Referring now to FIG. 4 , the MTJ stack 20 is patterned with a first IBE while forming a first MTJ column 21 by etching a pattern pad 32 with spacers 34 for the pattern. As shown in FIG. 4 , the etching is stopped inside the dielectric layer 16 (or near the top thereof). In some embodiments, the MTJ stack 20 is patterned by IBE at multiple angles or RIE or a combination thereof. Thus, after the etching process, multiple first MTJ columns 21 separated by vias 36 are formed. Considering that this IBE is not used for the final MTJ column formation, a non-aggressive or gentle IBE in the opening 35 may be used. In some embodiments, the IBE may use a low bias voltage for a short time.

Referring now to FIG. 5 , a first dielectric layer 38 is deposited to fill the via 36. This first dielectric layer 38 may be made of any suitable ILD oxide, low-κ, flowable oxide. In some embodiments, the first dielectric layer 38 has an extremely low adhesion coefficient to the MTJ pillar, so that it can be easily removed from the surface of the first MTJ pillar 21. In some embodiments, the dielectric material may be made of low-quality SiN, SiBCN, SiON, SiOx, SiCON, or a combination thereof, so that it may be susceptible to damage caused by IBE etching. The first dielectric layer 38 is deposited to a sufficient height to cover the sidewalls of the spacer 34 and the top surface of the spacer 34 and the etched pattern pad 32. After dielectric filling of via 36, CMP is performed to expose the top surface of etched pattern pad 32 with spacers 34.

Referring now to FIG. 6 , the spacers 34 are removed, leaving etch openings 40 on both sides of the etch pattern pad 32. The etch openings 40 are smaller than the first openings 35. The spacers are removed using selective RIE or a suitable wet or dry etching process. In some embodiments, the spacers are removed to define the etch openings 40 to have a nearly vertical etch slope or a nearly vertical contact angle. The term "nearly vertical etch slope" or "nearly vertical contact angle" is used to mean an angle defined by the sidewalls of the opening and the top plane of the etch pattern 32 of at least 80 degrees, preferably about 90 degrees.

As shown in FIG. 7 , a second IBE is performed to etch the first MTJ pillar 21 while forming a second MTJ pillar 41 by etching the pattern pad 32 without using the spacer 34 for the pattern. As shown in FIG. 7 , the etching is stopped inside the dielectric layer 16 (or near its top), thereby forming a via 42 between the MTJ pillar 41 and the first dielectric 38. The IBE budget can be much higher because the smaller etch opening 40 results in less specification of the dielectric 16. Therefore, the second IBE can be more aggressive using a higher bias voltage for a longer time with a straighter etch angle than the first IBE etch. No additional lithography process is required. The pre-filled sacrificial dielectric 38 will be etched during the second IBE etch, so that two second vias 42 are formed between the second MTJ pillar pair 41. The dielectric 38 also serves as a protective layer for the underlying NBLOK layer 16. Therefore, due to the small opening 40, the NBLOK loss during this second IBE step will be minimal compared to the conventional MTJ stack patterning with a much larger opening. Due to the etching of the first dielectric 38, the top 44 of the opening 40 will be wider, which will be beneficial for the subsequent angled IBE clean etch. As shown in Figure 7, the first dielectric 38 is separated from the second MTJ pillar 41.

A dielectric encapsulation layer 46 is formed to fill the through hole 42, thereby covering the exposed surface of the second MTJ column 41 and the etched pattern pad 32, followed by a CMP planarization process. As shown in FIG. 8 , CMP exposes the upper surface of the second MTJ column 41 and the dielectric encapsulation layer 46. For example, the dielectric encapsulation layer 46 may include at least one of PVD, ALD, PECVD, AlOx, TiOx, BN, SiN, and SiBCN.

Referring now to FIG. 9 , after the CMP planarization process, a metal contact layer 48 is formed on the exposed surfaces of the encapsulation layer 46 and the second MTJ column 41 by conventional lithography. In some embodiments, after the metal contact layer 48 is formed, a second ILD or NBLOK layer 50 is formed to cover the top surface of the metal contact layer 48. In some embodiments, the metal contact layer 48 is composed of Ta, TaN, Cu, or any suitable combination thereof. In some embodiments, as shown in FIG. 9 , a metal contact layer is formed on the side surface of the metal hard mask layer 30 of the second MTJ column 41 by removing a portion of the encapsulation layer 46 using selective RIE or other suitable wet or dry etching.

The final MRAM device 52 shown in FIG. 9 is composed of a second MTJ stack pillar 41 with two different underline dielectric layers 38 and 46 having different cross-sectional profiles adjacent to the second MTJ stack pillar 41. The MRAM device 52 is formed using a two-step etch process, one step for removing the MTJ stack material in the field region using the etch opening 36 shown in FIG. 4, and a second etch process using the smaller etch opening 40 shown in FIG. 6. The two different dielectric fills 38 and 46 adjacent to the MTJ pillars result in better retention of the underline NBLOK 16. The dielectric layer 38 is an etched intermediate sacrificial dielectric between the second MTJ pillars 41.

The descriptions of various embodiments have been presented for illustrative purposes and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements to technologies found in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

10:Structure

12:BEOL substrate

14:BEOL metal layer

16:BEOL dielectric layer

18: Micro-short column layer

20:MTJ stacking

22: Seed layer

24: Magnetic free layer

26: Tunnel barrier layer

28: Reference layer

30: Hard mask stacking

Claims (20)

A method for manufacturing an MRAM device having a magnetic tunneling junction (MTJ) pillar, the method comprising: forming a plurality of layers defining an MTJ stack on a substrate; forming a metal hard mask layer on the MTJ stack; forming a plurality of etched pattern pads on the metal hard mask layer; forming a spacer on a side of the plurality of etched pattern pads to form a plurality of first openings exposing the hard mask layer; patterning the MTJ stack by a first etch using the first openings to form A plurality of first MTJ pillars separated by first through holes; filling the first through holes with a first dielectric; removing the spacers from the plurality of etch pattern pads to form a plurality of second openings between the first dielectric and the plurality of etch pattern pads; patterning the plurality of first MTJ pillars by a second etch using the second openings to form a plurality of second MTJ pillars separated by second through holes; and filling the second through holes with a second dielectric to encapsulate the plurality of second MTJ pillars. In the method of claim 1, the second openings have a width smaller than that of the first openings. The method of claim 2, wherein the first etching is performed in a first time by using an IBE with a first bias voltage, and the second etching is performed in a second time by using an IBE with a second bias voltage, the second bias voltage is higher than the first bias voltage, and the second time is longer than the first time. The method of claim 1, wherein the first dielectric is corroded during the second etching so that two second through holes are formed between the second MTJ pillar pair. The method of claim 1, wherein the first dielectric is etched during the second etching so that the second vias are wider at the top than at the bottom. The method of claim 1, wherein a cross-sectional profile of the first dielectric in a first direction is different from a cross-sectional profile of the second dielectric in the first direction. The method of claim 1, wherein the first dielectric and the second dielectric are made of different materials. As in the method of claim 1, after encapsulating the plurality of second MTJ pillars with the second dielectric, a CMP planarization is performed and a metal contact layer is deposited on the second MTJ pillars. The method of claim 1, wherein the plurality of layers defining the MTJ stack include a magnetic free layer on one side of a tunneling barrier layer and a reference layer having a fixed magnetic polarity on an opposite side of the tunneling barrier layer. The method of claim 1, further comprising forming a seed layer on the substrate before forming the plurality of layers defining the MTJ stack. An MRAM device having a magnetic tunneling junction (MTJ) pillar, comprising: a plurality of MTJ pillars located on a substrate; a first dielectric located between MTJ pillar pairs defining two vias between each MTJ pillar pair, and wherein the first dielectric is separated from the plurality of MTJ pillars; and a second dielectric filling the via pairs and encapsulating the plurality of MTJ pillars. An MRAM device as claimed in claim 11, wherein the first dielectric is formed by a first etching using a first bias voltage within a first time, and the second dielectric is formed by a second etching using a second bias voltage within a second time, the second bias voltage is higher than the first bias voltage, and the second time is longer than the first time. An MRAM device as claimed in claim 12, wherein the first dielectric is corroded during the second etching period so that the two through holes are formed between the MTJ pillar pairs. An MRAM device as claimed in claim 11, wherein the two through holes between each MTJ pillar pair are wider at the top than at the bottom. An MRAM device as claimed in claim 11, wherein a cross-sectional profile of the first dielectric in a first direction is different from a cross-sectional profile of the second dielectric in the first direction. An MRAM device as claimed in claim 11, wherein the first dielectric and the second dielectric are made of different materials. The MRAM device of claim 11 further comprises a metal contact layer on the plurality of MTJ pillars. An MRAM device as claimed in claim 11, wherein the plurality of MTJ pillars include a magnetic free layer on one side of a tunneling barrier layer and a reference layer having a fixed magnetic polarity on an opposite side of the tunneling barrier layer. An MRAM device as claimed in claim 18, wherein the MTJ pillar further comprises a seed layer between the substrate and the plurality of MTJ pillars. An MRAM device as claimed in claim 19, wherein the MTJ pillar further comprises a metal hard mask layer on the magnetic free layer.