TWI848274B - Routing pattern - Google Patents
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Abstract
Description
本發明係有關於佈線圖案,且特別有關於形成於半導體晶片上的佈線圖案。 The present invention relates to wiring patterns, and in particular to wiring patterns formed on semiconductor chips.
微影(photolithography)製程係為積體電路(integrated circuits,ICs)製造中重要的製程之一,其可應用於將佈線圖案自光罩上以一定的比例轉移至半導體晶片表面上的光阻層,進而將積體電路的佈線圖案轉移至半導體晶片上。上述形成佈線圖案的製程還可能包含使用流體之清潔步驟與乾燥步驟,以去除多個處理步驟留下的殘餘物。 The photolithography process is one of the important processes in the manufacture of integrated circuits (ICs). It can be used to transfer the wiring pattern from the mask to the photoresist layer on the surface of the semiconductor chip at a certain ratio, and then transfer the wiring pattern of the integrated circuit to the semiconductor chip. The above-mentioned process for forming the wiring pattern may also include a cleaning step and a drying step using a fluid to remove the residues left by multiple processing steps.
然而,隨著積體電路的複雜度與集成度日益提升,佈線圖案的線寬與間距亦隨之不斷縮小,具有細小線寬與間距的佈線圖案容易倒塌(collapse),進而降低產品的可靠度(reliability)與良率。 However, as the complexity and integration of integrated circuits increase, the line width and spacing of wiring patterns are also shrinking. Wiring patterns with small line width and spacing are prone to collapse, thereby reducing the reliability and yield of products.
因此,改善圖案倒塌問題是相當重要的。 Therefore, it is very important to improve the pattern collapse problem.
本發明係有關於佈線圖案(routing pattern),其可改善圖案倒塌問題,並可有效提升佈線圖案製造過程之製程裕度(process window)。 The present invention relates to a routing pattern, which can improve the pattern collapse problem and effectively improve the process window of the routing pattern manufacturing process.
根據本發明之一實施例,提供佈線圖案。佈線圖案包含複數個線型特徵與配置於複數個線型特徵中的二者之間的內連線特徵。複數個線型特徵沿著第一方向延伸且具有沿著第二方向的第一線寬(line width)。第二方向垂直於第一方向。內連線特徵包含沿著第二方向凹陷的凹部。內連線特徵具有沿著第二方向的第二線寬。第一線寬小於第二線寬。 According to one embodiment of the present invention, a wiring pattern is provided. The wiring pattern includes a plurality of linear features and an internal connection feature arranged between two of the plurality of linear features. The plurality of linear features extend along a first direction and have a first line width along a second direction. The second direction is perpendicular to the first direction. The internal connection feature includes a concave portion concave along the second direction. The internal connection feature has a second line width along the second direction. The first line width is smaller than the second line width.
根據本發明之一實施例,提供佈線圖案。佈線圖案包含第一佈線區域、第二佈線區域與內連線區。第一佈線區域包含複數條沿著第一方向延伸的第一導線。複數條第一導線沿垂直於該第一方向的第二方向具有第一節距(pitch)。第二佈線區域包含複數條沿著第一方向延伸的第二導線。複數條第二導線沿著第二方向具有第二節距,第二節距大致相等於第一節距。內連線區包含二沿著第一方向分離配置的主體部、以及連接於二主體部的連接部。連接部沿著第二方向的寬度小於二主體部沿著第二方向的寬度。 According to one embodiment of the present invention, a wiring pattern is provided. The wiring pattern includes a first wiring area, a second wiring area and an internal connection area. The first wiring area includes a plurality of first wires extending along a first direction. The plurality of first wires have a first pitch along a second direction perpendicular to the first direction. The second wiring area includes a plurality of second wires extending along the first direction. The plurality of second wires have a second pitch along the second direction, and the second pitch is substantially equal to the first pitch. The internal connection area includes two main bodies separated and arranged along the first direction, and a connecting part connected to the two main bodies. The width of the connecting part along the second direction is smaller than the width of the two main bodies along the second direction.
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉實施例,並配合所附圖式詳細說明如下。 In order to better understand the above and other aspects of the present invention, the following is a specific example and a detailed description with the attached drawings.
10,20,30,40,50,60:佈線圖案 10,20,30,40,50,60: wiring pattern
101,102:佈線區域 101,102: Wiring area
101a,102a:線型特徵 101a,102a: Linear features
101LW,102LW,103LW:線寬 101LW, 102LW, 103LW: Line width
101p,102p,103p:節距 101p,102p,103p:Pitch
103,203,403:內連線區 103,203,403: Internal connection area
103a,203a,403a,503a,603a,907:內連線特徵 103a,203a,403a,503a,603a,907: Internal connection characteristics
104,204,904:絕緣區 104,204,904: Isolation Zone
105,205,405:通孔元件 105,205,405:Through-hole components
110,210,410:主體部 110,210,410: Main body
110w,111w:寬度 110w,111w:Width
111,211,411:連接部 111,211,411:Connection
112,212,412,512,612:凹部 112,212,412,512,612: concave part
201-1~201-n,401-1~401-n,501-1~501-n,906-1,906-2,906-3:線型特徵 201-1~201-n,401-1~401-n,501-1~501-n,906-1,906-2,906-3: Linear characteristics
203S1,203S2:側邊 203S1,203S2: Side
701:基板 701: Substrate
702:絕緣層 702: Insulation layer
703:未圖案化光阻層 703: Unpatterned photoresist layer
801:光罩 801: Photomask
802:光罩圖案 802: Mask pattern
803:光阻曝光區 803: Photoresist exposure area
804:光阻非曝光區 804: Photoresist non-exposure area
960:圖案化光阻層 960: Patterned photoresist layer
962:溝槽 962: Groove
961:線型光阻特徵 961: Linear photoresist characteristics
905:導電材料層 905: Conductive material layer
D1,D2:方向 D1,D2: Direction
E1:延伸線 E1: Extension line
L1,L2:凹部長度 L1, L2: concave length
LW1,LW2,LW3,LW4:線寬 LW1, LW2, LW3, LW4: Line width
P1,P2,P3,P4:節距 P1,P2,P3,P4: Pitch
VL1,VL2:通孔長度 VL1, VL2: through hole length
VW1,VW2:通孔寬度 VW1, VW2: through hole width
W1,W2,W3,W4:寬度 W1,W2,W3,W4:Width
第1圖係繪示根據本發明之第一實施例之佈線圖案的俯視示意圖;第1A圖係為沿著第1圖之延伸線E1繪示之佈線圖案的剖面示意圖;第2圖係繪示根據本發明之第二實施例之佈線圖案的俯視示意圖;第2A圖係為第2圖之圈選處之放大示意圖;第3圖係繪示根據本發明之第三實施例之佈線圖案的俯視示意圖;第4圖係繪示根據本發明之第四實施例之佈線圖案的俯視示意圖;第4A圖係為第4圖之圈選處之放大示意圖;第5圖係繪示根據本發明之第五實施例之佈線圖案的俯視示意圖;第6圖係繪示根據本發明之第六實施例之佈線圖案的俯視示意圖;及第7-12圖係繪示根據本發明一實施例之用以形成佈線圖案的方法。 FIG. 1 is a schematic top view of a wiring pattern according to a first embodiment of the present invention; FIG. 1A is a schematic cross-sectional view of a wiring pattern drawn along an extension line E1 of FIG. 1; FIG. 2 is a schematic top view of a wiring pattern according to a second embodiment of the present invention; FIG. 2A is an enlarged schematic view of a circled portion of FIG. 2; FIG. 3 is a schematic top view of a wiring pattern according to a third embodiment of the present invention; Figure 4 is a schematic top view of a wiring pattern according to the fourth embodiment of the present invention; Figure 4A is an enlarged schematic view of the circled portion of Figure 4; Figure 5 is a schematic top view of a wiring pattern according to the fifth embodiment of the present invention; Figure 6 is a schematic top view of a wiring pattern according to the sixth embodiment of the present invention; and Figures 7-12 are diagrams of a method for forming a wiring pattern according to an embodiment of the present invention.
以下係提出相關實施例,配合圖式以詳細說明本發明所提出之佈線圖案及其製造方法。然而,本發明並不以此為限。實施例中之敘述,例如細部結構、製造方法之步驟和材料應用等,僅為舉例說明之用,本發明欲保護之範圍並非僅限於所述態樣。相關技術領域者當可在不脫離本發明之精神和範圍之前提下,對實施例之結構和製造方法加以變化與修飾,以符合實際應用所需。因此,未於本發明提出的其他實施態樣也可能可以應用。再者,圖式係簡化以利清楚說明實施例之內容,圖式上的尺寸比例並非按照實際產品等比例繪製。因此,說明書和圖式僅作敘述實施例之用,而非用以限縮本發明保護範圍。相同或相似的元件符號用以代表相同或相似的元件。 The following is a related embodiment, which is accompanied by drawings to illustrate in detail the wiring pattern and the manufacturing method thereof proposed in the present invention. However, the present invention is not limited to this. The description in the embodiment, such as the detailed structure, the steps of the manufacturing method and the application of materials, is for illustrative purposes only, and the scope of protection of the present invention is not limited to the described aspects. Those skilled in the relevant technical field can change and modify the structure and manufacturing method of the embodiment without departing from the spirit and scope of the present invention to meet the needs of actual applications. Therefore, other embodiments not proposed in the present invention may also be applicable. Furthermore, the drawings are simplified to facilitate a clear explanation of the contents of the embodiments, and the size ratios in the drawings are not drawn in proportion to the actual product. Therefore, the description and drawings are only used to describe the embodiments and are not intended to limit the scope of protection of the present invention. The same or similar element symbols are used to represent the same or similar elements.
說明書與申請專利範圍中所使用的序數例如「第一」、「第二」、「第三」等用詞是為了修飾元件,其本身並不意含及代表該元件有任何之前的序數,也不代表某一元件與另一元件的順序、或是製造方法上的順序,該些序數的使用,僅是用來使具有某命名的一元件得以和另一具有相同命名的元件能作出清楚區分。 The ordinal numbers used in the specification and patent application, such as "first", "second", "third", etc., are used to modify the components. They do not imply or represent any previous ordinal number of the component, nor do they represent the order of one component and another component, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name.
本發明之多個實施例可應用於多種佈線圖案。例如,實施例可應用於,但不限於,形成於層間(inter-layer)介電層中或層間介電層上的導電線路。佈線圖案可例如形成於半導體結構中的第一金屬層(ML1)、第二金屬層(ML2)及/或第三金屬層(ML3)中。 Various embodiments of the present invention may be applied to various wiring patterns. For example, the embodiments may be applied to, but not limited to, conductive lines formed in or on an inter-layer dielectric layer. The wiring pattern may be formed, for example, in a first metal layer (ML1), a second metal layer (ML2), and/or a third metal layer (ML3) in a semiconductor structure.
請參照第1圖,第1圖係繪示根據本發明之第一實施例之佈線圖案10的俯視示意圖。佈線圖案10包含佈線區域101、佈線區域102與內連線區103。內連線區103可配置於佈線區域101與佈線區域102之間。
Please refer to FIG. 1, which is a top view schematic diagram of the
佈線區域101可包含複數個線型特徵101a。複數個線型特徵101a可沿著第一方向D1延伸。複數個線型特徵101a可彼此分散地配置。佈線區域102可包含複數個線型特徵102a。複數個線型特徵102a可沿著第一方向D1延伸。複數個線型特徵102a可彼此分散地配置。內連線區103可包含內連線特徵103a,內連線特徵103a可配置於線型特徵101a與線型特徵102a之間。內連線特徵103a包含凹部112。凹部112可例如是沿著第二方向D2凹陷的側向凹部,第一方向D1垂直於第二方向D2。在此實施例中,如第1圖所示,凹部112的開口沿第二方向D2朝向佈線區域102。但本發明不以此為限,凹部112的開口可沿第二方向D2朝向佈線區域101。
The
具體而言,內連線區103的內連線特徵103a可包含二主體部110與配置於二主體部110之間的連接部111。二主體部110可沿著第一方向D1彼此分離地配置。二主體部110可配置為在第二方向D2上互不重疊。連接部111可連接二主體部110。主體部110可具有沿著第二方向D2的寬度110w,連接部111可具有沿著第二方向D2的寬度111w,連接部111之寬度
111w可小於主體部110之寬度110w。內連線特徵103a的二主體部110與連接部111的寬度差異可界定出凹部112。
Specifically, the
線型特徵101a具有沿著第二方向D2的線寬101LW。複數個線型特徵101a中的二相鄰線型特徵101a之間具有沿著第二方向D2的節距101p。線型特徵102a具有沿著第二方向D2的線寬102LW。複數個線型特徵102a中的二相鄰線型特徵102a之間可具有沿著第二方向D2的節距102p。在一實施例中,每一線型特徵101a具有大致相同的線寬;每一線型特徵102a具有大致相同的線寬。在一實施例中,複數個線型特徵101a具有相同的節距;複數個線型特徵102a具有相同的節距。在一實施例中,線型特徵101a的線寬101LW可大致相等於線型特徵102a的線寬102LW。在一實施例中,線型特徵101a的節距101p可大致相等於線型特徵102a的節距102p。內連線特徵103a具有沿著第二方向D2的線寬103LW。內連線特徵103a的線寬103LW可相等於主體部110的寬度110w。內連線特徵103a與相鄰的線型特徵(例如是線型特徵102a)之間可具有沿著第二方向D2的節距103p。在一實施例中,內連線特徵103a的線寬103LW可大於線型特徵101a的線寬101LW和線型特徵102a的線寬102LW。在一實施例中,內連線特徵103a的節距103p可大於線型特徵101a的節距101p和線型特徵102a的節距102p。在一實施例中,節距101p與節距102p可等於或小於100奈米(nm)。線型特徵101a、線型特徵102a與內連線特徵103a可包
含導電材料,例如金屬。在一實施例中,線型特徵101a與線型特徵102a可為導線。
The
佈線圖案10還可包含絕緣區104。絕緣區104可配置於線型特徵101a、線型特徵102a與內連線特徵103a之間。絕緣區104可包含絕緣材料,例如氧化物。
The
請同時參照第1圖與第1A圖,第1A圖係為沿著第1圖之延伸線E1繪示之佈線圖案10的剖面示意圖。佈線圖案10還可包含配置於內連線區103的二通孔元件105。通孔元件105可分別配置於內連線區103的內連線特徵103a的連接部111的相對兩側。具體而言,如第1A圖所示,通孔元件105可分別配置於內連線區103的內連線特徵103a的主體部110,且可和內連線特徵103a位於不同層中。例如,通孔元件105可位於內連線特徵103a上方的層中且直接接觸主體部110。通孔元件105可包含導電材料,例如金屬。在一實施例中,通孔元件105可用以提供層間電性連接。本發明之佈線圖案之內連線區可包含多於一個的內連線特徵及/或不同態樣的內連線特徵,以下將以第二實施例至第六實施例示例性說明。
Please refer to FIG. 1 and FIG. 1A simultaneously. FIG. 1A is a schematic cross-sectional view of the
請同時參照第2圖與第2A圖,第2圖係繪示根據本發明之第二實施例之佈線圖案20的俯視示意圖,第2A圖係為第2圖之圈選處之放大示意圖。佈線圖案20可包含沿著第一方向D1延伸的複數個線型特徵201-1、201-2、201-3、201-4、201-5、201-6、201-7、201-8、...、201-n、以及配置於複數個線型特徵
201-1~201-n之間的內連線區203。複數個線型特徵201-1~201-n可例如彼此大致平行地配置。佈線圖案20中的內連線區203以外的區域可理解為一或多個佈線區域。
Please refer to FIG. 2 and FIG. 2A at the same time. FIG. 2 is a schematic top view of the
內連線區203可包含至少一配置於任意二線型特徵之間的內連線特徵203a,例如配置於線型特徵201-3與線型特徵201-6之間,或配置於線型特徵201-6與線型特徵201-9之間。以下將以配置於線型特徵201-3與線型特徵201-6之間的內連線特徵203a為例說明,其他內連線特徵203a可以此類推。
The
內連線特徵203a包含凹部212。凹部212可例如是沿著第二方向D2凹陷的側向凹部。如第2A圖所示,凹部212可沿著第二方向D2從內連線特徵203a的第一側邊203S1朝向第二側邊203S2凹陷,第一側邊203S1相對於第二側邊203S2。具體而言,內連線區203的內連線特徵203a可包含二主體部210與配置於二主體部210之間的連接部211。二主體部210可沿著第一方向D1彼此分離地配置。二主體部210可配置為在第二方向D2上互不重疊。連接部211可連接二主體部210。主體部210在第二方向D2上的寬度W1可大於連接部211在第二方向D2上的寬度W2。內連線特徵203a的二主體部210與連接部211的寬度差異可界定出凹部212。在一實施例中,凹部212的底部和第二側邊203S2之間在第二方向D2的距離可等於連接部211在第二方向D2上的寬度W2。線型特徵201-1~201-n與內連線
特徵203a可包含導電材料,例如金屬。在一實施例中,線型特徵201-1~201-n可為導線。
The
佈線圖案20可包含配置於內連線區203的二通孔元件205。二通孔元件205可分別配置於內連線區203的內連線特徵203a的二主體部210,且位於內連線區203的內連線特徵203a的連接部211的相對兩側。二通孔元件205可分別配置於凹部212的相對兩側。通孔元件205可和內連線特徵203a位於不同層中。例如,通孔元件205可位於內連線特徵203a上方的層中且直接接觸主體部210。通孔元件205可包含導電材料,例如金屬。在一實施例中,通孔元件205可用以提供層間電性連接。
The
如第2A圖所示,線型特徵201-3具有沿著第二方向D2的線寬LW1。複數個線型特徵201-1~201-n中的二相鄰線型特徵之間(例如線型特徵201-2與線型特徵201-3之間)具有沿著第二方向D2的節距P1。在一實施例中,複數個線型特徵201-1~201-n中的每一者具有大致相同的線寬,複數個線型特徵201-1~201-n中的二相鄰線型特徵之間的節距大致相等。內連線特徵203a具有沿著第二方向D2的線寬LW2。內連線特徵203a的線寬LW2可相等於主體部210的寬度W1。內連線特徵203a與相鄰的線型特徵(例如是線型特徵201-3)之間可具有沿著第二方向D2的節距P2。在一實施例中,內連線特徵203a的線寬LW2可大於線型特徵201-3的線寬LW1。在一實施例中,節距P2可大於節距P1。連接部211的寬度W2可大於或等於線型特
徵201-3的線寬LW1。在一實施例中,線型特徵201-3的線寬LW1可等於或小於50奈米。節距P1可等於或小於100奈米。在一實施例中,內連線特徵203a的線寬LW2可等於或小於150奈米,但本發明不以此為限。
As shown in FIG. 2A , the linear feature 201-3 has a line width LW1 along the second direction D2. Two adjacent linear features among the plurality of linear features 201-1 to 201-n (e.g., between the linear feature 201-2 and the linear feature 201-3) have a pitch P1 along the second direction D2. In one embodiment, each of the plurality of linear features 201-1 to 201-n has substantially the same line width, and the pitches between two adjacent linear features among the plurality of linear features 201-1 to 201-n are substantially equal. The
內連線特徵203a之凹部212具有沿著第一方向D1的凹部長度L1,凹部長度L1可例如介於線型特徵201-3的線寬LW1的2倍至4倍之間。
The
通孔元件205具有沿著第一方向D1的通孔長度VL1,通孔長度VL1可例如介於線型特徵201-3的線寬LW1的2倍至3倍之間。通孔元件205具有沿著第二方向D2的通孔寬度VW1,通孔寬度VW1可例如介於線型特徵201-3的線寬LW1的1倍至2倍之間。在一實施例中,通孔元件205之通孔寬度VW1可約為線型特徵201-3的線寬LW1的1.5倍。
The through-
佈線圖案20還可包含絕緣區204。絕緣區204可配置於線型特徵201-1~201-n與內連線特徵203a之間。絕緣區204可包含絕緣材料,例如氧化物。
The
在一實施例中,佈線圖案中20可包含凹部開口朝向不同方向的多個內連線特徵。舉例來說,第2圖中,介於線型特徵201-3與線型特徵201-6之間的內連線特徵203a的凹部212開口朝向正的第二方向D2(或朝向圖的右側),介於線型特徵201-6與線型特徵201-9之間的內連線特徵203a的凹部開口朝向負的第二方向D2(或朝向圖的左側)。本發明之佈線圖案可包含
任意數量的凹部開口朝向不同方向的多個內連線特徵或凹部開口朝向相同方向的多個內連線特徵。例如,在第3圖所示中,佈線圖案30的內連線區203可包含多個內連線特徵203a,多個內連線特徵203a的凹部212的開口朝向相同方向。
In one embodiment, the
請同時參照第4圖與第4A圖,第4圖係繪示根據本發明之第四實施例之佈線圖案40的俯視示意圖,第4A圖係為第4圖之圈選處之放大示意圖。佈線圖案40和佈線圖案20的差異在於,佈線圖案40的內連線區403的每一內連線特徵403a所包含的凹部數量可多於佈線圖案20的內連線區203的每一內連線特徵203a所包含的凹部數量,且佈線圖案40中配置於每一內連線特徵403a的通孔元件405的數量可多於佈線圖案20中配置於每一內連線特徵203a的通孔元件205的數量。
Please refer to FIG. 4 and FIG. 4A at the same time. FIG. 4 is a schematic top view of the
佈線圖案40可包含沿著第一方向D1延伸的複數個線型特徵401-1、401-2、401-3、...、401-n、以及配置於複數個線型特徵401-1~401-n之間的內連線區403。複數個線型特徵401-1~401-n可例如彼此大致平行地配置。在一實施例中,線型特徵401-1~401-n可例如是導線,內連線區403以外的區域可理解為一或多個佈線區域。佈線圖案40之線型特徵401-1~401-n可相似於佈線圖案20的線型特徵201-1~201-n。
The
內連線區403可包含至少一配置於任意二線型特徵之間的內連線特徵403a,例如配置於線型特徵401-2與線型特徵401-5之間,或配置於線型特徵401-5與線型特徵401-8之間。
以下將以配置於線型特徵401-2與線型特徵401-5之間的內連線特徵403a為例說明,其他內連線特徵403a可以此類推。內連線特徵403a包含二凹部412。凹部412可例如是沿著第二方向D2凹陷的側向凹部。二凹部412可彼此分散地配置。二凹部412可在第二方向D2上不重疊。在此實施例中,內連線特徵403a的二凹部412的開口朝向相同方向。內連線區403的內連線特徵403a可包含三主體部410與配置於三主體部410之間的二連接部411。三主體部410可沿著第一方向D1彼此分離地配置。三主體部410可配置為在第二方向D2上互不重疊。連接部411可連接相鄰的二主體部410。如第4A圖所示,主體部410在第二方向D2上的寬度W3可大於連接部411在第二方向D2上的寬度W4。主體部410與連接部411的寬度差異可界定出凹部412。線型特徵401-1~401-n與內連線特徵403a可包含導電材料,例如金屬。在一實施例中,線型特徵401-1~401-n可為導線。
The
佈線圖案40可包含配置於內連線區403的三通孔元件405。三通孔元件405可分別配置於內連線區403的內連線特徵403a的三主體部410,且位於內連線區403的內連線特徵403a的連接部411的相對兩側。三通孔元件405與內連線特徵403a的二凹部412可沿著第一方向D1交錯配置。通孔元件405可和內連線特徵403a位於不同層中。例如,通孔元件405可位於內連線特徵403a上方的層中且直接接觸主體部410。通孔元件
405可包含導電材料,例如金屬。在一實施例中,通孔元件405可用以提供層間電性連接。
The
如第4A圖所示,線型特徵401-2具有沿著第二方向D2的線寬LW3。複數個線型特徵401-1~401-n中的二相鄰線型特徵之間(例如線型特徵401-1與線型特徵401-2之間)具有沿著第二方向D2的節距P3。在一實施例中,複數個線型特徵401-1~401-n中的每一者具有大致相同的線寬,複數個線型特徵401-1~401-n中的二相鄰線型特徵之間的節距大致相等。內連線特徵403a具有沿著第二方向D2的線寬LW4。內連線特徵403a的線寬LW4可相等於主體部410的寬度W3。內連線特徵403a與相鄰的線型特徵(例如是線型特徵401-2)之間可具有沿著第二方向D2的節距P4。在一實施例中,內連線特徵403a的線寬LW4可大於線型特徵401-2的線寬LW3。在一實施例中,節距P4可大於節距P3。連接部411的寬度W4可大於或等於線型特徵401-2的線寬LW3。在一實施例中,線型特徵401-2的線寬LW3可等於或小於50奈米。節距P3可等於或小於100奈米。在一實施例中,內連線特徵403a的線寬LW4可等於或小於150奈米,但本發明不以此為限。
As shown in FIG. 4A , the linear feature 401-2 has a line width LW3 along the second direction D2. Two adjacent linear features among the plurality of linear features 401-1 to 401-n (e.g., between the linear feature 401-1 and the linear feature 401-2) have a pitch P3 along the second direction D2. In one embodiment, each of the plurality of linear features 401-1 to 401-n has substantially the same line width, and the pitches between two adjacent linear features among the plurality of linear features 401-1 to 401-n are substantially equal. The
內連線特徵403a的凹部412具有沿著第一方向D1的凹部長度L2,凹部長度L2可例如介於線型特徵401-2的線寬LW3的2倍至4倍之間。內連線特徵403a的二凹部412的尺寸可彼此相同或不同。
The
通孔元件405具有沿著第一方向D1的通孔長度VL2,通孔長度VL2可介於線型特徵401-2的線寬LW3的2倍至3倍之間。通孔元件405具有沿著第二方向D2的通孔寬度VW2,通孔寬度VW2可介於線型特徵401-2的線寬LW3的1倍至2倍之間。在一實施例中,通孔元件405之通孔寬度VW2可約為線型特徵401-2的線寬LW3的1.5倍。
The through-
請參照第5圖,第5圖係繪示根據本發明之第五實施例之佈線圖案50的俯視示意圖。佈線圖案50和佈線圖案40的差異在於,佈線圖案40的單一內連線特徵403a之二凹部412的開口朝向同一側,而佈線圖案50的單一內連線特徵503a之二凹部512的開口朝向相異側。
Please refer to FIG. 5, which is a schematic top view of a
佈線圖案50包含複數個線型特徵501-1~501-n、以及配置於複數個線型特徵501-1~501-n之間的內連線區。佈線圖案50之複數個線型特徵501-1~501-n可相似於佈線圖案20的線型特徵201-1~201-n及/或佈線圖案40的線型特徵401-1~401-n。內連線區可包含至少一配置於任意二線型特徵之間的內連線特徵503a。內連線特徵503a包含二凹部512,二凹部512的開口朝向不同方向。凹部512可例如是沿著第二方向D2凹陷的側向凹部。二凹部512可彼此分散地配置。二凹部512可在第二方向D2上不重疊。
The
在一實施例中,第4圖所示之佈線圖案40所包含的內連線特徵403a與第5圖所示之佈線圖案50所包含的內連線
特徵503a可併用於一佈線圖案中,如第6圖所示。第6圖係繪示根據本發明之第六實施例之佈線圖案60的俯視示意圖,在此實施例中,佈線圖案60同時包含內連線特徵403a(其凹部的開口朝向同一側)與內連線特徵503a(其凹部的開口朝向相異側)。佈線圖案60還可包含內連線特徵603a。內連線特徵603a和內連線特徵403a的差異在於,內連線特徵403a的二凹部開口皆朝向正的第二方向D2(或朝向圖的右側),而內連線特徵603a的二凹部612開口皆朝向負的第二方向D2(或朝向圖的左側)。本發明之佈線圖案的內連線區可包含多個內連線特徵彼此分散地配置於複數個線型特徵之間,且可包含上述不同類型的內連線特徵(例如內連線特徵103a、203a、403a、503a、603a)之任意組合。
In one embodiment, the
第7-12圖係繪示根據本發明一實施例之用以形成佈線圖案的方法。 Figures 7-12 illustrate a method for forming a wiring pattern according to an embodiment of the present invention.
請參照第7圖。在基板701上形成絕緣層702與未圖案化光阻層703。
Please refer to Figure 7. An insulating
請參照第8-9圖。使用光罩801對未圖案化光阻層703進行曝光處理,以形成可對應於光罩圖案802的光阻曝光區803與光阻非曝光區804。在經過適當的烘烤步驟後,使用顯影液處理光阻曝光區803與光阻非曝光區804,再經過清洗、旋乾等步驟以移除光阻曝光區803,從而定義出複數個線型光阻特徵961(例如對應於光阻非曝光區804)與複數個溝槽962(例如對應於光阻曝光區803),形成圖案化光阻層960。
Please refer to Figures 8-9. The
接著,透過圖案化光阻層960中的溝槽962對絕緣層702進行蝕刻處理以移除部分的絕緣層702,並移除絕緣層702上的圖案化光阻層960(例如透過乾式光阻去除製程(photoresist dry stripping)或溼式光阻去除製程(photoresist wet stripping)),形成如第10圖所示之絕緣區904。請參照第11圖,對第10圖所示的結構進行沉積處理,以在絕緣區904上形成導電材料層905。在一實施例中,導電材料層905可包含銅。接著,對第11圖所示的結構進行化學機械研磨(chemical-mechanical planarization;CMP)處理,移除部分的導電材料層905後,形成線型特徵906-1、906-2、906-3與內連線特徵907,如第12圖所示。
Next, the insulating
在一實施例中,透過施行上述第7-12圖之方法,可形成如第1-6圖所示之佈線圖案。圖案化光阻層中的線型光阻特徵的位置可對應於佈線圖案之絕緣區的位置。圖案化光阻層中的溝槽的位置可對應於佈線圖案之線型特徵與內連線特徵的位置。圖案化光阻層中的線型光阻特徵可包含光阻凸部,光阻凸部可形狀互補於佈線圖案之內連線特徵之凹部。 In one embodiment, by implementing the method of Figures 7-12 above, a wiring pattern as shown in Figures 1-6 can be formed. The position of the linear photoresist feature in the patterned photoresist layer can correspond to the position of the insulating region of the wiring pattern. The position of the groove in the patterned photoresist layer can correspond to the position of the linear feature and the internal connection feature of the wiring pattern. The linear photoresist feature in the patterned photoresist layer can include a photoresist convex portion, and the photoresist convex portion can complement the shape of the concave portion of the internal connection feature of the wiring pattern.
佈線圖案通常包含具有密集排列的線型特徵或導線之佈線區域、以及具有內連線特徵的內連線區以配置多種半導體元件,半導體元件例如是通孔元件。內連線區中的內連線特徵的線寬通常會大於佈線區域中的線型特徵的線寬以便於配置半導體元件。然而,此種線寬不一致的配置可能會在光阻顯影的清洗 及旋乾的過程中,因光阻圖案受力不平均,而發生光阻圖案倒塌問題,進而影響電性的良率與可靠度。 The wiring pattern usually includes a wiring area with densely arranged linear features or wires, and an internal connection area with internal connection features to configure various semiconductor components, such as through-hole components. The line width of the internal connection features in the internal connection area is usually larger than the line width of the linear features in the wiring area to facilitate the configuration of semiconductor components. However, such inconsistent line width configuration may cause the photoresist pattern to collapse during the cleaning and spin-drying process of the photoresist development due to uneven force on the photoresist pattern, thereby affecting the electrical yield and reliability.
在本發明之佈線圖案中,內連線區中的內連線特徵包含凹部,其可改善受力不平均而導致的圖案倒塌問題。此外,在形成本發明之包含凹部的內連線特徵的過程中,用以形成佈線圖案之線型光阻特徵包含形狀互補於內連線特徵之凹部的光阻凸部,此種配置可進一步避免線型光阻特徵因兩側受力不平均(例如線型光阻特徵兩側的清洗液在旋乾的動態過程中,兩側液面高度不一致,而導致的光阻兩側受力不平均)而倒塌,並可避免圖案倒塌造成的佈線圖案不良之問題。因此,本發明可有效減少圖案倒塌問題,並可提升製程裕度、產品可靠度與良率。本發明之凹部之尺寸可以在不影響通孔元件的安裝空間的情況下解決圖案倒塌問題,亦適用於密集圖案中,特別適用於節距等於或小於100奈米之精細圖案。 In the wiring pattern of the present invention, the interconnect feature in the interconnect area includes a concave portion, which can improve the pattern collapse problem caused by uneven force. In addition, in the process of forming the interconnect feature including the concave portion of the present invention, the linear photoresist feature used to form the wiring pattern includes a photoresist convex portion whose shape complements the concave portion of the internal connection feature. This configuration can further prevent the linear photoresist feature from collapsing due to uneven force on both sides (for example, the cleaning liquid on both sides of the linear photoresist feature has inconsistent liquid level heights on both sides during the dynamic process of spinning, resulting in uneven force on both sides of the photoresist), and can avoid the problem of defective wiring pattern caused by pattern collapse. Therefore, the present invention can effectively reduce the pattern collapse problem, and can improve process margin, product reliability and yield. The size of the recess of the present invention can solve the pattern collapse problem without affecting the installation space of through-hole components. It is also applicable to dense patterns, especially fine patterns with a pitch equal to or less than 100 nanometers.
綜上所述,雖然本發明已以實施例揭露如上,然而其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍前提下,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In summary, although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Those with common knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of the patent application attached hereto.
10:佈線圖案 10: Wiring pattern
101,102:佈線區域 101,102: Wiring area
101a,102a:線型特徵 101a,102a: Linear features
101LW,102LW,103LW:線寬 101LW, 102LW, 103LW: Line width
101p,102p,103p:節距 101p,102p,103p:Pitch
103:內連線區 103: Internal connection area
103a:內連線特徵 103a: Internal connection characteristics
104:絕緣區 104: Isolation Zone
105:通孔元件 105:Through-hole components
110:主體部 110: Main body
110w,111w:寬度 110w,111w:Width
111:連接部 111: Connection part
112:凹部 112: Concave part
D1,D2:方向 D1,D2: Direction
E1:延伸線 E1: Extension line
Claims (9)
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| TW202338658A TW202338658A (en) | 2023-10-01 |
| TWI848274B true TWI848274B (en) | 2024-07-11 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6412097B1 (en) * | 1999-02-02 | 2002-06-25 | Nec Corporation | Compacting method of circuit layout by moving components using margins and bundle widths in compliance with the design rule, a device using the method and a computer product enabling processor to perform the method |
| CN1630068A (en) * | 2003-12-16 | 2005-06-22 | 日东电工株式会社 | Wiring circuit board |
| TW200636907A (en) * | 2005-01-31 | 2006-10-16 | Renesas Tech Corp | Semiconductor device and manufacturing method thereof, and semiconductor integrated circuit |
| US20150110383A1 (en) * | 2013-10-21 | 2015-04-23 | Samsung Electronics Co., Ltd. | Methods of inspecting a semiconductor device and semiconductor inspection systems |
| TW201806107A (en) * | 2016-05-27 | 2018-02-16 | 英特爾股份有限公司 | Inlay embedding and tab patterning of photolithography barrels for back-end process (BEOL) spacer-based interconnects |
| TW201913836A (en) * | 2017-08-25 | 2019-04-01 | 台灣積體電路製造股份有限公司 | Method for fabricating integrated circuit |
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- 2022-03-17 TW TW111109798A patent/TWI848274B/en active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6412097B1 (en) * | 1999-02-02 | 2002-06-25 | Nec Corporation | Compacting method of circuit layout by moving components using margins and bundle widths in compliance with the design rule, a device using the method and a computer product enabling processor to perform the method |
| CN1630068A (en) * | 2003-12-16 | 2005-06-22 | 日东电工株式会社 | Wiring circuit board |
| TW200636907A (en) * | 2005-01-31 | 2006-10-16 | Renesas Tech Corp | Semiconductor device and manufacturing method thereof, and semiconductor integrated circuit |
| US20150110383A1 (en) * | 2013-10-21 | 2015-04-23 | Samsung Electronics Co., Ltd. | Methods of inspecting a semiconductor device and semiconductor inspection systems |
| TW201806107A (en) * | 2016-05-27 | 2018-02-16 | 英特爾股份有限公司 | Inlay embedding and tab patterning of photolithography barrels for back-end process (BEOL) spacer-based interconnects |
| TW201913836A (en) * | 2017-08-25 | 2019-04-01 | 台灣積體電路製造股份有限公司 | Method for fabricating integrated circuit |
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| TW202338658A (en) | 2023-10-01 |
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