TWI846207B - Probe assembly, system and method for testing rf device of phased array antenna - Google Patents

Abstract

A method for testing radio-frequency (RF) device, including: receiving a first RF device having a signal port for transmitting RF signals; arranging a first probe needle of a probe assembly to couple to the signal port; arranging a testing tool to couple to the probe assembly for testing the first RF device through the probe assembly; and arranging a first resistive element to couple to the first probe needle in parallel connection to make a first input impedance looking into the probe assembly from the testing tool substantially equal to a second input impedance looking into the testing tool from the probe assembly.

Description

Probe assembly, system and method for testing phased array antenna RF components

This case is about a probe assembly and a test system and method, in particular, about a probe assembly, system and method capable of testing phase array antennas.

In modern wireless communication technology, satellite communication has received widespread attention due to its advantages such as better signal coverage and high bandwidth compared to traditional terrestrial communication technology. It seems promising to integrate satellite communication into the common cellular terrestrial communication to enhance the coverage and bandwidth of wireless communication networks. In addition, phase array antenna technology is usually used in conjunction with satellite communication to improve power efficiency for longer transmission distances. However, the phase delay of each antenna element in the antenna array needs to be well controlled to achieve small delay and high accuracy, so the cost of phase array antennas is still high. Therefore, the commercialization of products based on satellite communication is not satisfactory. Therefore, it is necessary to develop a new phase array antenna and its testing method, and improve the phase control design to reduce its manufacturing cost.

The present invention provides a method for testing an RF component, including: receiving a first RF component having a signal port for transmitting an RF signal; connecting a first probe of a probe assembly to the signal port; connecting a test machine to the probe assembly to test the first RF component through the probe assembly; and connecting a first resistor element to the first probe in parallel so that a first input impedance from the test machine to the probe assembly is substantially equal to a second input impedance from the probe assembly to the test machine.

The present invention provides a probe assembly for testing a radio frequency component, the probe assembly comprising: a first probe for contacting a signal port of the radio frequency component; a first connection port for electrically connecting to a second connection port of a test machine for testing the radio frequency component via the probe assembly; and a first resistor element configured to be connected in parallel with the first probe so that a first input impedance viewed from the first connection port is substantially equal to a second input impedance viewed from the second connection port.

The present invention provides a test system, including: a radio frequency component including a signal port; a probe assembly including a probe that can be connected to the signal port; a test machine having a first connection port that can be connected to a second connection port of the probe assembly, the test machine being used to test the radio frequency component through the probe assembly; and a resistor element that is configured to be connected to the probe in parallel so that a first input impedance looking toward the first connection port is substantially equal to a second input impedance looking toward the second connection port.

By setting up the proposed phase array antenna test probe assembly, test system and test method, the test task of the phase array antenna RF chip can be managed more easily and accurately, and the manufacturing cost of the RF transmitter and receiver can be lowered, the operating power can be lowered, and the reliability of the components can be improved.

The above description has been a fairly broad overview of the technical features and advantages of the embodiments of the present invention, so that the detailed implementation of the present invention described below can be more easily understood. Other technical features and advantages of the subject matter of the patent application scope of the present invention will be described below. Those with ordinary knowledge in the technical field to which the present invention belongs should understand that, using the concepts and specific embodiments disclosed below, it is quite easy to modify or design other structures or methods to achieve the same purpose as the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs should also understand that such a conception of achieving similar effects still does not deviate from the spirit and scope of the present invention as defined by the patent application scope described herein.

10: Wireless communication system

12, 14, 16, 18: User equipment

22: Ground base station

24: Non-ground base station

100: Transmitter

101:Receiver

200A: Antenna components

202: Substrate

204: Interconnection structure

206: Radiation component/antenna patch

208, 209: Radio frequency (RF) chip

208A: Signal port/input port

2081, 2091: Radio frequency (RF) components

209A: Signal port/output port

210: Conductive pad

211:Signal channel

212, 213: Antenna feed

220: Transmission line

221: Branch transmission line

222A, 222B, 222C: first conductor/conductive pad

224A, 224B: Conductive vias

226A, 226B, 226C: Insulation materials

300: Transmitter array

301:Receiver array

302: External power supply

304: Control unit

306, 307: Processing unit

308, 309: Radio frequency (RF) chip

308A: Signal port/input port

3081, 3091: Radio frequency (RF) components

309A: Signal port/output port

310: Transmitter block

311: Receiver block

342, 346: Power distributor network

344: Power distributor

352, 356: Power combiner network

372: Resistor element

502, 522: Testing machine

504: Probe assembly

505: Signal port/connection port

506: Transmission line

510, 710: Substrate

512: Line area

514, 515, 516, 517, 714: Resistor elements

520: Cutting tools

525: Signal port/connection port

531, 532: Resistor element

600:Methods

602: Steps

604: Steps

606: Steps

608: Steps

910, 920, 930: Probe assembly

1010, 1020: Probe assembly

1110, 1120: Probe assembly

1210, 1220: Probe assembly

1302: Subject

1304: Protrusion

1306:Probe

1308:Probe

1310: Probe assembly

A1: Active components

C, Cp, Cp1: Capacitance

CLK: data clock signal

D1, D2...DL: Location

D11, D12, D21, D22: diodes

Din, Dout: calibration data

G1, G2, G3: probe ground terminal

I _out : Current

IP, IP1, IP2: Input

OP: Output

L: Inductance

L1, L2, L3: Boundary lines

M1, M2: transistors

M1D, M2D: Drain

M1G, M2G: Gate

M1S, M2S: Source

RF_in: radio frequency (RF) input signal

RF_out: radio frequency (RF) output signal

RF_out_I: In-phase component of RF signal

RF_out_Q: RF signal quadrature component

Rp: input impedance

S, S1, S2: probe signal end

SYNC: Synchronous clock signal

TP: Test port

VD: Power supply voltage

V _T : Ideal voltage source

Z _T : Input impedance/resistance

Various aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG1 shows a schematic diagram of a wireless communication system for next generation communication scenarios according to some embodiments of the present application.

FIG2A is a schematic three-dimensional diagram of an antenna array of a transmitter or receiver of a user device in some embodiments of the present application.

FIG2B is a schematic cross-sectional view of the transmitter or receiver of FIG2A according to some embodiments of the present application.

FIG3A is a schematic block diagram of a transmitter according to some embodiments.

FIG. 3B is a schematic block diagram showing a transmitter array of the transmitter shown in FIG. 3A according to some embodiments of the present application.

FIG. 3C is a schematic block diagram showing a transmitter block of the transmitter array shown in FIG. 3B according to some embodiments of the present application.

FIG. 3D is a schematic block diagram showing the RF chip shown in FIG. 3C according to some embodiments of the present application.

FIG4A is a schematic block diagram of a receiver according to some embodiments of the present application.

FIG. 4B is a schematic block diagram showing a receiver array of the receiver shown in FIG. 4A according to some embodiments of the present application.

FIG. 4C is a schematic block diagram showing a receiver block of the receiver array shown in FIG. 3 according to some embodiments of the present application.

FIG. 4D is a schematic block diagram showing the RF chip shown in FIG. 4C according to some embodiments of the present application.

Figures 5A to 5D are schematic block diagrams showing the intermediate stages of a method for manufacturing a phase array antenna according to some embodiments of the present application.

FIG6 is a schematic diagram showing the manufacturing method flow of the phase array antenna shown in FIG5A-5D according to some embodiments of the present application.

Figures 7A to 7F are schematic block diagrams showing the intermediate stages of the manufacturing method of the antenna array according to some embodiments of the present application.

Figures 8A and 8B are schematic block diagrams showing different circuit environments seen by the RF chip when the RF chip is respectively set in a substrate or in an antenna element according to some embodiments of the present application.

FIG9 is a schematic block diagram showing a probe assembly according to some embodiments of the present application.

FIG10 is a schematic block diagram showing a probe assembly according to some embodiments of the present application.

FIG11 is a schematic block diagram showing a probe assembly according to some embodiments of the present application.

FIG12 is a schematic block diagram showing a probe assembly according to some embodiments of the present application.

FIG13 is a schematic block diagram showing a probe assembly according to some embodiments of the present application.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present case. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the two features, so that the first and second features may not be in direct contact. In addition, the present case may repeatedly refer to numbers and/or letters in various examples. This repetition is for the purpose of simplicity and clarity, and is not itself intended to describe the relationship between the various embodiments and/or configurations discussed.

Additionally, for ease of description, spatially relative terms such as "below," "below," "below," "above," and "above" may be used herein to describe one element or feature relative to another element or feature as shown in the figure. Spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figure. The element may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

Although the numerical ranges and parameters describing the broad scope of the present invention are approximate, the numerical values described in the specific embodiments are reported as accurately as possible. However, any numerical value inherently contains certain errors, which must be caused by the deviations normally found in the corresponding test measurements. In addition, as used herein, the terms "approximately", "substantially" or "substantially" generally refer to within 10%, 5%, 1% or 0.5% of a given value or range. Alternatively, when considered by a person of ordinary skill in the art, the terms "approximately", "substantially" or "substantially" mean within an acceptable standard error of the mean. Except in operational/operational examples, or unless otherwise expressly specified, all numerical ranges, amounts, values and percentages, such as material amounts, durations, temperatures, operating conditions, quantitative ratios, etc., disclosed herein should be understood to be modified in all cases by the terms "approximately", "substantially" or "substantially". Therefore, unless otherwise indicated, the numerical parameters set forth in the present case and the appended patent claims are approximate values that can be varied as necessary. At a minimum, each numerical parameter should at least be interpreted in terms of the number of reported significant digits and by applying ordinary rounding techniques. Ranges may be expressed herein as from one endpoint to another or between two endpoints. Unless otherwise indicated, all ranges disclosed herein include the endpoints.

As used herein, the term "connected" may be interpreted as "electrically connected", and the term "coupled" may also be interpreted as "electrically coupled". "Connected" and "coupled" may also be used to indicate that two or more elements cooperate or interact with each other.

FIG1 shows a schematic diagram of a wireless communication system 10 in a next generation communication scenario according to some embodiments of the present invention. The wireless communication system 10 includes one or more user devices 12, 14, 16, and 18, a ground base station 22, and a non-ground base station 24. In some embodiments, the user devices 12, 14 are carried and moved by a person and are referred to as handheld devices. In some embodiments, the user device 16 is a mobile device equipped in a vehicle moving on the ground, such as a car, a train, etc. In some embodiments, the user device 18 is a user device equipped in a ship moving in the sea, a river, etc.

In some embodiments, the ground base station 22 is an example of a base station deployed in a communication network such as a cellular communication network. The ground base station 22 is used to provide a communication network to the user equipment 12, 14, and 16, wherein the user equipment 12, 14, and 16 can transmit or receive information to each other through the network established by multiple ground base stations 22. The ground base station 22 can also be referred to as a low-altitude platform. In some embodiments, the non-ground base station 24 is an example of a communication satellite deployed in a communication satellite network. The non-ground base station 24 is configured to provide a communication network to the user equipment 12, 14, 16, and 18, wherein the user equipment 12, 14, 16, and 18 can transmit or receive information to each other through the satellite network. Multiple ground base stations 22 and multiple non-ground base stations 24 can be interconnected to form a unified communication network, realizing a global communication network that covers user equipment around the world, whose users can be located at low altitudes, high altitudes, or anywhere that is not covered by the network of ground base stations 22.

In order to realize the goal of a global communication network, such as the wireless communication system 10, the user equipment 12, 14, 16 or 18 may need to be redesigned to include a transmitter or receiver with greater communication capabilities to communicate with the non-ground base station 24 located at high altitude. Among various transmitter or receiver designs, phase array antenna technology is a promising solution for implementing beamforming technology, which can significantly improve the gain of the transmitter or receiver, have higher reliability, and is suitable for satellite communications.

FIG. 2A is a schematic perspective view of an antenna array of a transmitter 100 or a receiver 101 of a user device 12, 14, 16, or 18 according to some embodiments of the present application. In some embodiments, the transmitter 100 is a radio frequency (RF) transmitter or receiver. In some embodiments, the transmitter 100 or the receiver 101 is a transmitter or receiver of a ground base station 22 or a non-ground base station 24. In some embodiments, although not shown separately, the transmitter 100 or the receiver 101 includes a control circuit board configured to generate and control RF signals to be transmitted by the transmitter 100, or configured to receive and control RF signals to be received by the receiver 101. In some embodiments, each user device 12, 14, 16, 18, ground base station 22, and non-ground base station 24 includes a transmitter 100 and a receiver 101, which have different operating frequencies, for example, operating at about 28 GHz and 18 GHz, respectively.

2A , the transmitter 100 or the receiver 101 includes an antenna array formed by a plurality of antenna elements 200A, wherein antenna components, such as a radiating element 206, are formed on a substrate 202 of an RF circuit board of the transmitter 100 or the receiver 101. In some embodiments, each antenna device 200A includes a substrate 202 and an interconnection structure 204 disposed below the substrate 202. The interconnection structure 204 has a lower surface, and the substrate 202 has an upper surface. In some embodiments, the plurality of antenna devices 200A share a common substrate 202 and a physically connected interconnection structure 204, as shown in FIG. 2A . In some embodiments, the array of radiating elements 206 is formed on the upper surface of the substrate 202, and a plurality of RF chips 208 are disposed on the lower surface of the interconnection structure 204. The RF chip 208 can be interconnected through a plurality of wires (not shown separately) on the lower surface of the interconnect structure 204. In some embodiments, the wires can be encapsulated by an electrically insulating material or exposed through the surface of the interconnect structure 204. In some embodiments, the antenna device 200A of each wire transmitter 100 or receiver 101 includes a patch antenna structure, and each radiating element 206 includes a patch structure of the antenna device 200A, such as a circular, elliptical or oval shape, and is referred to as an antenna patch 206 corresponding to the antenna device 200A.

FIG. 2B is a schematic cross-sectional view of an antenna device 200A of the transmitter 100 or the receiver 101 of FIG. 2A according to some embodiments of the present application. The cross-sectional view is taken along the section line AA of FIG. 2A. As shown in FIG. 2B, the substrate 202 is formed of a transparent material such as glass, fused silicon, silicon oxide, quartz, etc. In some embodiments, the substrate 202 separates the antenna patch 206 from the electronic circuit of the interconnect structure 204 or the RF chip 208. In some embodiments, the RF signal is transmitted through the RF chip 208 formed on the lower side of the substrate 202, through the RF circuit formed in the interconnect structure 204, and then transmitted through the signal channel 211 in the transparent substrate 202, and coupled to the antenna patch 206 formed on the upper side of the substrate 202. In some embodiments, the antenna patch 206 includes additional patches on the circular or elliptical circumference of the antenna patch 206 to produce a better field distribution of the output RF signal. In some embodiments, the antenna patch 206 can be modified to include a truncated portion or a semicircle on the circular or elliptical circumference of the antenna patch 206 to provide a better field distribution of the output RF signal. The signal channel 211 can be formed by the transparent material of the substrate 202. In some embodiments, the thickness of the substrate 202 is determined according to the operating frequency of the RF signal of the antenna device 200A. In some embodiments, where the material of substrate 202 is transparent to RF signals, substrate 202 may not require any conductive components within the projection area of antenna patch 206, but still allow interconnect structure 204 to be electromagnetically coupled to antenna patch 206.

In some other embodiments, substrate 202 is formed of an opaque material, such as an elemental semiconductor material, such as bulk silicon. In some embodiments, substrate 202 includes a conductive via formed in signal path 211 to electrically connect the RF circuit in interconnect structure 204 to antenna patch 206. As a result, the RF signal is transmitted between RF chip 208 formed on the lower side of substrate 202 and antenna patch 206 formed on the upper side of substrate 202 through the RF circuit formed in interconnect structure 204 and the conductive via in signal path 211 of non-transparent substrate 202. In some embodiments, an isolation film is deposited between the conductive path of substrate 202 and the surrounding silicon material to provide better electrical insulation.

In some embodiments, the interconnect structure 204 is formed of a plurality of stacked metallization layers. These metallization layers include patterned wires or conductive vias, and these patterned wires and vias are patterned or electrically interconnected to form interconnect paths and other parts of the antenna device 200A. For example, a first metallization layer formed on the lower surface of the substrate 202 includes a first wire or conductive pad 222A. The first wire or conductive pad 222A can be patterned as a ground plane, and the remaining space can be formed as a slit or hole for coupling RF signals to or from the antenna patch 206. In some other embodiments, the wire or conductive pad 222A is formed as a signal contact for transmitting the RF signal to or from the signal channel 211 in the non-transparent substrate 202.

A second metallization layer is formed below the first metallization layer and includes a first conductive via, such as exemplary first conductive via 224A. Similarly, a third metallization layer is formed below the second metallization layer and includes a second conductive line or conductive pad 222B, and a fourth metallization layer is formed below the third metallization layer and includes a plurality of second conductive vias, such as exemplary second conductive via 224B. The second conductive line 222B may be patterned to form a power line or a signal transmission line. A fifth metallization layer is formed below the fourth metallization layer and includes a third conductive line 222C. The third conductive line 222C may be patterned to form a transmission line for transmitting RF signals or control signals between ports of the RF chip 208. In some embodiments, the wires 222A, 222B, 222C are interconnected through conductive vias 224A and 224B. In some embodiments, a plurality of conductive pads 210 are disposed under the sixth metallization layer and electrically connect the wire 222C to the RF chip 208.

Please note that due to the routing considerations of the RF chip 208 and the antenna patch 206, the RF chip 208 may correspond to but not align with the corresponding antenna patch 206. The RF chip 208 is drawn in FIG. 2 to be aligned with the antenna patch 206 for illustrative purposes only, but does not mean that the antenna patch 206 and the corresponding RF chip 208 must be aligned.

In some embodiments, the wires 222A, 222B, 222C and the conductive pad 210 and the conductive vias 224A and 224B are formed of a conductive material, such as copper, tungsten, aluminum, titanium, tantalum, alloys thereof, etc. The wires 222A, 222B, 222C and the conductive vias 224A and 224B are further electrically insulated by an insulating material 226A, 226B or 226C, such as a polymer-based material, such as polyimide or epoxy.

FIG. 3A is a schematic block diagram of a transmitter 100 according to some embodiments of the present application. In some embodiments, the transmitter 100 includes a processing unit 306, wherein the processing unit 306 includes a power conversion module, a controller, and a data processing module (none of which is shown separately for simplicity). The power conversion module is configured to provide a power supply voltage VD, for example, based on an input power received from an external power source 302. In some embodiments, the data processing module is configured to receive input data or instructions from a control unit 304 outside the transmitter 100. In some embodiments, the data processing module includes a network interface circuit configured to receive or transmit data or instructions under a transmission protocol. The processing unit 306 can be configured to extract transmission data or control signals from the input data.

In some embodiments, the controller is configured to generate one or more RF signals RF_in to be transmitted by the antenna patch 206. In some embodiments, the controller is also configured to generate control signals for calibrating the RF signal RF_in, such as calibration data Din, a data clock signal CLK, and a synchronization clock signal SYNC. In some embodiments, the calibration data Din is used to calibrate the amplitude or phase of the RF signal RF_in according to the transmission data or instructions. The calibration data may include amplitude calibration data or phase calibration data, or both. In some embodiments, the data clock signal CLK is used to provide a common clock for registers in the components of the transmitter 100. The frequency of the data clock signal CLK can represent the operating frequency of the digital data processing in the transmitter 100. In some embodiments, the synchronous clock signal SYNC is used to provide a clock for some registers in different stages to output calibration data at the same clock moment. The synchronous clock signal SYNC can represent the update frequency of the calibration data. In some embodiments, since the control signals include digital forms, they are also called digital control signals.

In some embodiments, the transmitter 100 further includes a power divider network 342 and a row of transmitter arrays 300. In some embodiments, the power divider network 342 is connected to the processing unit 306. In some embodiments, the power divider network 342 is a multi-stage power divider network formed by connecting a plurality of power dividers 344 in a tree structure or a binary structure. In some embodiments, the power divider network 342 includes two stages K1 and K2, and each power divider 344 in the K1 or K2 stage is configured to substantially equally distribute the power of the RF signal RF_in to the two outputs of the power divider 344. The output end of each K2-stage power divider 344 is connected to the corresponding transmitter array 300. In some embodiments, the power divider 344 can also be used as a power combiner in a receiver architecture, where the input and output of the power divider 344 are reversed to become the output and input of the power combiner.

In some embodiments, control signals including calibration data Din, data clock signal CLK, and synchronization clock signal SYNC are provided to each transmitter array 300 through a bus or a plurality of signal lines. In some embodiments, the illustrated embodiment shows only two-stage power divider network 342. However, power divider network 342 with more or less than two stages may also be applied to transmitters 100 of other embodiments. In some embodiments, the illustrated embodiment shows only four transmitter arrays 300 in a row of transmitter arrays 300. However, more or less than four transmitter arrays 300 in a row may also be used in transmitters 100 of other embodiments, where the number of transmitter arrays 300 is proportional to the number of stages of the power divider network 342.

FIG3B is a schematic block diagram of a transmitter array 300 of the transmitter 100 shown in FIG3A according to some embodiments of the present application. In some embodiments, the transmitter array 300 includes another power divider network 346 and a plurality of transmitter blocks 310. In some embodiments, the power divider network 346 forms a combined N-stage power divider network with the power divider network 342, wherein the power divider 344 in the last stage _KN of the power divider network 346 is connected to the corresponding transmitter block 310. In some embodiments, the power divider network 346 includes N-2 stages, and each power divider 344 in each stage is configured so that the power of the RF signal RF_in at the input end is substantially equal to the output of the two output ends of the power divider 344. In some embodiments, the power supply voltage VD and control signals Din, CLK, and SYNC are also provided to each transmitter block 310 via a bus or multiple signal lines.

FIG. 3C is a schematic block diagram showing a transmitter block 310 of the transmitter array 300 shown in FIG. 3B according to some embodiments of the present application. In some embodiments, the transmitter block 310 is formed by a row of RF chips 208 and a row of antenna feeds 212 corresponding to the row of RF chips 208. In some embodiments, as shown in FIG. 2B above, each RF chip 208 includes a separate RF circuit, and is therefore also referred to as an RF circuit 208. In some embodiments, a power supply voltage VD is provided and transmitted to each RF chip 208. In addition, control signals, including calibration data Din, data clock CLK, and synchronization clock SYNC, are fed to each RF chip 208 through one or more signal lines. In some embodiments, the RF signal RF_in is also fed into each RF chip 208 via the transmission line 220.

The RF chip 208 is configured to generate a calibrated RF signal as an RF output signal RF_out after performing calibration of the RF signal RF_in according to the calibration data Din. In some embodiments, the RF chip 208 includes input ports for the corresponding RF signal RF_in, the power voltage VD, the calibration data Din, the data clock signal CLK, and the synchronization clock signal SYNC. In some embodiments, the RF chip 208 includes output ports for the corresponding calibration data Dout and two components of the RF output signal RF_out, namely RF_out_I and RF_out_Q.

In some embodiments, the RF output signal RF_out is divided into an in-phase component RF_out_I and a quadrature component RF_out_Q corresponding to a horizontal (H) polarization component and a vertical (V) polarization component, respectively. The individual components RF_out_I and RF_out_Q represent the in-phase component RF_out_I and the quadrature component RF_out_Q, which are orthogonal to each other. The individual quadrature components of the RF output signal can help calibrate the RF signal RF_in or the RF output signal RF_out.

In some embodiments, the transmission line 220 is provided between a first end (i.e., an input port of the transmitter block 310 to be connected to an RF signal source) and a second end of the transmission line 220. In some embodiments, as shown, the second end of the transmission line 220 is grounded through a resistive element 372. The resistive element 372 may include a resistor. In some embodiments, the resistance of the resistive element 372 is determined to match the impedance of the transmission line 220 to eliminate signal reflections or ripples. In some embodiments, the resistive element 372 has a resistance value of approximately 50 ohms.

In some embodiments, the RF signal RF_in is transmitted from the first end to the second end of the transmission line 220. In some embodiments, in the configuration of the phase array antenna, adjacent antenna feeds 212 are separated by a predetermined antenna spacing. In addition, the RF output signals RF_out_I and RF_out_Q transmitted by each antenna feed 212 should be modulated with appropriate phase delays according to the phase adjustment data in the calibration data Din to jointly establish an RF signal beam with a specific direction. Therefore, each RF output signal component RF_out_I and RF_out_Q is phase modulated according to one or more design criteria, such as their position in the antenna array.

In some embodiments, the RF chip 208 may not be arranged on the interconnect structure 204 in any manner. In some embodiments, a row of RF chips 208 in the same transmitter block 310 is connected to different positions Di of the transmission line 220, where the parameter i represents the i-th RF chip 208 in the transmitter block 310, and 1<i<=L, where L can be any integer greater than 1. Each position Di is separated by a predetermined distance. The type of signal feeding using a separate transmission line 220 for the RF chip 208 in the transmitter block 310 is called a "serial feeding" signal feeding method. The RF signal RF_in may have a phase difference between different positions D1, D2, ...D7...DL of the transmission line 220. Unwanted phase differences of the RF signal RF_in at different positions D1 to DL can be compensated at the same time when the calibration data Din is used for phase adjustment. In this way, the problem of inaccurate phase of the phase array antenna can be solved without increasing the cost.

In some embodiments, the RF chip 208 is designed to have a high input impedance of the RF chip 208 when viewed from the input port 208A of the RF chip 208. For example, the input impedance Rin of the RF chip 208 is relatively high when viewed from the transmission line 220 through the input port 208A of the RF chip 208 to the RF chip 208, for example, more than ten times the input impedance of the test machine. In some embodiments, the input impedance of the test machine is substantially 50 ohms when viewed from the signal port of the test machine.

FIG3D shows a schematic block diagram of the RF chip 208 shown in FIG3C in the left sub-figure according to some embodiments of the present application. In some embodiments, the input port 208A of the RF chip 208 is connected to a field effect transistor (FET) M1, such as a metal oxide semiconductor FET (MOSFET), wherein the gate terminal M1G or the gate is directly connected to the transmission line 220 through the branch transmission line 221. In some embodiments, the MOSFET M1 is connected to the input port 208A of the RF chip 208 through the capacitor Cp1. In some embodiments, the capacitor Cp1 is connected to the diodes D11 and D12 of the RF chip 208 at the gate terminal M1G. Referring to the right sub-figure of FIG. 3D , the circuit of the RF chip 208 connected to the input port 208A shown in the left sub-figure can be represented as an equivalent circuit formed by a capacitor Cp and an input impedance Rp in parallel. In some embodiments, the input impedance Rp (or Rin) or input impedance of the RF chip 208 is substantially equal to or greater than ten times the input impedance Z _T of the test machine, for example, greater than about 500 ohms, wherein the input impedance Z _T is determined by observing the test machine through the signal port of the test machine. In some embodiments, the input impedance Rp is equal to the input resistance Rin shown in FIG. 3C , and is at least equal to or greater than 500 ohms, 1000 ohms, or 5000 ohms. In some embodiments, the series feeding signal feeding method of the RF signal RF_in is implemented by a voltage driving signal feeding method. The RF output signal RF_out is generated based on the voltage signal transmitted at the input gate terminal M1G of the MOSFET M1, rather than the current driving signal.

Based on the foregoing, the proposed serial signal feeding method provides advantages. If the leakage current can be properly managed, the current value flowing into the input port 208A of the RF chip 208 is very low due to the high impedance characteristics of the MOSFET. Therefore, the power consumption of the RF chip 208 will be relatively low without affecting the component performance. In addition, the phase calibration module attached to the transmitter block 310 is not necessary, because the calibration data in the control signal already includes the phase calibration data in the phase array antenna architecture to assist the calibration of the RF signal RF_in, wherein the adjustment of the delay phase also includes phase adjustment or calibration.

Existing RF chips use current-driven signal feeding to transmit RF signals, with a tree-shaped power divider network. Each power divider at the end of the tree-shaped power divider network is connected to a corresponding RF chip. The input end is designed to comply with impedance matching rules, for example, including an input impedance of about 50 ohms. The driving current flows from the RF signal source through the tree-shaped power divider network into each RF chip. This RF signal feeding architecture consumes power when the RF signal is distributed to the RF chips at the end points of the power divider network. Although the phase error between RF chips in the current-driven signal feeding type may be smaller than that of the voltage-driven signal feeding type because the transmission lengths of all RF chips relative to the RF signal source are basically equal, the component variation caused by the process still often leads to non-negligible phase differences. Therefore, a phase calibration module is usually still required to ensure the performance of the phase array antenna. In contrast, the proposed voltage-driven signal type consumes less power and requires fewer power dividers without affecting component performance. Therefore, the power, cost and reliability of the transmitter can be improved through the proposed antenna array structure.

The in-phase RF signal RF_out_I and the quadrature RF signal RF_out_Q are coupled to the antenna patch 206 and radiated outward through the antenna patch 206 after being combined. The combined RF signal RF_out generates a circularly polarized RF signal RF_out according to the in-phase RF signal RF_out_I and the quadrature RF signal RF_out_Q. In some embodiments, the combined RF signal RF_out is a right-handed circularly polarized RF signal or a left-handed circularly polarized RF signal, depending on the phase sequence of the in-phase RF signal RF_out_I relative to the quadrature RF signal RF_out_Q. In some embodiments, since the ideal circular polarization of the RF signal output RF_out is achieved by equal amplitude and precise 90-degree phase difference between the in-phase RF signal RF_out_I and the quadrature RF signal RF_out_Q, the validity of the calibration data has an important function. In some embodiments, the in-phase RF signal RF_out_I and the quadrature RF signal RF_out_Q are separated and independently amplitude-calibrated and phase-calibrated before being transmitted to the antenna patch 206. In addition, in some embodiments, the in-phase RF signal RF_out_I and the quadrature RF signal RF_out_Q are received from the antenna patch 206 and independently amplitude-calibrated and phase-calibrated in the RF chip 208 before they are combined and transmitted out of the RF chip 208. Therefore, the calibration task can be easily completed without complex calibration circuits.

FIG4A is a schematic block diagram of a receiver 101 according to some embodiments of the present application. Receiver 101 is an RF receiver. In some embodiments, receiver 101 is considered as a peer device of transmitter 100, wherein receiver 101 includes processing unit 307. Receiver 101 may differ from transmitter 100 in operating frequency to facilitate duplex transmission, for example, one of transmitter 100 and receiver 101 is configured to operate at a frequency of 18 GHz, while the other is configured to operate at a frequency of 28 GHz. Due to the different operating frequencies, the design parameters of the components of transmitter 100 and receiver 101 may be different. In some embodiments, receiver 101 is suitable for user equipment 12, 14, 16, 18, ground base station 22, or non-ground base station 24.

In some embodiments, the processing unit 307 includes a power conversion module, a controller, and a data processing module (all of which are not shown separately for simplicity). In some embodiments, the processing unit 307 may be added with additional modules, or some of the above modules may be omitted or replaced by other modules. The function and configuration of the power conversion module of the processing unit 307 are similar to the function and configuration of the transmitter 100 described with reference to FIG. 3A, so similar features are not repeated here for simplicity.

In some embodiments, the controller of the processing unit 307 is configured to control the demodulation action of the receiver signal. In some embodiments, the receiver signal received by the processing unit 307 will be down-converted to a baseband signal. In some embodiments, the processing unit 307 is powered by an external power supply 302. In some embodiments, the controller is configured to generate control signals for the phase array antenna, such as calibration data Din, data clock signal CLK and synchronization clock signal SYNC.

In some embodiments, the data processing module of the receiver 101 is configured to receive instructions from the control unit 304 located outside the receiver 101. The data processing module can be configured to receive transmission data extracted from the RF signal RF_out and transmit the transmission data to the control unit 304.

The receiver 101 may further include a power combiner network 352 and a row of receiver arrays 301. In some embodiments, the power combiner network 352 is connected to the input end of the processing unit 307 and is configured to collect the RF signal RF_out of each RF chip 209 (see FIG. 4C) therefrom to convert it into a combined RF data signal RF_out. The power combiner network 352 shown in FIG. 4A is similar to the multi-stage power combiner network in the power divider network 342 shown in FIG. 3A, except that its input end is opposite to the output end. In some embodiments, control signals including calibration data Din, data clock signal CLK, and synchronization clock signal SYNC are provided to each receiver array 301 through a bus or a plurality of signal lines.

FIG. 4B is a schematic block diagram of a receiver array 301 of the receiver 101 of FIG. 4A according to some embodiments of the present application. In some embodiments, the receiver array 301 includes another power combiner network 356 and multiple receiver blocks 311. In some embodiments, the power combiner network 356 shown in FIG. 4B is similar to the power divider network 346 shown in FIG. 3B, except that its input end is opposite to the output end. In some embodiments, the power supply voltage VD and control signals including calibration data Din, data clock signal CLK and synchronization clock signal SYNC are also provided to each receiver block 311 through a bus or multiple signal lines.

FIG. 4C is a schematic block diagram showing a receiver block 311 of the receiver array 301 of FIG. 4B according to some embodiments of the present application. In some embodiments, the receiver block 311 is formed by a column of RF chips 209 and a column of antenna feeds 213 corresponding to the column of RF chips 209. In some embodiments, as shown in FIG. 2B above, each RF chip 209 includes a separate RF circuit, and is therefore also referred to as an RF circuit 209. In some embodiments, a power supply voltage VD is provided and transmitted to each RF chip 209. In addition, control signals, including calibration data Din, a data clock signal CLK, and a synchronization clock signal SYNC, are fed into each RF chip 209.

The RF chip 209 is configured to provide a calibrated RF signal RF_out from the RF input signal RF_out on the antenna feed 213 according to the calibration data Din. In some embodiments, the RF chip 209 includes input ports for corresponding in-phase RF signal components RF_in_I and quadrature RF signal components RF_in_Q, power supply voltage VD, calibration data Din, data clock signal CLK and synchronization clock signal. In some embodiments, the RF chip 209 includes output ports for corresponding calibration data and output port Dout of the RF signal RF_out. The functions and settings of the calibration data Din, the data clock signal CLK and the synchronization clock signal SYNC are similar to those described previously with reference to FIGS. 3A-3C, and the details of these features will not be repeated here.

In some embodiments, the receiver block 311 includes a transmission line 220 between a first end (i.e., an output port of the receiver block 311) and a second end of the transmission line 220. In some embodiments, the second end of the transmission line 220 of the receiver block is grounded through a resistive element 372. The resistive element 372 may include a resistor. In some embodiments, the resistance of the resistive element 372 is determined to match the impedance of the transmission line 220 to eliminate signal reflections. In some embodiments, the resistive element 372 has a resistance value of approximately 50 ohms.

In some embodiments, the provided RF signal RF_out is transmitted between the first end and the second end of the transmission line 220. The RF signals provided by the respective antenna feeds 213 should be phase-delayed according to the phase to form a constructive RF signal RF_out together with the adjustment data in the calibration data Din. Therefore, the RF signal components RF_out_I and RF_out_Q may be phase-calibrated before being combined, or the individual RF signals RF_out may be phase-calibrated before being fed to the transmission line 220 according to one or more design criteria, such as their positions in the antenna array.

The left sub-figure of FIG. 4D is a schematic block diagram of the RF chip 209 of FIG. 4C according to some embodiments of the present application. In some embodiments, the output port 209A of the RF chip 209 is formed by a FET M2, wherein the drain terminal D2 is directly connected to the transmission line 220 through a branch transmission line 221. In some embodiments, the output port 209A of the RF chip 209 is designed to have a relatively high input impedance to ensure that most of the output current Iout provided to the transmission line 220 by the received RF signal RF_out of one RF chip 209 will not flow back to other RF chips 209 of the same receiver block 311.

In some embodiments, MOSFET M2 is connected to output port 209A of RF chip 209 through capacitor Cp1. In some embodiments, capacitor Cp1 is connected to diodes D21 and D22 of RF chip 209 at drain terminal M2D. Referring to the right sub-figure of FIG. 4D, the circuit of RF chip 209 connected to input port 208A shown in the left sub-figure can be represented as an equivalent circuit consisting of capacitor Cp and input impedance Rp in parallel. In some embodiments, the input impedance or impedance Rp of RF chip 209 is substantially equal to or greater than ten times the input impedance Z _T of the test machine, for example, greater than about 500 ohms. In some embodiments, the input impedance Rp of RF chip 209 is at least equal to or greater than 500 ohms, 1000 ohms, or 5000 ohms.

Based on the foregoing, the proposed serial signal collection method provides advantages. If the leakage current can be properly managed, the current value flowing from one RF chip 209 to other RF chips 209 in the same receiver block 311 is very low due to the high impedance characteristics of MOSFET. Therefore, the power collection efficiency of the RF chip 209 will be relatively high without affecting the component performance. In addition, the phase calibration module attached to the transmitter block 310 is not necessary because the calibration data in the control signal already includes the phase calibration data in the phase array antenna architecture to assist the calibration of the RF signal RF_in, where the adjustment of the delay phase also includes phase adjustment or calibration.

Figures 5A to 5D are schematic block diagrams of intermediate stages of a method for manufacturing and testing a phased array antenna of a transmitter 100 or a receiver 101 according to some embodiments of the present application. Figure 6 is a schematic flow chart of a method 600 for manufacturing and testing a phased array antenna shown in Figure 5. It should be understood that additional steps may be provided before, during, and after each step in method 600, and some of the steps described below may be replaced by other embodiments, or removed. The order of the steps shown in Figures 5A to 5D or Figure 6 may be interchangeable. Some steps may be performed simultaneously or independently.

In some embodiments, manufacturing the phased array antenna includes manufacturing the phased array antenna, followed by a testing step of the manufactured phased array antenna to ensure the integrity of the phased array antenna. Referring to FIG. 5A , a substrate 510 including a first RF element 2081 or 2091 is received. The related steps are shown in step S602 of FIG. 6 . In some embodiments, the substrate 510 includes a plurality of RF elements 2081 or 2091, including the first RF element 2081 or 2091, formed in an array on the upper surface of the substrate 510. In some embodiments, the plurality of RF elements 2081 or 2091 are separated and defined by a ruled area 512. RF element 2081 or 2091 is similar to RF chip 208 or 209, but RF element 2081 or 2091 remains on a substrate together with other RF elements 2081 or 2091 before cutting or singulation, and RF chip 208 or 209 is a single chip formed by RF elements 2081 or 2091 and can be bonded to transmitter block 310 or receiver block 311. In some embodiments, RF element 2081 or 2091 is tested before cutting or singulation process to evaluate the electrical characteristics of RF chip 208 or 2091 bonded to transmitter block 310 or receiver block 311.

In some embodiments, the lined area 512 includes a test pattern or a test port configured to perform a test on the RF element 2081 or 2091 after the RF element 2081 or 2091 is formed. In some embodiments, each RF element 2081/2091 has a signal (input/output) port 208A/209A for receiving/transmitting an RF signal, and its input impedance Rp is greater than ten times the input impedance Z _T of a test machine, for example, the test machine 502 shown in FIG5 . Referring to FIG5B , the input impedance Rp is determined by observing the signal port 208A or 209A of the RF device 2081 or 2091 from the probe 508, and the input impedance Z _T is determined by looking from the signal port (or connection port) 525 toward the test machine 502. In some embodiments, the input port 208A of the RF element 2081 is used for an RF transmitter, and the output port 209A of the RF element 2091 is used for an RF receiver. Throughout this application, the input port 208A and the output port 209A are collectively referred to as signal ports.

Referring to FIG. 5B , the probe assembly 504 is connected to the input port 208A and the test machine 502 to test the RF element 2081 or 2091. In some embodiments, the probe assembly 504 includes a probe 508 and a signal port (or connection port) 505, which are respectively connected to the input port 208A and the test machine 502. Similarly, referring to FIG. 5C , the probe assembly 504 is connected to the output port 209A and the test machine 522. In some embodiments, the probe assembly 504 includes a probe 508 and a signal port 505, which are respectively connected to the output port 209A and the test machine 522. The relevant steps are shown in step S604 of FIG. 6 .

In some embodiments, referring to FIG. 5B , a test machine 502 for testing RF element 2081 includes at least one or more of a signal generator and a spectrum analyzer. Test machine 502 may alternatively include a network analyzer. In some embodiments, test machine 502 includes an ideal voltage source _VT having an input impedance _ZT . In some embodiments, input impedance _ZT is substantially equal to 50 ohms. In some embodiments, probe assembly 504 includes a transmission line 506 that connects probe 508 and signal port 505 in series. Probe assembly 504 connects RF element 2081 through physical contact of probe 508 with input port 208A.

5C , a test machine 522 for testing the RF component 2091 includes at least one or more of a signal generator and a spectrum analyzer. The test machine 522 may alternatively include a network analyzer or a noise figure analyzer. In some embodiments, the test machine 522 includes an input impedance Z _T from a signal port (or connection port) 525 of the test machine 522 looking toward the test machine 522. In some embodiments, the input impedance Z _T is substantially equal to 50 ohms. The probe assembly 504 connects the RF component 2091 through the physical contact of the probe 508 with the output port 209A.

3D and 5B or 4D and 5C, the probe assembly 504 sees the input impedance Z _T of the test machine 502 or 522 from the boundary line L1 between the probe assembly 504 and the test machine 502. The probe assembly 504 also sees the output impedance Rp from the boundary line L2 between the probe assembly 504 and the RF element 2081 or 2091. As described above, the input impedance Rp is at least ten times (10x) the input impedance Z _T. As a result, the input impedance Rp of the probe assembly 504 cannot be matched with Z _T. As a result, a ripple or signal reflection may be generated during the test process, resulting in inaccurate test results.

Referring again to FIGS. 5B and 5C , the probe assembly 504 is further connected to a first end of a resistor element 514. The resistor element 514 is connected in parallel with the probe 508 so that the impedance from the test machine 502 or 522 to the probe assembly 504 is substantially equal to Z _T , which is equal to the input impedance from the probe assembly 504 to the test machine 502 or 522. The corresponding step is shown in step S606 of FIG. 6 . In some embodiments, the resistor element 514 has a second end connected to a reference voltage (e.g., a ground terminal). Referring to the lower sub-figures of FIGS. 5B and 5C , the output impedance of the probe assembly 504 from the boundary line L2 to the RF chip 2081 or 2091 is the parallel value of the input impedance Rp and the resistor element 514. Since the input impedance Rp is at least ten times (10x) greater than the resistance Z _T of the resistor element 514, the resulting effective resistance is substantially equal to the resistance Z _T of the resistor element 514, which is substantially equal to the input impedance Z _T of the tester 502 or 522. In this way, the impedance matching achieved on both sides of the transmission line 506 of the probe assembly 504 is equal to Z _T , and the test performance of the tester 502 or 522 can be maintained.

Referring to FIG. 5D , a plurality of RF elements 2081 or 2091 are separated from the substrate 510 into individual RF chips 208 or 209. The related steps are shown in step S608 of FIG. 5D . The separation step may be performed by a cutting tool 520 , such as a cutting blade or a cutting laser. In some embodiments, the individual RF chips 208 or 209 are bonded to the substrate 202 and the interconnect structure 204 to form the transmitter 100 or the receiver 101. In some embodiments, the RF chips 208 or 209 are packaged to form the transmitter 100 or the receiver 101.

Figures 7A to 7F are schematic block diagrams of intermediate stages of a method for manufacturing and testing a phased array antenna of a transmitter 100 or a receiver 101 according to some embodiments of the present application. Figure 6 is a method 600 for manufacturing and testing a phased array antenna of Figures 7A to 7F according to some embodiments. It should be understood that additional steps may be provided before, during, and after the steps in method 600, and some of the steps described below may be replaced by other embodiments, or removed. The order of the steps in Figures 7A to 7F or Figure 6 may be interchangeable. Some steps may be performed simultaneously or independently.

In some embodiments, manufacturing the phased array antenna includes manufacturing the phased array antenna, followed by a testing step of the manufactured phased array antenna to ensure the integrity of the phased array antenna. Referring to FIG. 7A , a substrate 710 including a first RF element 3081 or 3091 is received. In some embodiments, a first RF element 3081 or 3091 having a signal (input or output) port 308A or 309A is received (see the enlarged view of the first RF element 3081 or 3091 of FIG. 7A ). The related steps are shown in step S602 of FIG. 6 . In some embodiments, the first RF element 3081 or 3091 forms an array on the upper surface of the substrate 710. In some embodiments, a plurality of RF elements 3081 or 3091 are separated and defined by a ruled area 512. In some embodiments, the line area 512 includes a test pattern or a test port, such as a resistor element, for testing a plurality of RF elements 3081 or 3091 after forming the RF elements 3081 or 3091. In some embodiments, each RF element 3081 or 3091 has an input port 308A or an output port 309A for receiving or transmitting an RF signal, and the input impedance of the RF element 3081 or 3091 through the signal port 308A or 309A is Rp, which is greater than ten times the input impedance Z _T of the test machine (such as the test machine 502 shown in FIG. 5B ).

In some embodiments, the input port 308A of the RF element 3081 is used for the RF transmitter, and the output port 309A of the RF element 3091 is used for the RF receiver. In addition, the RF elements 3081 and 3091 are similar to the RF elements 2081 and 2091 shown in Figures 3C and 4C, respectively, except that the RF elements 3081 and 3091 further include a test port TP and a resistor element 714. The resistor element 714 is connected to the probe assembly during the test step. And, after the RF chip 308 or 309 is formed on the transmitter block 310 or the receiver block 311, the resistor element 714 may not provide any other function during the normal operation of the RF chip 308 or 309. In some embodiments, the resistor element 714 has a first end connected to the test port TP and a second end connected to a reference voltage (e.g., a ground terminal).

Alternatively, in some embodiments, as shown in FIG. 7B , a corresponding test port TP and a resistor element 714 for the RF element 3081 or 3091 are formed in the area of the lined area 512. The resistor element 714 is connected to the probe assembly during the testing step and can be removed during the cutting step of the RF element 3081 or 3091. In some embodiments, the resistor element 714 has a first end connected to the test port TP and a second end connected to a reference voltage (e.g., a ground end).

Referring to FIG. 7C , the probe assembly 524 is connected to the input port 308A of the RF element 3081 and the test machine 502 through the probe 508 and the signal port 505 respectively for testing the RF element 3081 or 3091. The probe assembly 524 is further connected to the first end of the resistive element having a resistance or impedance substantially equal to the input impedance Z _T. In some embodiments, the probe 508 of the probe assembly 504 is configured to be coupled to the signal port 505 of the test machine 502. In some embodiments, the test machine 522 is configured to be coupled to the probe assembly 524 for testing the first RF element 3081 or 3091 through the probe assembly 524. The relevant steps are shown in steps S604 and S606 of FIG. 6 . The probe assembly 524 includes a first probe 508 and a second probe 509, which are configured to respectively probe the input port 308A and the test port TP during the test step. In some embodiments, the probe assembly 524 connects the RF element 2081 through the physical contact of the first probe 508 and the second probe 509 with the input port 308A and the test port TP.

Similarly, referring to FIG. 7D , the probe assembly 524 is connected to the output port 309A of the RF element 3091 and the test machine 522 through the probe 508 and the signal port 505, respectively. In some embodiments, the (first) probe 508 of the probe assembly 524 is configured to be coupled to the signal port 505 of the test machine 502. In some embodiments, the test machine 522 is configured to be coupled to the probe assembly 524 for testing the first RF element 3081 or 3091 through the probe assembly 524. The probe assembly 524 is further connected to the first end of the resistor element 714, wherein the resistor element 714 has a resistance or impedance substantially equal to the input impedance Z _T. The related steps are shown in steps S604 and S606 of FIG. 6 . The probe assembly 524 includes a first probe 508 and a second probe 509, which are configured to respectively probe the output port 309A and the test port TP during the test step. Further, the probe assembly 524 is connected to the RF element 3091 by physically contacting the first probe 508 and the second probe 509 with the output port 309A and the test port TP respectively.

7C and 7D , in the test step, the first probe 508 and the second probe 509 are respectively in contact with the probe assembly 524, so that the input impedance Rp is connected in parallel with the resistance element 714. The resistance element 714 is connected in parallel with the probe 509, so that the input impedance from the test machine 502 or 522 to the probe assembly 524 is substantially equal to the input impedance Z _T from the probe assembly 524 to the test machine 502 or 522. Since the input impedance Rp determined by the probe 508 looking toward the signal port 308A or 309A of the RF element 3081 or 3091 is at least ten times greater than the resistance value of the resistor element 714, the effective resistance generated is substantially equal to the resistance of the resistor element 714, which is substantially equal to the input impedance Z _T of the test machine 502 or 522. Therefore, the impedance matching is achieved on both sides of the transmission line 506 of the probe assembly 524, which is equal to Z _T , which is the same effect as that achieved by the setting of the resistor element 514 on the probe as shown in FIGS. 5B and 5C. Therefore, the test performance of the test machine 502 or 522 is maintained.

7E , the RF element 3081 or 3091 is separated from the substrate 710 into a separate RF chip 308 or 309. The relevant step is shown in step S608 of FIG6 . The separation step can be performed by a cutting tool 520, such as a cutting blade or a cutting laser, to cut the substrate 710 along the score line area 512. In some embodiments, the separate RF chip 308 or 309 is bonded to the substrate 202 and the interconnect structure 204 to form the transmitter 100 or the receiver 101. In some embodiments, the RF chip 308 or 309 is packaged to form the transmitter 100 or the receiver 101. After the formation of the transmitter 100 or the receiver 101 is completed, the resistor element 714 and the test port TP remain in the respective RF chip 3081 or 3091.

Alternatively, as shown in FIG. 7F , the RF element 3081 or 3091 is separated from the substrate 710 into a separate RF chip 308 or 309 . The relevant step is shown in step S608 of FIG. 7F . During the cutting step, the resistor element 714 and the test port TP can be removed along with the removal of the ruled area 512 . Therefore, after the formation of the transmitter 100 or the receiver 101 is completed, the resistor element 714 and the test port TP are no longer included in the respective RF chip 3081 or 3091 .

8A and 8B are schematic block diagrams showing different circuit contexts seen by the RF chip 2081 or 2091 when the RF element 2081 or 2091 is disposed in the substrate 510/710 or the antenna element 200A, respectively, according to some embodiments of the present application. As previously mentioned, the input impedance (e.g., Rp) of the RF chip 208 or 209 does not match the input impedance Z _T of the test machine 502 or 522, respectively. In addition, when the RF element 2081 or 2091 undergoes a testing step before being cut (as shown in FIGS. 5A-5C and 7A-7D), the impedance of the transmission line 506 of FIGS. 3C and 4C is not taken into consideration. Therefore, it is necessary to check whether the test environment or input impedance seen by the individual RF element 2081/3081 or 2091/3091 when formed on the substrate 510 or 710 is equal to the input impedance seen by the individual RF chip 208 or 209 cut and bonded to the transmitter 100 or receiver 101.

Referring to 3D, 4D and 8A, the output impedance of the RF element 2081 or 2091 can be represented as an equivalent circuit consisting of an input impedance Rp and a capacitor Cp in parallel. The probe assembly 504 or 524 is configured to connect the RF element 2081 or 2091 to the test machine 502 or 522. As shown in FIG8A, whether it is an embedded resistor element 514 in the probe assembly 504 or an on-chip resistor element 714 in the RF element 2081 or 2091, the resistor element 514 or 714 can provide the same function. As described above, the resistance of the resistor element 514 or 714 is equal to the input impedance Z _T of the test machine 502 or 522, which is usually equal to about 50 ohms. Therefore, the output impedance seen by the RF element 2081 or 2091 from the input/output port 208A/209A at the boundary L3 between the RF element 2081/2091 and the probe assembly 504/524 is equal to the resistor element 514/714 in parallel with the input resistor _ZT , which is equal to _ZT /2, typically 25 ohms.

3C, 4C and 8B, when the RF chip 208 or 209 is cut from the RF element 2081 or 2091 or separated from the substrate 510 or 710 and connected to the transmission line 220, the output impedance of the RF chip 208 or 209 seen from the input/output port 208A/209A is caused by the equivalent impedance of the segment of the transmission line 220 connecting the respective RF chips 208/209. In some embodiments, when the RF chip 2081 having a relatively high impedance compared to the resistor element 372 is connected to the transmission line 220, the impedance of each segment in the transmission line 220 can be considered to be equal to the resistance 372 of the resistor element, i.e., Z _T. Therefore, for each individual RF chip 208 or 209, the RF chip 208 and 209 sees a parallel connection of two transmission line 220 segments, one of which is connected to the RF signal input port signal RF_in, and the other is connected to the resistor element 372. In some embodiments, each segment of the transmission line 220 is represented by an equivalent inductor-capacitor (LC) circuit, which is formed by a capacitor with a capacitance value C and an inductor with an inductance value L/2. In this way, the effective output impedance seen by the RF chip 208 or 209 is equal to the parallel connection of two segments with a resistance of Z _T , and the effective output impedance is equal to Z _T /2.

In summary, it can be seen that the impedance seen by the RF element 2081 or 2091 before bonding with the transmission line 220 is substantially equal to the impedance seen by the RF chip 208 or 209 after bonding with the transmission line 220. As a result, the circuit environment of the test scenario of Figures 5A-5C or 7A-7D provides a substantially identical impedance matching environment for the environment of the RF chip 208 or 209 after bonding, so the test results tested on the substrate before the cutting step have no deviation or distortion, and can therefore be applied to the test results after cutting and bonding.

FIG. 9 shows a schematic block diagram of probe assemblies 910, 920, and 930 according to some embodiments of the present application. Probe assemblies 910, 920, and 930 may include an embedded impedance-matched resistor element, similar to probe assembly 504 shown in FIG. 5B or 5C for single-ended signal input applications. In some embodiments, each probe assembly 910, 920, and 930 includes three probes labeled "G1," "S," and "G2," respectively. The probe labeled "S" represents a signal probe connected to a signal input/output port, and the probe labeled "G1" or "G2" represents a ground terminal for connecting to a reference voltage of a component under test, such as ground.

In some embodiments, each of the probe assemblies 910, 920, and 930 further includes an embedded resistor element 514 having a resistance Z _T. The connection configuration of the resistor element 514 may be different in the probe assemblies 910 to 930. The resistor element 514 has a first end and a second end, wherein the first end is connected to the probe S, and the second end is connected to the probe G1 in the probe assembly 910, to the probe G2 in the probe assembly 920, or to another reference voltage of the probe assembly 930 different from the probes G1 and G2, such as ground. The probe assemblies 910, 920, and 930 may provide substantially the same function of achieving impedance matching during the test step performed on the RF element 208 or 209.

FIG. 10 is a schematic block diagram of probe assemblies 1010 and 1020 shown according to some embodiments of the present application. Probe assemblies 1010 and 1020 may be similar to probe assembly 504 shown in FIG. 5B or 5C and configured to receive a pair of differential signal inputs. In some embodiments, each probe assembly 1010 and 1020 includes five probes labeled "G1", "S1", "G2", "S2" and "G3", respectively. The probes labeled S1 and S2 represent a pair of differential signal probes for connecting a pair of differential signal input/output ports, where the pair of differential signals can be transmitted in the form of equal amplitude and opposite polarity. The probes labeled G1, G2 or G3 represent ground terminals configured to connect to a reference voltage (e.g., ground) of the device under test.

In some embodiments, the probe assembly 1010 further includes embedded resistor elements 514 and 515 each having a resistance Z _T. In some embodiments, each resistor element 514 and 515 has a first end and a second end, wherein the first end is connected to the probes S1 and S2, respectively, and the second end is connected to the probes G1 and G3, respectively. In some other embodiments, the second end is connected to the probe "G2".

Alternatively, the probe assembly 1020 further includes an embedded resistor element 516. In some embodiments, the resistor element 516 has a first end and a second end, connected to the probes "S1" and "S2", respectively. The resistor element 516 can have an effective resistance of 2xZ _T because the second end of the resistor element 516 connected to the probe "S2" is equivalent to receiving a signal with an amplitude equal to the signal received from the probe S1 and having an opposite polarity. The probe assemblies 1010 and 1020 can provide substantially the same function of achieving impedance matching during the test steps performed on the RF element 208 or 209.

FIG. 11 is a schematic block diagram of probe assemblies 1110 and 1120 according to some embodiments of the present application. Probe assemblies 1110 and 1120 are similar to probe assemblies 910 to 930 shown in FIG. 9 , except that probe assemblies 1110 and 1120 each further include an active element A1 connected in series with a probe S. In some embodiments, active element A1 connects the probe S and a signal port (connection port) 505 in series. In some embodiments, active element A1 includes an input IP coupled to the probe S and an output OP coupled to the signal port 505. In some embodiments, active element A1 is an amplifier, such as an operational amplifier. In some embodiments, the input impedance of active element A1 is greater than ten times the input impedance Z _T of the test machine 502 or 522, and the output impedance is substantially equal to Z _T. Probe assembly 1110 or 1120 includes a resistor element 517, wherein the resistor element 517 has a first end connected to probe S. The resistor element 517 also includes a second end, which is connected to a reference voltage (e.g., ground) through a terminal of the probe assembly 1110 different from the probes G1 and G2; or connected to probe G1 or G2, as shown in probe assembly 1120. In Figures 8A, 8B, and 11, the test machine 502 or 522 always sees a fixed equivalent impedance Z _T provided by the active element A1, regardless of the circuit on the other side of the active element A1. The RF chip 2081 or 2091 must see an effective output impedance of Z _T /2 for impedance matching. Therefore, the effective resistance of the resistor element 517 is half of the input impedance Z _T , that is, Z _T /2.

FIG. 12 shows a schematic block diagram of probe assemblies 1210 and 1220 according to some embodiments. Probe assemblies 1210 and 1220 are similar to probe assemblies 1010 and 1020 shown in FIG. 10 , except that probe assemblies 1210 and 1220 each further include an active element A1. Active element A1 includes two terminals connected to probes S1 and S2 as a pair of differential signal input terminals. In some embodiments, active element A1 includes a first input IP1 and a second input IP2 coupled to probes S1 and S2, respectively, and an output OP coupled to signal port 505. In some embodiments, probe assembly 1210 further includes two embedded resistor elements 531. In some embodiments, each resistor element 531 has a first end and a second end, wherein the first end is connected to probes S1 and S2, respectively, and the second end is connected to probes G1 and G2, respectively. In some embodiments, the left resistor element 531 is connected in parallel with probe S1, and the right resistor element 531 is connected in parallel with probe S2. Referring to the analysis of probe assemblies 1110 and 1120, each resistor element 531 has a resistance of Z _T /2.

In some embodiments, the probe assembly 1220 includes an embedded resistor element 532. In some embodiments, the resistor element 532 has a first end and a second end, which are connected to the probes S1 and S2, respectively. Since the signal received by the second end of the resistor element 532 connected to the probe S2 is equal in amplitude and opposite in polarity to the signal received from the probe S1, the equivalent resistance of the resistor element 532 may be twice the input impedance of the resistor element 531, that is, the effective resistance of the resistor element 532 is equal to Z _T. The probe assemblies 1210 and 1220 may provide substantially the same function of achieving impedance matching during the test steps performed on the RF element 208 or 209.

Based on the foregoing, the resistor elements 514, 515, 516, 517, 531, and 532 embedded in the various probe assemblies 504, 910, 920, 930, 1010, 1020, 1110, 1120, 1210, and 1220 may have different resistance values for matching the impedance seen by the RF chip 2081 or 2091 in various circuit environments. In some embodiments, the embedded individual resistor element of the probe assembly 504 has a resistance value that is substantially no greater than 2 times the input impedance Z _T of the test platform 502 or 522, for example, 2xZ _T .

FIG. 13 is a schematic block diagram of a probe assembly 1310 according to some embodiments of the present application. The probe assembly 1310 includes a body 1302, a protrusion 1304, and two probes 1306 and 1308. The probes 1306 and 1308 are configured to respectively probe the input/output ports 208A/209A or 308A/309A and the test port TP of the RF chip 2081, 2091, 3081, or 3091. In some embodiments, the probe assembly 1310 only shows the probes for the input/output ports 208A/209A or 308A/309A and the test port TP, and omits the probe for grounding. In some embodiments, probes 1306 and 1308 are parallel to each other and closely arranged to probe closely arranged input/output ports 208A/209A or 308A/309A and test ports TP. Other configurations using multiple probes closely arranged and sharing a common protrusion 1304 are also within the contemplated scope of the present application.

The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis for designing or modifying other processes and structures for performing the same purpose and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the present invention, and that various modifications, substitutions and changes can be made to the present invention without departing from the spirit and scope of the present invention.

600: Method S602: Step S604: Step S606: Step S608: Step

Claims (20)

A method for testing an RF component includes: receiving a first RF component having a signal port for transmitting an RF signal; connecting a first probe of a probe assembly to the signal port; connecting a test machine to the probe assembly to test the first RF component through the probe assembly; and connecting a first resistor element to the first probe in parallel so that a first input impedance from the test machine to the probe assembly is substantially equal to a second input impedance from the probe assembly to the test machine. The method of claim 1, wherein the first input impedance and the second input impedance are approximately 50 ohms. The method of claim 1, wherein a third input impedance viewed from the first probe toward the signal port is at least ten times greater than the first input impedance and the second input impedance. The method of claim 1 further includes: Configuring a first resistive element having an impedance substantially equal to the first input impedance. The method of claim 1 further includes: Embedding the first resistor element into the first RF element. The method of claim 1 further includes: Embedding the first resistor element into the probe assembly. The method of claim 1, wherein connecting the first resistor element in parallel with the first probe comprises: Connecting the first end and the second end of the first resistor element to the first probe and a reference voltage, respectively. A probe assembly for testing a radio frequency component, the probe assembly comprising: a first probe for contacting a signal port of the radio frequency component; a first connection port for electrically connecting to a second connection port of a test machine for testing the radio frequency component via the probe assembly; and a first resistor element configured to be connected in parallel with the first probe so that a first input impedance viewed from the first connection port is substantially equal to a second input impedance viewed from the second connection port. A probe assembly as claimed in claim 8, wherein the first input impedance is approximately 50 ohms. A probe assembly as claimed in claim 8, wherein the first resistive element has an impedance substantially equal to the first input impedance. A probe assembly as claimed in claim 8, wherein the first resistor element has a first end and a second end, which are respectively connected to the first probe and a reference voltage. The probe assembly of claim 8 further includes: A second probe configured to form a pair of differential probes with the first probe, wherein the first resistor element has a first end and a second end, respectively connecting the first probe and the second probe. The probe assembly of claim 8 further includes: An active element that connects the first probe and the first connection port in series. The probe assembly of claim 8 further includes: A transmission line that connects the first probe and the first connection port in series. The probe assembly of claim 8 further includes: A second probe, which forms a pair of differential probes with the first probe; A second resistor element, which is configured to be connected in parallel with the first probe; and An active element, which has a first input terminal and a second input terminal respectively connected to the first and second probes, and an output terminal connected to the first connection port. The probe assembly of claim 8 further comprises: A second probe, which forms a pair of differential probes with the first probe; and An active element, which has a first input terminal and a second input terminal respectively connected to the first and second probes, and an output terminal connected to the first connection port, wherein the first resistor element has a first terminal and a second terminal respectively connected to the first probe and the second probe. A test system includes: a radio frequency component including a signal port; a probe assembly including a probe connectable to the signal port; a test machine having a first connection port connectable to a second connection port of the probe assembly, the test machine being used to test the radio frequency component via the probe assembly; and a resistor element configured to connect the probe in parallel so that a first input impedance looking toward the first connection port is substantially equal to a second input impedance looking toward the second connection port. A test system as claimed in claim 17, wherein the RF component has a third input impedance looking into the signal port, and the third input impedance is at least ten times greater than the first input impedance and the second input impedance. A test system as claimed in claim 17, wherein the resistor element is embedded in the probe assembly. A test system as claimed in claim 17, wherein the resistor element is embedded in the RF element.