TWI844071B - Process method and manufacturing structure of high power surface emitting laser with low series resistance structure - Google Patents

Abstract

The present invention is a process method and a manufacturing structure of a high-power surface-emitting laser with a low series resistance structure, which improves the series resistance structure of a VCSEL structure with a multi-layer resonant cavity. The multi-layer resonant cavity has 2 to 9 active layers. By adopting the technical means of respectively setting a first stop layer and a second stop layer of n/p heavy doping at the upper and lower adjacent parts of the multi-layer resonant cavity, the present invention adjusts the setting position of the positive and negative metal contact layers to optimize the reduction of the device current path length, and avoids the problem of over-etching in the process so that the positive and negative metal contact layers can be accurately set at the required position, thereby effectively reducing the resistance of the device series resistance. Furthermore, by utilizing the low resistance characteristics of the first and second stop layers, the series resistance can be effectively reduced.

Description

Process method and manufacturing structure of high power surface emitting laser with low series resistance structure

The present invention relates to the process technology field of a VCSEL (Vertical Cavity Surface Emitting Laser) component, and in particular to a process method and manufacturing structure of a high-power surface emitting laser with a low series resistance structure.

VCSEL is a type of LD (Laser Diode) element. Its structure generally includes a substrate, a lower DBR (Distributed Bragg Reflector) layer, a resonant cavity, an upper DBR layer, and a set of positive and negative metal contact layers from bottom to top. The high-reflectivity DBR produces a resonance effect to emit laser light vertically from the surface of the crystal. However, the high-reflectivity DBR is made of two materials with different refractive indices stacked alternately. In addition to the problem of sharp reflectivity distribution curve, there is also the problem of excessive series resistance due to the obvious energy gap difference on the crystal interface. Furthermore, in response to the market demand for high-speed data transmission, a VCSEL device with a resonant cavity having multiple active layers has been introduced to the market, so as to enhance the resonance effect by stacking the active layers and thus increase the emitted laser light power. However, as is generally known, the total resistance generated by the resonant cavity will be formed by the series connection of the resistances of the active layers, causing the device to present a more aggravated series resistance and a high critical voltage, which in turn leads to the problem of high power consumption of the device.

To this end, the known process technology is to adjust the arrangement structure of the positive and negative electrode metal contact layers accordingly. For example, the negative electrode metal contact layer can be arranged at two positions, such as above the substrate or above the lower DBR layer, so as to adjust the resistance value of the component series resistance corresponding to the overall component current path. However, in order to set the negative metal contact layer, the upper DBR layer, the resonant cavity and even the lower DBR layer must be etched away first. However, in the etching process, there are often problems such as the inability to accurately control the etching depth and the inability to reproduce the depth difference during batch etching. Even if a monitoring system is used to control the etching stop point, over-etching may occur due to the etching gas or etching solution remaining in the reaction chamber, which in turn causes a high error in the series resistance of the component and affects the component quality. Furthermore, in response to the current Internet operation mode that constantly pursues high-speed and high-traffic transmission, VCSEL components with high power consumption and unstable quality problems may limit the information modulation efficiency and transmission speed of the entire Internet system, which is not conducive to the development of the industry.

In view of this, how to make good use of the chemical characteristics of each epitaxial layer to improve the process technology, so as to provide a minimum series resistance structure design for VCSEL elements with multi-layer active layer resonant cavity, thereby achieving the effect of greatly reducing the series resistance of high-power VCSEL elements and improving the resistance stability, so as to improve the deficiencies of the above-mentioned known technologies, is the subject that the present invention intends to explore.

The main purpose of the present invention is to provide a process method and manufacturing structure of a high-power surface-emitting laser with a low series resistance structure, so as to reduce the series resistance value through the application of an etching stop layer, and to improve the over-etching problem in the etching process to ensure a constant resistance value.

To achieve the above-mentioned purpose, the present invention discloses a process method for manufacturing a high-power surface-emitting laser with a low series resistance structure, which includes the following steps: constructing a design structure, which is stacked from bottom to top with a substrate, a lower DBR layer, a multi-layer resonant cavity and an upper DBR layer, wherein the multi-layer resonant cavity is provided with 2 to 9 resonant chambers, each of which is provided with an active layer, and the upper DB The R layer is provided with 22 to 30 upper double-layer stacking pairs, and the lower DBR layer is provided with 32 to 40 lower double-layer stacking pairs; a heavily doped first stop layer and a second stop layer are provided at the upper and lower adjacent positions of the multi-layer resonant cavity, wherein the first stop layer is provided at the lower adjacent position of the upper DBR layer, and the second stop layer is provided at the upper adjacent position of the lower DBR layer, thereby The first stop layer and the second stop layer are arranged at a position where the resistance of the series resistor is effectively reduced without considering the capacitance value; a semiconductor structure is formed by epitaxial deposition according to the design structure; a negative electrode metal contact region is arranged on the peripheral side of the semiconductor structure, and the negative electrode metal contact region is etched from top to bottom to the second stop layer corresponding to the position of the negative electrode metal contact region so that a central portion of the semiconductor structure is formed. A first platform; a positive metal contact area is arranged on one side of the first platform, and etching is performed from top to bottom to the first stop layer corresponding to the position of the positive metal contact area so that a second platform is formed on the upper part of the first platform, and the area of the second platform is smaller than that of the first platform; and a positive metal contact layer is arranged on the first stop layer, and a negative metal contact layer is arranged on the second stop layer.

The first stop layer and the second stop layer are made of phosphorus-containing materials such as InP, InGaP, GaAsP or AlGaAsP and are heavily doped with n/p type to reduce the etching rate and improve the positioning accuracy of the positive metal contact layer and the negative metal contact layer, thereby ensuring the resistance accuracy of the series resistor. Each of the upper double-layer stacking pairs is an Al _(0.9) Ga _(0.1) As/Al _(0.1) Ga _(0.9) As stacking structure, and when the first stop layer is set, one of the upper double-layer stacking pairs adjacent to the multi-layer resonant cavity is replaced by an In _(x) Ga _(1-x) P/Al _(0.1) Ga _(0.9) As structure; each of the lower double-layer stacking pairs is an Al _(0.9) Ga _(0.1) As/Al _(0.1) Ga _(0.9) As stacking structure, and when the second stop layer is set, one of the lower double-layer stacking pairs adjacent to the multi-layer resonant cavity is replaced by an In _(x) Ga _(1-x) P/Al _(0.1) Ga _(0.9) As structure, and X is 0.56-0.71. The negative electrode metal contact region is arranged around the semiconductor structure, and the upper DBR layer, the first stop layer and the multi-layer resonant cavity are etched from top to bottom by dry etching corresponding to the position of the negative electrode metal contact region to the position adjacent to the upper part of the second stop layer, and then the remaining part above the second stop layer is etched to the second stop layer by wet etching, so that the first high platform is formed in the central part of the semiconductor structure; then, the multi-layer resonant cavity is etched by wet etching. The side surface of the DBR layer is oxidized to form an oxide hole in an oxide layer disposed on the active layer in each resonant cavity, and the positive metal contact region is disposed on one side of the first platform. The upper DBR layer is etched from top to bottom to the position adjacent to the first stop layer by dry etching corresponding to the position of the positive metal contact region, and the remaining portion is etched to the first stop layer by wet etching, so that the second platform is formed on the upper portion of the first platform. When etching to the stop layer by wet etching, an NH ₄ OH:H ₂ O ₂ etching solution is used. When etching to the stop layer by wet etching, an NH ₄ OH:H ₂ O ₂ etching solution with a formula ratio of 1:10 is used. When the first stop layer and the second stop layer made of InGaAsP material are etched by wet etching, HCL:H ₃ PO ₄ etching solution is used; when the first stop layer and the second stop layer made of InP or InGaP material are etched by wet etching, H ₃ PO ₄ :H ₂ O ₂ :H ₂ O etching solution is used. When the first stop layer and the second stop layer made of InP material are etched by wet etching, H ₂ SO ₄ :H ₂ O ₂ :H ₂ O etching solution or C ₆ H ₈ O ₇ :H ₂ O ₂ etching solution is used.

In addition, to achieve the second purpose, the present invention further discloses a high-power surface-emitting laser structure manufactured using the above-mentioned process method. When the semiconductor structure is formed by epitaxial deposition, the center of the semiconductor structure is etched from top to bottom to the substrate, so that two high-power surface-emitting laser structures sharing the substrate are formed through subsequent processes, and the positive metal contact layers of each high-power surface-emitting laser structure are connected to each other by wire bonding; the negative metal contact layers of each high-power surface-emitting laser structure are connected to each other by wire bonding, so that the two high-power surface-emitting laser structures are connected in parallel.

In summary, the present invention considers the high resistance problem caused by the superposition of multiple resonant chambers in the multi-layer resonant cavity, and the first stop layer and the second stop layer are respectively arranged at the upper and lower adjacent parts of the multi-layer resonant cavity, thereby reducing the length of the device current path and reducing the corresponding series resistance. In addition, the first and second stop layers are respectively n/p type heavily doped epitaxial layers with low resistance characteristics, and the resistance between the positive and negative metal contact layers and the multi-layer resonant cavity can be further reduced, thereby optimizing and perfecting the setting state of the low series resistance structure. Furthermore, the present invention utilizes the first and second stop layers of phosphorus-containing materials in combination with corresponding etching solutions to slow down the etching rate of the epitaxial layer, which can solve the problem of over-etching of the upper DBR layer and the multi-layer resonant cavity during the etching process, and can accurately control the placement of the positive and negative metal contact layers and achieve the effect of improving the overall VCSEL structure quality stability.

By the way, when the first stop layer is placed in the upper DBR layer and the second stop layer is placed in the lower DBR layer, if the In _(x) Ga _(1-x) P/Al _(0.1) Ga _(0.9) As structure is used to replace the original Al _(0.9) Ga _(0.1) As/Al _(0.1) Ga _(0.9) As structure double layer stacking pair, there may be a carrier concentration difference △ There are concerns that the reflectivity of this layer stacking pair may be affected as n becomes smaller. However, because the present invention provides the upper DBR layer with 22 to 30 upper double-layer stacking pairs and the lower DBR layer with 32 to 40 lower double-layer stacking pairs, the overall reflectivity of the upper and lower DBR layers can still be maintained at >99%, which means that the luminous efficiency of the overall component is not affected.

S10~S15: Steps

S20~S28: Steps

1: High-power surface-emitting laser structure

10:Semiconductor structure

100: Substrate

101: Lower DBR layer

1010: Lower double stacking pair

102: Second stop layer

103: Multi-layer resonance cavity

1030: Next batch of coating

1031: Active layer

1032: Upper batch of covering

1033: Oxide layer

10330: Oxidation holes

1034: Upper isolation layer

104: First stop layer

105: Upper DBR layer

1050: Upper double stacking pair

106: Positive metal contact layer

107: Negative metal contact layer

11: The first high platform

12: The second highest platform

13: Negative metal contact area

14: Positive metal contact area

Figure 1 is a flow chart of a preferred embodiment of the present invention.

Figure 2 is a schematic diagram of the structure of a preferred embodiment of the present invention.

Figures 3A and 3B are flow charts of the second preferred embodiment of the present invention.

Figures 4A, 4B, 4C, 4D, and 4E are schematic diagrams of the process of the second preferred embodiment of the present invention.

Figure 5 is a schematic diagram of the resistance state of the series resistor of the second preferred embodiment of the present invention.

Figure 6 is a schematic diagram of the top view of the corresponding cross-section of the components of the single-substrate dual-structure parallel connection of the second preferred embodiment of the present invention.

In order to enable people with general knowledge in this field to clearly understand the content of this new model, please refer to the following description with diagrams.

Please refer to Figures 1 and 2, which are respectively a flow chart and a structural schematic diagram of a preferred embodiment of the present invention. As shown in the figure, the process method of the high-power surface-emitting laser with a low series resistance structure includes the following steps: Step S10, constructing a design structure, which is stacked from bottom to top with at least a substrate 100, a lower DBR layer 101, a multi-layer resonant cavity 103 and an upper DBR layer 105, wherein the multi-layer resonant cavity 103 is provided with 2 to 9 resonant chambers, each of which is provided with an active layer 1031, and the upper DBR layer 105 is provided with 22 to 30 The upper double layer stacking pair 1050 is provided in the lower DBR layer 101, and the lower DBR layer 101 is provided with 32-40 lower double layer stacking pairs 1010; Step S11, a heavily doped first stop layer 104 and a second stop layer 102 are provided at the upper and lower adjacent portions of the multi-layer resonant cavity 103, wherein the first stop layer 104 is provided at the lower adjacent portion of the upper DBR layer 105, and the second stop layer 102 is provided at the upper adjacent portion of the lower DBR layer 101, thereby The first stop layer 104 and the second stop layer 102 are arranged at positions that reduce the length of the current path and effectively reduce the resistance of the series resistor; step S12, epitaxially forming a semiconductor structure according to the design structure; step S13, a negative electrode metal contact region is arranged on the side of the semiconductor structure, and etching is performed from top to bottom to the second stop layer 102 corresponding to the position of the negative electrode metal contact region to form a first high platform 11 in the central part of the semiconductor structure 10; step S14, Step S14, a positive metal contact area is set on one side of the first platform 11, and the positive metal contact area is etched from top to bottom to the first stop layer 104 corresponding to the position of the positive metal contact area so that a second platform 12 is formed on the first platform 11, and the area of the second platform 12 is smaller than that of the first platform 11; and step S15, a positive metal contact layer 106 is set on the first stop layer 104, and a negative metal contact layer 107 is set on the second stop layer 102.

It can be seen that the high-power surface-emitting laser structure 1 manufactured by the process method is provided with at least the substrate 100, the lower DBR layer 101, the second stop layer 102, the multi-layer resonant cavity 103, the first stop layer 104 and the upper DBR layer 105 from bottom to top. The high-power surface-emitting laser structure 1 has the first high platform 11 formed in the central part above the second stop layer 102, and the second high platform 12 with a relatively smaller area is formed on the first high platform 11. The negative metal contact layer 107 is provided on the second stop layer 102 next to the first high platform 11, and the positive metal contact layer 106 is provided on the first stop layer 104 next to the second high platform 12. The first stop layer 104 is disposed at a position adjacent to the lower DBR layer 105, that is, between the upper DBR layer 105 and the multi-layer resonant cavity 103; the second stop layer 102 is disposed at a position adjacent to the upper DBR layer 101, that is, between the lower DBR layer 101 and the multi-layer resonant cavity 103. The first stop layer 104 and the second stop layer 102 are arranged at the upper and lower adjacent positions of the multi-layer resonant cavity 103 to greatly shorten the distance between the positive metal contact layer 106 and the negative metal contact layer 107. In other words, the resistance of the series resistor corresponding to the current path of the component is greatly shortened to achieve the effect of effectively reducing the resistance value.

Please refer to Figures 3A, 3B, 4A-4E, which are respectively the flow chart and the process diagram of the second preferred embodiment of the present invention. As shown in the figure, the high-power surface-emitting laser structure 1 can improve the light resonance intensity and the output laser light power through a multi-layer resonant cavity 103, thereby meeting the application requirements of the current high-end market. The multi-layer resonant cavity 103 is formed by stacking a plurality of resonant chambers, so it has a higher resistance value than the conventional resonant cavity containing only a single active layer, which causes the component to have the disadvantage of high power consumption and is not conducive to industrial application. Therefore, in order to improve the ohmic contact to achieve an optimized low series resistance, the process method of the high-power surface-emitting laser structure 1 may include the following steps: Step S20, constructing a design structure, which at least stacks a substrate 100, a lower DBR layer 101, a multi-layer resonant cavity 103 and an upper DBR layer 105 from bottom to top, and the multi-layer resonant cavity 103 may be provided with 2 to 9 resonant chambers, and each of the resonant chambers may include at least a lower batch cladding layer 1030, an active layer 1031, an upper batch cladding layer 1032, an oxide layer 1033 and an upper isolation layer 1034 from bottom to top. The upper DBR layer 105 is provided with 22 to 30 upper double-layer stacking pairs 1050, and the lower DBR layer 101 is provided with 32 to 40 lower double-layer stacking pairs 1010.

Step S21: a first stop layer 104 and a second stop layer 102 of n/p type heavy doping are respectively set at a setting position at the upper and lower adjacent positions of the multi-layer resonant cavity 103, that is, the setting position of the first stop layer 104 is located at the lower adjacent position of the upper DBR layer 105; the setting position of the second stop layer 102 is located at the upper adjacent position of the lower DBR layer 101, so as to further determine the setting positions of a positive metal contact layer 106 and a negative metal contact layer 107 in the subsequent process through the setting positions of the first stop layer 104 and the second stop layer 102, thereby effectively reducing the resistance value of the series resistor. In this embodiment, each of the upper double-layer stacking pairs 1050 is an Al _(0.9) Ga _(0.1) As/Al _(0.1) Ga _(0.9) As stacking structure, and the first stop layer 104 is made of a phosphorus-containing material such as InP, InGaP, GaAsP or AlGaAsP. Therefore, when the first stop layer 104 is provided, one of the upper double-layer stacking pairs 1050 adjacent to the multi-layer resonant cavity 103 is replaced by an In _(x) Ga _(1-x) P/Al _(0.1) Ga _(0.9) As structure, where x is 0.56-0.71; each of the lower double-layer stacking pairs 1010 is an Al _(0.9) Ga _(0.1) As/Al _(0.1) Ga _(0.9) As stacked structure, and the second stop layer 102 is also made of phosphorus-containing materials such as InP, InGaP, GaAsP or AlGaAsP, so when the second stop layer 102 is set, the lower double-layer stack pair 1010 adjacent to the multi-layer resonant cavity 103 is replaced by an In _(x) Ga _(1-x) P/Al _(0.1) Ga _(0.9) As structure, and X is 0.56~0.71. Step S22, according to the design structure, epitaxially form a semiconductor structure 10.

Next, in step S23, a negative electrode metal contact region 13 is disposed around the semiconductor structure 10, and the upper DBR layer 105, the first stop layer 104 and the multi-layer resonant cavity 103 are etched from top to bottom to the position adjacent to the second stop layer 102 by dry etching, and then in step S230, an etching solution such as _NH4OH : _H2O2 with a formula ratio of _1:10 is used to wet-etch the remaining vertical structure portion above the second stop layer 102 to the second stop layer 102, so that a first high platform 11 is formed in the central portion of the semiconductor structure 10. In step S24, the multi-layer resonant cavity 103 in the first platform 11 is subjected to side oxidation, so that each of the oxide layers 1033 in each of the resonant cavities is provided with an oxide hole 10330.

In step S25, a positive metal contact region 14 is provided on one side of the first platform 11, and the upper DBR layer 105 is etched from top to bottom to the position adjacent to the upper portion of the first stop layer 104 by dry etching corresponding to the position of the positive metal contact region 14. Then in step S250, an etching solution such as _NH4OH : _H2O2 with a formula ratio of _1:10 is used to wet-etch the remaining vertical structure portion above the first stop layer 104 to the first stop layer 104, so that the upper portion of the first platform 11 forms a second platform 12 with a smaller area than the first platform 11. In this embodiment, when the first stop layer 104 and the second stop layer 102 are made of InGaAsP material, HCL:H ₃ PO ₄ etching solution can be used for wet etching; when the first stop layer 104 and the second stop layer 102 are made of InP or InGaP material, H ₃ PO ₄ :H ₂ O ₂ :H ₂ O etching solution can be used for wet etching; when the first stop layer 104 and the second stop layer 102 are made of InP material, H ₂ SO ₄ :H ₂ O ₂ :H ₂ O etching solution or C ₆ H ₈ O ₇ :H ₂ O ₂ etching solution can be used for wet etching.

In step S26, the positive electrode metal contact layer 106 is disposed on the first stop layer 104 by sputtering, and the negative electrode metal contact layer 107 is disposed on the second stop layer 102 by sputtering. Accordingly, by using the chemical reaction between the first stop layer 104 and the second stop layer 102 made of phosphorus-containing material and the etching solution, the etching rate is slowed down and the over-etching problem of the upper DBR layer 105 and the multi-layer resonant cavity 103 in the etching process can be avoided, thereby improving the positioning accuracy of the positive metal contact layer 106 and the negative metal contact layer 107, thereby achieving the effect of ensuring that the resistance of the series resistor corresponding to the component current path from the positive metal contact layer 106 to the negative metal contact layer 107 is constant. As mentioned above, the resistance value (R) of the series resistor of the high-power surface-emitting laser structure 1 manufactured by the process method can be R=R1+Ra+R2 as shown in FIG. 5 without considering the capacitance value, and R1 and R2 have extremely low resistance values because the first stop layer 104 and the second stop layer 102 are n/p-type heavily doped, which is beneficial to reduce the overall resistance value of the series resistor.

Furthermore, in order to solve the high resistance problem of the multi-layer resonant cavity 103, the present invention further proposes a component structure that shares the substrate and is in a parallel state. After the semiconductor structure 10 is epitaxially formed in step S22, step S27 is performed to etch from top to bottom at the center of the semiconductor structure 10 to the substrate 100, and the epitaxial layers such as the lower DBR layer 101, the first stop layer 102, the multi-layer resonant cavity 103, the second stop layer 102 and the upper DBR layer 105 above the substrate 100 are cut into two parts. Next, the two parts of the semiconductor structure 10 are processed through the subsequent steps S23 to S26 to form two high-power surface-emitting laser structures 1 that share the substrate 100. Then, in step S28, wire bonding is performed to connect the positive metal contact layers 106 of each high-power surface-emitting laser structure 1 to each other; and the negative metal contact layers 107 of each high-power surface-emitting laser structure 1 are connected to each other by wire bonding, so that the two high-power surface-emitting laser structures 1 are connected in parallel as shown in FIG. 6. Thus, through this parallel structure, when the multi-layer resonant cavity 103 of each high-power surface-emitting laser structure 1 has three layers of resonant chambers, the overall device can obtain the same device optical power as the six-layer resonant chamber series structure, but can maintain a relatively low device voltage, which is beneficial to reduce the device energy consumption rate and meet the market application requirements.

However, the above is only a preferred embodiment of the present invention and is not intended to limit the scope of implementation of the present invention; therefore, all equivalent changes and modifications made without departing from the spirit and scope of the present invention should be included in the patent scope of the present invention.

S10~S15: Steps

Claims (10)

A process method for a high-power surface-emitting laser with a low series resistance structure includes the following steps: constructing a design structure, which is stacked from bottom to top with a substrate, a lower DBR layer, a multi-layer resonant cavity and an upper DBR layer, wherein the multi-layer resonant cavity is provided with 2 to 9 resonant chambers, each of which is provided with an active layer, and the upper DBR layer is provided with 22 to 30 The upper double layer stacking pair is provided, and the lower DBR layer is provided with 32 to 40 lower double layer stacking pairs; a heavily doped first stop layer and a second stop layer are provided at the upper and lower adjacent parts of the multi-layer resonant cavity, wherein the first stop layer is provided at the lower adjacent part of the upper DBR layer, and the second stop layer is provided at the upper adjacent part of the lower DBR layer, thereby The setting position of the second stop layer and the setting position of the second stop layer effectively reduce the resistance value of the series resistor without considering the capacitance value; according to the design structure, a semiconductor structure is formed by epitaxial crystal; a negative electrode metal contact area is set on the side of the semiconductor structure, and a first metal contact area is formed in the center of the semiconductor structure by etching from top to bottom corresponding to the position of the negative electrode metal contact area to the second stop layer. A platform; a positive metal contact area is arranged on one side of the first platform, and the positive metal contact area is etched from top to bottom to the first stop layer corresponding to the position of the positive metal contact area so that a second platform is formed on the upper part of the first platform, and the area of the second platform is smaller than that of the first platform; and a positive metal contact layer is arranged on the first stop layer, and a negative metal contact layer is arranged on the second stop layer. The process method as described in claim 1, wherein the first stop layer and the second stop layer are made of phosphorus-containing materials such as InP, InGaP, GaAsP or AlGaAsP and are heavily doped with n/p type to reduce the etching rate and improve the positioning accuracy of the positive metal contact layer and the negative metal contact layer, thereby ensuring the resistance accuracy of the series resistor. A process method as described in claim 2, wherein each of the upper double-layer stacking pairs is an Al _(0.9) Ga _(0.1) As/Al _(0.1) Ga _(0.9) As stacking structure, and when the first stop layer is set, one of the upper double-layer stacking pairs adjacent to the multi-layer resonant cavity is replaced by an In _(x) Ga _(1-x) P/Al _(0.1) Ga _(0.9) As structure; and each of the lower double-layer stacking pairs is an Al _(0.9) Ga _(0.1) As/Al _(0.1) Ga _(0.9) As stacking structure, and when the second stop layer is set, one of the lower double-layer stacking pairs adjacent to the multi-layer resonant cavity is replaced by an In _(x) Ga _(1-x) P/Al _(0.1) Ga _(0.9) As structure, and X is 0.56~0.71. The manufacturing method as described in claim 3, wherein the negative electrode metal contact region is disposed on the peripheral side of the semiconductor structure, and the upper DBR layer, the first stop layer and the multi-layer resonant cavity are etched from top to bottom by dry etching corresponding to the position of the negative electrode metal contact region to the position adjacent to the upper part of the second stop layer, and then the remaining part above the second stop layer is etched to the second stop layer by wet etching, so that the first high platform is formed in the central part of the semiconductor structure; then, the The multi-layer resonant cavity is subjected to side oxidation so that an oxide hole is formed in an oxide layer disposed on the active layer in each resonant cavity, and the positive metal contact area is disposed on one side of the first platform, and the upper DBR layer is etched from top to bottom to the position adjacent to the upper part of the first stop layer by dry etching corresponding to the position of the positive metal contact area, and then the remaining part is etched to the first stop layer by wet etching, so that the upper part of the first platform forms the second platform. The process method as claimed in claim 4, wherein when etching to the stop layer by wet etching, an etching solution of NH ₄ OH:H ₂ O ₂ is used. The process method as claimed in claim 5, wherein when etching to the stop layer by wet etching, an etching solution of NH ₄ OH:H ₂ O ₂ with a formula ratio of 1:10 is used. The process method as described in claim 4, wherein when the first stop layer and the second stop layer made of InGaAsP material are etched by wet etching, HCL: _H3PO4 etching solution is used; when the first stop layer and the second stop layer made of InP or InGaP material _are etched by wet etching, _H3PO4 : _H2O2 : _{H2O etching} solution is _used . The process method as claimed in claim 4, wherein when the first stop layer and the second stop layer made of InP material are etched by wet etching, _an etching solution of _H2SO4 : _H2O2 : _{H2O or an} etching solution _{of C6H8O7 : H2O2 is} used. A high-power surface-emitting laser structure manufactured using the process method described in claim 1 to claim 8. As described in claim 9, the high-power surface-emitting laser structure, wherein when the semiconductor structure is epitaxially formed, etching is performed from top to bottom at the center of the semiconductor structure to the substrate, so as to form two high-power surface-emitting laser structures sharing the substrate through subsequent processes, and the positive metal contact layers of each high-power surface-emitting laser structure are mutually wired; the negative metal contact layers of each high-power surface-emitting laser structure are mutually wired, so that the two high-power surface-emitting laser structures are connected in parallel.