TWI843535B - Display panel - Google Patents

Abstract

This invention discloses a display panel which includes a sub-pixel, a first metal layer, a second metal layer, a transparent conductive layer and a third metal layer. The sub-pixel includes a switching element. The first metal layer includes a scan line electrically connected with the switch element. The second metal layer is disposed on the first metal layer and includes a pixel electrode and a data line, the pixel electrode and the data line are electrically connected with the switching element, and a portion of the data line includes a blackened layer. The transparent conductive layer includes a transparent electrode disposed on the pixel electrode and electrically connected with the pixel electrode. The third metal layer includes a reflective electrode disposed on the transparent electrode and electrically connected with the transparent electrode.

Description

Display panel

The present invention relates to a display panel, in particular to a reflective display panel.

In a reflective display panel, there are gaps between adjacent sub-pixels, and light reflected by the metal electrode may leak out from these gaps, resulting in poor contrast. Therefore, how to reduce light leakage in reflective display panels has become one of the important research issues for improving display quality.

The technical problem that this invention aims to solve is how to reduce light leakage from the display panel to improve display quality.

To solve the above technical problems, the present invention provides a display panel, including a display area and a non-display area, wherein the non-display area is arranged on at least one side of the display area. The display panel includes a first substrate, a first sub-pixel, a first metal layer, a second metal layer, a transparent conductive layer and a third metal layer. The first sub-pixel is arranged on the first substrate and in the display area, and the first sub-pixel includes a first switch element. The first metal layer is arranged on the first substrate, the first metal layer includes a plurality of first signal lines arranged in the display area, the first signal line includes a first scanning line electrically connected to the first switch element, and the first scanning line extends along a first direction. A second metal layer is arranged on the first metal layer, the second metal layer includes a first pixel electrode of the first sub-pixel and a plurality of second signal lines. The first pixel electrode is electrically connected to the first switch element. The second signal line is arranged in the display area, the second signal line includes a data line electrically connected to the first switch element, the data line extends along a second direction, the first direction and the second direction are different, and a portion of the data line includes a blackening layer. The transparent conductive layer is arranged on the second metal layer, the second metal layer is arranged between the transparent conductive layer and the first metal layer, the transparent conductive layer includes a first transparent electrode of the first sub-pixel, and the first transparent electrode is arranged on the first pixel electrode and electrically connected to the first pixel electrode. The third metal layer is arranged on the transparent conductive layer, the transparent conductive layer is arranged between the third metal layer and the second metal layer, the third metal layer includes a first reflective electrode of the first sub-pixel, and the first reflective electrode is arranged on the first transparent electrode and electrically connected to the first transparent electrode.

In the display panel of the present invention, part or all of the metal layer below the gap includes a blackened layer, which can reduce reflected light and reduce light leakage, thereby improving contrast.

10: Display panel

100,200: Substrate

100s: upper surface

102,108,116:Metal layer

104,110,112: Insulation layer

114: Transparent conductive layer

1180: Part 1

1182: Part 2

1200: Part 3

1202: Part 4

1220,1221,1260,1261:Edge

124: Black layer

1280,1282,1284: Sublayer

300: Liquid crystal layer

AA: Display area

CH: semiconductor layer

CE1, CE2, 202: Common electrode

CL: Public Line

D: Drain

DL1, DL2, DL3: data lines

G: Gate

GL1,GL2: Scan line

GP: Gap

IL: Ambient Light

PA: Non-display area

PE1, PE2: pixel electrodes

RE1,RE2: Reflection electrode

S: Source

SP,SP1,SP2: sub-pixel

SW1, SW2: switch components

TE1,TE2: Transparent electrode

V1, V2: contact holes

W1: First width

W2: Second width

X,Y,Z: Direction

Figure 1 is a schematic top view of the display panel of the first embodiment of the present invention.

Figure 2 is a top view schematic diagram of the pixel structure of the display panel of the first embodiment of the present invention.

Figure 3 is a schematic cross-sectional view of the display panel of the first embodiment of the present invention.

Figure 4 is a schematic cross-sectional view of the blackening layer of the first embodiment of the present invention.

Figure 5 is a schematic cross-sectional view of the blackening layer of the first variant embodiment of the first embodiment of the present invention.

Figure 6 is a schematic cross-sectional view of the blackening layer of the second variant embodiment of the first embodiment of the present invention.

Figure 7 is a schematic cross-sectional view of the display panel of the second embodiment of the present invention.

In order to enable technical personnel in this field to further understand the present invention, the preferred embodiments of the present invention are listed below, and the components and intended effects of the present invention are described in detail with the accompanying drawings. It should be noted that the accompanying drawings are simplified schematic diagrams, and therefore only show the components and combination relationships related to the present invention to provide a clearer description of the basic structure or implementation method of the present invention, while the actual components and layout may be more complicated. In addition, for the convenience of explanation, the components shown in the various drawings of the present invention are not drawn in proportion to the actual number, shape, and size, and the detailed proportions can be adjusted according to the design requirements.

The following figure shows a direction X (or a first direction), a direction Y (or a second direction), and a direction Z (or a vertical projection direction). Direction Z may be perpendicular to an upper surface 100s of a substrate 100 (as shown in FIG. 3 ), and direction X and direction Y may be parallel to the upper surface 100s of the substrate 100. Direction Z may be perpendicular to direction X and direction Y, and direction X may be perpendicular to direction Y. The following figure may describe the spatial relationship of the structure according to direction X, direction Y, and direction Z.

Please refer to Figures 1 to 4, Figure 1 is a schematic top view of the display panel of the first embodiment of the present invention, Figure 2 is a schematic top view of the pixel structure of the display panel of the first embodiment of the present invention, Figure 3 is a schematic cross-sectional view of the display panel of the first embodiment of the present invention, and Figure 4 is a schematic cross-sectional view of the blackening layer of the first embodiment of the present invention. The structure of Figure 3 may correspond to the section lines A-A', B-B' and C-C' in Figure 2. The display panel of this embodiment may be a reflective liquid crystal panel, but the present invention is not limited thereto.

As shown in FIG1 , the display panel 10 includes a display area AA and a non-display area PA. The non-display area PA is disposed on at least one side of the display area AA. As shown in FIG1 , the non-display area PA may surround the display area AA, but is not limited thereto. In addition, the display panel 10 includes a plurality of sub-pixels SP disposed in the display area AA. As shown in FIG1 and FIG2 , the display panel 10 includes a sub-pixel SP1 (or may be referred to as a first sub-pixel) and a sub-pixel SP2 (or may be referred to as a second sub-pixel), and the sub-pixel SP1 and the sub-pixel SP2 are disposed adjacent to each other in the direction X. Each sub-pixel SP includes at least one switching element. As shown in FIG2 , the sub-pixel SP1 includes a switching element SW1 (or may be referred to as a first switching element), and the sub-pixel SP2 includes a switching element SW2 (or may be referred to as a second switching element).

The switch element may include a thin film transistor, and the thin film transistor may be, for example, a bottom-gate thin film transistor, but is not limited thereto. In other embodiments, the thin film transistor may also be a top-gate thin film transistor. In addition, the thin film transistor may be a low temperature polysilicon (LTPS) thin film transistor, an indium gallium zinc oxide (IGZO) thin film transistor, or an amorphous silicon (a-Si) thin film transistor, but is not limited thereto.

As shown in FIG3 , the display panel 10 includes a substrate 100 (or may be referred to as a first substrate), a substrate 200 (or may be referred to as a second substrate), and a liquid crystal layer 300. The substrate 200 is disposed relative to the substrate 100 in the direction Z, and the liquid crystal layer 300 is disposed between the substrate 100 and the substrate 200. In addition, sub-pixels SP1, SP2 and switch elements SW1, SW2 are disposed on the substrate 100.

The substrates 100 and 200 may include hard substrates such as glass substrates, plastic substrates, quartz substrates or sapphire substrates, but are not limited thereto. The substrates 100 and 200 may also include flexible substrates such as polyimide (PI) substrates or polyethylene terephthalate (PET) substrates, but are not limited thereto. The liquid crystal layer 300 may include any suitable type of liquid crystal, but is not limited thereto.

As shown in FIG3 , the display panel 10 includes a metal layer 102 (or may be referred to as a first metal layer), an insulating layer 104, a metal layer 108 (or may be referred to as a second metal layer), an insulating layer 110, an insulating layer 112, a transparent conductive layer 114, and a metal layer 116 (or may be referred to as a third metal layer), but is not limited thereto.

The metal layer 102 is disposed on the substrate 100. The metal layer 102 includes a gate G of each switch element (such as the switch element SW1). The metal layer 102 includes a plurality of first signal lines disposed in the display area AA. As shown in FIG. 2 , the first signal line may include at least a scanning line GL1 (or may be referred to as a first scanning line), a scanning line GL2 (or may be referred to as a second scanning line) and a common signal line CL, but is not limited thereto. Scanning line GL1, scanning line GL2 and common signal line CL extend along direction X, scanning line GL1 and scanning line GL2 are arranged along direction Y, and common signal line CL is arranged between scanning line GL1 and scanning line GL2 in direction Y, that is, a common signal line can be arranged between two adjacent scanning lines in direction Y, but is not limited thereto.

Scan line GL1 is electrically connected to gate G of switch element SW1, and scan line GL2 is electrically connected to gate G of switch element SW2. In addition, metal layer 102 includes a common electrode CE1 (or first common electrode) of sub-pixel SP1 and a common electrode CE2 (or second common electrode) of sub-pixel SP2. Common electrode CE1 and common electrode CE2 are arranged along direction X, and common signal line CL electrically connects common electrode CE1 and common electrode CE2.

As shown in FIG3 , each switch element (such as switch element SW1) includes a semiconductor layer CH, the semiconductor layer CH and the metal layer 108 are disposed on the metal layer 102, and the insulating layer 104 is disposed between the semiconductor layer CH and the metal layer 102 and between the metal layer 108 and the metal layer 102. The semiconductor layer CH includes polycrystalline silicon, amorphous silicon or metal oxide, but is not limited thereto.

The metal layer 108 includes a plurality of second signal lines disposed in the display area AA, as shown in FIG2 , and the second signal lines may include at least one data line DL1, one data line DL2, and one data line DL3, but are not limited thereto. The data line DL1, the data line DL2, and the data line DL3 extend along the direction Y and are arranged along the direction X, and the data line DL1 is disposed between the data line DL2 and the data line DL3 in the direction X. The data line DL1 is electrically connected to a source S of the switch element SW1 and is electrically connected to a source S of the switch element SW2.

The metal layer 108 includes a pixel electrode of each sub-pixel. As shown in FIG2 , the metal layer 108 includes a pixel electrode PE1 (or a first pixel electrode) of the sub-pixel SP1 and a pixel electrode PE2 (or a second pixel electrode) of the sub-pixel SP2. The pixel electrode PE1 is electrically connected to a drain D of the switch element SW1, and the pixel electrode PE2 is electrically connected to the drain D of the switch element SW2. The metal layer 108 includes a source S and a drain D of each sub-pixel.

As shown in FIG2 , in the direction Z, the common electrode CE1 is disposed between the pixel electrode PE1 and the substrate 100, and the common electrode CE2 is disposed between the pixel electrode PE2 and the substrate 100. In the direction Y, the pixel electrode PE1, the common electrode CE1, the pixel electrode PE2 and the common electrode CE2 are disposed between the scanning line GL1 and the scanning line GL2, the pixel electrode PE1 and the common electrode CE1 are disposed above the switching element SW1 and the scanning line GL1, and the pixel electrode PE2 and the common electrode CE2 are disposed below the switching element SW2 and the scanning line GL2.

As shown in FIG3 , the insulating layer 110 is disposed on the metal layer 108 and the semiconductor layer CH, and the insulating layer 112, the transparent conductive layer 114 and the metal layer 116 are sequentially disposed on the insulating layer 110, but not limited thereto. The thickness of the insulating layer 112 may be greater than the thickness of the insulating layer 110, but not limited thereto. The insulating layer 104, the insulating layer 110 and the insulating layer 112 may include inorganic or organic insulating materials, but not limited thereto.

The insulating layer 110 includes a plurality of contact holes V1, each of which can expose a portion of the upper surface of a pixel electrode. As shown in FIG3 , the contact hole V1 passes through the insulating layer 110 and exposes a portion of the upper surface of the pixel electrode PE1. The insulating layer 112 includes a plurality of contact holes V2, each of which can expose a contact hole V1. As shown in FIG3 , the contact hole V2 passes through the insulating layer 112 and exposes the contact hole V1 and a portion of the upper surface of the insulating layer 110.

The transparent conductive layer 114 is disposed on the metal layer 108, and the metal layer 108 is disposed between the transparent conductive layer 114 and the metal layer 102. The transparent conductive layer 114 includes a transparent electrode for each sub-pixel. As shown in FIG2 , the transparent conductive layer 114 includes a transparent electrode TE1 (or a first transparent electrode) for the sub-pixel SP1 and a transparent electrode TE2 (or a second transparent electrode) for the sub-pixel SP2.

The transparent electrode TE1 is disposed on the pixel electrode PE1 and electrically connected to the pixel electrode PE1, and the transparent electrode TE2 is disposed on the pixel electrode PE2 and electrically connected to the pixel electrode PE2. As shown in FIG3 , the transparent electrode TE1 can extend into the contact hole V2 and the contact hole V1 and can contact the pixel electrode PE1. Similarly, the transparent electrode TE2 in FIG2 can also extend into the corresponding contact hole V2 and the contact hole V1 and can contact the pixel electrode PE2. The transparent conductive layer 114 may include indium tin oxide (ITO), indium zinc oxide (IZO) or aluminum zinc oxide (AZO), but is not limited thereto.

The metal layer 116 is disposed on the transparent conductive layer 114, and the transparent conductive layer 114 is disposed between the metal layer 116 and the metal layer 108. The metal layer 116 includes a reflective electrode for each sub-pixel. As shown in FIG2 , the metal layer 116 includes a reflective electrode RE1 (or a first reflective electrode) for the sub-pixel SP1 and a reflective electrode RE2 (or a second reflective electrode) for the sub-pixel SP2.

As shown in FIG3 , the reflective electrode RE1 is disposed on the transparent electrode TE1 and electrically connected to the transparent electrode TE1, the reflective electrode RE1 can contact the transparent electrode TE1, and the reflective electrode RE1 can also extend into the contact hole V2 and the contact hole V1. Similarly, the reflective electrode RE2 is disposed on the transparent electrode TE2 and electrically connected to the transparent electrode TE2, the reflective electrode RE2 can contact the transparent electrode TE2, and the reflective electrode RE2 can also extend into the contact hole V2 and the contact hole V1.

The metal layer 102 and the metal layer 108 may include a single metal layer such as aluminum, copper, titanium, tungsten, or a composite metal layer such as molybdenum/aluminum/molybdenum, titanium/aluminum/titanium, titanium/copper/titanium, titanium/copper..., but are not limited thereto. The metal layer 116 may include a suitable reflective metal material such as silver, and the conductive layer 116 may also include a single metal layer or a composite metal layer, but are not limited thereto.

The reflective electrode RE1, the transparent electrode TE1 and the pixel electrode PE1 can be electrically connected to each other and can be used together as pixel electrodes. Similarly, the reflective electrode RE2, the transparent electrode TE2 and the pixel electrode PE2 can be electrically connected to each other and can also be used together as pixel electrodes, but this is not limited to this.

There is a gap GP between the reflective electrode RE1 and the reflective electrode RE2. For example, the gap GP may be located between an edge 1220 of the reflective electrode RE1 and an edge 1221 of the reflective electrode RE2, but is not limited thereto.

As shown in FIG3 , a portion of the data line DL1 located below the gap GP in the direction Z includes a black layer 124. In other words, the gap GP and the black layer 124 of a portion of the data line DL1 partially overlap in the direction Z. The data line DL1 may also include the black layer 124 in its entirety, but is not limited thereto. In addition, as shown in FIG2 , the data line DL1, the data line DL2, and the data line DL3 may all be located below the corresponding gap GP and may all include the black layer 124 in part or in its entirety, but is not limited thereto.

When the gap GP is too large when manufacturing the reflective electrodes RE1 and RE2, the electric field in the display panel 10 may be unstable in the area near the gap GP, so the liquid crystal in the area cannot be effectively controlled. At this time, when an ambient light IL is incident from the substrate 200 into the display panel 10, and is reflected by the metal layer (such as the data line DL1) below the gap GP, the reflected light may penetrate the gap GP and emit from the display panel 10 to cause light leakage, thereby causing poor contrast.

However, in this embodiment, part or all of the metal layer (such as the data line DL1) below the gap GP includes a black layer 124, which can reduce the light leakage caused by the ambient light IL incident on the display panel 10 after being reflected by the metal layer, thereby improving the contrast. In addition, it is also possible to omit the shielding layer (such as a black matrix) on the substrate 200. Therefore, the shielding layer is not provided on the substrate 200 of this case, thereby saving costs.

In addition, in the metal layer 108 of the present embodiment, except for the portion below the gap GP (such as the data line DL1, the data line DL2 and/or the data line DL3), the remaining portion may not include a blackening layer, but the present invention is not limited thereto. In addition, the metal layer 102 of the present embodiment may not include a blackening layer, but the present invention is not limited thereto.

As shown in FIG. 4 , in this embodiment, the blackening layer 124 may include a single-layer structure, and the single-layer structure includes a blackening metal. The blackening metal may include blackening molybdenum, but is not limited thereto.

In addition, as shown in FIG. 2 , the transparent electrode may include designs with different widths. The transparent electrode TE1 includes a first portion 1180 and a second portion 1182. The pixel electrode PE1 may overlap with a portion of the first portion 1180 in the direction Z, and the first portion 1180 includes a first width W1 in the direction X. The second portion 1182 is disposed on one side of the first portion 1180 in the direction Y. As shown in FIG. 2 , the second portion 1182 may be disposed above the first portion 1180 in the direction Y, but is not limited thereto. The second portion 1182 includes a second width W2 in the direction X, and the second width W2 is greater than the first width W1.

The transparent electrode TE2 includes a third portion 1200 and a fourth portion 1202. As shown in FIG2 , the pixel electrode PE2 can overlap with a portion of the third portion 1200 in the direction Z. The fourth portion 1202 is disposed on one side of the third portion 1200 in the direction Y. As shown in FIG2 , the fourth portion 1202 can be disposed below the third portion 1200 in the direction Y, but is not limited thereto. The width of the fourth portion 1202 in the direction X is greater than the width of the third portion 1200 in the direction X.

In the existing display panel design, the transparent electrode does not have a retracted portion, that is, the edge of the transparent electrode is aligned with or overlaps the edge of the reflective electrode in the direction Z. However, in some embodiments of the present invention, the transparent electrode TE1 includes a retracted first portion 1180 and the transparent electrode TE2 includes a retracted third portion 1200 to increase the distance between the transparent electrode TE1 and the transparent electrode TE2, and make an edge 1260 of the transparent electrode TE1 away from the edge 1220 of the reflective electrode RE1 without overlapping each other, and also make an edge 1261 of the transparent electrode TE2 away from the edge 1221 of the reflective electrode RE2 without overlapping each other.

In addition, as shown in FIG. 3 , the display panel 10 includes a common electrode 202 disposed on the substrate 200, and the common electrode 202 is disposed between the liquid crystal layer 300 and the substrate 200. In this embodiment, the common electrode 202 may be formed entirely on the substrate 200 and not patterned, but is not limited thereto. In some embodiments, the common electrode 202 may be patterned.

The display panel of the present invention is not limited to the above-mentioned embodiments. Other embodiments of the present invention will be further disclosed below. However, in order to simplify the description and highlight the differences between the embodiments or variations, the same reference numerals are used below to mark the same components, and the repeated parts will not be elaborated.

Please refer to FIG. 5 , which is a cross-sectional schematic diagram of the blackening layer of the first variant embodiment of the first embodiment of the present invention. The difference from the first embodiment is that the blackening layer 124 in this variant embodiment includes a stacked structure. As shown in FIG. 5 , the stacked structure may include a sublayer 1280 and a sublayer 1282, but the number of sublayers is not limited thereto. Sublayer 1280 is disposed on sublayer 1282. Since blackening layer 124 can be disposed on substrate 100, sublayer 1282 can be closer to substrate 100 and sublayer 1280 can be farther from substrate 100, and sublayer 1282 can be disposed between sublayer 1280 and substrate 100. In the stacked structure, the sublayer farthest from the substrate 100 (i.e., sublayer 1280) includes blackened metal (such as blackened molybdenum), but is not limited thereto. Sublayer 1282 may include non-blackened metal, such as aluminum, but is not limited thereto. The stacked structure of the blackened layer 124 in this variant embodiment may be applied to other embodiments of the present invention.

Please refer to FIG. 6, which is a cross-sectional schematic diagram of the blackening layer of the second variant embodiment of the first embodiment of the present invention. The difference from the first variant embodiment is that the stacked structure in this variant embodiment may include a sublayer 1280, a sublayer 1282 and a sublayer 1284, but the number of sublayers is not limited thereto.

Since the black layer 124 can be disposed on the substrate 100, the sub-layer 1284 can be closer to the substrate 100, the sub-layer 1280 can be farther from the substrate 100, the sub-layer 1284 can be disposed between the sub-layer 1280 and the substrate 100, and the sub-layer 1282 can be disposed between the sub-layer 1280 and the sub-layer 1284.

In the stacked structure, the sublayer farthest from the substrate 100 (i.e., sublayer 1280) includes blackened metal (such as blackened molybdenum), but is not limited thereto. Sublayer 1282 and sublayer 1284 may include non-blackened metal. Sublayer 1282 may include aluminum, and sublayer 1284 may include molybdenum, but is not limited thereto. The stacked structure of the blackened layer 124 in this variant embodiment may be applied to other embodiments of the present invention.

Please refer to FIG. 7, which is a cross-sectional schematic diagram of a display panel of the second embodiment of the present invention. The difference from the first embodiment is that the metal layer 102 and the metal layer 108 in this embodiment both include a blackening layer 124, but not limited thereto. More specifically, the entire metal layer 102 and the entire metal layer 108 both include a blackening layer 124, so all devices in the metal layer 102 and all devices in the metal layer 108 can be formed by the blackening layer 124.

In some embodiments, the entire metal layer 108 may include the blackening layer 124, and the metal layer 102 may not include the blackening layer 124, but the present invention is not limited thereto. In some embodiments, the entire or a portion of the metal layer 108 may include the stacked structure of the blackening layer 124 in FIG. 5 or FIG. 6, but the present invention is not limited thereto. In some embodiments, the entire or a portion of the metal layer 102 may include the stacked structure of the blackening layer 124 in FIG. 5 or FIG. 6, but the present invention is not limited thereto.

In summary, in the display panel of the present invention, part or all of the metal layer below the gap includes a blackened layer, so that the ambient light incident into the display panel and reflected by the metal layer can be reduced to cause light leakage, thereby improving the contrast. The transparent electrode includes a retracted portion, so that the edge of the transparent electrode is far away from the edge of the reflective electrode and no longer overlaps with each other. Even if the manufacturing deviation of the reflective electrode is large, the phenomenon of residual metal material of the reflective electrode can be reduced, and the short circuit caused by the migration of residual metal ions is also reduced.

The above is only a preferred embodiment of the present invention and is not intended to limit the present invention. For technicians in this field, the present invention may have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

100,200: Substrate

100s: upper surface

102,108,116:Metal layer

104,110,112: Insulation layer

114: Transparent conductive layer

1220,1221:Edge

124: Black layer

202,CE1: Common electrode

300: Liquid crystal layer

CH: semiconductor layer

D: Drain

DL1: Data line

G: Gate

GL1: Scan line

GP: Gap

IL: Ambient Light

PE1: Pixel electrode

RE1,RE2: Reflection electrode

S: Source

SW1: switch element

TE1: Transparent electrode

V1, V2: contact holes

X,Y,Z: Direction

Claims (10)

A display panel comprises: a display area and a non-display area, wherein the non-display area is arranged on at least one side of the display area; a first substrate; a first sub-pixel is arranged on the first substrate and in the display area, and the first sub-pixel includes a first switch element; a first metal layer is arranged on the first substrate, the first metal layer includes a plurality of first signal lines arranged in the display area, the plurality of first signal lines include a first scanning line electrically connected to the first switch element, and the first scanning line is arranged along The display area includes a first sub-pixel and a second metal layer, the second metal layer including: a first pixel electrode of the first sub-pixel, the first pixel electrode being electrically connected to the first switch element; and a plurality of second signal lines arranged in the display area, the plurality of second signal lines including a data line being electrically connected to the first switch element, the data line extending along a second direction, the first direction and the second direction being different, and a portion of the data line including a black layer; a transparent conductive layer; a transparent conductive layer disposed on the second metal layer, the second metal layer disposed between the transparent conductive layer and the first metal layer, the transparent conductive layer including a first transparent electrode of the first sub-pixel, and the first transparent electrode disposed on the first pixel electrode and electrically connected to the first pixel electrode; a third metal layer disposed on the transparent conductive layer, the transparent conductive layer disposed between the third metal layer and the second metal layer, the third metal layer including a first reflective electrode of the first sub-pixel , and the first reflective electrode is disposed on the first transparent electrode and electrically connected to the first transparent electrode; and a second sub-pixel is disposed on the first substrate, the first sub-pixel and the second sub-pixel are disposed adjacent to each other in the first direction; wherein there is a gap between the first sub-pixel and the second sub-pixel, and the gap and the blackened layer of the portion of the data line partially overlap in a vertical projection direction, wherein the vertical projection direction is perpendicular to an upper surface of the first substrate. The display panel as described in claim 1, wherein the second sub-pixel includes: a second switch element disposed on the first substrate; a second pixel electrode electrically connected to the second switch element, and the second metal layer includes the second pixel electrode; a second transparent electrode disposed on the second pixel electrode and electrically connected to the second pixel electrode, and the transparent conductive layer includes the second transparent electrode; and a second reflective electrode disposed on the second transparent electrode and electrically connected to the second transparent electrode, the third metal layer includes the second reflective electrode, and the first reflective electrode and the second reflective electrode have the gap between them. A display panel as described in claim 2, wherein the first metal layer includes a first common electrode of the first sub-pixel, a second common electrode of the second sub-pixel and a common signal line, and the plurality of first signal lines of the first metal layer include a second scan line, wherein the second scan line extends along the first direction and is electrically connected to the second switch element, and the second switch element is electrically connected to the data line, wherein the first common electrode is disposed between the first pixel electrode and the first substrate, the second common electrode is disposed between the second pixel electrode and the first substrate, and the common signal line extends along the first direction and is electrically connected to the first common electrode and the second common electrode. A display panel as described in claim 1, wherein all of the second metal layers include the blackening layer. A display panel as described in claim 4, wherein all of the first metal layers include the blackening layer. A display panel as described in claim 1, wherein the blackening layer includes a stacked structure, and a first sublayer in the stacked structure that is farthest from the first substrate includes a blackening metal. A display panel as described in claim 6, wherein the stacked structure includes a second sublayer disposed between the first sublayer and the first substrate, and the second sublayer includes an unblackened metal. A display panel as described in claim 6, wherein the stacked structure includes a second sublayer and a third sublayer, the second sublayer is disposed between the first sublayer and the first substrate, the third sublayer is disposed between the first sublayer and the second sublayer, and the second sublayer and the third sublayer include an unblackened metal. A display panel as described in claim 1, wherein the blackening layer comprises a single-layer structure, and the single-layer structure comprises a blackening metal. The display panel as described in claim 1 further comprises: a second substrate disposed opposite to the first substrate in the vertical projection direction, and a shielding layer is not disposed on the second substrate; and a liquid crystal layer disposed between the first substrate and the second substrate.

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