TWI843434B - Memory device and in-memory search methode thereof - Google Patents

Abstract

A memory device and an in-memory search method are provided. The in-memory search includes: providing, in a first step, a first voltage or a second voltage to a word line of at least one selected memory cell according to a logical status of a searched data, and reading a first current; providing, in a second step, a third voltage or a fourth voltage to the word line of the at least one selected memory cell according to the logical status of the searched data, and reading a second current; obtaining a search result according to a difference of the second current and the first current.

Description

Memory device and in-memory search method thereof

The present invention relates to a memory device and a method for searching in the memory, and in particular to a memory device and a method for searching in the memory that do not require setting up reference memory cells.

With the rise of hardware accelerators for big data and artificial intelligence, data matching/searching has become an indispensable function. In the existing technology, the so-called ternary content addressable memory (TCAM) can achieve highly parallel data search. The ternary content addressable memory in the known technology is often composed of static memory, so it often has problems of insufficient storage density and high power consumption.

In response to this, the known technology proposes to use non-volatile memory to implement ternary content addressable memory. However, in the known technology, a non-volatile memory cell is always required to store data, and another non-volatile memory cell is used as a reference memory cell to complete the search action of one bit of data. As a result, the memory device requires a larger circuit area and causes waste.

The present invention provides a memory device and a method for searching in memory thereof, which performs a data search in memory in a two-stage manner.

The in-memory search method of the present invention includes: according to the logical state of the data to be searched, in the first stage, providing a first voltage or a second voltage to the word line of at least one target memory cell, and reading a first current; according to the logical state of the data to be searched, in the second stage, providing a third voltage or a fourth voltage to the word line of at least one target memory cell, and reading a second current; obtaining a search result according to the difference between the first current and the second current, wherein the first voltage is less than the third voltage, the third voltage is less than or equal to the second voltage, and the second voltage is less than the fourth voltage.

The memory device of the present invention includes a memory cell array and a controller. The controller is coupled to the memory cell array. The controller is used to: provide a first voltage or a second voltage to a word line of at least one target memory cell and read a first current in a first stage according to the logic state of the data to be searched; provide a third voltage or a fourth voltage to a word line of at least one target memory cell and read a second current in a second stage according to the logic state of the data to be searched; obtain a search result according to the difference between the first current and the second current, wherein the first voltage is less than the third voltage, the third voltage is less than or equal to the second voltage, and the second voltage is less than the fourth voltage.

Based on the above, the present invention can use a single non-volatile memory cell to complete the search operation in the memory without setting a reference memory cell through a two-stage method. It effectively improves the utilization rate of the memory cell, increases the capacity of the search in the memory, and reduces the circuit area required for the memory device.

210~240: Distribution curve

400, 500, 620: memory cell array

700: Memory device

710: Controller

BL1~BL3: bit line

C1~C8: memory cell group

EG1~EG4:Boundary

HD similarity information

I: Reference current value

I1, Isp1: first current

I2, Isp2: second current

S1, S2: Stage

S110~S130: Steps

SA1~SA3: sensor amplifier

SHD: Data to be searched

SL1~SL4: Source line

SMC: Select memory cell

STD:Data

VSL1: first voltage

VSL2: Second voltage

VSL2’: third voltage

VSL4: Fourth voltage

VT: critical voltage

WL1~WL8: character line

FIG1 is a flow chart of an in-memory search method according to an embodiment of the present invention.

FIG2 is a schematic diagram showing the operation of the in-memory search method of an embodiment of the present invention.

Figures 3A to 3E are schematic diagrams showing the implementation of the in-memory search action for a single selected memory cell in an embodiment of the present invention.

FIG4 is a schematic diagram showing the implementation of the search action of multiple bits in the memory search method of the embodiment of the present invention.

FIG5 is a schematic diagram showing another implementation of the search action of multiple bits in the memory search method of the embodiment of the present invention.

FIG6 is a schematic diagram showing another implementation of the search action of multiple bits in the memory search method of the embodiment of the present invention.

FIG7 is a schematic diagram of a memory device according to an embodiment of the present invention.

Please refer to FIG. 1 and FIG. 2 simultaneously, wherein FIG. 1 is a flow chart of a memory search method according to an embodiment of the present invention. FIG. 2 is a schematic diagram of the operation of the memory search method according to an embodiment of the present invention. The vertical axis of FIG. 2 is the number of memory cells, and the horizontal axis is the critical voltage VT of the memory cells. The distribution curves 210 to 240 are respectively the distribution ranges of the critical voltages of memory cells with different storage data. The distribution curve 210 is, for example, the distribution range of the critical voltage of the memory cell storing the data of logic 0; the distribution curve 220 is, for example, the distribution range of the critical voltage of the memory cell storing the data of logic 1; the distribution curves 230 and 240 are both the distribution range of the critical voltage of the memory cell storing invalid data. In this embodiment, the distribution curve 210 has a lower boundary EG1 and an upper boundary EG2, wherein the lower boundary EG1 is smaller than the upper boundary EG2. The distribution curve 220 has a lower boundary EG3 and an upper boundary EG4, wherein the lower boundary EG3 is smaller than the upper boundary EG4, and the lower boundary EG3 is larger than the upper boundary EG2.

Please refer to FIG. 1. The steps in FIG. 1 can be executed by a controller in a memory device. In step S110, the controller can provide a first voltage VSL1 or a second voltage VSL2 to a word line of at least one target memory cell in a first stage according to the logical state of the data to be searched, and read a first current. As shown in FIG. 2, the first voltage VSL1 is less than the lower boundary EG1, and the second voltage VSL2 is greater than the upper boundary EG2.

In step S120, the controller can provide a third voltage VSL2' or a fourth voltage VSL4 to the word line of at least one target memory cell in the second stage according to the logic state of the data to be searched, and read the second current. As shown in FIG2, the third voltage VSL2' is greater than or equal to the second voltage VSL2, and the third voltage VSL2' is greater than the upper boundary EG2 and less than the lower boundary EG3. The fourth voltage VSL3 is greater than the upper boundary EG4.

Next, in step S130, the controller can subtract the second current from the first current, and generate a search result based on whether the difference between the second current and the first current is greater than a preset current threshold. In this embodiment, when the difference between the second current and the first current is greater than the preset current, the controller can generate a matching search result. Conversely, if the difference between the second current and the first current is not less than the preset current and approaches 0, the controller can generate an unmatched search result.

To further explain, when the logic state of the data to be searched is logic 0, in the first stage (step S110), the controller can provide a relatively low first voltage VSL1 to the word line of the target memory cell performing the search action, and perform a read action on the target memory cell to obtain a first current. Since the first voltage VSL1 is lower than the lower boundary EG1, regardless of whether the data stored in the target memory cell is logic 0 or logic 1, the first current obtained by performing a read action on the target memory cell tends to be close to 0.

Then, the controller can provide a third voltage VSL2' to the word line of the target memory cell performing the search action in the second stage (step S120), and perform a read action on the target memory cell to obtain a second current. Wherein, based on the third voltage VSL2' being higher than the upper boundary EG2 but lower than the lower boundary EG3. Therefore, when the data stored in the target memory cell is logical 0, the second current can be a reference current value greater than 0. When the data stored in the target memory cell is logical 1, the second current can be close to 0.

Therefore, when the logic state of the data to be searched is logic 0, and the data stored in the target memory cell is logic 0, the controller can calculate that the difference between the second current and the first current is equal to the reference current value (greater than the preset current threshold), and can generate a corresponding search result. Conversely, when the logic state of the data to be searched is logic 0, and the data stored in the target memory cell is logic 1, the controller can calculate that the difference between the second current and the first current is close to 0 (less than the preset current threshold), and can generate a corresponding search result that does not match.

On the other hand, when the logic state of the data to be searched is logic 1, in the first stage (step S110), the controller may provide a second voltage VSL2 to the word line of the target memory cell performing the search action, and perform a read action on the target memory cell to obtain a first current. Wherein, based on the second voltage VSL2 being between the upper boundary EG2 and the lower boundary EG3, if the data stored in the target memory cell is logic 0, the first current obtained by performing the read action on the target memory cell may be a reference current value greater than 0. On the other hand, if the data stored in the target memory cell is logical 1, the first current obtained by performing a read operation on the target memory cell may be close to 0.

Next, when the logic state of the data to be searched is logic 1, in the second stage (step S120), the controller can provide a fourth voltage VSL4 to the word line of the target memory cell performing the search action, and perform a read action on the target memory cell to obtain a second current. Wherein, based on the fourth voltage VSL2 being greater than the upper boundary EG4, regardless of whether the data stored in the target memory cell is logic 0 or 1, the second current obtained by performing a read action on the target memory cell can be a reference current value greater than 0.

Therefore, when the logic state of the data to be searched is logic 1, and the data stored in the target memory cell is logic 0, the controller can calculate that the difference between the second current and the first current is close to 0 (less than the preset current threshold), and can generate a corresponding incompatible search result. Conversely, when the logic state of the data to be searched is logic 0, and the data stored in the target memory cell is logic 1, the controller can calculate that the difference between the second current and the first current is equal to the reference current value (greater than the preset current threshold), and can generate a corresponding matching search result.

It is worth mentioning that when the logic state of the data to be searched is don’t care (also known as wild card state), the controller can provide the first voltage VSL1 to the word line of the target memory cell in the first stage and perform a read operation on the target memory cell. Regardless of whether the data stored in the target memory cell is logic 0 or logic 1, the first voltage VSL1 is less than the critical voltage of the target memory cell, and the first current close to 0 can be obtained by performing a read operation on the target memory cell. In addition, in the second stage, the controller can provide the fourth voltage VSL3 to the word line of the target memory cell and perform a read operation on the target memory cell. Regardless of whether the data stored in the target memory cell is logic 0 or logic 1, the fourth voltage VSL3 is greater than the critical voltage of the target memory cell. Therefore, a second current equal to the reference current value can be obtained by reading the target memory cell. In this way, the difference between the second current and the first current can be greater than the preset current threshold, and the controller can generate a corresponding search result.

In addition, when the data stored in the selected memory cell is invalid data, the first current obtained by the controller in the first stage and the second current obtained in the second stage will be substantially equal (both approach 0 or are equal to the reference current value). Therefore, the controller can generate an inconsistent search result by calculating the difference between the second current and the first current.

Please refer to Figures 3A to 3E below, which are schematic diagrams of the implementation of the in-memory search action for a single selected memory cell in an embodiment of the present invention. In Figure 3A, the logic state of the data to be searched is logic 0, and the data stored in the selected memory cell SMC is logic 0. When performing the search action, the word line WL1 of the selected memory cell SMC can receive a first voltage VSL1 in the first stage S1. The source line SL1 of the selected memory cell SMC can receive a bias voltage, and a read action can be performed on the selected memory cell SMC. Since the first voltage VSL1 is lower than the critical voltage of the selected memory cell SMC, in the first stage S1, no current will be generated on the bit line BL1 of the selected memory cell SMC (the first current approaches 0).

In the second stage S2, the word line WL1 of the selected memory cell SMC can receive the third voltage VSL2' and perform a read operation of the selected memory cell SMC. Because the second voltage VSL2' is higher than the critical voltage of the selected memory cell SMC, a second current I2 equal to the reference current value can be generated on the bit line BL1 of the selected memory cell SMC.

In this embodiment, by calculating the difference between the second current I2 and the first current (approaching 0), the search result of the selected memory cell SMC in FIG. 3A is consistent.

In FIG. 3B , the logic state of the data to be searched is logic 1, and the data stored in the selected memory cell SMC is logic 0. When performing the search action, the word line WL1 of the selected memory cell SMC can receive the second voltage VSL2 in the first stage S1, and perform a read action on the selected memory cell SMC. Based on the second voltage VSL2 being higher than the critical voltage of the selected memory cell SMC, in the first stage S1, a first current I1 (equal to the reference current value) can be generated on the bit line BL1 of the selected memory cell SMC.

In the second stage S2, the word line WL1 of the selected memory cell SMC can receive the fourth voltage VSL3 and perform a read operation of the selected memory cell SMC. Because the fourth voltage VSL3 is higher than the critical voltage of the selected memory cell SMC, a second current I2 equal to the reference current value can be generated on the bit line BL1 of the selected memory cell SMC.

In this embodiment, by calculating the difference between the second current I2 and the first current I1, the search result of the selected memory cell SMC in FIG3B is inconsistent.

In FIG. 3C , the logic state of the data to be searched is logic 0, and the data stored in the selected memory cell SMC is logic 1. When performing the search operation, the word line WL1 of the selected memory cell SMC can receive the first voltage VSL1 in the first stage S1, and a read operation can be performed on the selected memory cell SMC. Since the first voltage VSL1 is lower than the critical voltage of the selected memory cell SMC, no current will be generated on the bit line BL1 of the selected memory cell SMC in the first stage S1 (the first current approaches 0).

In the second stage S2, the word line WL1 of the selected memory cell SMC can receive the third voltage VSL2' and perform a read operation on the selected memory cell SMC. Since the second voltage VSL2' is lower than the critical voltage of the selected memory cell SMC, no current will be generated on the bit line BL1 of the selected memory cell SMC (the second current approaches 0).

In this embodiment, by calculating the difference between the second current and the first current, the search result of the selected memory cell SMC in FIG3C is inconsistent.

In FIG. 3D , the logic state of the data to be searched is logic 1, and the data stored in the selected memory cell SMC is logic 1. When performing the search action, the word line WL1 of the selected memory cell SMC can receive the second voltage VSL2 in the first stage S1, and perform a read action on the selected memory cell SMC. Because the second voltage VSL2 is lower than the critical voltage of the selected memory cell SMC, in the first stage S1, no current is generated on the bit line BL1 of the selected memory cell SMC (the first current approaches 0).

In the second stage S2, the word line WL1 of the selected memory cell SMC can receive the fourth voltage VSL3 and perform a read operation of the selected memory cell SMC. Because the fourth voltage VSL3 is higher than the critical voltage of the selected memory cell SMC, a second current I2 equal to the reference current value can be generated on the bit line BL1 of the selected memory cell SMC.

In this embodiment, by calculating the difference between the second current I2 and the first current (approaching 0), the search result of the selected memory cell SMC in FIG3D is consistent.

In FIG. 3E , the logic state of the data to be searched is don't care, and the data stored in the selected memory cell SMC can be logic 0 or logic 1. When performing the search action, the word line WL1 of the selected memory cell SMC can receive the first voltage VSL1 in the first stage S1, and perform a read action on the selected memory cell SMC. Because the first voltage VSL1 is lower than the critical voltage of the selected memory cell SMC, in the first stage S1, no current is generated on the bit line BL1 of the selected memory cell SMC (the first current approaches 0).

In the second stage S2, the word line WL1 of the selected memory cell SMC can receive the fourth voltage VSL3 and perform a read operation of the selected memory cell SMC. Because the fourth voltage VSL3 is higher than the critical voltage of the selected memory cell SMC, a second current I2 equal to the reference current value can be generated on the bit line BL1 of the selected memory cell SMC.

In this embodiment, by calculating the difference between the second current I2 and the first current (approaching 0), no matter the data stored in the selected memory cell is logical 0 or logical 1, the search result of the selected memory cell SMC in FIG. 3E is consistent.

Please refer to FIG. 4, which is a schematic diagram of an implementation method of the search action of multiple bits in the memory search method of the embodiment of the present invention. In this implementation method, the memory cell array 400 is a NOR flash memory cell array. The memory cell array 400 has a plurality of bit lines BL1 to BL3, a plurality of source lines SL1 to SL4, and a plurality of word lines WL1 to WL8. In the memory cell array 400, each bit line BL1 to BL3 has a plurality of memory cells respectively coupled to the word lines WL1 to WL8. The bit lines BL1 to BL3 are also respectively coupled to the sense amplifiers SA1 to SA3.

In this embodiment, the data stored in the memory cells corresponding to the word lines WL1 to WL8 on the bit line BL1 are logic 0, logic 0, logic 1, logic 1, logic 0, logic 1, logic 0, and logic 1. The data stored in the memory cells corresponding to the word lines WL1 to WL8 on the bit line BL2 are logic 1, logic 0, invalid data, invalid data, logic 1, logic 1, logic 0, and logic 1. On the bit line BL3, the memory cells corresponding to the word lines WL1~WL8 store data of logic 0, logic 1, logic 1, logic 0, logic 0, logic 0, logic 1, logic 0. In this embodiment, the memory search operation can be performed synchronously for multiple memory cells on the bit lines BL1~BL3.

其中無效資料1對應圖2的分布曲線230，無效資料2對應圖2的分布曲線240。I則為一個單位電流值(大於0)。 In the memory search operation, the relationship between the memory cell's storage data, search data, and the corresponding current generated can be expressed as shown in Table 1:

Invalid data 1 corresponds to the distribution curve 230 of FIG. 2 , and invalid data 2 corresponds to the distribution curve 240 of FIG. 2 . I is a unit current value (greater than 0).

In this embodiment, the data to be searched in the memory search action has, for example, eight bits, and its logical value is 100111XX, where X is don't care. 100111XX corresponds to the memory cells on word lines WL1 to WL8 respectively. When performing the memory search action, in the first stage S1, the second voltage VSL2, the first voltage VSL1, the first voltage VSL1, the second voltage VSL2, the second voltage VSL2, the second voltage VSL2, the second voltage VSL2, the first voltage VSL1, and the first voltage VSL1 can be applied to the word lines WL1 to WL8 respectively, and the memory cells are read. In the first stage S1 of the read operation, the memory cells on the bit line BL1 and the memory cells on the word lines WL1 and WL5 generate a first current equal to the reference current value, and the memory cells on the remaining word lines WL2-4 and WL6-8 generate a first current close to 0; the memory cells on the bit line BL2 and the memory cells on the word line WL3 generate a first current equal to the reference current value. The first current is generated by the memory cells on the remaining word lines WL1, WL2, WL4~8, which are close to 0; the memory cells on the bit line BL3, which correspond to the memory cells on the word lines WL1, WL4~WL6, generate the first current equal to the reference current value, and the memory cells on the remaining word lines WL2, WL3, WL7, and WL8 generate the first current close to 0.

Next, in the second stage S2, the fourth voltage VSL3, the third voltage VSL2', the third voltage VSL2', the fourth voltage VSL3, the fourth voltage VSL3, the fourth voltage VSL3, the fourth voltage VSL3, the fourth voltage VSL3, the fourth voltage VSL3, and the fourth voltage VSL3 can be applied to the word lines WL1~WL8 respectively, and the memory cells are read. In the reading operation of the second stage S2, the memory cells on the bit line BL1 corresponding to the memory cells of the word lines WL1, WL2, and WL4~8 generate a second current equal to the reference current value, and the memory cells on the remaining word line WL3 generate a second current close to 0; the memory cells on the bit line BL2 corresponding to the memory cells of the word lines WL1~WL3, WL5~WL8 The memory cells generate a second current equal to the reference current value, and the memory cells on the remaining word lines WL4 generate a second current close to 0; the memory cells on the bit line BL3, corresponding to the memory cells on the word lines WL1, WL4~WL8, generate a second current equal to the reference current value, and the memory cells on the remaining word lines WL3 and WL4 generate a second current close to 0.

The sense amplifiers SA1-SA3 can respectively generate a difference for the memory cells on the bit lines BL1-BL3 by subtracting the sum of the first currents generated in the first stage S1 from the sum of the second currents generated in the second stage S2, thereby generating a search result. In this embodiment, the bit lines BL1-BL3 having a relatively large difference can have a relatively high similarity with the desired search data. In this embodiment, the sense amplifier SA1 can sense that the difference on the bit line BL1 is 5 reference current values, and can generate similarity information HD=3 (the number of bits of the data to be searched is 8 minus the multiple relationship between the difference and the reference current value, which is 5); the sense amplifier SA2 can sense that the difference on the bit line BL2 is 6 reference current values, and can generate similarity information HD=2; the sense amplifier SA3 can sense that the difference on the bit line BL3 is 2 reference current values, and can generate similarity information HD=6. Among them, the memory cell on the bit line BL2 corresponding to the similarity information HD=2 with the lowest value has the highest similarity with the data to be searched, and the memory cell on the bit line BL3 corresponding to the similarity information HD=6 with the highest value has the lowest similarity with the data to be searched.

Please refer to FIG. 5 below, which is a schematic diagram of another implementation of the search action of multiple bits in the memory search method of the embodiment of the present invention. In this implementation, the memory cell array 500 is an AND-type flash memory cell array. The memory cell array 500 has a plurality of bit lines BL1-BL3, a plurality of source lines SL1-SL4, and a plurality of word lines WL1-WL8. In the memory cell array 500, each bit line BL1-BL3 has a plurality of memory cells respectively coupled to the word lines WL1-WL8. The bit lines BL1-BL3 are also respectively coupled to the sense amplifiers SA1-SA3.

In the present embodiment, the data stored in the memory cells on the bit lines BL1 to BL3 in the memory cell array 500 is the same as the data stored in the memory cells at the corresponding positions in the memory cell array 400. In the in-memory search operation, the logical value of the data to be searched is also 100111XX. When performing the in-memory search operation, in the first stage S1, the second voltage VSL2, the first voltage VSL1, the first voltage VSL1, the second voltage VSL2, the second voltage VSL2, the second voltage VSL2, the first voltage VSL1, and the first voltage VSL1 may be applied to the word lines WL1 to WL8, respectively, and a read operation may be performed on the memory cells. In the second stage S2, the fourth voltage VSL3, the third voltage VSL2', the third voltage VSL2', the fourth voltage VSL3, the fourth voltage VSL3, the fourth voltage VSL3, the fourth voltage VSL3, the fourth voltage VSL3, and the fourth voltage VSL3 can be applied to the word lines WL1~WL8 respectively, and the memory cell can be read.

The sense amplifiers SA1~SA3 respectively calculate the differences between the currents on the bit lines BL1~BL3 in the second stage S2 and the currents on the bit lines BL1~BL3 in the first stage S1, and respectively generate search results and similarity information HD according to the above-mentioned multiple differences. The similarity information HD generated by the sense amplifiers SA1~SA3 is equal to 3, 2 and 6 respectively.

Please refer to FIG. 6 below, which is a schematic diagram of another embodiment of the search action of multiple bits in the memory search method of the embodiment of the present invention. In this embodiment, the memory cell array has multiple memory cell groups C1~C8. Each memory cell group, for example, has three memory cells corresponding to three different word lines. In this embodiment, the memory cell groups C1~C8 store different data STDs such as 000, 001, 010, 011, 100, 101, 110, 111, etc. In addition, the data SHD to be searched is, for example, 010. When performing the search action in the memory, the controller can perform the search action on the memory cell groups C1~C8 in chronological order.

In the memory search operation, the relationship between the memory cell's storage data, search data, and the corresponding current generated can be shown in the aforementioned Table 1.

For example, in the first time period, the controller may generate a first voltage or a second voltage corresponding to the first stage according to the search data SHD to provide to the word line of the memory cell group C1, and perform a read operation on the memory cell group C1 to obtain a plurality of first currents Isp1. In this embodiment, the first current Isp1 is equal to 1 reference current value I. The controller may also generate a third voltage or a fourth voltage corresponding to the second stage according to the search data SHD to provide to the word line of the memory cell group C1, and perform a read operation on the memory cell group C1 to obtain a plurality of second currents Isp2. In this embodiment, the second current Isp2 is equal to 3 reference current values I. By calculating the difference between the second current Isp2 and the first current (=2I), the controller can generate similarity information HD=1.

Then, in the second time period, the controller can perform a search operation for the memory cell group C2. In the two-stage reading operation, by calculating the difference (=1I) between the second current Isp2 and the first current, the controller can generate similarity information HD=2.

By analogy, the controller can continue to perform the search action of memory cell groups C3~C8. The details are not described in detail here.

In this embodiment, the lowest similarity information HD=0 can be obtained in the search action for the memory cell group C3. That is, the memory cell group C3 has the greatest similarity with the search data SHD. The controller can stop the search action in the memory to save time, or the controller can continue to search the remaining memory cell groups C4~C8 actions without any restrictions.

It is worth mentioning that in the embodiment of the present invention, the sense amplifier corresponding to the bit line can temporarily store the current value obtained in the first stage in the page buffer. And in the second stage, the sense amplifier can subtract the obtained current value from the current value temporarily stored in the page buffer to generate a search result.

In addition, the controller can calculate the similarity information HD based on the subtraction result of the current generated by the sense amplifier.

Please refer to FIG. 7, which shows a schematic diagram of a memory device according to an embodiment of the present invention. The memory device 700 includes a controller 710 and a memory cell array 720. The controller 710 and the memory cell array 720 are coupled to each other. The memory cell array 720 can be a two-dimensional or three-dimensional memory cell array. For example, the memory cell array 720 can be a negative OR (NOR) or AND (AND) flash memory cell array. The memory cell array 720 includes a plurality of memory cells, and the memory cells can be floating gate memory cells, split gate memory cells, silicon nitride memory cells, floating point memory cells or ferrogate field effect transistor memory cells, without fixed restrictions.

In this embodiment, the controller 710 can be implemented by a digital circuit or any processing unit with computing capabilities. The controller 710 can be implemented by a memory controller that is well known to those skilled in the art and can perform memory read and write operations, without any specific restrictions.

The details of the in-memory search operation performed in the memory device 700 have been described in detail in the aforementioned multiple implementations and implementation methods, and will not be elaborated in detail below.

In summary, the memory device of the present invention performs a search operation for the data stored in the memory cell through a two-stage in-memory search method. In this way, the in-memory search operation can be completed effectively and correctly without setting a reference memory cell. In this way, the circuit area of the memory device can be effectively reduced, which can reduce the production cost and improve the working performance of the system.

S110~S130: Steps

Claims (17)

A method for searching in memory includes: providing a first voltage or a second voltage to a word line of at least one target memory cell in a first stage according to a logic state of data to be searched, and reading a first current; providing a third voltage or a fourth voltage to the word line of at least one target memory cell in a second stage according to the logic state of the data to be searched, and reading a second current; obtaining a search result according to a difference between the first current and the second current, wherein the first voltage is less than the third voltage, the third voltage is less than or equal to the second voltage, and the second voltage is less than the fourth voltage, wherein the current value of the first current is temporarily stored in a page buffer. The in-memory search method as described in claim 1, wherein the critical voltage of the plurality of first memory cells storing the logical value 0 is between a first critical voltage and a second critical voltage, and the critical voltage of the plurality of second memory cells storing the logical value 1 is between a third critical voltage and a fourth critical voltage, the first critical voltage < the second critical voltage < the third critical voltage < the fourth critical voltage, wherein the first voltage is less than the first critical voltage, the third voltage and the second voltage are between the second critical voltage and the third critical voltage, and the fourth voltage is greater than the fourth critical voltage. The in-memory search method as described in claim 1, wherein when the number of the at least one target memory cell is 1 and the logical value of the data to be searched is the logical value 0, comprises: In the first stage, providing the first voltage to the word line of the at least one target memory cell and reading the first current; in the second stage, providing the third voltage to the word line of the at least one target memory cell and reading the second current; and when the difference between the second current and the first current is greater than a preset current threshold, generating the matching search result. The in-memory search method as described in claim 1, wherein when the number of the at least one target memory cell is 1 and the logical value of the data to be searched is the logical value 1, comprises: in the first stage, providing the second voltage to the word line of the at least one target memory cell and reading the first current; in the second stage, providing the fourth voltage to the word line of the at least one target memory cell and reading the second current; and when the difference between the second current and the first current is substantially equal to the preset current threshold, generating the matching search result. The in-memory search method as described in claim 1, wherein when the number of the at least one target memory cell is 1 and the data to be searched is a don't care, comprises: in the first stage, providing the first voltage to the word line of the at least one target memory cell and reading the first current; in the second stage, providing the second voltage to the word line of the at least one target memory cell and reading the second current; and when the difference between the second current and the first current is substantially equal to the preset current threshold, generating the matching search result. The in-memory search method as described in claim 1, wherein when the critical voltage of at least one target memory cell is greater than the fourth voltage or less than the first voltage, the search result is inconsistent. The in-memory search method as described in claim 1, wherein when the number of the at least one target memory cell is greater than 1, comprises: in the first stage, providing the first voltage to the multiple word lines of the target memory cells and reading the first current; in the second stage, providing the second voltage to the word lines of the target memory cells and reading the second current; and generating the search result according to the size of the difference between the second current and the first current, wherein the search result indicates the similarity between the data to be searched and the data stored in the target memory cells. A memory device includes: a memory cell array; a controller coupled to the memory cell array, for: providing a first voltage or a second voltage to a word line of at least one target memory cell in a first phase according to a logic state of the data to be searched, and reading a first current; providing a third voltage in a second phase according to the logic state of the data to be searched or a fourth voltage to the word line of at least the target memory cell, and read a second current; obtain a search result according to the difference between the first current and the second current, wherein the first voltage is less than the third voltage, the third voltage is less than or equal to the second voltage, and the second voltage is less than the fourth voltage; and a page buffer for temporarily storing the current value of the first current. A memory device as described in claim 8, wherein the critical voltage of a plurality of first memory cells storing a logic value of 0 is between a first critical voltage and a second critical voltage, and the critical voltage of a plurality of second memory cells storing a logic value of 1 is between a third critical voltage and a fourth critical voltage, the first critical voltage < the second critical voltage < the third critical voltage < the fourth critical voltage, wherein the first voltage is less than the first critical voltage, the third voltage and the second voltage are between the second critical voltage and the third critical voltage, and the fourth voltage is greater than the fourth critical voltage. A memory device as described in claim 8, wherein when the number of the at least one target memory cell is 1 and the logical value of the data to be searched is a logical value of 0, the controller is used to: in the first stage, provide the first voltage to the word line of the at least one target memory cell and read the first current; in the second stage, provide the third voltage to the word line of the at least one target memory cell and read the second current; and when the difference between the second current and the first current is substantially equal to the preset current threshold, generate the matching search result. A memory device as described in claim 8, wherein when the number of the at least one target memory cell is 1 and the logical value of the data to be searched is a logical value of 1, the controller is used to: in the first stage, provide the second voltage to the word line of the at least one target memory cell and read the first current; in the second stage, provide the fourth voltage to the word line of the at least one target memory cell and read the second current; and when the difference between the second current and the first current is substantially equal to the preset current threshold, generate the matching search result. A memory device as described in claim 8, wherein when the number of the at least one target memory cell is 1 and the data to be searched is a don't care, the controller is used to: in the first stage, provide the first voltage to the word line of the at least one target memory cell and read the first current; in the second stage, provide the second voltage to the word line of the at least one target memory cell and read the second current; and when the difference between the second current and the first current is substantially equal to the preset current threshold, generate the search result as matching. A memory device as described in claim 8, wherein when the critical voltage of at least one target memory cell is greater than the fourth voltage or less than the first voltage, the search results generated by the controller are all inconsistent. A memory device as described in claim 8, wherein when the number of the at least one target memory cell is greater than 1, the controller is used to: in the first stage, provide the first voltage to the multiple word lines of the target memory cells and read the first current; in the second stage, provide the second voltage to the word lines of the target memory cells and read the second current; and generate the search result according to the size of the difference between the second current and the first current, wherein the search result indicates the similarity between the data to be searched and the data stored in the target memory cells. A memory device as described in claim 8, wherein the memory cell array is a two-dimensional or three-dimensional memory cell array. A memory device as described in claim 8, wherein the memory cell array is an anti-OR and AND flash memory cell array. A memory device as described in claim 8, wherein the memory cells in the memory cell array are floating gate memory cells, split gate memory cells, silicon nitride memory cells, floating point memory cells or ferrogate field effect transistor memory cells.

Images